2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/module.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
37 #include <sys/endian.h>
38 #include <sys/malloc.h>
40 #include <sys/mutex.h>
42 #include <sys/taskqueue.h>
44 #include <machine/stdarg.h>
45 #include <machine/resource.h>
46 #include <machine/bus.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pcireg.h>
50 #include <dev/ata/ata-all.h>
51 #include <dev/ata/ata-pci.h>
54 /* local prototypes */
55 static int ata_marvell_pata_chipinit(device_t dev);
56 static int ata_marvell_pata_ch_attach(device_t dev);
57 static void ata_marvell_pata_setmode(device_t dev, int mode);
58 static int ata_marvell_edma_ch_attach(device_t dev);
59 static int ata_marvell_edma_ch_detach(device_t dev);
60 static int ata_marvell_edma_status(device_t dev);
61 static int ata_marvell_edma_begin_transaction(struct ata_request *request);
62 static int ata_marvell_edma_end_transaction(struct ata_request *request);
63 static void ata_marvell_edma_reset(device_t dev);
64 static void ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
65 static void ata_marvell_edma_dmainit(device_t dev);
74 * Marvell chipset support functions
76 #define ATA_MV_HOST_BASE(ch) \
77 ((ch->unit & 3) * 0x0100) + (ch->unit > 3 ? 0x30000 : 0x20000)
78 #define ATA_MV_EDMA_BASE(ch) \
79 ((ch->unit & 3) * 0x2000) + (ch->unit > 3 ? 0x30000 : 0x20000)
81 struct ata_marvell_response {
88 struct ata_marvell_dma_prdentry {
96 ata_marvell_probe(device_t dev)
98 struct ata_pci_controller *ctlr = device_get_softc(dev);
99 static struct ata_chip_id ids[] =
100 {{ ATA_M88SX5040, 0, 4, MV_50XX, ATA_SA150, "88SX5040" },
101 { ATA_M88SX5041, 0, 4, MV_50XX, ATA_SA150, "88SX5041" },
102 { ATA_M88SX5080, 0, 8, MV_50XX, ATA_SA150, "88SX5080" },
103 { ATA_M88SX5081, 0, 8, MV_50XX, ATA_SA150, "88SX5081" },
104 { ATA_M88SX6041, 0, 4, MV_60XX, ATA_SA300, "88SX6041" },
105 { ATA_M88SX6081, 0, 8, MV_60XX, ATA_SA300, "88SX6081" },
106 { ATA_M88SX6101, 0, 1, MV_61XX, ATA_UDMA6, "88SX6101" },
107 { ATA_M88SX6121, 0, 1, MV_61XX, ATA_UDMA6, "88SX6121" },
108 { ATA_M88SX6145, 0, 2, MV_61XX, ATA_UDMA6, "88SX6145" },
109 { 0, 0, 0, 0, 0, 0}};
111 if (pci_get_vendor(dev) != ATA_MARVELL_ID)
114 if (!(ctlr->chip = ata_match_chip(dev, ids)))
119 switch (ctlr->chip->cfg2) {
122 ctlr->chipinit = ata_marvell_edma_chipinit;
125 ctlr->chipinit = ata_marvell_pata_chipinit;
128 return (BUS_PROBE_DEFAULT);
132 ata_marvell_pata_chipinit(device_t dev)
134 struct ata_pci_controller *ctlr = device_get_softc(dev);
136 if (ata_setup_interrupt(dev, ata_generic_intr))
139 ctlr->ch_attach = ata_marvell_pata_ch_attach;
140 ctlr->ch_detach = ata_pci_ch_detach;
141 ctlr->setmode = ata_marvell_pata_setmode;
142 ctlr->channels = ctlr->chip->cfg1;
147 ata_marvell_pata_ch_attach(device_t dev)
149 struct ata_channel *ch = device_get_softc(dev);
151 /* setup the usual register normal pci style */
152 if (ata_pci_ch_attach(dev))
155 /* dont use 32 bit PIO transfers */
156 ch->flags |= ATA_USE_16BIT;
162 ata_marvell_pata_setmode(device_t dev, int mode)
164 device_t gparent = GRANDPARENT(dev);
165 struct ata_pci_controller *ctlr = device_get_softc(gparent);
166 struct ata_device *atadev = device_get_softc(dev);
168 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
169 mode = ata_check_80pin(dev, mode);
170 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
175 ata_marvell_edma_chipinit(device_t dev)
177 struct ata_pci_controller *ctlr = device_get_softc(dev);
179 if (ata_setup_interrupt(dev, ata_generic_intr))
182 ctlr->r_type1 = SYS_RES_MEMORY;
183 ctlr->r_rid1 = PCIR_BAR(0);
184 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
185 &ctlr->r_rid1, RF_ACTIVE)))
188 /* mask all host controller interrupts */
189 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000);
191 /* mask all PCI interrupts */
192 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000);
194 ctlr->ch_attach = ata_marvell_edma_ch_attach;
195 ctlr->ch_detach = ata_marvell_edma_ch_detach;
196 ctlr->reset = ata_marvell_edma_reset;
197 ctlr->setmode = ata_sata_setmode;
198 ctlr->channels = ctlr->chip->cfg1;
200 /* clear host controller interrupts */
201 ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000);
202 if (ctlr->chip->cfg1 > 4)
203 ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000);
205 /* clear PCI interrupts */
206 ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000);
208 /* unmask PCI interrupts we want */
209 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff);
211 /* unmask host controller interrupts we want */
212 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ |
213 /*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25));
219 ata_marvell_edma_ch_attach(device_t dev)
221 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
222 struct ata_channel *ch = device_get_softc(dev);
226 ata_marvell_edma_dmainit(dev);
227 work = ch->dma.work_bus;
228 /* clear work area */
229 bzero(ch->dma.work, 1024+256);
231 /* set legacy ATA resources */
232 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
233 ch->r_io[i].res = ctlr->r_res1;
234 ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch);
236 ch->r_io[ATA_CONTROL].res = ctlr->r_res1;
237 ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch);
238 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1;
239 ata_default_registers(dev);
241 /* set SATA resources */
242 switch (ctlr->chip->cfg2) {
244 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
245 ch->r_io[ATA_SSTATUS].offset = 0x00100 + ATA_MV_HOST_BASE(ch);
246 ch->r_io[ATA_SERROR].res = ctlr->r_res1;
247 ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch);
248 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
249 ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch);
252 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
253 ch->r_io[ATA_SSTATUS].offset = 0x02300 + ATA_MV_EDMA_BASE(ch);
254 ch->r_io[ATA_SERROR].res = ctlr->r_res1;
255 ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch);
256 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
257 ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch);
258 ch->r_io[ATA_SACTIVE].res = ctlr->r_res1;
259 ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch);
263 ch->flags |= ATA_NO_SLAVE;
264 ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */
266 ch->hw.begin_transaction = ata_marvell_edma_begin_transaction;
267 ch->hw.end_transaction = ata_marvell_edma_end_transaction;
268 ch->hw.status = ata_marvell_edma_status;
270 /* disable the EDMA machinery */
271 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
272 DELAY(100000); /* SOS should poll for disabled */
274 /* set configuration to non-queued 128b read transfers stop on error */
275 ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13));
277 /* request queue base high */
278 ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), work >> 32);
280 /* request queue in ptr */
281 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
283 /* request queue out ptr */
284 ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0);
286 /* response queue base high */
288 ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), work >> 32);
290 /* response queue in ptr */
291 ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0);
293 /* response queue out ptr */
294 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
296 /* clear SATA error register */
297 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
299 /* clear any outstanding error interrupts */
300 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
302 /* unmask all error interrupts */
303 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
305 /* enable EDMA machinery */
306 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
311 ata_marvell_edma_ch_detach(device_t dev)
319 ata_marvell_edma_status(device_t dev)
321 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
322 struct ata_channel *ch = device_get_softc(dev);
323 u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60);
324 int shift = (ch->unit << 1) + (ch->unit > 3);
326 if (cause & (1 << shift)) {
328 /* clear interrupt(s) */
329 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
331 /* do we have any PHY events ? */
332 ata_sata_phy_check_events(dev);
335 /* do we have any device action ? */
336 return (cause & (2 << shift));
339 /* must be called with ATA channel locked and state_mtx held */
341 ata_marvell_edma_begin_transaction(struct ata_request *request)
343 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
344 struct ata_channel *ch = device_get_softc(request->parent);
352 /* only DMA R/W goes through the EMDA machine */
353 if (request->u.ata.command != ATA_READ_DMA &&
354 request->u.ata.command != ATA_WRITE_DMA) {
356 /* disable the EDMA machinery */
357 if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)
358 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
359 return ata_begin_transaction(request);
362 /* check for 48 bit access and convert if needed */
363 ata_modify_if_48bit(request);
365 /* check sanity, setup SG list and DMA engine */
366 if ((error = ch->dma.load(request, NULL, NULL))) {
367 device_printf(request->dev, "setting up DMA failed\n");
368 request->result = error;
369 return ATA_OP_FINISHED;
372 /* get next free request queue slot */
373 req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch));
374 slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f;
375 bytep = (u_int8_t *)(ch->dma.work);
376 bytep += (slot << 5);
377 wordp = (u_int16_t *)bytep;
378 quadp = (u_int32_t *)bytep;
380 /* fill in this request */
381 quadp[0] = (long)request->dma->sg_bus & 0xffffffff;
382 quadp[1] = (u_int64_t)request->dma->sg_bus >> 32;
383 wordp[4] = (request->flags & ATA_R_READ ? 0x01 : 0x00) | (request->tag<<1);
386 bytep[i++] = (request->u.ata.count >> 8) & 0xff;
387 bytep[i++] = 0x10 | ATA_COUNT;
388 bytep[i++] = request->u.ata.count & 0xff;
389 bytep[i++] = 0x10 | ATA_COUNT;
391 bytep[i++] = (request->u.ata.lba >> 24) & 0xff;
392 bytep[i++] = 0x10 | ATA_SECTOR;
393 bytep[i++] = request->u.ata.lba & 0xff;
394 bytep[i++] = 0x10 | ATA_SECTOR;
396 bytep[i++] = (request->u.ata.lba >> 32) & 0xff;
397 bytep[i++] = 0x10 | ATA_CYL_LSB;
398 bytep[i++] = (request->u.ata.lba >> 8) & 0xff;
399 bytep[i++] = 0x10 | ATA_CYL_LSB;
401 bytep[i++] = (request->u.ata.lba >> 40) & 0xff;
402 bytep[i++] = 0x10 | ATA_CYL_MSB;
403 bytep[i++] = (request->u.ata.lba >> 16) & 0xff;
404 bytep[i++] = 0x10 | ATA_CYL_MSB;
406 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf);
407 bytep[i++] = 0x10 | ATA_DRIVE;
409 bytep[i++] = request->u.ata.command;
410 bytep[i++] = 0x90 | ATA_COMMAND;
412 /* enable EDMA machinery if needed */
413 if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) {
414 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
415 while (!(ATA_INL(ctlr->r_res1,
416 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
420 /* tell EDMA it has a new request */
421 slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f;
422 req_in &= 0xfffffc00;
423 req_in += (slot << 5);
424 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in);
426 return ATA_OP_CONTINUES;
429 /* must be called with ATA channel locked and state_mtx held */
431 ata_marvell_edma_end_transaction(struct ata_request *request)
433 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
434 struct ata_channel *ch = device_get_softc(request->parent);
435 int offset = (ch->unit > 3 ? 0x30014 : 0x20014);
436 u_int32_t icr = ATA_INL(ctlr->r_res1, offset);
440 if ((icr & (0x0001 << (ch->unit & 3)))) {
441 struct ata_marvell_response *response;
442 u_int32_t rsp_in, rsp_out;
446 callout_stop(&request->callout);
448 /* get response ptr's */
449 rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch));
450 rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch));
451 slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f;
452 rsp_out &= 0xffffff00;
453 rsp_out += (slot << 3);
454 response = (struct ata_marvell_response *)
455 (ch->dma.work + 1024 + (slot << 3));
457 /* record status for this request */
458 request->status = response->dev_status;
462 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out);
464 /* update progress */
465 if (!(request->status & ATA_S_ERROR) &&
466 !(request->flags & ATA_R_TIMEOUT))
467 request->donecount = request->bytecount;
470 ch->dma.unload(request);
472 res = ATA_OP_FINISHED;
475 /* legacy ATA interrupt */
477 res = ata_end_transaction(request);
481 ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3))));
486 ata_marvell_edma_reset(device_t dev)
488 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
489 struct ata_channel *ch = device_get_softc(dev);
491 /* disable the EDMA machinery */
492 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
493 while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
496 /* clear SATA error register */
497 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
499 /* clear any outstanding error interrupts */
500 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
502 /* unmask all error interrupts */
503 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
505 /* enable channel and test for devices */
506 if (ata_sata_phy_reset(dev, -1, 1))
507 ata_generic_reset(dev);
509 /* enable EDMA machinery */
510 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
514 ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs,
517 struct ata_dmasetprd_args *args = xsc;
518 struct ata_marvell_dma_prdentry *prd = args->dmatab;
521 if ((args->error = error))
524 for (i = 0; i < nsegs; i++) {
525 prd[i].addrlo = htole32(segs[i].ds_addr);
526 prd[i].count = htole32(segs[i].ds_len);
527 prd[i].addrhi = htole32((u_int64_t)segs[i].ds_addr >> 32);
529 prd[i - 1].count |= htole32(ATA_DMA_EOT);
530 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n"));
535 ata_marvell_edma_dmainit(device_t dev)
537 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
538 struct ata_channel *ch = device_get_softc(dev);
541 /* note start and stop are not used here */
542 ch->dma.setprd = ata_marvell_edma_dmasetprd;
544 /* if 64bit support present adjust max address used */
545 if (ATA_INL(ctlr->r_res1, 0x00d00) & 0x00000004)
546 ch->dma.max_address = BUS_SPACE_MAXADDR;
548 /* chip does not reliably do 64K DMA transfers */
549 ch->dma.max_iosize = 64 * DEV_BSIZE;
552 ATA_DECLARE_DRIVER(ata_marvell);