2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 * Atheros Hardware Access Layer
25 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal
26 * structure for use with the device. Hardware-related operations that
27 * follow must call back into the HAL through interface, supplying the
28 * reference as the first parameter.
34 * __ahdecl is analogous to _cdecl; it defines the calling
35 * convention used within the HAL. For most systems this
36 * can just default to be empty and the compiler will (should)
37 * use _cdecl. For systems where _cdecl is not compatible this
38 * must be defined. See linux/ah_osdep.h for an example.
45 * Status codes that may be returned by the HAL. Note that
46 * interfaces that return a status code set it only when an
47 * error occurs--i.e. you cannot check it for success.
50 HAL_OK = 0, /* No error */
51 HAL_ENXIO = 1, /* No hardware present */
52 HAL_ENOMEM = 2, /* Memory allocation failed */
53 HAL_EIO = 3, /* Hardware didn't respond as expected */
54 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */
55 HAL_EEVERSION = 5, /* EEPROM version invalid */
56 HAL_EELOCKED = 6, /* EEPROM unreadable */
57 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */
58 HAL_EEREAD = 8, /* EEPROM read problem */
59 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */
60 HAL_EESIZE = 10, /* EEPROM size not supported */
61 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */
62 HAL_EINVAL = 12, /* Invalid parameter to function */
63 HAL_ENOTSUPP = 13, /* Hardware revision not supported */
64 HAL_ESELFTEST = 14, /* Hardware self-test failed */
65 HAL_EINPROGRESS = 15, /* Operation incomplete */
66 HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */
67 HAL_EEBADCC = 17, /* EEPROM invalid country code */
71 AH_FALSE = 0, /* NB: lots of code assumes false is zero */
76 HAL_CAP_REG_DMN = 0, /* current regulatory domain */
77 HAL_CAP_CIPHER = 1, /* hardware supports cipher */
78 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */
79 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */
80 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */
81 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */
82 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */
83 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */
84 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */
85 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */
86 HAL_CAP_DIAG = 11, /* hardware diagnostic support */
87 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */
88 HAL_CAP_BURST = 13, /* hardware supports packet bursting */
89 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */
90 HAL_CAP_TXPOW = 15, /* global tx power limit */
91 HAL_CAP_TPC = 16, /* per-packet tx power control */
92 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */
93 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */
94 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */
95 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */
96 /* 21 was HAL_CAP_XR */
97 HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */
98 /* 23 was HAL_CAP_CHAN_HALFRATE */
99 /* 24 was HAL_CAP_CHAN_QUARTERRATE */
100 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */
101 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */
102 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */
103 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */
104 HAL_CAP_INTMIT = 29, /* interference mitigation */
105 HAL_CAP_RXORN_FATAL = 30, /* HAL_INT_RXORN treated as fatal */
106 HAL_CAP_HT = 31, /* hardware can support HT */
107 HAL_CAP_TX_CHAINMASK = 32, /* mask of TX chains supported */
108 HAL_CAP_RX_CHAINMASK = 33, /* mask of RX chains supported */
109 HAL_CAP_RXTSTAMP_PREC = 34, /* rx desc tstamp precision (bits) */
110 HAL_CAP_BB_HANG = 35, /* can baseband hang */
111 HAL_CAP_MAC_HANG = 36, /* can MAC hang */
112 HAL_CAP_INTRMASK = 37, /* bitmask of supported interrupts */
113 HAL_CAP_BSSIDMATCH = 38, /* hardware has disable bssid match */
114 } HAL_CAPABILITY_TYPE;
117 * "States" for setting the LED. These correspond to
118 * the possible 802.11 operational states and there may
119 * be a many-to-one mapping between these states and the
120 * actual hardware state for the LED's (i.e. the hardware
121 * may have fewer states).
132 * Transmit queue types/numbers. These are used to tag
133 * each transmit queue in the hardware and to identify a set
134 * of transmit queues for operations such as start/stop dma.
137 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */
138 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */
139 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */
140 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */
141 HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */
144 #define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */
147 * Transmit queue subtype. These map directly to
148 * WME Access Categories (except for UPSD). Refer
149 * to Table 5 of the WME spec.
152 HAL_WME_AC_BK = 0, /* background access category */
153 HAL_WME_AC_BE = 1, /* best effort access category*/
154 HAL_WME_AC_VI = 2, /* video access category */
155 HAL_WME_AC_VO = 3, /* voice access category */
156 HAL_WME_UPSD = 4, /* uplink power save */
157 } HAL_TX_QUEUE_SUBTYPE;
160 * Transmit queue flags that control various
161 * operational parameters.
165 * Per queue interrupt enables. When set the associated
166 * interrupt may be delivered for packets sent through
167 * the queue. Without these enabled no interrupts will
168 * be delivered for transmits through the queue.
170 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */
171 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */
172 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */
173 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */
174 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */
176 * Enable hardware compression for packets sent through
177 * the queue. The compression buffer must be setup and
178 * packets must have a key entry marked in the tx descriptor.
180 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */
182 * Disable queue when veol is hit or ready time expires.
183 * By default the queue is disabled only on reaching the
184 * physical end of queue (i.e. a null link ptr in the
187 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020,
189 * Schedule frames on delivery of a DBA (DMA Beacon Alert)
190 * event. Frames will be transmitted only when this timer
191 * fires, e.g to transmit a beacon in ap or adhoc modes.
193 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */
195 * Each transmit queue has a counter that is incremented
196 * each time the queue is enabled and decremented when
197 * the list of frames to transmit is traversed (or when
198 * the ready time for the queue expires). This counter
199 * must be non-zero for frames to be scheduled for
200 * transmission. The following controls disable bumping
201 * this counter under certain conditions. Typically this
202 * is used to gate frames based on the contents of another
203 * queue (e.g. CAB traffic may only follow a beacon frame).
204 * These are meaningful only when frames are scheduled
205 * with a non-ASAP policy (e.g. DBA-gated).
207 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */
208 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */
211 * Fragment burst backoff policy. Normally the no backoff
212 * is done after a successful transmission, the next fragment
213 * is sent at SIFS. If this flag is set backoff is done
214 * after each fragment, regardless whether it was ack'd or
215 * not, after the backoff count reaches zero a normal channel
216 * access procedure is done before the next transmit (i.e.
217 * wait AIFS instead of SIFS).
219 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000,
221 * Disable post-tx backoff following each frame.
223 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */
225 * DCU arbiter lockout control. This controls how
226 * lower priority tx queues are handled with respect to
227 * to a specific queue when multiple queues have frames
228 * to send. No lockout means lower priority queues arbitrate
229 * concurrently with this queue. Intra-frame lockout
230 * means lower priority queues are locked out until the
231 * current frame transmits (e.g. including backoffs and bursting).
232 * Global lockout means nothing lower can arbitrary so
233 * long as there is traffic activity on this queue (frames,
236 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */
237 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */
239 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */
240 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */
241 } HAL_TX_QUEUE_FLAGS;
244 uint32_t tqi_ver; /* hal TXQ version */
245 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */
246 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */
247 uint32_t tqi_priority; /* (not used) */
248 uint32_t tqi_aifs; /* aifs */
249 uint32_t tqi_cwmin; /* cwMin */
250 uint32_t tqi_cwmax; /* cwMax */
251 uint16_t tqi_shretry; /* rts retry limit */
252 uint16_t tqi_lgretry; /* long retry limit (not used)*/
253 uint32_t tqi_cbrPeriod; /* CBR period (us) */
254 uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */
255 uint32_t tqi_burstTime; /* max burst duration (us) */
256 uint32_t tqi_readyTime; /* frame schedule time (us) */
257 uint32_t tqi_compBuf; /* comp buffer phys addr */
260 #define HAL_TQI_NONVAL 0xffff
262 /* token to use for aifs, cwmin, cwmax */
263 #define HAL_TXQ_USEDEFAULT ((uint32_t) -1)
265 /* compression definitions */
266 #define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */
267 #define HAL_COMP_BUF_ALIGN_SIZE 512
270 * Transmit packet types. This belongs in ah_desc.h, but
271 * is here so we can give a proper type to various parameters
272 * (and not require everyone include the file).
274 * NB: These values are intentionally assigned for
275 * direct use when setting up h/w descriptors.
278 HAL_PKT_TYPE_NORMAL = 0,
279 HAL_PKT_TYPE_ATIM = 1,
280 HAL_PKT_TYPE_PSPOLL = 2,
281 HAL_PKT_TYPE_BEACON = 3,
282 HAL_PKT_TYPE_PROBE_RESP = 4,
283 HAL_PKT_TYPE_CHIRP = 5,
284 HAL_PKT_TYPE_GRP_POLL = 6,
285 HAL_PKT_TYPE_AMPDU = 7,
288 /* Rx Filter Frame Types */
290 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */
291 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */
292 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */
293 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */
294 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */
295 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */
296 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */
297 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */
298 HAL_RX_FILTER_PHYRADAR = 0x00000200, /* Allow phy radar errors */
299 HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */
300 HAL_RX_FILTER_BSSID = 0x00000800, /* Disable BSSID match */
305 HAL_PM_FULL_SLEEP = 1,
306 HAL_PM_NETWORK_SLEEP = 2,
312 * These are mapped to take advantage of the common locations for many of
313 * the bits on all of the currently supported MAC chips. This is to make
314 * the ISR as efficient as possible, while still abstracting HW differences.
315 * When new hardware breaks this commonality this enumerated type, as well
316 * as the HAL functions using it, must be modified. All values are directly
317 * mapped unless commented otherwise.
320 HAL_INT_RX = 0x00000001, /* Non-common mapping */
321 HAL_INT_RXDESC = 0x00000002,
322 HAL_INT_RXNOFRM = 0x00000008,
323 HAL_INT_RXEOL = 0x00000010,
324 HAL_INT_RXORN = 0x00000020,
325 HAL_INT_TX = 0x00000040, /* Non-common mapping */
326 HAL_INT_TXDESC = 0x00000080,
327 HAL_INT_TXURN = 0x00000800,
328 HAL_INT_MIB = 0x00001000,
329 HAL_INT_RXPHY = 0x00004000,
330 HAL_INT_RXKCM = 0x00008000,
331 HAL_INT_SWBA = 0x00010000,
332 HAL_INT_BMISS = 0x00040000,
333 HAL_INT_BNR = 0x00100000,
334 HAL_INT_TIM = 0x00200000, /* Non-common mapping */
335 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */
336 HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */
337 HAL_INT_GPIO = 0x01000000,
338 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */
339 HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */
340 HAL_INT_TBTT = 0x08000000, /* Non-common mapping */
341 HAL_INT_CST = 0x10000000, /* Non-common mapping */
342 HAL_INT_GTT = 0x20000000, /* Non-common mapping */
343 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */
344 #define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */
345 HAL_INT_BMISC = HAL_INT_TIM
351 /* Interrupt bits that map directly to ISR/IMR bits */
352 HAL_INT_COMMON = HAL_INT_RXNOFRM
368 HAL_GPIO_MUX_OUTPUT = 0,
369 HAL_GPIO_MUX_PCIE_ATTENTION_LED = 1,
370 HAL_GPIO_MUX_PCIE_POWER_LED = 2,
371 HAL_GPIO_MUX_TX_FRAME = 3,
372 HAL_GPIO_MUX_RX_CLEAR_EXTERNAL = 4,
373 HAL_GPIO_MUX_MAC_NETWORK_LED = 5,
374 HAL_GPIO_MUX_MAC_POWER_LED = 6
378 HAL_GPIO_INTR_LOW = 0,
379 HAL_GPIO_INTR_HIGH = 1,
380 HAL_GPIO_INTR_DISABLE = 2
381 } HAL_GPIO_INTR_TYPE;
384 HAL_RFGAIN_INACTIVE = 0,
385 HAL_RFGAIN_READ_REQUESTED = 1,
386 HAL_RFGAIN_NEED_CHANGE = 2
389 typedef uint16_t HAL_CTRY_CODE; /* country code */
390 typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */
392 #define HAL_ANTENNA_MIN_MODE 0
393 #define HAL_ANTENNA_FIXED_A 1
394 #define HAL_ANTENNA_FIXED_B 2
395 #define HAL_ANTENNA_MAX_MODE 3
406 HAL_MODE_11A = 0x001, /* 11a channels */
407 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */
408 HAL_MODE_11B = 0x004, /* 11b channels */
409 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */
411 HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */
413 HAL_MODE_11G = 0x008, /* XXX historical */
415 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */
416 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */
417 HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */
418 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */
419 HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */
420 HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */
421 HAL_MODE_11NG_HT20 = 0x008000,
422 HAL_MODE_11NA_HT20 = 0x010000,
423 HAL_MODE_11NG_HT40PLUS = 0x020000,
424 HAL_MODE_11NG_HT40MINUS = 0x040000,
425 HAL_MODE_11NA_HT40PLUS = 0x080000,
426 HAL_MODE_11NA_HT40MINUS = 0x100000,
427 HAL_MODE_ALL = 0xffffff
431 int rateCount; /* NB: for proper padding */
432 uint8_t rateCodeToIndex[144]; /* back mapping */
434 uint8_t valid; /* valid for rate control use */
435 uint8_t phy; /* CCK/OFDM/XR */
436 uint32_t rateKbps; /* transfer rate in kbs */
437 uint8_t rateCode; /* rate for h/w descriptors */
438 uint8_t shortPreamble; /* mask for enabling short
439 * preamble in CCK rate code */
440 uint8_t dot11Rate; /* value for supported rates
441 * info element of MLME */
442 uint8_t controlRate; /* index of next lower basic
443 * rate; used for dur. calcs */
444 uint16_t lpAckDuration; /* long preamble ACK duration */
445 uint16_t spAckDuration; /* short preamble ACK duration*/
450 u_int rs_count; /* number of valid entries */
451 uint8_t rs_rates[32]; /* rates */
455 * 802.11n specific structures and enums
458 HAL_CHAINTYPE_TX = 1, /* Tx chain type */
459 HAL_CHAINTYPE_RX = 2, /* RX chain type */
468 #define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */
469 #define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */
470 #define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */
471 } HAL_11N_RATE_SERIES;
474 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */
475 HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */
479 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */
480 HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */
484 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */
485 HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */
486 } HAL_HT_EXTPROTSPACING;
490 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */
491 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */
495 * Antenna switch control. By default antenna selection
496 * enables multiple (2) antenna use. To force use of the
497 * A or B antenna only specify a fixed setting. Fixing
498 * the antenna will also disable any diversity support.
501 HAL_ANT_VARIABLE = 0, /* variable by programming */
502 HAL_ANT_FIXED_A = 1, /* fixed antenna A */
503 HAL_ANT_FIXED_B = 2, /* fixed antenna B */
507 HAL_M_STA = 1, /* infrastructure station */
508 HAL_M_IBSS = 0, /* IBSS (adhoc) station */
509 HAL_M_HOSTAP = 6, /* Software Access Point */
510 HAL_M_MONITOR = 8 /* Monitor mode */
514 uint8_t kv_type; /* one of HAL_CIPHER */
516 uint16_t kv_len; /* length in bits */
517 uint8_t kv_val[16]; /* enough for 128-bit keys */
518 uint8_t kv_mic[8]; /* TKIP MIC key */
519 uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */
524 HAL_CIPHER_AES_OCB = 1,
525 HAL_CIPHER_AES_CCM = 2,
528 HAL_CIPHER_CLR = 5, /* no encryption */
530 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */
534 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */
536 HAL_SLOT_TIME_20 = 20,
540 * Per-station beacon timer state. Note that the specified
541 * beacon interval (given in TU's) can also include flags
542 * to force a TSF reset and to enable the beacon xmit logic.
543 * If bs_cfpmaxduration is non-zero the hardware is setup to
544 * coexist with a PCF-capable AP.
547 uint32_t bs_nexttbtt; /* next beacon in TU */
548 uint32_t bs_nextdtim; /* next DTIM in TU */
549 uint32_t bs_intval; /* beacon interval+flags */
550 #define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */
551 #define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */
552 #define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */
553 uint32_t bs_dtimperiod;
554 uint16_t bs_cfpperiod; /* CFP period in TU */
555 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */
556 uint32_t bs_cfpnext; /* next CFP in TU */
557 uint16_t bs_timoffset; /* byte offset to TIM bitmap */
558 uint16_t bs_bmissthreshold; /* beacon miss threshold */
559 uint32_t bs_sleepduration; /* max sleep duration */
563 * Like HAL_BEACON_STATE but for non-station mode setup.
564 * NB: see above flag definitions for bt_intval.
567 uint32_t bt_intval; /* beacon interval+flags */
568 uint32_t bt_nexttbtt; /* next beacon in TU */
569 uint32_t bt_nextatim; /* next ATIM in TU */
570 uint32_t bt_nextdba; /* next DBA in 1/8th TU */
571 uint32_t bt_nextswba; /* next SWBA in 1/8th TU */
572 uint32_t bt_flags; /* timer enables */
573 #define HAL_BEACON_TBTT_EN 0x00000001
574 #define HAL_BEACON_DBA_EN 0x00000002
575 #define HAL_BEACON_SWBA_EN 0x00000004
579 * Per-node statistics maintained by the driver for use in
580 * optimizing signal quality and other operational aspects.
583 uint32_t ns_avgbrssi; /* average beacon rssi */
584 uint32_t ns_avgrssi; /* average data rssi */
585 uint32_t ns_avgtxrssi; /* average tx rssi */
588 #define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
591 struct ath_tx_status;
592 struct ath_rx_status;
593 struct ieee80211_channel;
596 * Hardware Access Layer (HAL) API.
598 * Clients of the HAL call ath_hal_attach to obtain a reference to an
599 * ath_hal structure for use with the device. Hardware-related operations
600 * that follow must call back into the HAL through interface, supplying
601 * the reference as the first parameter. Note that before using the
602 * reference returned by ath_hal_attach the caller should verify the
603 * ABI version number.
606 uint32_t ah_magic; /* consistency check magic number */
607 uint16_t ah_devid; /* PCI device ID */
608 uint16_t ah_subvendorid; /* PCI subvendor ID */
609 HAL_SOFTC ah_sc; /* back pointer to driver/os state */
610 HAL_BUS_TAG ah_st; /* params for register r+w */
611 HAL_BUS_HANDLE ah_sh;
612 HAL_CTRY_CODE ah_countryCode;
614 uint32_t ah_macVersion; /* MAC version id */
615 uint16_t ah_macRev; /* MAC revision */
616 uint16_t ah_phyRev; /* PHY revision */
617 /* NB: when only one radio is present the rev is in 5Ghz */
618 uint16_t ah_analog5GhzRev;/* 5GHz radio revision */
619 uint16_t ah_analog2GhzRev;/* 2GHz radio revision */
621 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *,
623 void __ahdecl(*ah_detach)(struct ath_hal*);
625 /* Reset functions */
626 HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE,
627 struct ieee80211_channel *,
628 HAL_BOOL bChannelChange, HAL_STATUS *status);
629 HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *);
630 HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *);
631 void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore);
632 void __ahdecl(*ah_disablePCIE)(struct ath_hal *);
633 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *);
634 HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*,
635 struct ieee80211_channel *, HAL_BOOL *);
636 HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *,
637 struct ieee80211_channel *, u_int chainMask,
638 HAL_BOOL longCal, HAL_BOOL *isCalDone);
639 HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *,
640 const struct ieee80211_channel *);
641 HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t);
643 /* Transmit functions */
644 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*,
645 HAL_BOOL incTrigLevel);
646 int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE,
647 const HAL_TXQ_INFO *qInfo);
648 HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q,
649 const HAL_TXQ_INFO *qInfo);
650 HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q,
651 HAL_TXQ_INFO *qInfo);
652 HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q);
653 HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q);
654 uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int);
655 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp);
656 uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q);
657 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int);
658 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int);
659 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *,
660 u_int pktLen, u_int hdrLen,
661 HAL_PKT_TYPE type, u_int txPower,
662 u_int txRate0, u_int txTries0,
663 u_int keyIx, u_int antMode, u_int flags,
664 u_int rtsctsRate, u_int rtsctsDuration,
665 u_int compicvLen, u_int compivLen,
667 HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*,
668 u_int txRate1, u_int txTries1,
669 u_int txRate2, u_int txTries2,
670 u_int txRate3, u_int txTries3);
671 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *,
672 u_int segLen, HAL_BOOL firstSeg,
673 HAL_BOOL lastSeg, const struct ath_desc *);
674 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *,
675 struct ath_desc *, struct ath_tx_status *);
676 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *);
677 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*);
679 /* Receive Functions */
680 uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*);
681 void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp);
682 void __ahdecl(*ah_enableReceive)(struct ath_hal*);
683 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*);
684 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*);
685 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*);
686 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*,
687 uint32_t filter0, uint32_t filter1);
688 HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*,
690 HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*,
692 uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*);
693 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t);
694 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *,
695 uint32_t size, u_int flags);
696 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *,
697 struct ath_desc *, uint32_t phyAddr,
698 struct ath_desc *next, uint64_t tsf,
699 struct ath_rx_status *);
700 void __ahdecl(*ah_rxMonitor)(struct ath_hal *,
701 const HAL_NODE_STATS *,
702 const struct ieee80211_channel *);
703 void __ahdecl(*ah_procMibEvent)(struct ath_hal *,
704 const HAL_NODE_STATS *);
707 HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *,
708 HAL_CAPABILITY_TYPE, uint32_t capability,
710 HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *,
711 HAL_CAPABILITY_TYPE, uint32_t capability,
712 uint32_t setting, HAL_STATUS *);
713 HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request,
714 const void *args, uint32_t argsize,
715 void **result, uint32_t *resultsize);
716 void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *);
717 HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*);
718 void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *);
719 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*);
720 HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*,
721 uint16_t, HAL_STATUS *);
722 void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE);
723 void __ahdecl(*ah_writeAssocid)(struct ath_hal*,
724 const uint8_t *bssid, uint16_t assocId);
725 HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *,
726 uint32_t gpio, HAL_GPIO_MUX_TYPE);
727 HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio);
728 uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio);
729 HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *,
730 uint32_t gpio, uint32_t val);
731 void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t);
732 uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*);
733 uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*);
734 void __ahdecl(*ah_resetTsf)(struct ath_hal*);
735 HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*);
736 void __ahdecl(*ah_updateMibCounters)(struct ath_hal*,
738 HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*);
739 u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*);
740 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int);
741 HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*);
742 HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*,
744 HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int);
745 u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*);
746 HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int);
747 u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*);
748 HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int);
749 u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*);
750 HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int);
751 u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*);
752 HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int);
753 u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*);
754 HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int);
755 void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int);
757 /* Key Cache Functions */
758 uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*);
759 HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t);
760 HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *,
762 HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*,
763 uint16_t, const HAL_KEYVAL *,
764 const uint8_t *, int);
765 HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*,
766 uint16_t, const uint8_t *);
768 /* Power Management Functions */
769 HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*,
770 HAL_POWER_MODE mode, int setChip);
771 HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*);
772 int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *,
773 const struct ieee80211_channel *);
775 /* Beacon Management Functions */
776 void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*,
777 const HAL_BEACON_TIMERS *);
778 /* NB: deprecated, use ah_setBeaconTimers instead */
779 void __ahdecl(*ah_beaconInit)(struct ath_hal *,
780 uint32_t nexttbtt, uint32_t intval);
781 void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*,
782 const HAL_BEACON_STATE *);
783 void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*);
785 /* Interrupt functions */
786 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*);
787 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*);
788 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*);
789 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT);
793 * Check the PCI vendor ID and device ID against Atheros' values
794 * and return a printable description for any Atheros hardware.
795 * AH_NULL is returned if the ID's do not describe Atheros hardware.
797 extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid);
800 * Attach the HAL for use with the specified device. The device is
801 * defined by the PCI device ID. The caller provides an opaque pointer
802 * to an upper-layer data structure (HAL_SOFTC) that is stored in the
803 * HAL state block for later use. Hardware register accesses are done
804 * using the specified bus tag and handle. On successful return a
805 * reference to a state block is returned that must be supplied in all
806 * subsequent HAL calls. Storage associated with this reference is
807 * dynamically allocated and must be freed by calling the ah_detach
808 * method when the client is done. If the attach operation fails a
809 * null (AH_NULL) reference will be returned and a status code will
810 * be returned if the status parameter is non-zero.
812 extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC,
813 HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS* status);
815 extern const char *ath_hal_mac_name(struct ath_hal *);
816 extern const char *ath_hal_rf_name(struct ath_hal *);
819 * Regulatory interfaces. Drivers should use ath_hal_init_channels to
820 * request a set of channels for a particular country code and/or
821 * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then
822 * this list is constructed according to the contents of the EEPROM.
823 * ath_hal_getchannels acts similarly but does not alter the operating
824 * state; this can be used to collect information for a particular
825 * regulatory configuration. Finally ath_hal_set_channels installs a
826 * channel list constructed outside the driver. The HAL will adopt the
827 * channel list and setup internal state according to the specified
828 * regulatory configuration (e.g. conformance test limits).
830 * For all interfaces the channel list is returned in the supplied array.
831 * maxchans defines the maximum size of this array. nchans contains the
832 * actual number of channels returned. If a problem occurred then a
833 * status code != HAL_OK is returned.
835 struct ieee80211_channel;
838 * Return a list of channels according to the specified regulatory.
840 extern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *,
841 struct ieee80211_channel *chans, u_int maxchans, int *nchans,
842 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn,
843 HAL_BOOL enableExtendedChannels);
846 * Return a list of channels and install it as the current operating
849 extern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *,
850 struct ieee80211_channel *chans, u_int maxchans, int *nchans,
851 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd,
852 HAL_BOOL enableExtendedChannels);
855 * Install the list of channels as the current operating regulatory
856 * and setup related state according to the country code and sku.
858 extern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *,
859 struct ieee80211_channel *chans, int nchans,
860 HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn);
863 * Calibrate noise floor data following a channel scan or similar.
864 * This must be called prior retrieving noise floor data.
866 extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah);
869 * Return bit mask of wireless modes supported by the hardware.
871 extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*);
874 * Calculate the transmit duration of a frame.
876 extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *,
877 const HAL_RATE_TABLE *rates, uint32_t frameLen,
878 uint16_t rateix, HAL_BOOL shortPreamble);
879 #endif /* _ATH_AH_H_ */