1 /**************************************************************************
3 Copyright (c) 2007-2009, Chelsio Inc.
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Neither the name of the Chelsio Corporation nor the names of its
13 contributors may be used to endorse or promote products derived from
14 this software without specific prior written permission.
16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 POSSIBILITY OF SUCH DAMAGE.
30 ***************************************************************************/
33 #ifndef _CXGB_ADAPTER_H_
34 #define _CXGB_ADAPTER_H_
37 #include <sys/mutex.h>
40 #include <sys/socket.h>
41 #include <sys/sockio.h>
42 #include <sys/condvar.h>
43 #include <sys/buf_ring.h>
45 #include <net/ethernet.h>
47 #include <net/if_media.h>
48 #include <net/if_dl.h>
50 #include <machine/bus.h>
51 #include <machine/resource.h>
53 #include <sys/bus_dma.h>
54 #include <dev/pci/pcireg.h>
55 #include <dev/pci/pcivar.h>
57 #include <cxgb_osdep.h>
59 #include <sys/mbufq.h>
62 #include <netinet/tcp_lro.h>
67 extern int cxgb_debug;
70 #define MTX_INIT(lock, lockname, class, flags) \
72 printf("initializing %s at %s:%d\n", lockname, __FILE__, __LINE__); \
73 mtx_init((lock), lockname, class, flags); \
76 #define MTX_DESTROY(lock) \
78 printf("destroying %s at %s:%d\n", (lock)->lock_object.lo_name, __FILE__, __LINE__); \
79 mtx_destroy((lock)); \
83 #define MTX_INIT mtx_init
84 #define MTX_DESTROY mtx_destroy
94 struct adapter *adapter;
98 const struct port_type_info *port_type;
101 struct link_config link_config;
102 struct ifmedia media;
111 uint8_t hw_addr[ETHER_ADDR_LEN];
112 struct task timer_reclaim_task;
113 struct cdev *port_cdev;
115 #define PORT_LOCK_NAME_LEN 32
116 #define PORT_NAME_LEN 32
117 char lockbuf[PORT_LOCK_NAME_LEN];
118 char namebuf[PORT_NAME_LEN];
119 } __aligned(L1_CACHE_BYTES);
123 FULL_INIT_DONE = (1 << 0),
124 USING_MSI = (1 << 1),
125 USING_MSIX = (1 << 2),
126 QUEUES_BOUND = (1 << 3),
127 FW_UPTODATE = (1 << 4),
128 TPS_UPTODATE = (1 << 5),
129 CXGB_SHUTDOWN = (1 << 6),
130 CXGB_OFLD_INIT = (1 << 7),
131 TP_PARITY_INIT = (1 << 8),
132 CXGB_BUSY = (1 << 9),
137 #define IS_DOOMED(p) (p->flags & DOOMED)
138 #define SET_DOOMED(p) do {p->flags |= DOOMED;} while (0)
139 #define DOOMED(p) (p->flags & DOOMED)
140 #define IS_BUSY(sc) (sc->flags & CXGB_BUSY)
141 #define SET_BUSY(sc) do {sc->flags |= CXGB_BUSY;} while (0)
142 #define CLR_BUSY(sc) do {sc->flags &= ~CXGB_BUSY;} while (0)
144 #define FL_Q_SIZE 4096
145 #define JUMBO_Q_SIZE 1024
146 #define RSPQ_Q_SIZE 1024
147 #define TX_ETH_Q_SIZE 1024
155 * work request size in bytes
157 #define WR_LEN (WR_FLITS * 8)
158 #define PIO_LEN (WR_LEN - sizeof(struct cpl_tx_pkt_lso))
162 unsigned short enabled;
163 struct lro_ctrl ctrl;
167 #define RX_BUNDLE_SIZE 8
177 uint32_t holdoff_tmr;
178 uint32_t next_holdoff;
180 uint32_t async_notif;
182 uint32_t offload_pkts;
183 uint32_t offload_bundles;
185 uint32_t unhandled_irqs;
187 bus_addr_t phys_addr;
188 bus_dma_tag_t desc_tag;
189 bus_dmamap_t desc_map;
191 struct t3_mbuf_hdr rspq_mh;
192 struct rsp_desc *desc;
194 #define RSPQ_NAME_LEN 32
195 char lockbuf[RSPQ_NAME_LEN];
196 uint32_t rspq_dump_start;
197 uint32_t rspq_dump_count;
210 bus_addr_t phys_addr;
213 bus_dma_tag_t desc_tag;
214 bus_dmamap_t desc_map;
215 bus_dma_tag_t entry_tag;
217 struct rx_desc *desc;
218 struct rx_sw_desc *sdesc;
225 #define TXQ_TRANSMITTING 0x1
238 struct tx_desc *desc;
239 struct tx_sw_desc *sdesc;
241 bus_addr_t phys_addr;
242 struct task qresume_task;
243 struct task qreclaim_task;
247 bus_dma_tag_t desc_tag;
248 bus_dmamap_t desc_map;
249 bus_dma_tag_t entry_tag;
250 struct mbuf_head sendq;
252 struct buf_ring *txq_mr;
253 struct ifaltq *txq_ifq;
254 struct callout txq_timer;
255 struct callout txq_watchdog;
256 uint64_t txq_coalesced;
258 uint32_t txq_skipped;
259 uint32_t txq_enqueued;
260 uint32_t txq_dump_start;
261 uint32_t txq_dump_count;
262 uint64_t txq_direct_packets;
263 uint64_t txq_direct_bytes;
265 struct sg_ent txq_sgl[TX_MAX_SEGS / 2 + 1];
270 SGE_PSTAT_TSO, /* # of TSO requests */
271 SGE_PSTAT_RX_CSUM_GOOD, /* # of successful RX csum offloads */
272 SGE_PSTAT_TX_CSUM, /* # of TX checksum offloads */
273 SGE_PSTAT_VLANEX, /* # of VLAN tag extractions */
274 SGE_PSTAT_VLANINS, /* # of VLAN tag insertions */
277 #define SGE_PSTAT_MAX (SGE_PSTAT_VLANINS+1)
279 #define QS_EXITING 0x1
280 #define QS_RUNNING 0x2
282 #define QS_FLUSHING 0x8
283 #define QS_TIMEOUT 0x10
286 struct sge_rspq rspq;
287 struct sge_fl fl[SGE_RXQ_PER_SET];
289 struct lro_state lro;
291 struct sge_txq txq[SGE_TXQ_PER_SET];
292 uint32_t txq_stopped; /* which Tx queues are stopped */
293 uint64_t port_stats[SGE_PSTAT_MAX];
294 struct port_info *port;
295 int idx; /* qset # */
300 #define QS_NAME_LEN 32
301 char namebuf[QS_NAME_LEN];
305 struct sge_qset qs[SGE_QSETS];
314 TAILQ_ENTRY(adapter) adapter_entry;
316 /* PCI register resources */
318 struct resource *regs_res;
320 struct resource *udbs_res;
321 bus_space_handle_t bh;
327 bus_dma_tag_t parent_dmat;
328 bus_dma_tag_t rx_dmat;
329 bus_dma_tag_t rx_jumbo_dmat;
330 bus_dma_tag_t tx_dmat;
332 /* Interrupt resources */
333 struct resource *irq_res;
337 uint32_t msix_regs_rid;
338 struct resource *msix_regs_res;
340 struct resource *msix_irq_res[SGE_QSETS];
341 int msix_irq_rid[SGE_QSETS];
342 void *msix_intr_tag[SGE_QSETS];
343 uint8_t rxpkt_map[8]; /* maps RX_PKT interface values to port ids */
344 uint8_t rrss_map[SGE_QSETS]; /* revers RSS map table */
345 uint16_t rspq_map[RSS_TABLE_SIZE]; /* maps 7-bit cookie to qidx */
347 uint8_t fill[SGE_QSETS];
351 #define tunq_fill u.fill
352 #define tunq_coalesce u.coalesce
354 struct filter_info *filters;
357 struct task ext_intr_task;
358 struct task slow_intr_task;
359 struct task tick_task;
360 struct taskqueue *tq;
361 struct callout cxgb_tick_ch;
362 struct callout sge_timer_ch;
364 unsigned int check_task_cnt;
366 /* Register lock for use by the hardware layer */
367 struct mtx mdio_lock;
368 struct mtx elmer_lock;
370 /* Bookkeeping for the hardware layer */
371 struct adapter_params params;
372 unsigned int slow_intr_mask;
373 unsigned long irq_stats[IRQ_NUM_STATS];
381 struct port_info port[MAX_NPORTS];
382 device_t portdev[MAX_NPORTS];
385 char port_types[MAX_NPORTS + 1];
386 uint32_t open_device_map;
387 uint32_t registered_device_map;
389 driver_intr_t *cxgb_intr;
392 #define ADAPTER_LOCK_NAME_LEN 32
393 char lockbuf[ADAPTER_LOCK_NAME_LEN];
394 char reglockbuf[ADAPTER_LOCK_NAME_LEN];
395 char mdiolockbuf[ADAPTER_LOCK_NAME_LEN];
396 char elmerlockbuf[ADAPTER_LOCK_NAME_LEN];
402 struct port_info *port;
405 #define MDIO_LOCK(adapter) mtx_lock(&(adapter)->mdio_lock)
406 #define MDIO_UNLOCK(adapter) mtx_unlock(&(adapter)->mdio_lock)
407 #define ELMR_LOCK(adapter) mtx_lock(&(adapter)->elmer_lock)
408 #define ELMR_UNLOCK(adapter) mtx_unlock(&(adapter)->elmer_lock)
411 #define PORT_LOCK(port) mtx_lock(&(port)->lock);
412 #define PORT_UNLOCK(port) mtx_unlock(&(port)->lock);
413 #define PORT_LOCK_INIT(port, name) mtx_init(&(port)->lock, name, 0, MTX_DEF)
414 #define PORT_LOCK_DEINIT(port) mtx_destroy(&(port)->lock)
415 #define PORT_LOCK_ASSERT_NOTOWNED(port) mtx_assert(&(port)->lock, MA_NOTOWNED)
416 #define PORT_LOCK_ASSERT_OWNED(port) mtx_assert(&(port)->lock, MA_OWNED)
418 #define ADAPTER_LOCK(adap) mtx_lock(&(adap)->lock);
419 #define ADAPTER_UNLOCK(adap) mtx_unlock(&(adap)->lock);
420 #define ADAPTER_LOCK_INIT(adap, name) mtx_init(&(adap)->lock, name, 0, MTX_DEF)
421 #define ADAPTER_LOCK_DEINIT(adap) mtx_destroy(&(adap)->lock)
422 #define ADAPTER_LOCK_ASSERT_NOTOWNED(adap) mtx_assert(&(adap)->lock, MA_NOTOWNED)
423 #define ADAPTER_LOCK_ASSERT_OWNED(adap) mtx_assert(&(adap)->lock, MA_OWNED)
426 static __inline uint32_t
427 t3_read_reg(adapter_t *adapter, uint32_t reg_addr)
429 return (bus_space_read_4(adapter->bt, adapter->bh, reg_addr));
433 t3_write_reg(adapter_t *adapter, uint32_t reg_addr, uint32_t val)
435 bus_space_write_4(adapter->bt, adapter->bh, reg_addr, val);
439 t3_os_pci_read_config_4(adapter_t *adapter, int reg, uint32_t *val)
441 *val = pci_read_config(adapter->dev, reg, 4);
445 t3_os_pci_write_config_4(adapter_t *adapter, int reg, uint32_t val)
447 pci_write_config(adapter->dev, reg, val, 4);
451 t3_os_pci_read_config_2(adapter_t *adapter, int reg, uint16_t *val)
453 *val = pci_read_config(adapter->dev, reg, 2);
457 t3_os_pci_write_config_2(adapter_t *adapter, int reg, uint16_t val)
459 pci_write_config(adapter->dev, reg, val, 2);
462 static __inline uint8_t *
463 t3_get_next_mcaddr(struct t3_rx_mode *rm)
465 uint8_t *macaddr = NULL;
466 struct ifnet *ifp = rm->port->ifp;
467 struct ifmultiaddr *ifma;
471 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
472 if (ifma->ifma_addr->sa_family != AF_LINK)
475 macaddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
480 if_maddr_runlock(ifp);
487 t3_init_rx_mode(struct t3_rx_mode *rm, struct port_info *port)
493 static __inline struct port_info *
494 adap2pinfo(struct adapter *adap, int idx)
496 return &adap->port[idx];
499 int t3_os_find_pci_capability(adapter_t *adapter, int cap);
500 int t3_os_pci_save_state(struct adapter *adapter);
501 int t3_os_pci_restore_state(struct adapter *adapter);
502 void t3_os_link_changed(adapter_t *adapter, int port_id, int link_status,
503 int speed, int duplex, int fc);
504 void t3_os_phymod_changed(struct adapter *adap, int port_id);
505 void t3_sge_err_intr_handler(adapter_t *adapter);
506 int t3_offload_tx(struct t3cdev *, struct mbuf *);
507 void t3_os_ext_intr_handler(adapter_t *adapter);
508 void t3_os_set_hw_addr(adapter_t *adapter, int port_idx, u8 hw_addr[]);
509 int t3_mgmt_tx(adapter_t *adap, struct mbuf *m);
512 int t3_sge_alloc(struct adapter *);
513 int t3_sge_free(struct adapter *);
514 int t3_sge_alloc_qset(adapter_t *, uint32_t, int, int, const struct qset_params *,
515 int, struct port_info *);
516 void t3_free_sge_resources(adapter_t *);
517 void t3_sge_start(adapter_t *);
518 void t3_sge_stop(adapter_t *);
519 void t3b_intr(void *data);
520 void t3_intr_msi(void *data);
521 void t3_intr_msix(void *data);
523 int t3_sge_init_adapter(adapter_t *);
524 int t3_sge_reset_adapter(adapter_t *);
525 int t3_sge_init_port(struct port_info *);
526 void t3_free_tx_desc(struct sge_qset *qs, int n, int qid);
528 void t3_rx_eth(struct adapter *adap, struct sge_rspq *rq, struct mbuf *m, int ethpad);
530 void t3_add_attach_sysctls(adapter_t *sc);
531 void t3_add_configured_sysctls(adapter_t *sc);
532 int t3_get_desc(const struct sge_qset *qs, unsigned int qnum, unsigned int idx,
533 unsigned char *data);
534 void t3_update_qset_coalesce(struct sge_qset *qs, const struct qset_params *p);
536 #define CXGB_TICKS(a) ((a)->params.linkpoll_period ? \
537 (hz * (a)->params.linkpoll_period) / 10 : \
538 (a)->params.stats_update_period * hz)
541 * XXX figure out how we can return this to being private to sge
543 #define desc_reclaimable(q) ((int)((q)->processed - (q)->cleaned - TX_MAX_DESC))
545 #define container_of(p, stype, field) ((stype *)(((uint8_t *)(p)) - offsetof(stype, field)))
547 static __inline struct sge_qset *
548 fl_to_qset(struct sge_fl *q, int qidx)
550 return container_of(q, struct sge_qset, fl[qidx]);
553 static __inline struct sge_qset *
554 rspq_to_qset(struct sge_rspq *q)
556 return container_of(q, struct sge_qset, rspq);
559 static __inline struct sge_qset *
560 txq_to_qset(struct sge_txq *q, int qidx)
562 return container_of(q, struct sge_qset, txq[qidx]);
565 static __inline struct adapter *
566 tdev2adap(struct t3cdev *d)
568 return container_of(d, struct adapter, tdev);
573 #define OFFLOAD_DEVMAP_BIT 15
574 static inline int offload_running(adapter_t *adapter)
576 return isset(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT);
579 void cxgb_tx_watchdog(void *arg);
580 int cxgb_transmit(struct ifnet *ifp, struct mbuf *m);
581 void cxgb_qflush(struct ifnet *ifp);
582 void cxgb_start(struct ifnet *ifp);