1 /******************************************************************************
3 Copyright (c) 2001-2009, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ******************************************************************************/
36 * 82571EB Gigabit Ethernet Controller
37 * 82571EB Gigabit Ethernet Controller (Copper)
38 * 82571EB Gigabit Ethernet Controller (Fiber)
39 * 82571EB Dual Port Gigabit Mezzanine Adapter
40 * 82571EB Quad Port Gigabit Mezzanine Adapter
41 * 82571PT Gigabit PT Quad Port Server ExpressModule
42 * 82572EI Gigabit Ethernet Controller (Copper)
43 * 82572EI Gigabit Ethernet Controller (Fiber)
44 * 82572EI Gigabit Ethernet Controller
45 * 82573V Gigabit Ethernet Controller (Copper)
46 * 82573E Gigabit Ethernet Controller (Copper)
47 * 82573L Gigabit Ethernet Controller
48 * 82574L Gigabit Network Connection
49 * 82574L Gigabit Network Connection
50 * 82583V Gigabit Network Connection
53 #include "e1000_api.h"
55 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw);
56 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw);
57 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw);
58 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw);
59 static void e1000_release_nvm_82571(struct e1000_hw *hw);
60 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
61 u16 words, u16 *data);
62 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
63 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
64 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw);
65 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
67 static s32 e1000_reset_hw_82571(struct e1000_hw *hw);
68 static s32 e1000_init_hw_82571(struct e1000_hw *hw);
69 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
70 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
71 static s32 e1000_led_on_82574(struct e1000_hw *hw);
72 static s32 e1000_setup_link_82571(struct e1000_hw *hw);
73 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
74 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
75 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
76 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
77 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
78 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
79 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
80 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
81 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
82 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
83 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
84 u16 words, u16 *data);
85 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw);
86 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
89 * e1000_init_phy_params_82571 - Init PHY func ptrs.
90 * @hw: pointer to the HW structure
92 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
94 struct e1000_phy_info *phy = &hw->phy;
95 s32 ret_val = E1000_SUCCESS;
97 DEBUGFUNC("e1000_init_phy_params_82571");
99 if (hw->phy.media_type != e1000_media_type_copper) {
100 phy->type = e1000_phy_none;
105 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
106 phy->reset_delay_us = 100;
108 phy->ops.acquire = e1000_get_hw_semaphore_82571;
109 phy->ops.check_polarity = e1000_check_polarity_igp;
110 phy->ops.check_reset_block = e1000_check_reset_block_generic;
111 phy->ops.release = e1000_put_hw_semaphore_82571;
112 phy->ops.reset = e1000_phy_hw_reset_generic;
113 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571;
114 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
115 phy->ops.power_up = e1000_power_up_phy_copper;
116 phy->ops.power_down = e1000_power_down_phy_copper_82571;
118 switch (hw->mac.type) {
121 phy->type = e1000_phy_igp_2;
122 phy->ops.get_cfg_done = e1000_get_cfg_done_82571;
123 phy->ops.get_info = e1000_get_phy_info_igp;
124 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
125 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
126 phy->ops.read_reg = e1000_read_phy_reg_igp;
127 phy->ops.write_reg = e1000_write_phy_reg_igp;
129 /* This uses above function pointers */
130 ret_val = e1000_get_phy_id_82571(hw);
133 if (phy->id != IGP01E1000_I_PHY_ID) {
134 ret_val = -E1000_ERR_PHY;
139 phy->type = e1000_phy_m88;
140 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
141 phy->ops.get_info = e1000_get_phy_info_m88;
142 phy->ops.commit = e1000_phy_sw_reset_generic;
143 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
144 phy->ops.get_cable_length = e1000_get_cable_length_m88;
145 phy->ops.read_reg = e1000_read_phy_reg_m88;
146 phy->ops.write_reg = e1000_write_phy_reg_m88;
148 /* This uses above function pointers */
149 ret_val = e1000_get_phy_id_82571(hw);
152 if (phy->id != M88E1111_I_PHY_ID) {
153 ret_val = -E1000_ERR_PHY;
154 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
160 phy->type = e1000_phy_bm;
161 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
162 phy->ops.get_info = e1000_get_phy_info_m88;
163 phy->ops.commit = e1000_phy_sw_reset_generic;
164 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
165 phy->ops.get_cable_length = e1000_get_cable_length_m88;
166 phy->ops.read_reg = e1000_read_phy_reg_bm2;
167 phy->ops.write_reg = e1000_write_phy_reg_bm2;
169 /* This uses above function pointers */
170 ret_val = e1000_get_phy_id_82571(hw);
172 if (phy->id != BME1000_E_PHY_ID_R2) {
173 ret_val = -E1000_ERR_PHY;
174 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
179 ret_val = -E1000_ERR_PHY;
189 * e1000_init_nvm_params_82571 - Init NVM func ptrs.
190 * @hw: pointer to the HW structure
192 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
194 struct e1000_nvm_info *nvm = &hw->nvm;
195 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
198 DEBUGFUNC("e1000_init_nvm_params_82571");
200 nvm->opcode_bits = 8;
202 switch (nvm->override) {
203 case e1000_nvm_override_spi_large:
205 nvm->address_bits = 16;
207 case e1000_nvm_override_spi_small:
209 nvm->address_bits = 8;
212 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
213 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
217 switch (hw->mac.type) {
221 if (((eecd >> 15) & 0x3) == 0x3) {
222 nvm->type = e1000_nvm_flash_hw;
223 nvm->word_size = 2048;
225 * Autonomous Flash update bit must be cleared due
226 * to Flash update issue.
228 eecd &= ~E1000_EECD_AUPDEN;
229 E1000_WRITE_REG(hw, E1000_EECD, eecd);
234 nvm->type = e1000_nvm_eeprom_spi;
235 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
236 E1000_EECD_SIZE_EX_SHIFT);
238 * Added to a constant, "size" becomes the left-shift value
239 * for setting word_size.
241 size += NVM_WORD_SIZE_BASE_SHIFT;
243 /* EEPROM access above 16k is unsupported */
246 nvm->word_size = 1 << size;
250 /* Function Pointers */
251 nvm->ops.acquire = e1000_acquire_nvm_82571;
252 nvm->ops.read = e1000_read_nvm_eerd;
253 nvm->ops.release = e1000_release_nvm_82571;
254 nvm->ops.update = e1000_update_nvm_checksum_82571;
255 nvm->ops.validate = e1000_validate_nvm_checksum_82571;
256 nvm->ops.valid_led_default = e1000_valid_led_default_82571;
257 nvm->ops.write = e1000_write_nvm_82571;
259 return E1000_SUCCESS;
263 * e1000_init_mac_params_82571 - Init MAC func ptrs.
264 * @hw: pointer to the HW structure
266 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
268 struct e1000_mac_info *mac = &hw->mac;
269 s32 ret_val = E1000_SUCCESS;
272 bool force_clear_smbi = FALSE;
274 DEBUGFUNC("e1000_init_mac_params_82571");
277 switch (hw->device_id) {
278 case E1000_DEV_ID_82571EB_FIBER:
279 case E1000_DEV_ID_82572EI_FIBER:
280 case E1000_DEV_ID_82571EB_QUAD_FIBER:
281 hw->phy.media_type = e1000_media_type_fiber;
283 case E1000_DEV_ID_82571EB_SERDES:
284 case E1000_DEV_ID_82571EB_SERDES_DUAL:
285 case E1000_DEV_ID_82571EB_SERDES_QUAD:
286 case E1000_DEV_ID_82572EI_SERDES:
287 hw->phy.media_type = e1000_media_type_internal_serdes;
290 hw->phy.media_type = e1000_media_type_copper;
294 /* Set mta register count */
295 mac->mta_reg_count = 128;
296 /* Set rar entry count */
297 mac->rar_entry_count = E1000_RAR_ENTRIES;
298 /* Set if part includes ASF firmware */
299 mac->asf_firmware_present = TRUE;
300 /* Set if manageability features are enabled. */
301 mac->arc_subsystem_valid =
302 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
305 /* Function pointers */
307 /* bus type/speed/width */
308 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
310 switch (hw->mac.type) {
314 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
320 mac->ops.reset_hw = e1000_reset_hw_82571;
321 /* hw initialization */
322 mac->ops.init_hw = e1000_init_hw_82571;
324 mac->ops.setup_link = e1000_setup_link_82571;
325 /* physical interface link setup */
326 mac->ops.setup_physical_interface =
327 (hw->phy.media_type == e1000_media_type_copper)
328 ? e1000_setup_copper_link_82571
329 : e1000_setup_fiber_serdes_link_82571;
331 switch (hw->phy.media_type) {
332 case e1000_media_type_copper:
333 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
335 case e1000_media_type_fiber:
336 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
338 case e1000_media_type_internal_serdes:
339 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
342 ret_val = -E1000_ERR_CONFIG;
346 /* check management mode */
347 switch (hw->mac.type) {
350 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
353 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
356 /* multicast address update */
357 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
359 mac->ops.write_vfta = e1000_write_vfta_generic;
361 mac->ops.clear_vfta = e1000_clear_vfta_82571;
363 mac->ops.mta_set = e1000_mta_set_generic;
364 /* read mac address */
365 mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
367 mac->ops.id_led_init = e1000_id_led_init_generic;
369 mac->ops.blink_led = e1000_blink_led_generic;
371 mac->ops.setup_led = e1000_setup_led_generic;
373 mac->ops.cleanup_led = e1000_cleanup_led_generic;
374 /* turn on/off LED */
375 switch (hw->mac.type) {
378 mac->ops.led_on = e1000_led_on_82574;
381 mac->ops.led_on = e1000_led_on_generic;
384 mac->ops.led_off = e1000_led_off_generic;
385 /* clear hardware counters */
386 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
388 mac->ops.get_link_up_info =
389 (hw->phy.media_type == e1000_media_type_copper)
390 ? e1000_get_speed_and_duplex_copper_generic
391 : e1000_get_speed_and_duplex_fiber_serdes_generic;
394 * Ensure that the inter-port SWSM.SMBI lock bit is clear before
395 * first NVM or PHY acess. This should be done for single-port
396 * devices, and for one port only on dual-port devices so that
397 * for those devices we can still use the SMBI lock to synchronize
398 * inter-port accesses to the PHY & NVM.
400 switch (hw->mac.type) {
403 swsm2 = E1000_READ_REG(hw, E1000_SWSM2);
405 if (!(swsm2 & E1000_SWSM2_LOCK)) {
406 /* Only do this for the first interface on this card */
407 E1000_WRITE_REG(hw, E1000_SWSM2,
408 swsm2 | E1000_SWSM2_LOCK);
409 force_clear_smbi = TRUE;
411 force_clear_smbi = FALSE;
414 force_clear_smbi = TRUE;
418 if (force_clear_smbi) {
419 /* Make sure SWSM.SMBI is clear */
420 swsm = E1000_READ_REG(hw, E1000_SWSM);
421 if (swsm & E1000_SWSM_SMBI) {
422 /* This bit should not be set on a first interface, and
423 * indicates that the bootagent or EFI code has
424 * improperly left this bit enabled
426 DEBUGOUT("Please update your 82571 Bootagent\n");
428 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI);
432 * Initialze device specific counter of SMBI acquisition
435 hw->dev_spec._82571.smb_counter = 0;
442 * e1000_init_function_pointers_82571 - Init func ptrs.
443 * @hw: pointer to the HW structure
445 * Called to initialize all function pointers and parameters.
447 void e1000_init_function_pointers_82571(struct e1000_hw *hw)
449 DEBUGFUNC("e1000_init_function_pointers_82571");
451 hw->mac.ops.init_params = e1000_init_mac_params_82571;
452 hw->nvm.ops.init_params = e1000_init_nvm_params_82571;
453 hw->phy.ops.init_params = e1000_init_phy_params_82571;
457 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
458 * @hw: pointer to the HW structure
460 * Reads the PHY registers and stores the PHY ID and possibly the PHY
461 * revision in the hardware structure.
463 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
465 struct e1000_phy_info *phy = &hw->phy;
466 s32 ret_val = E1000_SUCCESS;
469 DEBUGFUNC("e1000_get_phy_id_82571");
471 switch (hw->mac.type) {
475 * The 82571 firmware may still be configuring the PHY.
476 * In this case, we cannot access the PHY until the
477 * configuration is done. So we explicitly set the
480 phy->id = IGP01E1000_I_PHY_ID;
483 ret_val = e1000_get_phy_id(hw);
487 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
491 phy->id = (u32)(phy_id << 16);
493 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
497 phy->id |= (u32)(phy_id);
498 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
501 ret_val = -E1000_ERR_PHY;
510 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
511 * @hw: pointer to the HW structure
513 * Acquire the HW semaphore to access the PHY or NVM
515 s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
518 s32 ret_val = E1000_SUCCESS;
519 s32 sw_timeout = hw->nvm.word_size + 1;
520 s32 fw_timeout = hw->nvm.word_size + 1;
523 DEBUGFUNC("e1000_get_hw_semaphore_82571");
526 * If we have timedout 3 times on trying to acquire
527 * the inter-port SMBI semaphore, there is old code
528 * operating on the other port, and it is not
529 * releasing SMBI. Modify the number of times that
530 * we try for the semaphore to interwork with this
533 if (hw->dev_spec._82571.smb_counter > 2)
536 /* Get the SW semaphore */
537 while (i < sw_timeout) {
538 swsm = E1000_READ_REG(hw, E1000_SWSM);
539 if (!(swsm & E1000_SWSM_SMBI))
546 if (i == sw_timeout) {
547 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
548 hw->dev_spec._82571.smb_counter++;
550 /* Get the FW semaphore. */
551 for (i = 0; i < fw_timeout; i++) {
552 swsm = E1000_READ_REG(hw, E1000_SWSM);
553 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
555 /* Semaphore acquired if bit latched */
556 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
562 if (i == fw_timeout) {
563 /* Release semaphores */
564 e1000_put_hw_semaphore_82571(hw);
565 DEBUGOUT("Driver can't access the NVM\n");
566 ret_val = -E1000_ERR_NVM;
575 * e1000_put_hw_semaphore_82571 - Release hardware semaphore
576 * @hw: pointer to the HW structure
578 * Release hardware semaphore used to access the PHY or NVM
580 void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
584 DEBUGFUNC("e1000_put_hw_semaphore_generic");
586 swsm = E1000_READ_REG(hw, E1000_SWSM);
588 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
590 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
594 * e1000_acquire_nvm_82571 - Request for access to the EEPROM
595 * @hw: pointer to the HW structure
597 * To gain access to the EEPROM, first we must obtain a hardware semaphore.
598 * Then for non-82573 hardware, set the EEPROM access request bit and wait
599 * for EEPROM access grant bit. If the access grant bit is not set, release
600 * hardware semaphore.
602 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
606 DEBUGFUNC("e1000_acquire_nvm_82571");
608 ret_val = e1000_get_hw_semaphore_82571(hw);
612 switch (hw->mac.type) {
618 ret_val = e1000_acquire_nvm_generic(hw);
623 e1000_put_hw_semaphore_82571(hw);
630 * e1000_release_nvm_82571 - Release exclusive access to EEPROM
631 * @hw: pointer to the HW structure
633 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
635 static void e1000_release_nvm_82571(struct e1000_hw *hw)
637 DEBUGFUNC("e1000_release_nvm_82571");
639 e1000_release_nvm_generic(hw);
640 e1000_put_hw_semaphore_82571(hw);
644 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
645 * @hw: pointer to the HW structure
646 * @offset: offset within the EEPROM to be written to
647 * @words: number of words to write
648 * @data: 16 bit word(s) to be written to the EEPROM
650 * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
652 * If e1000_update_nvm_checksum is not called after this function, the
653 * EEPROM will most likely contain an invalid checksum.
655 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
658 s32 ret_val = E1000_SUCCESS;
660 DEBUGFUNC("e1000_write_nvm_82571");
662 switch (hw->mac.type) {
666 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
670 ret_val = e1000_write_nvm_spi(hw, offset, words, data);
673 ret_val = -E1000_ERR_NVM;
681 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum
682 * @hw: pointer to the HW structure
684 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
685 * up to the checksum. Then calculates the EEPROM checksum and writes the
686 * value to the EEPROM.
688 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
694 DEBUGFUNC("e1000_update_nvm_checksum_82571");
696 ret_val = e1000_update_nvm_checksum_generic(hw);
701 * If our nvm is an EEPROM, then we're done
702 * otherwise, commit the checksum to the flash NVM.
704 if (hw->nvm.type != e1000_nvm_flash_hw)
707 /* Check for pending operations. */
708 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
710 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0)
714 if (i == E1000_FLASH_UPDATES) {
715 ret_val = -E1000_ERR_NVM;
719 /* Reset the firmware if using STM opcode. */
720 if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) {
722 * The enabling of and the actual reset must be done
723 * in two write cycles.
725 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE);
726 E1000_WRITE_FLUSH(hw);
727 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET);
730 /* Commit the write to flash */
731 eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD;
732 E1000_WRITE_REG(hw, E1000_EECD, eecd);
734 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
736 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0)
740 if (i == E1000_FLASH_UPDATES) {
741 ret_val = -E1000_ERR_NVM;
750 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
751 * @hw: pointer to the HW structure
753 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
754 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
756 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
758 DEBUGFUNC("e1000_validate_nvm_checksum_82571");
760 if (hw->nvm.type == e1000_nvm_flash_hw)
761 e1000_fix_nvm_checksum_82571(hw);
763 return e1000_validate_nvm_checksum_generic(hw);
767 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
768 * @hw: pointer to the HW structure
769 * @offset: offset within the EEPROM to be written to
770 * @words: number of words to write
771 * @data: 16 bit word(s) to be written to the EEPROM
773 * After checking for invalid values, poll the EEPROM to ensure the previous
774 * command has completed before trying to write the next word. After write
775 * poll for completion.
777 * If e1000_update_nvm_checksum is not called after this function, the
778 * EEPROM will most likely contain an invalid checksum.
780 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
781 u16 words, u16 *data)
783 struct e1000_nvm_info *nvm = &hw->nvm;
787 DEBUGFUNC("e1000_write_nvm_eewr_82571");
790 * A check for invalid values: offset too large, too many words,
791 * and not enough words.
793 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
795 DEBUGOUT("nvm parameter(s) out of bounds\n");
796 ret_val = -E1000_ERR_NVM;
800 for (i = 0; i < words; i++) {
801 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
802 ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
803 E1000_NVM_RW_REG_START;
805 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
809 E1000_WRITE_REG(hw, E1000_EEWR, eewr);
811 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
821 * e1000_get_cfg_done_82571 - Poll for configuration done
822 * @hw: pointer to the HW structure
824 * Reads the management control register for the config done bit to be set.
826 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
828 s32 timeout = PHY_CFG_TIMEOUT;
829 s32 ret_val = E1000_SUCCESS;
831 DEBUGFUNC("e1000_get_cfg_done_82571");
834 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0)
840 DEBUGOUT("MNG configuration cycle has not completed.\n");
841 ret_val = -E1000_ERR_RESET;
850 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
851 * @hw: pointer to the HW structure
852 * @active: TRUE to enable LPLU, FALSE to disable
854 * Sets the LPLU D0 state according to the active flag. When activating LPLU
855 * this function also disables smart speed and vice versa. LPLU will not be
856 * activated unless the device autonegotiation advertisement meets standards
857 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function
858 * pointer entry point only called by PHY setup routines.
860 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
862 struct e1000_phy_info *phy = &hw->phy;
863 s32 ret_val = E1000_SUCCESS;
866 DEBUGFUNC("e1000_set_d0_lplu_state_82571");
868 if (!(phy->ops.read_reg))
871 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
876 data |= IGP02E1000_PM_D0_LPLU;
877 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
882 /* When LPLU is enabled, we should disable SmartSpeed */
883 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
885 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
886 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
891 data &= ~IGP02E1000_PM_D0_LPLU;
892 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
895 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
896 * during Dx states where the power conservation is most
897 * important. During driver activity we should enable
898 * SmartSpeed, so performance is maintained.
900 if (phy->smart_speed == e1000_smart_speed_on) {
901 ret_val = phy->ops.read_reg(hw,
902 IGP01E1000_PHY_PORT_CONFIG,
907 data |= IGP01E1000_PSCFR_SMART_SPEED;
908 ret_val = phy->ops.write_reg(hw,
909 IGP01E1000_PHY_PORT_CONFIG,
913 } else if (phy->smart_speed == e1000_smart_speed_off) {
914 ret_val = phy->ops.read_reg(hw,
915 IGP01E1000_PHY_PORT_CONFIG,
920 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
921 ret_val = phy->ops.write_reg(hw,
922 IGP01E1000_PHY_PORT_CONFIG,
934 * e1000_reset_hw_82571 - Reset hardware
935 * @hw: pointer to the HW structure
937 * This resets the hardware into a known state.
939 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
941 u32 ctrl, extcnf_ctrl, ctrl_ext, icr;
945 DEBUGFUNC("e1000_reset_hw_82571");
948 * Prevent the PCI-E bus from sticking if there is no TLP connection
949 * on the last TLP read/write transaction when MAC is reset.
951 ret_val = e1000_disable_pcie_master_generic(hw);
953 DEBUGOUT("PCI-E Master disable polling has failed.\n");
955 DEBUGOUT("Masking off all interrupts\n");
956 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
958 E1000_WRITE_REG(hw, E1000_RCTL, 0);
959 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
960 E1000_WRITE_FLUSH(hw);
965 * Must acquire the MDIO ownership before MAC reset.
966 * Ownership defaults to firmware after a reset.
968 switch (hw->mac.type) {
972 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
973 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
976 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
977 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
979 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
982 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
986 } while (i < MDIO_OWNERSHIP_TIMEOUT);
992 ctrl = E1000_READ_REG(hw, E1000_CTRL);
994 DEBUGOUT("Issuing a global reset to MAC\n");
995 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
997 if (hw->nvm.type == e1000_nvm_flash_hw) {
999 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1000 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1001 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1002 E1000_WRITE_FLUSH(hw);
1005 ret_val = e1000_get_auto_rd_done_generic(hw);
1007 /* We don't want to continue accessing MAC registers. */
1011 * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1012 * Need to wait for Phy configuration completion before accessing
1016 switch (hw->mac.type) {
1026 /* Clear any pending interrupt events. */
1027 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1028 icr = E1000_READ_REG(hw, E1000_ICR);
1030 /* Install any alternate MAC address into RAR0 */
1031 ret_val = e1000_check_alt_mac_addr_generic(hw);
1035 e1000_set_laa_state_82571(hw, TRUE);
1037 /* Reinitialize the 82571 serdes link state machine */
1038 if (hw->phy.media_type == e1000_media_type_internal_serdes)
1039 hw->mac.serdes_link_state = e1000_serdes_link_down;
1046 * e1000_init_hw_82571 - Initialize hardware
1047 * @hw: pointer to the HW structure
1049 * This inits the hardware readying it for operation.
1051 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1053 struct e1000_mac_info *mac = &hw->mac;
1056 u16 i, rar_count = mac->rar_entry_count;
1058 DEBUGFUNC("e1000_init_hw_82571");
1060 e1000_initialize_hw_bits_82571(hw);
1062 /* Initialize identification LED */
1063 ret_val = mac->ops.id_led_init(hw);
1065 DEBUGOUT("Error initializing identification LED\n");
1066 /* This is not fatal and we should not stop init due to this */
1069 /* Disabling VLAN filtering */
1070 DEBUGOUT("Initializing the IEEE VLAN\n");
1071 mac->ops.clear_vfta(hw);
1073 /* Setup the receive address. */
1075 * If, however, a locally administered address was assigned to the
1076 * 82571, we must reserve a RAR for it to work around an issue where
1077 * resetting one port will reload the MAC on the other port.
1079 if (e1000_get_laa_state_82571(hw))
1081 e1000_init_rx_addrs_generic(hw, rar_count);
1083 /* Zero out the Multicast HASH table */
1084 DEBUGOUT("Zeroing the MTA\n");
1085 for (i = 0; i < mac->mta_reg_count; i++)
1086 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1088 /* Setup link and flow control */
1089 ret_val = mac->ops.setup_link(hw);
1091 /* Set the transmit descriptor write-back policy */
1092 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
1093 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1094 E1000_TXDCTL_FULL_TX_DESC_WB |
1095 E1000_TXDCTL_COUNT_DESC;
1096 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
1098 /* ...for both queues. */
1099 switch (mac->type) {
1103 e1000_enable_tx_pkt_filtering_generic(hw);
1104 reg_data = E1000_READ_REG(hw, E1000_GCR);
1105 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1106 E1000_WRITE_REG(hw, E1000_GCR, reg_data);
1109 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
1110 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1111 E1000_TXDCTL_FULL_TX_DESC_WB |
1112 E1000_TXDCTL_COUNT_DESC;
1113 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
1118 * Clear all of the statistics registers (clear on read). It is
1119 * important that we do this after we have tried to establish link
1120 * because the symbol error count will increment wildly if there
1123 e1000_clear_hw_cntrs_82571(hw);
1129 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1130 * @hw: pointer to the HW structure
1132 * Initializes required hardware-dependent bits needed for normal operation.
1134 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1138 DEBUGFUNC("e1000_initialize_hw_bits_82571");
1140 /* Transmit Descriptor Control 0 */
1141 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1143 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1145 /* Transmit Descriptor Control 1 */
1146 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1148 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1150 /* Transmit Arbitration Control 0 */
1151 reg = E1000_READ_REG(hw, E1000_TARC(0));
1152 reg &= ~(0xF << 27); /* 30:27 */
1153 switch (hw->mac.type) {
1156 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1161 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1163 /* Transmit Arbitration Control 1 */
1164 reg = E1000_READ_REG(hw, E1000_TARC(1));
1165 switch (hw->mac.type) {
1168 reg &= ~((1 << 29) | (1 << 30));
1169 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1170 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1174 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1180 /* Device Control */
1182 switch (hw->mac.type) {
1186 reg = E1000_READ_REG(hw, E1000_CTRL);
1188 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1194 /* Extended Device Control */
1195 switch (hw->mac.type) {
1199 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1202 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1209 if (hw->mac.type == e1000_82571) {
1210 reg = E1000_READ_REG(hw, E1000_PBA_ECC);
1211 reg |= E1000_PBA_ECC_CORR_EN;
1212 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);
1216 * Workaround for hardware errata.
1217 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1220 if ((hw->mac.type == e1000_82571) ||
1221 (hw->mac.type == e1000_82572)) {
1222 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1223 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1224 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1227 /* PCI-Ex Control Registers */
1229 switch (hw->mac.type) {
1232 reg = E1000_READ_REG(hw, E1000_GCR);
1234 E1000_WRITE_REG(hw, E1000_GCR, reg);
1236 * Workaround for hardware errata.
1237 * apply workaround for hardware errata documented in errata
1238 * docs Fixes issue where some error prone or unreliable PCIe
1239 * completions are occurring, particularly with ASPM enabled.
1240 * Without fix, issue can cause tx timeouts.
1242 reg = E1000_READ_REG(hw, E1000_GCR2);
1244 E1000_WRITE_REG(hw, E1000_GCR2, reg);
1254 * e1000_clear_vfta_82571 - Clear VLAN filter table
1255 * @hw: pointer to the HW structure
1257 * Clears the register array which contains the VLAN filter table by
1258 * setting all the values to 0.
1260 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1264 u32 vfta_offset = 0;
1265 u32 vfta_bit_in_reg = 0;
1267 DEBUGFUNC("e1000_clear_vfta_82571");
1269 switch (hw->mac.type) {
1273 if (hw->mng_cookie.vlan_id != 0) {
1275 *The VFTA is a 4096b bit-field, each identifying
1276 *a single VLAN ID. The following operations
1277 *determine which 32b entry (i.e. offset) into the
1278 *array we want to set the VLAN ID (i.e. bit) of
1279 *the manageability unit.
1281 vfta_offset = (hw->mng_cookie.vlan_id >>
1282 E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK;
1283 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
1284 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1287 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1289 *If the offset we want to clear is the same offset of
1290 *the manageability VLAN ID, then clear all bits except
1291 *that of the manageability unit
1293 vfta_value = (offset == vfta_offset) ?
1294 vfta_bit_in_reg : 0;
1295 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset,
1297 E1000_WRITE_FLUSH(hw);
1306 * e1000_check_mng_mode_82574 - Check manageability is enabled
1307 * @hw: pointer to the HW structure
1309 * Reads the NVM Initialization Control Word 2 and returns TRUE
1310 * (>0) if any manageability is enabled, else FALSE (0).
1312 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1316 DEBUGFUNC("e1000_check_mng_mode_82574");
1318 hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1319 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1323 * e1000_led_on_82574 - Turn LED on
1324 * @hw: pointer to the HW structure
1328 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1333 DEBUGFUNC("e1000_led_on_82574");
1335 ctrl = hw->mac.ledctl_mode2;
1336 if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) {
1338 * If no link, then turn LED on by setting the invert bit
1339 * for each LED that's "on" (0x0E) in ledctl_mode2.
1341 for (i = 0; i < 4; i++)
1342 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1343 E1000_LEDCTL_MODE_LED_ON)
1344 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1346 E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl);
1348 return E1000_SUCCESS;
1353 * e1000_setup_link_82571 - Setup flow control and link settings
1354 * @hw: pointer to the HW structure
1356 * Determines which flow control settings to use, then configures flow
1357 * control. Calls the appropriate media-specific link configuration
1358 * function. Assuming the adapter has a valid link partner, a valid link
1359 * should be established. Assumes the hardware has previously been reset
1360 * and the transmitter and receiver are not enabled.
1362 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1364 DEBUGFUNC("e1000_setup_link_82571");
1367 * 82573 does not have a word in the NVM to determine
1368 * the default flow control setting, so we explicitly
1371 switch (hw->mac.type) {
1375 if (hw->fc.requested_mode == e1000_fc_default)
1376 hw->fc.requested_mode = e1000_fc_full;
1381 return e1000_setup_link_generic(hw);
1385 * e1000_setup_copper_link_82571 - Configure copper link settings
1386 * @hw: pointer to the HW structure
1388 * Configures the link for auto-neg or forced speed and duplex. Then we check
1389 * for link, once link is established calls to configure collision distance
1390 * and flow control are called.
1392 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1397 DEBUGFUNC("e1000_setup_copper_link_82571");
1399 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1400 ctrl |= E1000_CTRL_SLU;
1401 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1402 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1404 switch (hw->phy.type) {
1407 ret_val = e1000_copper_link_setup_m88(hw);
1409 case e1000_phy_igp_2:
1410 ret_val = e1000_copper_link_setup_igp(hw);
1413 ret_val = -E1000_ERR_PHY;
1420 ret_val = e1000_setup_copper_link_generic(hw);
1427 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1428 * @hw: pointer to the HW structure
1430 * Configures collision distance and flow control for fiber and serdes links.
1431 * Upon successful setup, poll for link.
1433 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1435 DEBUGFUNC("e1000_setup_fiber_serdes_link_82571");
1437 switch (hw->mac.type) {
1441 * If SerDes loopback mode is entered, there is no form
1442 * of reset to take the adapter out of that mode. So we
1443 * have to explicitly take the adapter out of loopback
1444 * mode. This prevents drivers from twiddling their thumbs
1445 * if another tool failed to take it out of loopback mode.
1447 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1453 return e1000_setup_fiber_serdes_link_generic(hw);
1457 * e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1458 * @hw: pointer to the HW structure
1460 * Reports the link state as up or down.
1462 * If autonegotiation is supported by the link partner, the link state is
1463 * determined by the result of autongotiation. This is the most likely case.
1464 * If autonegotiation is not supported by the link partner, and the link
1465 * has a valid signal, force the link up.
1467 * The link state is represented internally here by 4 states:
1470 * 2) autoneg_progress
1471 * 3) autoneg_complete (the link sucessfully autonegotiated)
1472 * 4) forced_up (the link has been forced up, it did not autonegotiate)
1475 s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1477 struct e1000_mac_info *mac = &hw->mac;
1481 s32 ret_val = E1000_SUCCESS;
1483 DEBUGFUNC("e1000_check_for_serdes_link_82571");
1485 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1486 status = E1000_READ_REG(hw, E1000_STATUS);
1487 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1489 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1491 /* Receiver is synchronized with no invalid bits. */
1492 switch (mac->serdes_link_state) {
1493 case e1000_serdes_link_autoneg_complete:
1494 if (!(status & E1000_STATUS_LU)) {
1496 * We have lost link, retry autoneg before
1497 * reporting link failure
1499 mac->serdes_link_state =
1500 e1000_serdes_link_autoneg_progress;
1501 mac->serdes_has_link = FALSE;
1502 DEBUGOUT("AN_UP -> AN_PROG\n");
1506 case e1000_serdes_link_forced_up:
1508 * If we are receiving /C/ ordered sets, re-enable
1509 * auto-negotiation in the TXCW register and disable
1510 * forced link in the Device Control register in an
1511 * attempt to auto-negotiate with our link partner.
1513 if (rxcw & E1000_RXCW_C) {
1514 /* Enable autoneg, and unforce link up */
1515 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1516 E1000_WRITE_REG(hw, E1000_CTRL,
1517 (ctrl & ~E1000_CTRL_SLU));
1518 mac->serdes_link_state =
1519 e1000_serdes_link_autoneg_progress;
1520 mac->serdes_has_link = FALSE;
1521 DEBUGOUT("FORCED_UP -> AN_PROG\n");
1525 case e1000_serdes_link_autoneg_progress:
1526 if (rxcw & E1000_RXCW_C) {
1527 /* We received /C/ ordered sets, meaning the
1528 * link partner has autonegotiated, and we can
1529 * trust the Link Up (LU) status bit
1531 if (status & E1000_STATUS_LU) {
1532 mac->serdes_link_state =
1533 e1000_serdes_link_autoneg_complete;
1534 DEBUGOUT("AN_PROG -> AN_UP\n");
1535 mac->serdes_has_link = TRUE;
1537 /* Autoneg completed, but failed */
1538 mac->serdes_link_state =
1539 e1000_serdes_link_down;
1540 DEBUGOUT("AN_PROG -> DOWN\n");
1543 /* The link partner did not autoneg.
1544 * Force link up and full duplex, and change
1547 E1000_WRITE_REG(hw, E1000_TXCW,
1548 (mac->txcw & ~E1000_TXCW_ANE));
1549 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1550 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1552 /* Configure Flow Control after link up. */
1554 e1000_config_fc_after_link_up_generic(hw);
1556 DEBUGOUT("Error config flow control\n");
1559 mac->serdes_link_state =
1560 e1000_serdes_link_forced_up;
1561 mac->serdes_has_link = TRUE;
1562 DEBUGOUT("AN_PROG -> FORCED_UP\n");
1566 case e1000_serdes_link_down:
1568 /* The link was down but the receiver has now gained
1569 * valid sync, so lets see if we can bring the link
1571 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1572 E1000_WRITE_REG(hw, E1000_CTRL,
1573 (ctrl & ~E1000_CTRL_SLU));
1574 mac->serdes_link_state =
1575 e1000_serdes_link_autoneg_progress;
1576 DEBUGOUT("DOWN -> AN_PROG\n");
1580 if (!(rxcw & E1000_RXCW_SYNCH)) {
1581 mac->serdes_has_link = FALSE;
1582 mac->serdes_link_state = e1000_serdes_link_down;
1583 DEBUGOUT("ANYSTATE -> DOWN\n");
1586 * We have sync, and can tolerate one
1587 * invalid (IV) codeword before declaring
1588 * link down, so reread to look again
1591 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1592 if (rxcw & E1000_RXCW_IV) {
1593 mac->serdes_link_state = e1000_serdes_link_down;
1594 mac->serdes_has_link = FALSE;
1595 DEBUGOUT("ANYSTATE -> DOWN\n");
1604 * e1000_valid_led_default_82571 - Verify a valid default LED config
1605 * @hw: pointer to the HW structure
1606 * @data: pointer to the NVM (EEPROM)
1608 * Read the EEPROM for the current default LED configuration. If the
1609 * LED configuration is not valid, set to a valid LED configuration.
1611 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1615 DEBUGFUNC("e1000_valid_led_default_82571");
1617 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1619 DEBUGOUT("NVM Read Error\n");
1623 switch (hw->mac.type) {
1627 if(*data == ID_LED_RESERVED_F746)
1628 *data = ID_LED_DEFAULT_82573;
1631 if (*data == ID_LED_RESERVED_0000 ||
1632 *data == ID_LED_RESERVED_FFFF)
1633 *data = ID_LED_DEFAULT;
1642 * e1000_get_laa_state_82571 - Get locally administered address state
1643 * @hw: pointer to the HW structure
1645 * Retrieve and return the current locally administered address state.
1647 bool e1000_get_laa_state_82571(struct e1000_hw *hw)
1649 DEBUGFUNC("e1000_get_laa_state_82571");
1651 if (hw->mac.type != e1000_82571)
1654 return hw->dev_spec._82571.laa_is_present;
1658 * e1000_set_laa_state_82571 - Set locally administered address state
1659 * @hw: pointer to the HW structure
1660 * @state: enable/disable locally administered address
1662 * Enable/Disable the current locally administered address state.
1664 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state)
1666 DEBUGFUNC("e1000_set_laa_state_82571");
1668 if (hw->mac.type != e1000_82571)
1671 hw->dev_spec._82571.laa_is_present = state;
1673 /* If workaround is activated... */
1676 * Hold a copy of the LAA in RAR[14] This is done so that
1677 * between the time RAR[0] gets clobbered and the time it
1678 * gets fixed, the actual LAA is in one of the RARs and no
1679 * incoming packets directed to this port are dropped.
1680 * Eventually the LAA will be in RAR[0] and RAR[14].
1682 e1000_rar_set_generic(hw, hw->mac.addr,
1683 hw->mac.rar_entry_count - 1);
1688 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1689 * @hw: pointer to the HW structure
1691 * Verifies that the EEPROM has completed the update. After updating the
1692 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If
1693 * the checksum fix is not implemented, we need to set the bit and update
1694 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
1695 * we need to return bad checksum.
1697 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1699 struct e1000_nvm_info *nvm = &hw->nvm;
1700 s32 ret_val = E1000_SUCCESS;
1703 DEBUGFUNC("e1000_fix_nvm_checksum_82571");
1705 if (nvm->type != e1000_nvm_flash_hw)
1709 * Check bit 4 of word 10h. If it is 0, firmware is done updating
1710 * 10h-12h. Checksum may need to be fixed.
1712 ret_val = nvm->ops.read(hw, 0x10, 1, &data);
1716 if (!(data & 0x10)) {
1718 * Read 0x23 and check bit 15. This bit is a 1
1719 * when the checksum has already been fixed. If
1720 * the checksum is still wrong and this bit is a
1721 * 1, we need to return bad checksum. Otherwise,
1722 * we need to set this bit to a 1 and update the
1725 ret_val = nvm->ops.read(hw, 0x23, 1, &data);
1729 if (!(data & 0x8000)) {
1731 ret_val = nvm->ops.write(hw, 0x23, 1, &data);
1734 ret_val = nvm->ops.update(hw);
1744 * e1000_read_mac_addr_82571 - Read device MAC address
1745 * @hw: pointer to the HW structure
1747 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1749 s32 ret_val = E1000_SUCCESS;
1751 DEBUGFUNC("e1000_read_mac_addr_82571");
1754 * If there's an alternate MAC address place it in RAR0
1755 * so that it will override the Si installed default perm
1758 ret_val = e1000_check_alt_mac_addr_generic(hw);
1762 ret_val = e1000_read_mac_addr_generic(hw);
1769 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1770 * @hw: pointer to the HW structure
1772 * In the case of a PHY power down to save power, or to turn off link during a
1773 * driver unload, or wake on lan is not enabled, remove the link.
1775 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1777 struct e1000_phy_info *phy = &hw->phy;
1778 struct e1000_mac_info *mac = &hw->mac;
1780 if (!(phy->ops.check_reset_block))
1783 /* If the management interface is not enabled, then power down */
1784 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1785 e1000_power_down_phy_copper(hw);
1791 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1792 * @hw: pointer to the HW structure
1794 * Clears the hardware counters by reading the counter registers.
1796 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1798 DEBUGFUNC("e1000_clear_hw_cntrs_82571");
1800 e1000_clear_hw_cntrs_base_generic(hw);
1802 E1000_READ_REG(hw, E1000_PRC64);
1803 E1000_READ_REG(hw, E1000_PRC127);
1804 E1000_READ_REG(hw, E1000_PRC255);
1805 E1000_READ_REG(hw, E1000_PRC511);
1806 E1000_READ_REG(hw, E1000_PRC1023);
1807 E1000_READ_REG(hw, E1000_PRC1522);
1808 E1000_READ_REG(hw, E1000_PTC64);
1809 E1000_READ_REG(hw, E1000_PTC127);
1810 E1000_READ_REG(hw, E1000_PTC255);
1811 E1000_READ_REG(hw, E1000_PTC511);
1812 E1000_READ_REG(hw, E1000_PTC1023);
1813 E1000_READ_REG(hw, E1000_PTC1522);
1815 E1000_READ_REG(hw, E1000_ALGNERRC);
1816 E1000_READ_REG(hw, E1000_RXERRC);
1817 E1000_READ_REG(hw, E1000_TNCRS);
1818 E1000_READ_REG(hw, E1000_CEXTERR);
1819 E1000_READ_REG(hw, E1000_TSCTC);
1820 E1000_READ_REG(hw, E1000_TSCTFC);
1822 E1000_READ_REG(hw, E1000_MGTPRC);
1823 E1000_READ_REG(hw, E1000_MGTPDC);
1824 E1000_READ_REG(hw, E1000_MGTPTC);
1826 E1000_READ_REG(hw, E1000_IAC);
1827 E1000_READ_REG(hw, E1000_ICRXOC);
1829 E1000_READ_REG(hw, E1000_ICRXPTC);
1830 E1000_READ_REG(hw, E1000_ICRXATC);
1831 E1000_READ_REG(hw, E1000_ICTXPTC);
1832 E1000_READ_REG(hw, E1000_ICTXATC);
1833 E1000_READ_REG(hw, E1000_ICTXQEC);
1834 E1000_READ_REG(hw, E1000_ICTXQMTC);
1835 E1000_READ_REG(hw, E1000_ICRXDMTC);