1 /******************************************************************************
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32 ******************************************************************************/
36 * 82575EB Gigabit Network Connection
37 * 82575EB Gigabit Backplane Connection
38 * 82575GB Gigabit Network Connection
39 * 82575GB Gigabit Network Connection
40 * 82576 Gigabit Network Connection
41 * 82576 Quad Port Gigabit Mezzanine Adapter
44 #include "e1000_api.h"
46 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
47 static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw);
48 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
49 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw);
50 static void e1000_release_phy_82575(struct e1000_hw *hw);
51 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
52 static void e1000_release_nvm_82575(struct e1000_hw *hw);
53 static s32 e1000_check_for_link_82575(struct e1000_hw *hw);
54 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
55 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
57 static s32 e1000_init_hw_82575(struct e1000_hw *hw);
58 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
59 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
61 static s32 e1000_reset_hw_82575(struct e1000_hw *hw);
62 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
64 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
65 static s32 e1000_setup_fiber_serdes_link_82575(struct e1000_hw *hw);
66 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
67 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
68 u32 offset, u16 data);
69 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
70 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
71 static s32 e1000_configure_pcs_link_82575(struct e1000_hw *hw);
72 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
73 u16 *speed, u16 *duplex);
74 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
75 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
76 static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
77 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
78 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
79 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
80 void e1000_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw);
81 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
84 * e1000_init_phy_params_82575 - Init PHY func ptrs.
85 * @hw: pointer to the HW structure
87 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
89 struct e1000_phy_info *phy = &hw->phy;
90 s32 ret_val = E1000_SUCCESS;
92 DEBUGFUNC("e1000_init_phy_params_82575");
94 if (hw->phy.media_type != e1000_media_type_copper) {
95 phy->type = e1000_phy_none;
98 phy->ops.power_up = e1000_power_up_phy_copper;
99 phy->ops.power_down = e1000_power_down_phy_copper_82575;
102 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
103 phy->reset_delay_us = 100;
105 phy->ops.acquire = e1000_acquire_phy_82575;
106 phy->ops.check_reset_block = e1000_check_reset_block_generic;
107 phy->ops.commit = e1000_phy_sw_reset_generic;
108 phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
109 phy->ops.release = e1000_release_phy_82575;
111 if (e1000_sgmii_active_82575(hw)) {
112 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
113 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
114 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
116 phy->ops.reset = e1000_phy_hw_reset_generic;
117 phy->ops.read_reg = e1000_read_phy_reg_igp;
118 phy->ops.write_reg = e1000_write_phy_reg_igp;
121 /* Set phy->phy_addr and phy->id. */
122 ret_val = e1000_get_phy_id_82575(hw);
124 /* Verify phy id and set remaining function pointers */
126 case M88E1111_I_PHY_ID:
127 phy->type = e1000_phy_m88;
128 phy->ops.check_polarity = e1000_check_polarity_m88;
129 phy->ops.get_info = e1000_get_phy_info_m88;
130 phy->ops.get_cable_length = e1000_get_cable_length_m88;
131 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
133 case IGP03E1000_E_PHY_ID:
134 case IGP04E1000_E_PHY_ID:
135 phy->type = e1000_phy_igp_3;
136 phy->ops.check_polarity = e1000_check_polarity_igp;
137 phy->ops.get_info = e1000_get_phy_info_igp;
138 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
139 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
140 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
141 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
144 ret_val = -E1000_ERR_PHY;
153 * e1000_init_nvm_params_82575 - Init NVM func ptrs.
154 * @hw: pointer to the HW structure
156 static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
158 struct e1000_nvm_info *nvm = &hw->nvm;
159 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
162 DEBUGFUNC("e1000_init_nvm_params_82575");
164 nvm->opcode_bits = 8;
166 switch (nvm->override) {
167 case e1000_nvm_override_spi_large:
169 nvm->address_bits = 16;
171 case e1000_nvm_override_spi_small:
173 nvm->address_bits = 8;
176 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
177 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
181 nvm->type = e1000_nvm_eeprom_spi;
183 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
184 E1000_EECD_SIZE_EX_SHIFT);
187 * Added to a constant, "size" becomes the left-shift value
188 * for setting word_size.
190 size += NVM_WORD_SIZE_BASE_SHIFT;
192 /* EEPROM access above 16k is unsupported */
195 nvm->word_size = 1 << size;
197 /* Function Pointers */
198 nvm->ops.acquire = e1000_acquire_nvm_82575;
199 nvm->ops.read = e1000_read_nvm_eerd;
200 nvm->ops.release = e1000_release_nvm_82575;
201 nvm->ops.update = e1000_update_nvm_checksum_generic;
202 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
203 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
204 nvm->ops.write = e1000_write_nvm_spi;
206 return E1000_SUCCESS;
210 * e1000_init_mac_params_82575 - Init MAC func ptrs.
211 * @hw: pointer to the HW structure
213 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
215 struct e1000_mac_info *mac = &hw->mac;
216 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
219 DEBUGFUNC("e1000_init_mac_params_82575");
223 * The 82575 uses bits 22:23 for link mode. The mode can be changed
224 * based on the EEPROM. We cannot rely upon device ID. There
225 * is no distinguishable difference between fiber and internal
226 * SerDes mode on the 82575. There can be an external PHY attached
227 * on the SGMII interface. For this, we'll set sgmii_active to TRUE.
229 hw->phy.media_type = e1000_media_type_copper;
230 dev_spec->sgmii_active = FALSE;
232 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
233 if ((ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) ==
234 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES) {
235 hw->phy.media_type = e1000_media_type_internal_serdes;
236 ctrl_ext |= E1000_CTRL_I2C_ENA;
237 } else if (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII) {
238 dev_spec->sgmii_active = TRUE;
239 ctrl_ext |= E1000_CTRL_I2C_ENA;
241 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
243 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
245 /* Set mta register count */
246 mac->mta_reg_count = 128;
247 /* Set rar entry count */
248 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
249 if (mac->type == e1000_82576)
250 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
251 /* Set if part includes ASF firmware */
252 mac->asf_firmware_present = TRUE;
253 /* Set if manageability features are enabled. */
254 mac->arc_subsystem_valid =
255 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
258 /* Function pointers */
260 /* bus type/speed/width */
261 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
263 mac->ops.reset_hw = e1000_reset_hw_82575;
264 /* hw initialization */
265 mac->ops.init_hw = e1000_init_hw_82575;
267 mac->ops.setup_link = e1000_setup_link_generic;
268 /* physical interface link setup */
269 mac->ops.setup_physical_interface =
270 (hw->phy.media_type == e1000_media_type_copper)
271 ? e1000_setup_copper_link_82575
272 : e1000_setup_fiber_serdes_link_82575;
273 /* physical interface shutdown */
274 mac->ops.shutdown_serdes = e1000_shutdown_fiber_serdes_link_82575;
276 mac->ops.check_for_link = e1000_check_for_link_82575;
277 /* receive address register setting */
278 mac->ops.rar_set = e1000_rar_set_generic;
279 /* read mac address */
280 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
281 /* multicast address update */
282 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
284 mac->ops.write_vfta = e1000_write_vfta_generic;
286 mac->ops.clear_vfta = e1000_clear_vfta_generic;
288 mac->ops.mta_set = e1000_mta_set_generic;
290 mac->ops.id_led_init = e1000_id_led_init_generic;
292 mac->ops.blink_led = e1000_blink_led_generic;
294 mac->ops.setup_led = e1000_setup_led_generic;
296 mac->ops.cleanup_led = e1000_cleanup_led_generic;
297 /* turn on/off LED */
298 mac->ops.led_on = e1000_led_on_generic;
299 mac->ops.led_off = e1000_led_off_generic;
300 /* clear hardware counters */
301 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
303 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
305 return E1000_SUCCESS;
309 * e1000_init_function_pointers_82575 - Init func ptrs.
310 * @hw: pointer to the HW structure
312 * Called to initialize all function pointers and parameters.
314 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
316 DEBUGFUNC("e1000_init_function_pointers_82575");
318 hw->mac.ops.init_params = e1000_init_mac_params_82575;
319 hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
320 hw->phy.ops.init_params = e1000_init_phy_params_82575;
324 * e1000_acquire_phy_82575 - Acquire rights to access PHY
325 * @hw: pointer to the HW structure
327 * Acquire access rights to the correct PHY.
329 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
331 u16 mask = E1000_SWFW_PHY0_SM;
333 DEBUGFUNC("e1000_acquire_phy_82575");
335 if (hw->bus.func == E1000_FUNC_1)
336 mask = E1000_SWFW_PHY1_SM;
338 return e1000_acquire_swfw_sync_82575(hw, mask);
342 * e1000_release_phy_82575 - Release rights to access PHY
343 * @hw: pointer to the HW structure
345 * A wrapper to release access rights to the correct PHY.
347 static void e1000_release_phy_82575(struct e1000_hw *hw)
349 u16 mask = E1000_SWFW_PHY0_SM;
351 DEBUGFUNC("e1000_release_phy_82575");
353 if (hw->bus.func == E1000_FUNC_1)
354 mask = E1000_SWFW_PHY1_SM;
356 e1000_release_swfw_sync_82575(hw, mask);
360 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
361 * @hw: pointer to the HW structure
362 * @offset: register offset to be read
363 * @data: pointer to the read data
365 * Reads the PHY register at offset using the serial gigabit media independent
366 * interface and stores the retrieved information in data.
368 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
371 struct e1000_phy_info *phy = &hw->phy;
374 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
376 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
377 DEBUGOUT1("PHY Address %u is out of range\n", offset);
378 return -E1000_ERR_PARAM;
382 * Set up Op-code, Phy Address, and register address in the I2CCMD
383 * register. The MAC will take care of interfacing with the
384 * PHY to retrieve the desired data.
386 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
387 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
388 (E1000_I2CCMD_OPCODE_READ));
390 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
392 /* Poll the ready bit to see if the I2C read completed */
393 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
395 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
396 if (i2ccmd & E1000_I2CCMD_READY)
399 if (!(i2ccmd & E1000_I2CCMD_READY)) {
400 DEBUGOUT("I2CCMD Read did not complete\n");
401 return -E1000_ERR_PHY;
403 if (i2ccmd & E1000_I2CCMD_ERROR) {
404 DEBUGOUT("I2CCMD Error bit set\n");
405 return -E1000_ERR_PHY;
408 /* Need to byte-swap the 16-bit value. */
409 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
411 return E1000_SUCCESS;
415 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
416 * @hw: pointer to the HW structure
417 * @offset: register offset to write to
418 * @data: data to write at register offset
420 * Writes the data to PHY register at the offset using the serial gigabit
421 * media independent interface.
423 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
426 struct e1000_phy_info *phy = &hw->phy;
428 u16 phy_data_swapped;
430 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
432 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
433 DEBUGOUT1("PHY Address %d is out of range\n", offset);
434 return -E1000_ERR_PARAM;
437 /* Swap the data bytes for the I2C interface */
438 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
441 * Set up Op-code, Phy Address, and register address in the I2CCMD
442 * register. The MAC will take care of interfacing with the
443 * PHY to retrieve the desired data.
445 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
446 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
447 E1000_I2CCMD_OPCODE_WRITE |
450 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
452 /* Poll the ready bit to see if the I2C read completed */
453 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
455 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
456 if (i2ccmd & E1000_I2CCMD_READY)
459 if (!(i2ccmd & E1000_I2CCMD_READY)) {
460 DEBUGOUT("I2CCMD Write did not complete\n");
461 return -E1000_ERR_PHY;
463 if (i2ccmd & E1000_I2CCMD_ERROR) {
464 DEBUGOUT("I2CCMD Error bit set\n");
465 return -E1000_ERR_PHY;
468 return E1000_SUCCESS;
472 * e1000_get_phy_id_82575 - Retrieve PHY addr and id
473 * @hw: pointer to the HW structure
475 * Retrieves the PHY address and ID for both PHY's which do and do not use
478 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
480 struct e1000_phy_info *phy = &hw->phy;
481 s32 ret_val = E1000_SUCCESS;
484 DEBUGFUNC("e1000_get_phy_id_82575");
487 * For SGMII PHYs, we try the list of possible addresses until
488 * we find one that works. For non-SGMII PHYs
489 * (e.g. integrated copper PHYs), an address of 1 should
490 * work. The result of this function should mean phy->phy_addr
491 * and phy->id are set correctly.
493 if (!(e1000_sgmii_active_82575(hw))) {
495 ret_val = e1000_get_phy_id(hw);
500 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
501 * Therefore, we need to test 1-7
503 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
504 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
505 if (ret_val == E1000_SUCCESS) {
506 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
510 * At the time of this writing, The M88 part is
511 * the only supported SGMII PHY product.
513 if (phy_id == M88_VENDOR)
516 DEBUGOUT1("PHY address %u was unreadable\n",
521 /* A valid PHY type couldn't be found. */
522 if (phy->addr == 8) {
524 ret_val = -E1000_ERR_PHY;
528 ret_val = e1000_get_phy_id(hw);
535 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
536 * @hw: pointer to the HW structure
538 * Resets the PHY using the serial gigabit media independent interface.
540 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
542 s32 ret_val = E1000_SUCCESS;
544 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
547 * This isn't a TRUE "hard" reset, but is the only reset
548 * available to us at this time.
551 DEBUGOUT("Soft resetting SGMII attached PHY...\n");
553 if (!(hw->phy.ops.write_reg))
557 * SFP documentation requires the following to configure the SPF module
558 * to work on SGMII. No further documentation is given.
560 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
564 ret_val = hw->phy.ops.commit(hw);
571 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
572 * @hw: pointer to the HW structure
573 * @active: TRUE to enable LPLU, FALSE to disable
575 * Sets the LPLU D0 state according to the active flag. When
576 * activating LPLU this function also disables smart speed
577 * and vice versa. LPLU will not be activated unless the
578 * device autonegotiation advertisement meets standards of
579 * either 10 or 10/100 or 10/100/1000 at all duplexes.
580 * This is a function pointer entry point only called by
581 * PHY setup routines.
583 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
585 struct e1000_phy_info *phy = &hw->phy;
586 s32 ret_val = E1000_SUCCESS;
589 DEBUGFUNC("e1000_set_d0_lplu_state_82575");
591 if (!(hw->phy.ops.read_reg))
594 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
599 data |= IGP02E1000_PM_D0_LPLU;
600 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
605 /* When LPLU is enabled, we should disable SmartSpeed */
606 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
608 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
609 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
614 data &= ~IGP02E1000_PM_D0_LPLU;
615 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
618 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
619 * during Dx states where the power conservation is most
620 * important. During driver activity we should enable
621 * SmartSpeed, so performance is maintained.
623 if (phy->smart_speed == e1000_smart_speed_on) {
624 ret_val = phy->ops.read_reg(hw,
625 IGP01E1000_PHY_PORT_CONFIG,
630 data |= IGP01E1000_PSCFR_SMART_SPEED;
631 ret_val = phy->ops.write_reg(hw,
632 IGP01E1000_PHY_PORT_CONFIG,
636 } else if (phy->smart_speed == e1000_smart_speed_off) {
637 ret_val = phy->ops.read_reg(hw,
638 IGP01E1000_PHY_PORT_CONFIG,
643 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
644 ret_val = phy->ops.write_reg(hw,
645 IGP01E1000_PHY_PORT_CONFIG,
657 * e1000_acquire_nvm_82575 - Request for access to EEPROM
658 * @hw: pointer to the HW structure
660 * Acquire the necessary semaphores for exclusive access to the EEPROM.
661 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
662 * Return successful if access grant bit set, else clear the request for
663 * EEPROM access and return -E1000_ERR_NVM (-1).
665 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
669 DEBUGFUNC("e1000_acquire_nvm_82575");
671 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
675 ret_val = e1000_acquire_nvm_generic(hw);
678 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
685 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
686 * @hw: pointer to the HW structure
688 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
689 * then release the semaphores acquired.
691 static void e1000_release_nvm_82575(struct e1000_hw *hw)
693 DEBUGFUNC("e1000_release_nvm_82575");
695 e1000_release_nvm_generic(hw);
696 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
700 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
701 * @hw: pointer to the HW structure
702 * @mask: specifies which semaphore to acquire
704 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
705 * will also specify which port we're acquiring the lock for.
707 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
711 u32 fwmask = mask << 16;
712 s32 ret_val = E1000_SUCCESS;
713 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
715 DEBUGFUNC("e1000_acquire_swfw_sync_82575");
717 while (i < timeout) {
718 if (e1000_get_hw_semaphore_generic(hw)) {
719 ret_val = -E1000_ERR_SWFW_SYNC;
723 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
724 if (!(swfw_sync & (fwmask | swmask)))
728 * Firmware currently using resource (fwmask)
729 * or other software thread using resource (swmask)
731 e1000_put_hw_semaphore_generic(hw);
737 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
738 ret_val = -E1000_ERR_SWFW_SYNC;
743 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
745 e1000_put_hw_semaphore_generic(hw);
752 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore
753 * @hw: pointer to the HW structure
754 * @mask: specifies which semaphore to acquire
756 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
757 * will also specify which port we're releasing the lock for.
759 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
763 DEBUGFUNC("e1000_release_swfw_sync_82575");
765 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS);
768 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
770 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
772 e1000_put_hw_semaphore_generic(hw);
776 * e1000_get_cfg_done_82575 - Read config done bit
777 * @hw: pointer to the HW structure
779 * Read the management control register for the config done bit for
780 * completion status. NOTE: silicon which is EEPROM-less will fail trying
781 * to read the config done bit, so an error is *ONLY* logged and returns
782 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
783 * would not be able to be reset or change link.
785 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
787 s32 timeout = PHY_CFG_TIMEOUT;
788 s32 ret_val = E1000_SUCCESS;
789 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
791 DEBUGFUNC("e1000_get_cfg_done_82575");
793 if (hw->bus.func == E1000_FUNC_1)
794 mask = E1000_NVM_CFG_DONE_PORT_1;
796 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
802 DEBUGOUT("MNG configuration cycle has not completed.\n");
805 /* If EEPROM is not marked present, init the PHY manually */
806 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) &&
807 (hw->phy.type == e1000_phy_igp_3)) {
808 e1000_phy_init_script_igp3(hw);
815 * e1000_get_link_up_info_82575 - Get link speed/duplex info
816 * @hw: pointer to the HW structure
817 * @speed: stores the current speed
818 * @duplex: stores the current duplex
820 * This is a wrapper function, if using the serial gigabit media independent
821 * interface, use PCS to retrieve the link speed and duplex information.
822 * Otherwise, use the generic function to get the link speed and duplex info.
824 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
829 DEBUGFUNC("e1000_get_link_up_info_82575");
831 if (hw->phy.media_type != e1000_media_type_copper ||
832 e1000_sgmii_active_82575(hw)) {
833 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
836 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
844 * e1000_check_for_link_82575 - Check for link
845 * @hw: pointer to the HW structure
847 * If sgmii is enabled, then use the pcs register to determine link, otherwise
848 * use the generic interface for determining link.
850 static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
855 DEBUGFUNC("e1000_check_for_link_82575");
857 /* SGMII link check is done through the PCS register. */
858 if ((hw->phy.media_type != e1000_media_type_copper) ||
859 (e1000_sgmii_active_82575(hw))) {
860 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
863 * Use this flag to determine if link needs to be checked or
864 * not. If we have link clear the flag so that we do not
865 * continue to check for link.
867 hw->mac.get_link_status = !hw->mac.serdes_has_link;
869 ret_val = e1000_check_for_copper_link_generic(hw);
876 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
877 * @hw: pointer to the HW structure
878 * @speed: stores the current speed
879 * @duplex: stores the current duplex
881 * Using the physical coding sub-layer (PCS), retrieve the current speed and
882 * duplex, then store the values in the pointers provided.
884 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
885 u16 *speed, u16 *duplex)
887 struct e1000_mac_info *mac = &hw->mac;
890 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
892 /* Set up defaults for the return values of this function */
893 mac->serdes_has_link = FALSE;
898 * Read the PCS Status register for link state. For non-copper mode,
899 * the status register is not accurate. The PCS status register is
902 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
905 * The link up bit determines when link is up on autoneg. The sync ok
906 * gets set once both sides sync up and agree upon link. Stable link
907 * can be determined by checking for both link up and link sync ok
909 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
910 mac->serdes_has_link = TRUE;
912 /* Detect and store PCS speed */
913 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
915 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
921 /* Detect and store PCS duplex */
922 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
923 *duplex = FULL_DUPLEX;
925 *duplex = HALF_DUPLEX;
929 return E1000_SUCCESS;
933 * e1000_shutdown_fiber_serdes_link_82575 - Remove link during power down
934 * @hw: pointer to the HW structure
936 * In the case of fiber serdes shut down optics and PCS on driver unload
937 * when management pass thru is not enabled.
939 void e1000_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw)
944 if (hw->phy.media_type != e1000_media_type_internal_serdes)
947 if (hw->bus.func == E1000_FUNC_0)
948 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
949 else if (hw->bus.func == E1000_FUNC_1)
950 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
953 * If APM is not enabled in the EEPROM and management interface is
954 * not enabled, then power down.
956 if (!(eeprom_data & E1000_NVM_APME_82575) &&
957 !e1000_enable_mng_pass_thru(hw)) {
958 /* Disable PCS to turn off link */
959 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
960 reg &= ~E1000_PCS_CFG_PCS_EN;
961 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
963 /* shutdown the laser */
964 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
965 reg |= E1000_CTRL_EXT_SDP7_DATA;
966 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
968 /* flush the write to verfiy completion */
969 E1000_WRITE_FLUSH(hw);
977 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
978 * @hw: pointer to the HW structure
979 * @enable: state to enter, either enabled or disabled
981 * enables/disables L2 switch loopback functionality
983 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
987 reg = E1000_READ_REG(hw, E1000_DTXSWC);
989 reg |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
991 reg &= ~(E1000_DTXSWC_VMDQ_LOOPBACK_EN);
992 E1000_WRITE_REG(hw, E1000_DTXSWC, reg);
996 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication
997 * @hw: pointer to the HW structure
998 * @enable: state to enter, either enabled or disabled
1000 * enables/disables replication of packets across multiple pools
1002 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
1006 reg = E1000_READ_REG(hw, E1000_VT_CTL);
1008 reg |= E1000_VT_CTL_VM_REPL_EN;
1010 reg &= ~(E1000_VT_CTL_VM_REPL_EN);
1012 E1000_WRITE_REG(hw, E1000_VT_CTL, reg);
1016 * e1000_reset_hw_82575 - Reset hardware
1017 * @hw: pointer to the HW structure
1019 * This resets the hardware into a known state.
1021 static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1026 DEBUGFUNC("e1000_reset_hw_82575");
1029 * Prevent the PCI-E bus from sticking if there is no TLP connection
1030 * on the last TLP read/write transaction when MAC is reset.
1032 ret_val = e1000_disable_pcie_master_generic(hw);
1034 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1037 /* set the completion timeout for interface */
1038 ret_val = e1000_set_pcie_completion_timeout(hw);
1040 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1043 DEBUGOUT("Masking off all interrupts\n");
1044 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1046 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1047 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1048 E1000_WRITE_FLUSH(hw);
1052 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1054 DEBUGOUT("Issuing a global reset to MAC\n");
1055 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1057 ret_val = e1000_get_auto_rd_done_generic(hw);
1060 * When auto config read does not complete, do not
1061 * return with an error. This can happen in situations
1062 * where there is no eeprom and prevents getting link.
1064 DEBUGOUT("Auto Read Done did not complete\n");
1067 /* If EEPROM is not present, run manual init scripts */
1068 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0)
1069 e1000_reset_init_script_82575(hw);
1071 /* Clear any pending interrupt events. */
1072 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1073 icr = E1000_READ_REG(hw, E1000_ICR);
1075 /* Install any alternate MAC address into RAR0 */
1076 ret_val = e1000_check_alt_mac_addr_generic(hw);
1082 * e1000_init_hw_82575 - Initialize hardware
1083 * @hw: pointer to the HW structure
1085 * This inits the hardware readying it for operation.
1087 static s32 e1000_init_hw_82575(struct e1000_hw *hw)
1089 struct e1000_mac_info *mac = &hw->mac;
1091 u16 i, rar_count = mac->rar_entry_count;
1093 DEBUGFUNC("e1000_init_hw_82575");
1095 /* Initialize identification LED */
1096 ret_val = mac->ops.id_led_init(hw);
1098 DEBUGOUT("Error initializing identification LED\n");
1099 /* This is not fatal and we should not stop init due to this */
1102 /* Disabling VLAN filtering */
1103 DEBUGOUT("Initializing the IEEE VLAN\n");
1104 mac->ops.clear_vfta(hw);
1106 /* Setup the receive address */
1107 e1000_init_rx_addrs_generic(hw, rar_count);
1109 /* Zero out the Multicast HASH table */
1110 DEBUGOUT("Zeroing the MTA\n");
1111 for (i = 0; i < mac->mta_reg_count; i++)
1112 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1114 /* Setup link and flow control */
1115 ret_val = mac->ops.setup_link(hw);
1118 * Clear all of the statistics registers (clear on read). It is
1119 * important that we do this after we have tried to establish link
1120 * because the symbol error count will increment wildly if there
1123 e1000_clear_hw_cntrs_82575(hw);
1129 * e1000_setup_copper_link_82575 - Configure copper link settings
1130 * @hw: pointer to the HW structure
1132 * Configures the link for auto-neg or forced speed and duplex. Then we check
1133 * for link, once link is established calls to configure collision distance
1134 * and flow control are called.
1136 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1142 DEBUGFUNC("e1000_setup_copper_link_82575");
1144 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1145 ctrl |= E1000_CTRL_SLU;
1146 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1147 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1149 switch (hw->phy.type) {
1151 ret_val = e1000_copper_link_setup_m88(hw);
1153 case e1000_phy_igp_3:
1154 ret_val = e1000_copper_link_setup_igp(hw);
1157 ret_val = -E1000_ERR_PHY;
1164 if (hw->mac.autoneg) {
1166 * Setup autoneg and flow control advertisement
1167 * and perform autonegotiation.
1169 ret_val = e1000_copper_link_autoneg(hw);
1174 * PHY will be set to 10H, 10F, 100H or 100F
1175 * depending on user settings.
1177 DEBUGOUT("Forcing Speed and Duplex\n");
1178 ret_val = hw->phy.ops.force_speed_duplex(hw);
1180 DEBUGOUT("Error Forcing Speed and Duplex\n");
1185 ret_val = e1000_configure_pcs_link_82575(hw);
1190 * Check link status. Wait up to 100 microseconds for link to become
1193 ret_val = e1000_phy_has_link_generic(hw,
1194 COPPER_LINK_UP_LIMIT,
1201 DEBUGOUT("Valid link established!!!\n");
1202 /* Config the MAC and PHY after link is up */
1203 e1000_config_collision_dist_generic(hw);
1204 ret_val = e1000_config_fc_after_link_up_generic(hw);
1206 DEBUGOUT("Unable to establish link!!!\n");
1214 * e1000_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes
1215 * @hw: pointer to the HW structure
1217 * Configures speed and duplex for fiber and serdes links.
1219 static s32 e1000_setup_fiber_serdes_link_82575(struct e1000_hw *hw)
1223 DEBUGFUNC("e1000_setup_fiber_serdes_link_82575");
1226 * On the 82575, SerDes loopback mode persists until it is
1227 * explicitly turned off or a power cycle is performed. A read to
1228 * the register does not indicate its status. Therefore, we ensure
1229 * loopback mode is disabled during initialization.
1231 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1233 /* Force link up, set 1gb */
1234 reg = E1000_READ_REG(hw, E1000_CTRL);
1235 reg |= E1000_CTRL_SLU | E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD;
1236 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1237 /* set both sw defined pins */
1238 reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1240 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1241 /* Power on phy for 82576 fiber adapters */
1242 if (hw->mac.type == e1000_82576) {
1243 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1244 reg &= ~E1000_CTRL_EXT_SDP7_DATA;
1245 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1248 /* Set switch control to serdes energy detect */
1249 reg = E1000_READ_REG(hw, E1000_CONNSW);
1250 reg |= E1000_CONNSW_ENRGSRC;
1251 E1000_WRITE_REG(hw, E1000_CONNSW, reg);
1254 * New SerDes mode allows for forcing speed or autonegotiating speed
1255 * at 1gb. Autoneg should be default set by most drivers. This is the
1256 * mode that will be compatible with older link partners and switches.
1257 * However, both are supported by the hardware and some drivers/tools.
1259 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1261 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1262 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1264 if (hw->mac.autoneg) {
1265 /* Set PCS register for autoneg */
1266 reg |= E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1267 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1268 E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1269 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1270 DEBUGOUT1("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg);
1272 /* Set PCS register for forced speed */
1273 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1274 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1275 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1276 E1000_PCS_LCTL_FSD | /* Force Speed */
1277 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1278 DEBUGOUT1("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg);
1281 if (hw->mac.type == e1000_82576) {
1282 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1283 e1000_force_mac_fc_generic(hw);
1286 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1288 return E1000_SUCCESS;
1292 * e1000_valid_led_default_82575 - Verify a valid default LED config
1293 * @hw: pointer to the HW structure
1294 * @data: pointer to the NVM (EEPROM)
1296 * Read the EEPROM for the current default LED configuration. If the
1297 * LED configuration is not valid, set to a valid LED configuration.
1299 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1303 DEBUGFUNC("e1000_valid_led_default_82575");
1305 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1307 DEBUGOUT("NVM Read Error\n");
1311 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1312 switch(hw->phy.media_type) {
1313 case e1000_media_type_internal_serdes:
1314 *data = ID_LED_DEFAULT_82575_SERDES;
1316 case e1000_media_type_copper:
1318 *data = ID_LED_DEFAULT;
1327 * e1000_configure_pcs_link_82575 - Configure PCS link
1328 * @hw: pointer to the HW structure
1330 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1331 * only used on copper connections where the serialized gigabit media
1332 * independent interface (sgmii) is being used. Configures the link
1333 * for auto-negotiation or forces speed/duplex.
1335 static s32 e1000_configure_pcs_link_82575(struct e1000_hw *hw)
1337 struct e1000_mac_info *mac = &hw->mac;
1340 DEBUGFUNC("e1000_configure_pcs_link_82575");
1342 if (hw->phy.media_type != e1000_media_type_copper ||
1343 !(e1000_sgmii_active_82575(hw)))
1346 /* For SGMII, we need to issue a PCS autoneg restart */
1347 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1349 /* AN time out should be disabled for SGMII mode */
1350 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1353 /* Make sure forced speed and force link are not set */
1354 reg &= ~(E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1357 * The PHY should be setup prior to calling this function.
1358 * All we need to do is restart autoneg and enable autoneg.
1360 reg |= E1000_PCS_LCTL_AN_RESTART | E1000_PCS_LCTL_AN_ENABLE;
1362 /* Set PCS register for forced speed */
1364 /* Turn off bits for full duplex, speed, and autoneg */
1365 reg &= ~(E1000_PCS_LCTL_FSV_1000 |
1366 E1000_PCS_LCTL_FSV_100 |
1367 E1000_PCS_LCTL_FDV_FULL |
1368 E1000_PCS_LCTL_AN_ENABLE);
1370 /* Check for duplex first */
1371 if (mac->forced_speed_duplex & E1000_ALL_FULL_DUPLEX)
1372 reg |= E1000_PCS_LCTL_FDV_FULL;
1375 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED)
1376 reg |= E1000_PCS_LCTL_FSV_100;
1378 /* Force speed and force link */
1379 reg |= E1000_PCS_LCTL_FSD |
1380 E1000_PCS_LCTL_FORCE_LINK |
1381 E1000_PCS_LCTL_FLV_LINK_UP;
1383 DEBUGOUT1("Wrote 0x%08X to PCS_LCTL to configure forced link\n",
1386 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1389 return E1000_SUCCESS;
1393 * e1000_sgmii_active_82575 - Return sgmii state
1394 * @hw: pointer to the HW structure
1396 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1397 * which can be enabled for use in the embedded applications. Simply
1398 * return the current state of the sgmii interface.
1400 static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1402 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1403 return dev_spec->sgmii_active;
1407 * e1000_reset_init_script_82575 - Inits HW defaults after reset
1408 * @hw: pointer to the HW structure
1410 * Inits recommended HW defaults after a reset when there is no EEPROM
1411 * detected. This is only for the 82575.
1413 static s32 e1000_reset_init_script_82575(struct e1000_hw* hw)
1415 DEBUGFUNC("e1000_reset_init_script_82575");
1417 if (hw->mac.type == e1000_82575) {
1418 DEBUGOUT("Running reset init script for 82575\n");
1419 /* SerDes configuration via SERDESCTRL */
1420 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1421 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1422 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1423 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1425 /* CCM configuration via CCMCTL register */
1426 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1427 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1429 /* PCIe lanes configuration */
1430 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1431 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1432 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1433 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1435 /* PCIe PLL Configuration */
1436 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1437 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1438 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1441 return E1000_SUCCESS;
1445 * e1000_read_mac_addr_82575 - Read device MAC address
1446 * @hw: pointer to the HW structure
1448 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1450 s32 ret_val = E1000_SUCCESS;
1452 DEBUGFUNC("e1000_read_mac_addr_82575");
1455 * If there's an alternate MAC address place it in RAR0
1456 * so that it will override the Si installed default perm
1459 ret_val = e1000_check_alt_mac_addr_generic(hw);
1463 ret_val = e1000_read_mac_addr_generic(hw);
1470 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
1471 * @hw: pointer to the HW structure
1473 * In the case of a PHY power down to save power, or to turn off link during a
1474 * driver unload, or wake on lan is not enabled, remove the link.
1476 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
1478 struct e1000_phy_info *phy = &hw->phy;
1479 struct e1000_mac_info *mac = &hw->mac;
1481 if (!(phy->ops.check_reset_block))
1484 /* If the management interface is not enabled, then power down */
1485 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1486 e1000_power_down_phy_copper(hw);
1492 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
1493 * @hw: pointer to the HW structure
1495 * Clears the hardware counters by reading the counter registers.
1497 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
1499 DEBUGFUNC("e1000_clear_hw_cntrs_82575");
1501 e1000_clear_hw_cntrs_base_generic(hw);
1503 E1000_READ_REG(hw, E1000_PRC64);
1504 E1000_READ_REG(hw, E1000_PRC127);
1505 E1000_READ_REG(hw, E1000_PRC255);
1506 E1000_READ_REG(hw, E1000_PRC511);
1507 E1000_READ_REG(hw, E1000_PRC1023);
1508 E1000_READ_REG(hw, E1000_PRC1522);
1509 E1000_READ_REG(hw, E1000_PTC64);
1510 E1000_READ_REG(hw, E1000_PTC127);
1511 E1000_READ_REG(hw, E1000_PTC255);
1512 E1000_READ_REG(hw, E1000_PTC511);
1513 E1000_READ_REG(hw, E1000_PTC1023);
1514 E1000_READ_REG(hw, E1000_PTC1522);
1516 E1000_READ_REG(hw, E1000_ALGNERRC);
1517 E1000_READ_REG(hw, E1000_RXERRC);
1518 E1000_READ_REG(hw, E1000_TNCRS);
1519 E1000_READ_REG(hw, E1000_CEXTERR);
1520 E1000_READ_REG(hw, E1000_TSCTC);
1521 E1000_READ_REG(hw, E1000_TSCTFC);
1523 E1000_READ_REG(hw, E1000_MGTPRC);
1524 E1000_READ_REG(hw, E1000_MGTPDC);
1525 E1000_READ_REG(hw, E1000_MGTPTC);
1527 E1000_READ_REG(hw, E1000_IAC);
1528 E1000_READ_REG(hw, E1000_ICRXOC);
1530 E1000_READ_REG(hw, E1000_ICRXPTC);
1531 E1000_READ_REG(hw, E1000_ICRXATC);
1532 E1000_READ_REG(hw, E1000_ICTXPTC);
1533 E1000_READ_REG(hw, E1000_ICTXATC);
1534 E1000_READ_REG(hw, E1000_ICTXQEC);
1535 E1000_READ_REG(hw, E1000_ICTXQMTC);
1536 E1000_READ_REG(hw, E1000_ICRXDMTC);
1538 E1000_READ_REG(hw, E1000_CBTMPC);
1539 E1000_READ_REG(hw, E1000_HTDPMC);
1540 E1000_READ_REG(hw, E1000_CBRMPC);
1541 E1000_READ_REG(hw, E1000_RPTHC);
1542 E1000_READ_REG(hw, E1000_HGPTC);
1543 E1000_READ_REG(hw, E1000_HTCBDPC);
1544 E1000_READ_REG(hw, E1000_HGORCL);
1545 E1000_READ_REG(hw, E1000_HGORCH);
1546 E1000_READ_REG(hw, E1000_HGOTCL);
1547 E1000_READ_REG(hw, E1000_HGOTCH);
1548 E1000_READ_REG(hw, E1000_LENERRS);
1550 /* This register should not be read in copper configurations */
1551 if (hw->phy.media_type == e1000_media_type_internal_serdes)
1552 E1000_READ_REG(hw, E1000_SCVPC);
1556 * e1000_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1557 * @hw: pointer to the HW structure
1559 * After rx enable if managability is enabled then there is likely some
1560 * bad data at the start of the fifo and possibly in the DMA fifo. This
1561 * function clears the fifos and flushes any packets that came in as rx was
1564 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
1566 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1569 DEBUGFUNC("e1000_rx_fifo_workaround_82575");
1570 if (hw->mac.type != e1000_82575 ||
1571 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1574 /* Disable all RX queues */
1575 for (i = 0; i < 4; i++) {
1576 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
1577 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
1578 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1580 /* Poll all queues to verify they have shut down */
1581 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1584 for (i = 0; i < 4; i++)
1585 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
1586 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1591 DEBUGOUT("Queue disable timed out after 10ms\n");
1593 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1594 * incoming packets are rejected. Set enable and wait 2ms so that
1595 * any packet that was coming in as RCTL.EN was set is flushed
1597 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
1598 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1600 rlpml = E1000_READ_REG(hw, E1000_RLPML);
1601 E1000_WRITE_REG(hw, E1000_RLPML, 0);
1603 rctl = E1000_READ_REG(hw, E1000_RCTL);
1604 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1605 temp_rctl |= E1000_RCTL_LPE;
1607 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
1608 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1609 E1000_WRITE_FLUSH(hw);
1612 /* Enable RX queues that were previously enabled and restore our
1615 for (i = 0; i < 4; i++)
1616 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
1617 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1618 E1000_WRITE_FLUSH(hw);
1620 E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
1621 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
1623 /* Flush receive errors generated by workaround */
1624 E1000_READ_REG(hw, E1000_ROC);
1625 E1000_READ_REG(hw, E1000_RNBC);
1626 E1000_READ_REG(hw, E1000_MPC);
1630 * e1000_set_pcie_completion_timeout - set pci-e completion timeout
1631 * @hw: pointer to the HW structure
1633 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1634 * however the hardware default for these parts is 500us to 1ms which is less
1635 * than the 10ms recommended by the pci-e spec. To address this we need to
1636 * increase the value to either 10ms to 200ms for capability version 1 config,
1637 * or 16ms to 55ms for version 2.
1639 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
1641 u32 gcr = E1000_READ_REG(hw, E1000_GCR);
1642 s32 ret_val = E1000_SUCCESS;
1645 /* only take action if timeout value is defaulted to 0 */
1646 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1650 * if capababilities version is type 1 we can write the
1651 * timeout of 10ms to 200ms through the GCR register
1653 if (!(gcr & E1000_GCR_CAP_VER2)) {
1654 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1659 * for version 2 capabilities we need to write the config space
1660 * directly in order to set the completion timeout value for
1663 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1668 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
1670 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1673 /* disable completion timeout resend */
1674 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
1676 E1000_WRITE_REG(hw, E1000_GCR, gcr);