sys/dev/hwpmc/hwpmc_ppro.c

   1 /*-
   2  * Copyright (c) 2003-2005,2008 Joseph Koshy
   3  * Copyright (c) 2007 The FreeBSD Foundation
   4  * All rights reserved.
   5  *
   6  * Portions of this software were developed by A. Joseph Koshy under
   7  * sponsorship from the FreeBSD Foundation and Google, Inc.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28  * SUCH DAMAGE.
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 #include <sys/param.h>
  35 #include <sys/lock.h>
  36 #include <sys/mutex.h>
  37 #include <sys/pmc.h>
  38 #include <sys/pmckern.h>
  39 #include <sys/smp.h>
  40 #include <sys/systm.h>
  41
  42 #include <machine/cpu.h>
  43 #include <machine/cpufunc.h>
  44 #include <machine/cputypes.h>
  45 #include <machine/md_var.h>
  46 #include <machine/pmc_mdep.h>
  47 #include <machine/specialreg.h>
  48
  49 /*
  50  * PENTIUM PRO SUPPORT
  51  *
  52  * Quirks:
  53  *
  54  * - Both PMCs are enabled by a single bit P6_EVSEL_EN in performance
  55  *   counter '0'.  This bit needs to be '1' if any of the two
  56  *   performance counters are in use.  Perf counters can also be
  57  *   switched off by writing zeros to their EVSEL register.
  58  *
  59  * - While the width of these counters is 40 bits, we do not appear to
  60  *   have a way of writing 40 bits to the counter MSRs.  A WRMSR
  61  *   instruction will sign extend bit 31 of the value being written to
  62  *   the perf counter -- a value of 0x80000000 written to an perf
  63  *   counter register will be sign extended to 0xFF80000000.
  64  *
  65  *   This quirk primarily affects thread-mode PMCs in counting mode, as
  66  *   these PMCs read and write PMC registers at every context switch.
  67  */
  68
  69 struct p6pmc_descr {
  70         struct pmc_descr pm_descr; /* common information */
  71         uint32_t        pm_pmc_msr;
  72         uint32_t        pm_evsel_msr;
  73 };
  74
  75 static struct p6pmc_descr p6_pmcdesc[P6_NPMCS] = {
  76
  77 #define P6_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \
  78     PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE |    \
  79     PMC_CAP_INVERT | PMC_CAP_QUALIFIER)
  80
  81         /* PMC 0 */
  82         {
  83                 .pm_descr =
  84                 {
  85                         .pd_name  ="P6-0",
  86                         .pd_class = PMC_CLASS_P6,
  87                         .pd_caps  = P6_PMC_CAPS,
  88                         .pd_width = 40
  89                 },
  90                 .pm_pmc_msr   = P6_MSR_PERFCTR0,
  91                 .pm_evsel_msr = P6_MSR_EVSEL0
  92         },
  93
  94         /* PMC 1 */
  95         {
  96                 .pm_descr =
  97                 {
  98                         .pd_name  ="P6-1",
  99                         .pd_class = PMC_CLASS_P6,
 100                         .pd_caps  = P6_PMC_CAPS,
 101                         .pd_width = 40
 102                 },
 103                 .pm_pmc_msr   = P6_MSR_PERFCTR1,
 104                 .pm_evsel_msr = P6_MSR_EVSEL1
 105         }
 106 };
 107
 108 static enum pmc_cputype p6_cputype;
 109
 110 /*
 111  * P6 Event descriptor
 112  *
 113  * The 'pm_flags' field has the following structure:
 114  * - The upper 4 bits are used to track which counter an event is valid on.
 115  * - The lower bits form a bitmask of flags indicating support for the event
 116  *   on a given CPU.
 117  */
 118
 119 struct p6_event_descr {
 120         const enum pmc_event pm_event;
 121         uint32_t             pm_evsel;
 122         uint32_t             pm_flags;
 123         uint32_t             pm_unitmask;
 124 };
 125
 126 #define P6F_CTR(C)      (1 << (28 + (C)))
 127 #define P6F_CTR0        P6F_CTR(0)
 128 #define P6F_CTR1        P6F_CTR(1)
 129 #define P6F(CPU)        (1 << ((CPU) - PMC_CPU_INTEL_P6))
 130 #define _P6F(C)         P6F(PMC_CPU_INTEL_##C)
 131 #define P6F_P6          _P6F(P6)
 132 #define P6F_CL          _P6F(CL)
 133 #define P6F_PII         _P6F(PII)
 134 #define P6F_PIII        _P6F(PIII)
 135 #define P6F_PM          _P6F(PM)
 136 #define P6F_ALL_CPUS    (P6F_P6 | P6F_PII | P6F_CL | P6F_PIII | P6F_PM)
 137 #define P6F_ALL_CTRS    (P6F_CTR0 | P6F_CTR1)
 138 #define P6F_ALL         (P6F_ALL_CPUS | P6F_ALL_CTRS)
 139
 140 #define P6_EVENT_VALID_FOR_CPU(P,CPU)   ((P)->pm_flags & P6F(CPU))
 141 #define P6_EVENT_VALID_FOR_CTR(P,CTR)   ((P)->pm_flags & P6F_CTR(CTR))
 142
 143 static const struct p6_event_descr p6_events[] = {
 144
 145 #define P6_EVDESCR(NAME, EVSEL, FLAGS, UMASK)   \
 146         {                                       \
 147                 .pm_event = PMC_EV_P6_##NAME,   \
 148                 .pm_evsel = (EVSEL),            \
 149                 .pm_flags = (FLAGS),            \
 150                 .pm_unitmask = (UMASK)          \
 151         }
 152
 153 P6_EVDESCR(DATA_MEM_REFS,               0x43, P6F_ALL, 0x00),
 154 P6_EVDESCR(DCU_LINES_IN,                0x45, P6F_ALL, 0x00),
 155 P6_EVDESCR(DCU_M_LINES_IN,              0x46, P6F_ALL, 0x00),
 156 P6_EVDESCR(DCU_M_LINES_OUT,             0x47, P6F_ALL, 0x00),
 157 P6_EVDESCR(DCU_MISS_OUTSTANDING,        0x47, P6F_ALL, 0x00),
 158 P6_EVDESCR(IFU_FETCH,                   0x80, P6F_ALL, 0x00),
 159 P6_EVDESCR(IFU_FETCH_MISS,              0x81, P6F_ALL, 0x00),
 160 P6_EVDESCR(ITLB_MISS,                   0x85, P6F_ALL, 0x00),
 161 P6_EVDESCR(IFU_MEM_STALL,               0x86, P6F_ALL, 0x00),
 162 P6_EVDESCR(ILD_STALL,                   0x87, P6F_ALL, 0x00),
 163 P6_EVDESCR(L2_IFETCH,                   0x28, P6F_ALL, 0x0F),
 164 P6_EVDESCR(L2_LD,                       0x29, P6F_ALL, 0x0F),
 165 P6_EVDESCR(L2_ST,                       0x2A, P6F_ALL, 0x0F),
 166 P6_EVDESCR(L2_LINES_IN,                 0x24, P6F_ALL, 0x0F),
 167 P6_EVDESCR(L2_LINES_OUT,                0x26, P6F_ALL, 0x0F),
 168 P6_EVDESCR(L2_M_LINES_INM,              0x25, P6F_ALL, 0x00),
 169 P6_EVDESCR(L2_M_LINES_OUTM,             0x27, P6F_ALL, 0x0F),
 170 P6_EVDESCR(L2_RQSTS,                    0x2E, P6F_ALL, 0x0F),
 171 P6_EVDESCR(L2_ADS,                      0x21, P6F_ALL, 0x00),
 172 P6_EVDESCR(L2_DBUS_BUSY,                0x22, P6F_ALL, 0x00),
 173 P6_EVDESCR(L2_DBUS_BUSY_RD,             0x23, P6F_ALL, 0x00),
 174 P6_EVDESCR(BUS_DRDY_CLOCKS,             0x62, P6F_ALL, 0x20),
 175 P6_EVDESCR(BUS_LOCK_CLOCKS,             0x63, P6F_ALL, 0x20),
 176 P6_EVDESCR(BUS_REQ_OUTSTANDING,         0x60, P6F_ALL, 0x00),
 177 P6_EVDESCR(BUS_TRAN_BRD,                0x65, P6F_ALL, 0x20),
 178 P6_EVDESCR(BUS_TRAN_RFO,                0x66, P6F_ALL, 0x20),
 179 P6_EVDESCR(BUS_TRANS_WB,                0x67, P6F_ALL, 0x20),
 180 P6_EVDESCR(BUS_TRAN_IFETCH,             0x68, P6F_ALL, 0x20),
 181 P6_EVDESCR(BUS_TRAN_INVAL,              0x69, P6F_ALL, 0x20),
 182 P6_EVDESCR(BUS_TRAN_PWR,                0x6A, P6F_ALL, 0x20),
 183 P6_EVDESCR(BUS_TRANS_P,                 0x6B, P6F_ALL, 0x20),
 184 P6_EVDESCR(BUS_TRANS_IO,                0x6C, P6F_ALL, 0x20),
 185 P6_EVDESCR(BUS_TRAN_DEF,                0x6D, P6F_ALL, 0x20),
 186 P6_EVDESCR(BUS_TRAN_BURST,              0x6E, P6F_ALL, 0x20),
 187 P6_EVDESCR(BUS_TRAN_ANY,                0x70, P6F_ALL, 0x20),
 188 P6_EVDESCR(BUS_TRAN_MEM,                0x6F, P6F_ALL, 0x20),
 189 P6_EVDESCR(BUS_DATA_RCV,                0x64, P6F_ALL, 0x00),
 190 P6_EVDESCR(BUS_BNR_DRV,                 0x61, P6F_ALL, 0x00),
 191 P6_EVDESCR(BUS_HIT_DRV,                 0x7A, P6F_ALL, 0x00),
 192 P6_EVDESCR(BUS_HITM_DRV,                0x7B, P6F_ALL, 0x00),
 193 P6_EVDESCR(BUS_SNOOP_STALL,             0x7E, P6F_ALL, 0x00),
 194 P6_EVDESCR(FLOPS,                       0xC1, P6F_ALL_CPUS | P6F_CTR0, 0x00),
 195 P6_EVDESCR(FP_COMPS_OPS_EXE,            0x10, P6F_ALL_CPUS | P6F_CTR0, 0x00),
 196 P6_EVDESCR(FP_ASSIST,                   0x11, P6F_ALL_CPUS | P6F_CTR1, 0x00),
 197 P6_EVDESCR(MUL,                         0x12, P6F_ALL_CPUS | P6F_CTR1, 0x00),
 198 P6_EVDESCR(DIV,                         0x13, P6F_ALL_CPUS | P6F_CTR1, 0x00),
 199 P6_EVDESCR(CYCLES_DIV_BUSY,             0x14, P6F_ALL_CPUS | P6F_CTR0, 0x00),
 200 P6_EVDESCR(LD_BLOCKS,                   0x03, P6F_ALL, 0x00),
 201 P6_EVDESCR(SB_DRAINS,                   0x04, P6F_ALL, 0x00),
 202 P6_EVDESCR(MISALIGN_MEM_REF,            0x05, P6F_ALL, 0x00),
 203 P6_EVDESCR(EMON_KNI_PREF_DISPATCHED,    0x07, P6F_PIII | P6F_ALL_CTRS, 0x03),
 204 P6_EVDESCR(EMON_KNI_PREF_MISS,          0x4B, P6F_PIII | P6F_ALL_CTRS, 0x03),
 205 P6_EVDESCR(INST_RETIRED,                0xC0, P6F_ALL, 0x00),
 206 P6_EVDESCR(UOPS_RETIRED,                0xC2, P6F_ALL, 0x00),
 207 P6_EVDESCR(INST_DECODED,                0xD0, P6F_ALL, 0x00),
 208 P6_EVDESCR(EMON_KNI_INST_RETIRED,       0xD8, P6F_PIII | P6F_ALL_CTRS, 0x01),
 209 P6_EVDESCR(EMON_KNI_COMP_INST_RET,      0xD9, P6F_PIII | P6F_ALL_CTRS, 0x01),
 210 P6_EVDESCR(HW_INT_RX,                   0xC8, P6F_ALL, 0x00),
 211 P6_EVDESCR(CYCLES_INT_MASKED,           0xC6, P6F_ALL, 0x00),
 212 P6_EVDESCR(CYCLES_INT_PENDING_AND_MASKED, 0xC7, P6F_ALL, 0x00),
 213 P6_EVDESCR(BR_INST_RETIRED,             0xC4, P6F_ALL, 0x00),
 214 P6_EVDESCR(BR_MISS_PRED_RETIRED,        0xC5, P6F_ALL, 0x00),
 215 P6_EVDESCR(BR_TAKEN_RETIRED,            0xC9, P6F_ALL, 0x00),
 216 P6_EVDESCR(BR_MISS_PRED_TAKEN_RET,      0xCA, P6F_ALL, 0x00),
 217 P6_EVDESCR(BR_INST_DECODED,             0xE0, P6F_ALL, 0x00),
 218 P6_EVDESCR(BTB_MISSES,                  0xE2, P6F_ALL, 0x00),
 219 P6_EVDESCR(BR_BOGUS,                    0xE4, P6F_ALL, 0x00),
 220 P6_EVDESCR(BACLEARS,                    0xE6, P6F_ALL, 0x00),
 221 P6_EVDESCR(RESOURCE_STALLS,             0xA2, P6F_ALL, 0x00),
 222 P6_EVDESCR(PARTIAL_RAT_STALLS,          0xD2, P6F_ALL, 0x00),
 223 P6_EVDESCR(SEGMENT_REG_LOADS,           0x06, P6F_ALL, 0x00),
 224 P6_EVDESCR(CPU_CLK_UNHALTED,            0x79, P6F_ALL, 0x00),
 225 P6_EVDESCR(MMX_INSTR_EXEC,              0xB0,
 226                         P6F_ALL_CTRS | P6F_CL | P6F_PII, 0x00),
 227 P6_EVDESCR(MMX_SAT_INSTR_EXEC,          0xB1,
 228                         P6F_ALL_CTRS | P6F_PII | P6F_PIII, 0x00),
 229 P6_EVDESCR(MMX_UOPS_EXEC,               0xB2,
 230                         P6F_ALL_CTRS | P6F_PII | P6F_PIII, 0x0F),
 231 P6_EVDESCR(MMX_INSTR_TYPE_EXEC,         0xB3,
 232                         P6F_ALL_CTRS | P6F_PII | P6F_PIII, 0x3F),
 233 P6_EVDESCR(FP_MMX_TRANS,                0xCC,
 234                         P6F_ALL_CTRS | P6F_PII | P6F_PIII, 0x01),
 235 P6_EVDESCR(MMX_ASSIST,                  0xCD,
 236                         P6F_ALL_CTRS | P6F_PII | P6F_PIII, 0x00),
 237 P6_EVDESCR(MMX_INSTR_RET,               0xCE, P6F_ALL_CTRS | P6F_PII, 0x00),
 238 P6_EVDESCR(SEG_RENAME_STALLS,           0xD4,
 239                         P6F_ALL_CTRS | P6F_PII | P6F_PIII, 0x0F),
 240 P6_EVDESCR(SEG_REG_RENAMES,             0xD5,
 241                         P6F_ALL_CTRS | P6F_PII | P6F_PIII, 0x0F),
 242 P6_EVDESCR(RET_SEG_RENAMES,             0xD6,
 243                         P6F_ALL_CTRS | P6F_PII | P6F_PIII, 0x00),
 244 P6_EVDESCR(EMON_EST_TRANS,              0x58, P6F_ALL_CTRS | P6F_PM, 0x02),
 245 P6_EVDESCR(EMON_THERMAL_TRIP,           0x59, P6F_ALL_CTRS | P6F_PM, 0x00),
 246 P6_EVDESCR(BR_INST_EXEC,                0x88, P6F_ALL_CTRS | P6F_PM, 0x00),
 247 P6_EVDESCR(BR_MISSP_EXEC,               0x89, P6F_ALL_CTRS | P6F_PM, 0x00),
 248 P6_EVDESCR(BR_BAC_MISSP_EXEC,           0x8A, P6F_ALL_CTRS | P6F_PM, 0x00),
 249 P6_EVDESCR(BR_CND_EXEC,                 0x8B, P6F_ALL_CTRS | P6F_PM, 0x00),
 250 P6_EVDESCR(BR_CND_MISSP_EXEC,           0x8C, P6F_ALL_CTRS | P6F_PM, 0x00),
 251 P6_EVDESCR(BR_IND_EXEC,                 0x8D, P6F_ALL_CTRS | P6F_PM, 0x00),
 252 P6_EVDESCR(BR_IND_MISSP_EXEC,           0x8E, P6F_ALL_CTRS | P6F_PM, 0x00),
 253 P6_EVDESCR(BR_RET_EXEC,                 0x8F, P6F_ALL_CTRS | P6F_PM, 0x00),
 254 P6_EVDESCR(BR_RET_MISSP_EXEC,           0x90, P6F_ALL_CTRS | P6F_PM, 0x00),
 255 P6_EVDESCR(BR_RET_BAC_MISSP_EXEC,       0x91, P6F_ALL_CTRS | P6F_PM, 0x00),
 256 P6_EVDESCR(BR_CALL_EXEC,                0x92, P6F_ALL_CTRS | P6F_PM, 0x00),
 257 P6_EVDESCR(BR_CALL_MISSP_EXEC,          0x93, P6F_ALL_CTRS | P6F_PM, 0x00),
 258 P6_EVDESCR(BR_IND_CALL_EXEC,            0x94, P6F_ALL_CTRS | P6F_PM, 0x00),
 259 P6_EVDESCR(EMON_SIMD_INSTR_RETIRED,     0xCE, P6F_ALL_CTRS | P6F_PM, 0x00),
 260 P6_EVDESCR(EMON_SYNCH_UOPS,             0xD3, P6F_ALL_CTRS | P6F_PM, 0x00),
 261 P6_EVDESCR(EMON_ESP_UOPS,               0xD7, P6F_ALL_CTRS | P6F_PM, 0x00),
 262 P6_EVDESCR(EMON_FUSED_UOPS_RET,         0xDA, P6F_ALL_CTRS | P6F_PM, 0x03),
 263 P6_EVDESCR(EMON_UNFUSION,               0xDB, P6F_ALL_CTRS | P6F_PM, 0x00),
 264 P6_EVDESCR(EMON_PREF_RQSTS_UP,          0xF0, P6F_ALL_CTRS | P6F_PM, 0x00),
 265 P6_EVDESCR(EMON_PREF_RQSTS_DN,          0xD8, P6F_ALL_CTRS | P6F_PM, 0x00),
 266 P6_EVDESCR(EMON_SSE_SSE2_INST_RETIRED,  0xD8, P6F_ALL_CTRS | P6F_PM, 0x03),
 267 P6_EVDESCR(EMON_SSE_SSE2_COMP_INST_RETIRED, 0xD9, P6F_ALL_CTRS | P6F_PM, 0x03)
 268
 269 #undef  P6_EVDESCR
 270 };
 271
 272 #define P6_NEVENTS      (PMC_EV_P6_LAST - PMC_EV_P6_FIRST + 1)
 273
 274 static const struct p6_event_descr *
 275 p6_find_event(enum pmc_event ev)
 276 {
 277         int n;
 278
 279         for (n = 0; n < P6_NEVENTS; n++)
 280                 if (p6_events[n].pm_event == ev)
 281                         break;
 282         if (n == P6_NEVENTS)
 283                 return NULL;
 284         return &p6_events[n];
 285 }
 286
 287 /*
 288  * Per-CPU data structure for P6 class CPUs
 289  *
 290  * [common stuff]
 291  * [flags for maintaining PMC start/stop state]
 292  * [3 struct pmc_hw pointers]
 293  * [3 struct pmc_hw structures]
 294  */
 295
 296 struct p6_cpu {
 297         struct pmc_hw   pc_p6pmcs[P6_NPMCS];
 298         uint32_t        pc_state;
 299 };
 300
 301 static struct p6_cpu **p6_pcpu;
 302
 303 /*
 304  * If CTR1 is active, we need to keep the 'EN' bit if CTR0 set,
 305  * with the rest of CTR0 being zero'ed out.
 306  */
 307 #define P6_SYNC_CTR_STATE(PC) do {                              \
 308                 uint32_t _config, _enable;                      \
 309                 _enable = 0;                                    \
 310                 if ((PC)->pc_state & 0x02)                      \
 311                         _enable |= P6_EVSEL_EN;                 \
 312                 if ((PC)->pc_state & 0x01)                      \
 313                         _config = rdmsr(P6_MSR_EVSEL0) |        \
 314                             P6_EVSEL_EN;                        \
 315                 else                                            \
 316                         _config = 0;                            \
 317                 wrmsr(P6_MSR_EVSEL0, _config | _enable);        \
 318         } while (0)
 319
 320 #define P6_MARK_STARTED(PC,RI) do {                             \
 321                 (PC)->pc_state |= (1 << ((RI)-1));              \
 322         } while (0)
 323
 324 #define P6_MARK_STOPPED(PC,RI) do {                             \
 325                 (PC)->pc_state &= ~(1<< ((RI)-1));              \
 326         } while (0)
 327
 328 static int
 329 p6_pcpu_init(struct pmc_mdep *md, int cpu)
 330 {
 331         int first_ri, n;
 332         struct p6_cpu *p6c;
 333         struct pmc_cpu *pc;
 334         struct pmc_hw *phw;
 335
 336         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 337             ("[p6,%d] bad cpu %d", __LINE__, cpu));
 338
 339         PMCDBG(MDP,INI,0,"p6-init cpu=%d", cpu);
 340
 341         p6c = malloc(sizeof (struct p6_cpu), M_PMC, M_WAITOK|M_ZERO);
 342         pc = pmc_pcpu[cpu];
 343
 344         KASSERT(pc != NULL, ("[p6,%d] cpu %d null per-cpu", __LINE__, cpu));
 345
 346         phw = p6c->pc_p6pmcs;
 347         p6_pcpu[cpu] = p6c;
 348
 349         first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_P6].pcd_ri;
 350
 351         for (n = 0; n < P6_NPMCS; n++, phw++) {
 352                 phw->phw_state   = PMC_PHW_FLAG_IS_ENABLED |
 353                     PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(n);
 354                 phw->phw_pmc     = NULL;
 355                 pc->pc_hwpmcs[n + first_ri] = phw;
 356         }
 357
 358         return (0);
 359 }
 360
 361 static int
 362 p6_pcpu_fini(struct pmc_mdep *md, int cpu)
 363 {
 364         int first_ri, n;
 365         struct p6_cpu *p6c;
 366         struct pmc_cpu *pc;
 367
 368         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 369             ("[p6,%d] bad cpu %d", __LINE__, cpu));
 370
 371         PMCDBG(MDP,INI,0,"p6-cleanup cpu=%d", cpu);
 372
 373         p6c = p6_pcpu[cpu];
 374         p6_pcpu[cpu] = NULL;
 375
 376         KASSERT(p6c != NULL, ("[p6,%d] null pcpu", __LINE__));
 377
 378         free(p6c, M_PMC);
 379
 380         first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_P6].pcd_ri;
 381         pc = pmc_pcpu[cpu];
 382         for (n = 0; n < P6_NPMCS; n++)
 383                 pc->pc_hwpmcs[n + first_ri] = NULL;
 384
 385         return (0);
 386 }
 387
 388 static int
 389 p6_read_pmc(int cpu, int ri, pmc_value_t *v)
 390 {
 391         struct pmc *pm;
 392         struct p6pmc_descr *pd;
 393         pmc_value_t tmp;
 394
 395         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 396             ("[p6,%d] illegal cpu value %d", __LINE__, cpu));
 397         KASSERT(ri >= 0 && ri < P6_NPMCS,
 398             ("[p6,%d] illegal row-index %d", __LINE__, ri));
 399
 400         pm = p6_pcpu[cpu]->pc_p6pmcs[ri].phw_pmc;
 401         pd = &p6_pmcdesc[ri];
 402
 403         KASSERT(pm,
 404             ("[p6,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri));
 405
 406         tmp = rdmsr(pd->pm_pmc_msr) & P6_PERFCTR_READ_MASK;
 407         if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
 408                 *v = P6_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
 409         else
 410                 *v = tmp;
 411
 412         PMCDBG(MDP,REA,1, "p6-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri,
 413             pd->pm_pmc_msr, *v);
 414
 415         return (0);
 416 }
 417
 418 static int
 419 p6_write_pmc(int cpu, int ri, pmc_value_t v)
 420 {
 421         struct pmc *pm;
 422         struct p6pmc_descr *pd;
 423
 424         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 425             ("[p6,%d] illegal cpu value %d", __LINE__, cpu));
 426         KASSERT(ri >= 0 && ri < P6_NPMCS,
 427             ("[p6,%d] illegal row-index %d", __LINE__, ri));
 428
 429         pm = p6_pcpu[cpu]->pc_p6pmcs[ri].phw_pmc;
 430         pd = &p6_pmcdesc[ri];
 431
 432         KASSERT(pm,
 433             ("[p6,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri));
 434
 435         PMCDBG(MDP,WRI,1, "p6-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri,
 436             pd->pm_pmc_msr, v);
 437
 438         if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
 439                 v = P6_RELOAD_COUNT_TO_PERFCTR_VALUE(v);
 440
 441         wrmsr(pd->pm_pmc_msr, v & P6_PERFCTR_WRITE_MASK);
 442
 443         return (0);
 444 }
 445
 446 static int
 447 p6_config_pmc(int cpu, int ri, struct pmc *pm)
 448 {
 449         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 450             ("[p6,%d] illegal CPU %d", __LINE__, cpu));
 451
 452         KASSERT(ri >= 0 && ri < P6_NPMCS,
 453             ("[p6,%d] illegal row-index %d", __LINE__, ri));
 454
 455         PMCDBG(MDP,CFG,1, "p6-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
 456
 457         KASSERT(p6_pcpu[cpu] != NULL, ("[p6,%d] null per-cpu %d", __LINE__,
 458             cpu));
 459
 460         p6_pcpu[cpu]->pc_p6pmcs[ri].phw_pmc = pm;
 461
 462         return (0);
 463 }
 464
 465 /*
 466  * Retrieve a configured PMC pointer from hardware state.
 467  */
 468
 469 static int
 470 p6_get_config(int cpu, int ri, struct pmc **ppm)
 471 {
 472
 473         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 474             ("[p6,%d] illegal CPU %d", __LINE__, cpu));
 475         KASSERT(ri >= 0 && ri < P6_NPMCS,
 476             ("[p6,%d] illegal row-index %d", __LINE__, ri));
 477
 478         *ppm = p6_pcpu[cpu]->pc_p6pmcs[ri].phw_pmc;
 479
 480         return (0);
 481 }
 482
 483
 484 /*
 485  * A pmc may be allocated to a given row index if:
 486  * - the event is valid for this CPU
 487  * - the event is valid for this counter index
 488  */
 489
 490 static int
 491 p6_allocate_pmc(int cpu, int ri, struct pmc *pm,
 492     const struct pmc_op_pmcallocate *a)
 493 {
 494         uint32_t allowed_unitmask, caps, config, unitmask;
 495         const struct p6pmc_descr *pd;
 496         const struct p6_event_descr *pevent;
 497         enum pmc_event ev;
 498
 499         (void) cpu;
 500
 501         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 502             ("[p6,%d] illegal CPU %d", __LINE__, cpu));
 503         KASSERT(ri >= 0 && ri < P6_NPMCS,
 504             ("[p6,%d] illegal row-index value %d", __LINE__, ri));
 505
 506         pd = &p6_pmcdesc[ri];
 507
 508         PMCDBG(MDP,ALL,1, "p6-allocate ri=%d class=%d pmccaps=0x%x "
 509             "reqcaps=0x%x", ri, pd->pm_descr.pd_class, pd->pm_descr.pd_caps,
 510             pm->pm_caps);
 511
 512         /* check class */
 513         if (pd->pm_descr.pd_class != a->pm_class)
 514                 return (EINVAL);
 515
 516         /* check requested capabilities */
 517         caps = a->pm_caps;
 518         if ((pd->pm_descr.pd_caps & caps) != caps)
 519                 return (EPERM);
 520
 521         ev = pm->pm_event;
 522
 523         if (ev < PMC_EV_P6_FIRST || ev > PMC_EV_P6_LAST)
 524                 return (EINVAL);
 525
 526         if ((pevent = p6_find_event(ev)) == NULL)
 527                 return (ESRCH);
 528
 529         if (!P6_EVENT_VALID_FOR_CPU(pevent, p6_cputype) ||
 530             !P6_EVENT_VALID_FOR_CTR(pevent, (ri-1)))
 531                 return (EINVAL);
 532
 533         /* For certain events, Pentium M differs from the stock P6 */
 534         allowed_unitmask = 0;
 535         if (p6_cputype == PMC_CPU_INTEL_PM) {
 536                 if (ev == PMC_EV_P6_L2_LD || ev == PMC_EV_P6_L2_LINES_IN ||
 537                     ev == PMC_EV_P6_L2_LINES_OUT)
 538                         allowed_unitmask = P6_EVSEL_TO_UMASK(0x3F);
 539                 else if (ev == PMC_EV_P6_L2_M_LINES_OUTM)
 540                         allowed_unitmask = P6_EVSEL_TO_UMASK(0x30);
 541         } else
 542                 allowed_unitmask = P6_EVSEL_TO_UMASK(pevent->pm_unitmask);
 543
 544         unitmask = a->pm_md.pm_ppro.pm_ppro_config & P6_EVSEL_UMASK_MASK;
 545         if (unitmask & ~allowed_unitmask) /* disallow reserved bits */
 546                 return (EINVAL);
 547
 548         if (ev == PMC_EV_P6_MMX_UOPS_EXEC) /* hardcoded mask */
 549                 unitmask = P6_EVSEL_TO_UMASK(0x0F);
 550
 551         config = 0;
 552
 553         config |= P6_EVSEL_EVENT_SELECT(pevent->pm_evsel);
 554
 555         if (unitmask & (caps & PMC_CAP_QUALIFIER))
 556                 config |= unitmask;
 557
 558         if (caps & PMC_CAP_THRESHOLD)
 559                 config |= a->pm_md.pm_ppro.pm_ppro_config &
 560                     P6_EVSEL_CMASK_MASK;
 561
 562         /* set at least one of the 'usr' or 'os' caps */
 563         if (caps & PMC_CAP_USER)
 564                 config |= P6_EVSEL_USR;
 565         if (caps & PMC_CAP_SYSTEM)
 566                 config |= P6_EVSEL_OS;
 567         if ((caps & (PMC_CAP_USER|PMC_CAP_SYSTEM)) == 0)
 568                 config |= (P6_EVSEL_USR|P6_EVSEL_OS);
 569
 570         if (caps & PMC_CAP_EDGE)
 571                 config |= P6_EVSEL_E;
 572         if (caps & PMC_CAP_INVERT)
 573                 config |= P6_EVSEL_INV;
 574         if (caps & PMC_CAP_INTERRUPT)
 575                 config |= P6_EVSEL_INT;
 576
 577         pm->pm_md.pm_ppro.pm_ppro_evsel = config;
 578
 579         PMCDBG(MDP,ALL,2, "p6-allocate config=0x%x", config);
 580
 581         return (0);
 582 }
 583
 584 static int
 585 p6_release_pmc(int cpu, int ri, struct pmc *pm)
 586 {
 587         (void) pm;
 588
 589         PMCDBG(MDP,REL,1, "p6-release cpu=%d ri=%d pm=%p", cpu, ri, pm);
 590
 591         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 592             ("[p6,%d] illegal CPU value %d", __LINE__, cpu));
 593         KASSERT(ri >= 0 && ri < P6_NPMCS,
 594             ("[p6,%d] illegal row-index %d", __LINE__, ri));
 595
 596         KASSERT(p6_pcpu[cpu]->pc_p6pmcs[ri].phw_pmc == NULL,
 597             ("[p6,%d] PHW pmc non-NULL", __LINE__));
 598
 599         return (0);
 600 }
 601
 602 static int
 603 p6_start_pmc(int cpu, int ri)
 604 {
 605         uint32_t config;
 606         struct pmc *pm;
 607         struct p6_cpu *pc;
 608         const struct p6pmc_descr *pd;
 609
 610         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 611             ("[p6,%d] illegal CPU value %d", __LINE__, cpu));
 612         KASSERT(ri >= 0 && ri < P6_NPMCS,
 613             ("[p6,%d] illegal row-index %d", __LINE__, ri));
 614
 615         pc = p6_pcpu[cpu];
 616         pm = pc->pc_p6pmcs[ri].phw_pmc;
 617         pd = &p6_pmcdesc[ri];
 618
 619         KASSERT(pm,
 620             ("[p6,%d] starting cpu%d,ri%d with no pmc configured",
 621                 __LINE__, cpu, ri));
 622
 623         PMCDBG(MDP,STA,1, "p6-start cpu=%d ri=%d", cpu, ri);
 624
 625         config = pm->pm_md.pm_ppro.pm_ppro_evsel;
 626
 627         PMCDBG(MDP,STA,2, "p6-start/2 cpu=%d ri=%d evselmsr=0x%x config=0x%x",
 628             cpu, ri, pd->pm_evsel_msr, config);
 629
 630         P6_MARK_STARTED(pc, ri);
 631         wrmsr(pd->pm_evsel_msr, config);
 632
 633         P6_SYNC_CTR_STATE(pc);
 634
 635         return (0);
 636 }
 637
 638 static int
 639 p6_stop_pmc(int cpu, int ri)
 640 {
 641         struct pmc *pm;
 642         struct p6_cpu *pc;
 643         struct p6pmc_descr *pd;
 644
 645         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 646             ("[p6,%d] illegal cpu value %d", __LINE__, cpu));
 647         KASSERT(ri >= 0 && ri < P6_NPMCS,
 648             ("[p6,%d] illegal row index %d", __LINE__, ri));
 649
 650         pc = p6_pcpu[cpu];
 651         pm = pc->pc_p6pmcs[ri].phw_pmc;
 652         pd = &p6_pmcdesc[ri];
 653
 654         KASSERT(pm,
 655             ("[p6,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
 656                 cpu, ri));
 657
 658         PMCDBG(MDP,STO,1, "p6-stop cpu=%d ri=%d", cpu, ri);
 659
 660         wrmsr(pd->pm_evsel_msr, 0);     /* stop hw */
 661         P6_MARK_STOPPED(pc, ri);        /* update software state */
 662
 663         P6_SYNC_CTR_STATE(pc);          /* restart CTR1 if need be */
 664
 665         PMCDBG(MDP,STO,2, "p6-stop/2 cpu=%d ri=%d", cpu, ri);
 666
 667         return (0);
 668 }
 669
 670 static int
 671 p6_intr(int cpu, struct trapframe *tf)
 672 {
 673         int error, retval, ri;
 674         uint32_t perf0cfg;
 675         struct pmc *pm;
 676         struct p6_cpu *pc;
 677         pmc_value_t v;
 678
 679         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 680             ("[p6,%d] CPU %d out of range", __LINE__, cpu));
 681
 682         retval = 0;
 683         pc = p6_pcpu[cpu];
 684
 685         /* stop both PMCs */
 686         perf0cfg = rdmsr(P6_MSR_EVSEL0);
 687         wrmsr(P6_MSR_EVSEL0, perf0cfg & ~P6_EVSEL_EN);
 688
 689         for (ri = 0; ri < P6_NPMCS; ri++) {
 690
 691                 if ((pm = pc->pc_p6pmcs[ri].phw_pmc) == NULL ||
 692                     !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) {
 693                         continue;
 694                 }
 695
 696                 if (!P6_PMC_HAS_OVERFLOWED(ri))
 697                         continue;
 698
 699                 retval = 1;
 700
 701                 if (pm->pm_state != PMC_STATE_RUNNING)
 702                         continue;
 703
 704                 error = pmc_process_interrupt(cpu, pm, tf,
 705                     TRAPF_USERMODE(tf));
 706                 if (error)
 707                         P6_MARK_STOPPED(pc,ri);
 708
 709                 /* reload sampling count */
 710                 v = pm->pm_sc.pm_reloadcount;
 711                 wrmsr(P6_MSR_PERFCTR0 + ri,
 712                     P6_RELOAD_COUNT_TO_PERFCTR_VALUE(v));
 713
 714         }
 715
 716         /*
 717          * On P6 processors, the LAPIC needs to have its PMC interrupt
 718          * unmasked after a PMC interrupt.
 719          */
 720         if (retval)
 721                 pmc_x86_lapic_enable_pmc_interrupt();
 722
 723         atomic_add_int(retval ? &pmc_stats.pm_intr_processed :
 724             &pmc_stats.pm_intr_ignored, 1);
 725
 726         /* restart counters that can be restarted */
 727         P6_SYNC_CTR_STATE(pc);
 728
 729         return (retval);
 730 }
 731
 732 static int
 733 p6_describe(int cpu, int ri, struct pmc_info *pi,
 734     struct pmc **ppmc)
 735 {
 736         int error;
 737         size_t copied;
 738         struct pmc_hw *phw;
 739         struct p6pmc_descr *pd;
 740
 741         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 742             ("[p6,%d] illegal CPU %d", __LINE__, cpu));
 743         KASSERT(ri >= 0 && ri < P6_NPMCS,
 744             ("[p6,%d] row-index %d out of range", __LINE__, ri));
 745
 746         phw = pmc_pcpu[cpu]->pc_hwpmcs[ri];
 747         pd  = &p6_pmcdesc[ri];
 748
 749         KASSERT(phw == &p6_pcpu[cpu]->pc_p6pmcs[ri],
 750             ("[p6,%d] phw mismatch", __LINE__));
 751
 752         if ((error = copystr(pd->pm_descr.pd_name, pi->pm_name,
 753                  PMC_NAME_MAX, &copied)) != 0)
 754                 return (error);
 755
 756         pi->pm_class = pd->pm_descr.pd_class;
 757
 758         if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
 759                 pi->pm_enabled = TRUE;
 760                 *ppmc          = phw->phw_pmc;
 761         } else {
 762                 pi->pm_enabled = FALSE;
 763                 *ppmc          = NULL;
 764         }
 765
 766         return (0);
 767 }
 768
 769 static int
 770 p6_get_msr(int ri, uint32_t *msr)
 771 {
 772         KASSERT(ri >= 0 && ri < P6_NPMCS,
 773             ("[p6,%d ri %d out of range", __LINE__, ri));
 774
 775         *msr = p6_pmcdesc[ri].pm_pmc_msr - P6_MSR_PERFCTR0;
 776
 777         return (0);
 778 }
 779
 780 int
 781 pmc_p6_initialize(struct pmc_mdep *md, int ncpus)
 782 {
 783         struct pmc_classdep *pcd;
 784
 785         KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL,
 786             ("[p6,%d] Initializing non-intel processor", __LINE__));
 787
 788         PMCDBG(MDP,INI,1, "%s", "p6-initialize");
 789
 790         /* Allocate space for pointers to per-cpu descriptors. */
 791         p6_pcpu = malloc(sizeof(struct p6_cpu **) * ncpus, M_PMC,
 792             M_ZERO|M_WAITOK);
 793
 794         /* Fill in the class dependent descriptor. */
 795         pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_P6];
 796
 797         switch (md->pmd_cputype) {
 798
 799                 /*
 800                  * P6 Family Processors
 801                  */
 802         case PMC_CPU_INTEL_P6:
 803         case PMC_CPU_INTEL_CL:
 804         case PMC_CPU_INTEL_PII:
 805         case PMC_CPU_INTEL_PIII:
 806         case PMC_CPU_INTEL_PM:
 807
 808                 p6_cputype = md->pmd_cputype;
 809
 810                 pcd->pcd_caps           = P6_PMC_CAPS;
 811                 pcd->pcd_class          = PMC_CLASS_P6;
 812                 pcd->pcd_num            = P6_NPMCS;
 813                 pcd->pcd_ri             = md->pmd_npmc;
 814                 pcd->pcd_width          = 40;
 815
 816                 pcd->pcd_allocate_pmc   = p6_allocate_pmc;
 817                 pcd->pcd_config_pmc     = p6_config_pmc;
 818                 pcd->pcd_describe       = p6_describe;
 819                 pcd->pcd_get_config     = p6_get_config;
 820                 pcd->pcd_get_msr        = p6_get_msr;
 821                 pcd->pcd_pcpu_fini      = p6_pcpu_fini;
 822                 pcd->pcd_pcpu_init      = p6_pcpu_init;
 823                 pcd->pcd_read_pmc       = p6_read_pmc;
 824                 pcd->pcd_release_pmc    = p6_release_pmc;
 825                 pcd->pcd_start_pmc      = p6_start_pmc;
 826                 pcd->pcd_stop_pmc       = p6_stop_pmc;
 827                 pcd->pcd_write_pmc      = p6_write_pmc;
 828
 829                 md->pmd_pcpu_fini       = NULL;
 830                 md->pmd_pcpu_init       = NULL;
 831                 md->pmd_intr            = p6_intr;
 832
 833                 md->pmd_npmc           += P6_NPMCS;
 834
 835                 break;
 836
 837         default:
 838                 KASSERT(0,("[p6,%d] Unknown CPU type", __LINE__));
 839                 return ENOSYS;
 840         }
 841
 842         return (0);
 843 }
 844
 845 void
 846 pmc_p6_finalize(struct pmc_mdep *md)
 847 {
 848 #if     defined(INVARIANTS)
 849         int i, ncpus;
 850 #endif
 851
 852         KASSERT(p6_pcpu != NULL, ("[p6,%d] NULL p6_pcpu", __LINE__));
 853
 854 #if     defined(INVARIANTS)
 855         ncpus = pmc_cpu_max();
 856         for (i = 0; i < ncpus; i++)
 857                 KASSERT(p6_pcpu[i] == NULL, ("[p6,%d] non-null pcpu %d",
 858                     __LINE__, i));
 859 #endif
 860
 861         free(p6_pcpu, M_PMC);
 862         p6_pcpu = NULL;
 863 }