1 /******************************************************************************
3 Copyright (c) 2001-2009, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
38 #include <sys/types.h>
39 #include <sys/param.h>
40 #include <sys/systm.h>
42 #include <sys/protosw.h>
43 #include <sys/socket.h>
44 #include <sys/malloc.h>
45 #include <sys/kernel.h>
47 #include <machine/bus.h>
49 #include <machine/resource.h>
52 #include <machine/clock.h>
53 #include <dev/pci/pcivar.h>
54 #include <dev/pci/pcireg.h>
56 #define ASSERT(x) if(!(x)) panic("IXGBE: x")
58 /* The happy-fun DELAY macro is defined in /usr/src/sys/i386/include/clock.h */
59 #define usec_delay(x) DELAY(x)
60 #define msec_delay(x) DELAY(1000*(x))
63 #define MSGOUT(S, A, B) printf(S "\n", A, B)
64 #define DEBUGFUNC(F) DEBUGOUT(F);
66 #define DEBUGOUT(S) printf(S "\n")
67 #define DEBUGOUT1(S,A) printf(S "\n",A)
68 #define DEBUGOUT2(S,A,B) printf(S "\n",A,B)
69 #define DEBUGOUT3(S,A,B,C) printf(S "\n",A,B,C)
70 #define DEBUGOUT7(S,A,B,C,D,E,F,G) printf(S "\n",A,B,C,D,E,F,G)
73 #define DEBUGOUT1(S,A)
74 #define DEBUGOUT2(S,A,B)
75 #define DEBUGOUT3(S,A,B,C)
76 #define DEBUGOUT6(S,A,B,C,D,E,F)
77 #define DEBUGOUT7(S,A,B,C,D,E,F,G)
81 #define false 0 /* shared code requires this */
84 #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */
85 #define PCI_COMMAND_REGISTER PCIR_COMMAND
86 #define UNREFERENCED_PARAMETER(_p)
89 #define IXGBE_HTONL htonl
97 typedef boolean_t bool;
101 #if __FreeBSD_version < 800000
102 #if defined(__i386__) || defined(__amd64__)
103 #define mb() __asm volatile("mfence" ::: "memory")
104 #define wmb() __asm volatile("sfence" ::: "memory")
105 #define rmb() __asm volatile("lfence" ::: "memory")
115 bus_space_tag_t mem_bus_space_tag;
116 bus_space_handle_t mem_bus_space_handle;
120 /* These routines are needed by the shared code */
122 extern u16 ixgbe_read_pci_cfg(struct ixgbe_hw *, u32);
123 #define IXGBE_READ_PCIE_WORD ixgbe_read_pci_cfg
125 extern void ixgbe_write_pci_cfg(struct ixgbe_hw *, u32, u16);
126 #define IXGBE_WRITE_PCIE_WORD ixgbe_write_pci_cfg
128 #define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS)
130 #define IXGBE_READ_REG(a, reg) (\
131 bus_space_read_4( ((struct ixgbe_osdep *)(a)->back)->mem_bus_space_tag, \
132 ((struct ixgbe_osdep *)(a)->back)->mem_bus_space_handle, \
135 #define IXGBE_WRITE_REG(a, reg, value) (\
136 bus_space_write_4( ((struct ixgbe_osdep *)(a)->back)->mem_bus_space_tag, \
137 ((struct ixgbe_osdep *)(a)->back)->mem_bus_space_handle, \
141 #define IXGBE_READ_REG_ARRAY(a, reg, offset) (\
142 bus_space_read_4( ((struct ixgbe_osdep *)(a)->back)->mem_bus_space_tag, \
143 ((struct ixgbe_osdep *)(a)->back)->mem_bus_space_handle, \
144 (reg + ((offset) << 2))))
146 #define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) (\
147 bus_space_write_4( ((struct ixgbe_osdep *)(a)->back)->mem_bus_space_tag, \
148 ((struct ixgbe_osdep *)(a)->back)->mem_bus_space_handle, \
149 (reg + ((offset) << 2)), value))
152 #endif /* _IXGBE_OS_H_ */