1 /******************************************************************************
3 Copyright (c) 2001-2009, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 #include "ixgbe_api.h"
36 #include "ixgbe_common.h"
37 #include "ixgbe_phy.h"
39 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
40 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
41 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
42 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
43 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
44 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
45 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
46 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
49 static bool ixgbe_get_i2c_data(u32 *i2cctl);
50 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
53 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
54 * @hw: pointer to the hardware structure
56 * Initialize the function pointers.
58 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
60 struct ixgbe_phy_info *phy = &hw->phy;
63 phy->ops.identify = &ixgbe_identify_phy_generic;
64 phy->ops.reset = &ixgbe_reset_phy_generic;
65 phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
66 phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
67 phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
68 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
69 phy->ops.check_link = NULL;
70 phy->ops.get_firmware_version = NULL;
71 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
72 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
73 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
74 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
75 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
76 phy->ops.identify_sfp = &ixgbe_identify_sfp_module_generic;
77 phy->sfp_type = ixgbe_sfp_type_unknown;
83 * ixgbe_identify_phy_generic - Get physical layer module
84 * @hw: pointer to hardware structure
86 * Determines the physical layer module found on the current adapter.
88 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
90 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
94 if (hw->phy.type == ixgbe_phy_unknown) {
95 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
96 if (ixgbe_validate_phy_addr(hw, phy_addr)) {
97 hw->phy.addr = phy_addr;
100 ixgbe_get_phy_type_from_id(hw->phy.id);
102 if (hw->phy.type == ixgbe_phy_unknown) {
103 hw->phy.ops.read_reg(hw,
104 IXGBE_MDIO_PHY_EXT_ABILITY,
105 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
108 IXGBE_MDIO_PHY_10GBASET_ABILITY ||
110 IXGBE_MDIO_PHY_1000BASET_ABILITY)
112 ixgbe_phy_cu_unknown;
118 status = IXGBE_SUCCESS;
122 if (status != IXGBE_SUCCESS)
125 status = IXGBE_SUCCESS;
132 * ixgbe_validate_phy_addr - Determines phy address is valid
133 * @hw: pointer to hardware structure
136 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
141 hw->phy.addr = phy_addr;
142 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
143 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
145 if (phy_id != 0xFFFF && phy_id != 0x0)
152 * ixgbe_get_phy_id - Get the phy type
153 * @hw: pointer to hardware structure
156 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
162 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
163 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
166 if (status == IXGBE_SUCCESS) {
167 hw->phy.id = (u32)(phy_id_high << 16);
168 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
169 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
171 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
172 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
178 * ixgbe_get_phy_type_from_id - Get the phy type
179 * @hw: pointer to hardware structure
182 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
184 enum ixgbe_phy_type phy_type;
188 phy_type = ixgbe_phy_tn;
191 phy_type = ixgbe_phy_aq;
194 phy_type = ixgbe_phy_qt;
197 phy_type = ixgbe_phy_nl;
200 phy_type = ixgbe_phy_unknown;
204 DEBUGOUT1("phy type found is %d\n", phy_type);
209 * ixgbe_reset_phy_generic - Performs a PHY reset
210 * @hw: pointer to hardware structure
212 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
216 s32 status = IXGBE_SUCCESS;
218 if (hw->phy.type == ixgbe_phy_unknown)
219 status = ixgbe_identify_phy_generic(hw);
221 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
225 * Perform soft PHY reset to the PHY_XS.
226 * This will cause a soft reset to the PHY
228 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
229 IXGBE_MDIO_PHY_XS_DEV_TYPE,
230 IXGBE_MDIO_PHY_XS_RESET);
232 /* Poll for reset bit to self-clear indicating reset is complete */
233 for (i = 0; i < 500; i++) {
235 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
236 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
237 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET))
241 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
242 status = IXGBE_ERR_RESET_FAILED;
243 DEBUGOUT("PHY reset polling failed to complete.\n");
251 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
252 * @hw: pointer to hardware structure
253 * @reg_addr: 32 bit address of PHY register to read
254 * @phy_data: Pointer to read data from PHY register
256 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
257 u32 device_type, u16 *phy_data)
262 s32 status = IXGBE_SUCCESS;
265 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
266 gssr = IXGBE_GSSR_PHY1_SM;
268 gssr = IXGBE_GSSR_PHY0_SM;
270 if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
271 status = IXGBE_ERR_SWFW_SYNC;
273 if (status == IXGBE_SUCCESS) {
274 /* Setup and write the address cycle command */
275 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
276 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
277 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
278 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
280 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
283 * Check every 10 usec to see if the address cycle completed.
284 * The MDI Command bit will clear when the operation is
287 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
290 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
292 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
296 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
297 DEBUGOUT("PHY address command did not complete.\n");
298 status = IXGBE_ERR_PHY;
301 if (status == IXGBE_SUCCESS) {
303 * Address cycle complete, setup and write the read
306 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
307 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
308 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
309 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
311 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
314 * Check every 10 usec to see if the address cycle
315 * completed. The MDI Command bit will clear when the
316 * operation is complete
318 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
321 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
323 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
327 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
328 DEBUGOUT("PHY read command didn't complete\n");
329 status = IXGBE_ERR_PHY;
332 * Read operation is complete. Get the data
335 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
336 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
337 *phy_data = (u16)(data);
341 ixgbe_release_swfw_sync(hw, gssr);
348 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
349 * @hw: pointer to hardware structure
350 * @reg_addr: 32 bit PHY register to write
351 * @device_type: 5 bit device type
352 * @phy_data: Data to write to the PHY register
354 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
355 u32 device_type, u16 phy_data)
359 s32 status = IXGBE_SUCCESS;
362 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
363 gssr = IXGBE_GSSR_PHY1_SM;
365 gssr = IXGBE_GSSR_PHY0_SM;
367 if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
368 status = IXGBE_ERR_SWFW_SYNC;
370 if (status == IXGBE_SUCCESS) {
371 /* Put the data in the MDI single read and write data register*/
372 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
374 /* Setup and write the address cycle command */
375 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
376 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
377 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
378 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
380 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
383 * Check every 10 usec to see if the address cycle completed.
384 * The MDI Command bit will clear when the operation is
387 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
390 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
392 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
396 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
397 DEBUGOUT("PHY address cmd didn't complete\n");
398 status = IXGBE_ERR_PHY;
401 if (status == IXGBE_SUCCESS) {
403 * Address cycle complete, setup and write the write
406 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
407 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
408 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
409 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
411 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
414 * Check every 10 usec to see if the address cycle
415 * completed. The MDI Command bit will clear when the
416 * operation is complete
418 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
421 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
423 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
427 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
428 DEBUGOUT("PHY address cmd didn't complete\n");
429 status = IXGBE_ERR_PHY;
433 ixgbe_release_swfw_sync(hw, gssr);
440 * ixgbe_setup_phy_link_generic - Set and restart autoneg
441 * @hw: pointer to hardware structure
443 * Restart autonegotiation and PHY and waits for completion.
445 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
447 s32 status = IXGBE_SUCCESS;
449 u32 max_time_out = 10;
450 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
453 * Set advertisement settings in PHY based on autoneg_advertised
454 * settings. If autoneg_advertised = 0, then advertise default values
455 * tnx devices cannot be "forced" to a autoneg 10G and fail. But can
458 hw->phy.ops.read_reg(hw, IXGBE_MII_SPEED_SELECTION_REG,
459 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
461 if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
462 autoneg_reg &= 0xEFFF; /* 0 in bit 12 is 1G operation */
464 autoneg_reg |= 0x1000; /* 1 in bit 12 is 10G/1G operation */
466 hw->phy.ops.write_reg(hw, IXGBE_MII_SPEED_SELECTION_REG,
467 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
469 /* Restart PHY autonegotiation and wait for completion */
470 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
471 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
473 autoneg_reg |= IXGBE_MII_RESTART;
475 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
476 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
478 /* Wait for autonegotiation to finish */
479 for (time_out = 0; time_out < max_time_out; time_out++) {
481 /* Restart PHY autonegotiation and wait for completion */
482 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
483 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
486 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
487 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) {
492 if (time_out == max_time_out)
493 status = IXGBE_ERR_LINK_SETUP;
499 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
500 * @hw: pointer to hardware structure
501 * @speed: new link speed
502 * @autoneg: TRUE if autonegotiation enabled
504 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
505 ixgbe_link_speed speed,
507 bool autoneg_wait_to_complete)
509 UNREFERENCED_PARAMETER(autoneg);
510 UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
513 * Clear autoneg_advertised and set new values based on input link
516 hw->phy.autoneg_advertised = 0;
518 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
519 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
521 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
522 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
524 if (speed & IXGBE_LINK_SPEED_100_FULL)
525 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
527 /* Setup link based on the new speed settings */
528 hw->phy.ops.setup_link(hw);
530 return IXGBE_SUCCESS;
534 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
535 * @hw: pointer to hardware structure
536 * @speed: pointer to link speed
537 * @autoneg: boolean auto-negotiation value
539 * Determines the link capabilities by reading the AUTOC register.
541 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
542 ixgbe_link_speed *speed,
545 s32 status = IXGBE_ERR_LINK_SETUP;
551 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
552 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
555 if (status == IXGBE_SUCCESS) {
556 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
557 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
558 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
559 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
560 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
561 *speed |= IXGBE_LINK_SPEED_100_FULL;
568 * ixgbe_check_phy_link_tnx - Determine link and speed status
569 * @hw: pointer to hardware structure
571 * Reads the VS1 register to determine if link is up and the current speed for
574 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
577 s32 status = IXGBE_SUCCESS;
579 u32 max_time_out = 10;
584 /* Initialize speed and link to default case */
586 *speed = IXGBE_LINK_SPEED_10GB_FULL;
589 * Check current speed and link status of the PHY register.
590 * This is a vendor specific register and may have to
591 * be changed for other copper PHYs.
593 for (time_out = 0; time_out < max_time_out; time_out++) {
595 status = hw->phy.ops.read_reg(hw,
596 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
597 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
599 phy_link = phy_data &
600 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
601 phy_speed = phy_data &
602 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
603 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
606 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
607 *speed = IXGBE_LINK_SPEED_1GB_FULL;
616 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
617 * @hw: pointer to hardware structure
618 * @firmware_version: pointer to the PHY Firmware Version
620 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
621 u16 *firmware_version)
623 s32 status = IXGBE_SUCCESS;
625 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
626 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
634 * ixgbe_get_phy_firmware_version_aq - Gets the PHY Firmware Version
635 * @hw: pointer to hardware structure
636 * @firmware_version: pointer to the PHY Firmware Version
638 s32 ixgbe_get_phy_firmware_version_aq(struct ixgbe_hw *hw,
639 u16 *firmware_version)
641 s32 status = IXGBE_SUCCESS;
643 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
644 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
651 * ixgbe_reset_phy_nl - Performs a PHY reset
652 * @hw: pointer to hardware structure
654 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
656 u16 phy_offset, control, eword, edata, block_crc;
657 bool end_data = FALSE;
658 u16 list_offset, data_offset;
660 s32 ret_val = IXGBE_SUCCESS;
663 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
664 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
666 /* reset the PHY and poll for completion */
667 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
668 IXGBE_MDIO_PHY_XS_DEV_TYPE,
669 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
671 for (i = 0; i < 100; i++) {
672 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
673 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
674 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
679 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
680 DEBUGOUT("PHY reset did not complete.\n");
681 ret_val = IXGBE_ERR_PHY;
685 /* Get init offsets */
686 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
688 if (ret_val != IXGBE_SUCCESS)
691 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
695 * Read control word from PHY init contents offset
697 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
698 control = (eword & IXGBE_CONTROL_MASK_NL) >>
699 IXGBE_CONTROL_SHIFT_NL;
700 edata = eword & IXGBE_DATA_MASK_NL;
704 DEBUGOUT1("DELAY: %d MS\n", edata);
708 DEBUGOUT("DATA: \n");
710 hw->eeprom.ops.read(hw, data_offset++,
712 for (i = 0; i < edata; i++) {
713 hw->eeprom.ops.read(hw, data_offset, &eword);
714 hw->phy.ops.write_reg(hw, phy_offset,
715 IXGBE_TWINAX_DEV, eword);
716 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
722 case IXGBE_CONTROL_NL:
724 DEBUGOUT("CONTROL: \n");
725 if (edata == IXGBE_CONTROL_EOL_NL) {
728 } else if (edata == IXGBE_CONTROL_SOL_NL) {
731 DEBUGOUT("Bad control value\n");
732 ret_val = IXGBE_ERR_PHY;
737 DEBUGOUT("Bad control type\n");
738 ret_val = IXGBE_ERR_PHY;
748 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
749 * @hw: pointer to hardware structure
751 * Searches for and identifies the SFP module and assigns appropriate PHY type.
753 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
755 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
757 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
759 u8 comp_codes_1g = 0;
760 u8 comp_codes_10g = 0;
761 u8 oui_bytes[3] = {0, 0, 0};
765 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
766 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
767 status = IXGBE_ERR_SFP_NOT_PRESENT;
771 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
774 if (status == IXGBE_ERR_SFP_NOT_PRESENT || status == IXGBE_ERR_I2C) {
775 status = IXGBE_ERR_SFP_NOT_PRESENT;
776 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
777 if (hw->phy.type != ixgbe_phy_nl) {
779 hw->phy.type = ixgbe_phy_unknown;
784 /* LAN ID is needed for sfp_type determination */
785 hw->mac.ops.set_lan_id(hw);
787 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
788 hw->phy.type = ixgbe_phy_sfp_unsupported;
789 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
791 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES,
793 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES,
795 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_CABLE_TECHNOLOGY,
803 * 3 SFP_DA_CORE0 - 82599-specific
804 * 4 SFP_DA_CORE1 - 82599-specific
805 * 5 SFP_SR/LR_CORE0 - 82599-specific
806 * 6 SFP_SR/LR_CORE1 - 82599-specific
808 if (hw->mac.type == ixgbe_mac_82598EB) {
809 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
810 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
811 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
812 hw->phy.sfp_type = ixgbe_sfp_type_sr;
813 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
814 hw->phy.sfp_type = ixgbe_sfp_type_lr;
816 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
817 } else if (hw->mac.type == ixgbe_mac_82599EB) {
818 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
819 if (hw->bus.lan_id == 0)
821 ixgbe_sfp_type_da_cu_core0;
824 ixgbe_sfp_type_da_cu_core1;
825 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
826 if (hw->bus.lan_id == 0)
828 ixgbe_sfp_type_srlr_core0;
831 ixgbe_sfp_type_srlr_core1;
832 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
833 if (hw->bus.lan_id == 0)
835 ixgbe_sfp_type_srlr_core0;
838 ixgbe_sfp_type_srlr_core1;
840 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
843 if (hw->phy.sfp_type != stored_sfp_type)
844 hw->phy.sfp_setup_needed = TRUE;
846 /* Determine if the SFP+ PHY is dual speed or not. */
847 hw->phy.multispeed_fiber = FALSE;
848 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
849 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
850 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
851 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
852 hw->phy.multispeed_fiber = TRUE;
853 /* Determine PHY vendor */
854 if (hw->phy.type != ixgbe_phy_nl) {
855 hw->phy.id = identifier;
856 hw->phy.ops.read_i2c_eeprom(hw,
857 IXGBE_SFF_VENDOR_OUI_BYTE0,
859 hw->phy.ops.read_i2c_eeprom(hw,
860 IXGBE_SFF_VENDOR_OUI_BYTE1,
862 hw->phy.ops.read_i2c_eeprom(hw,
863 IXGBE_SFF_VENDOR_OUI_BYTE2,
867 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
868 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
869 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
871 switch (vendor_oui) {
872 case IXGBE_SFF_VENDOR_OUI_TYCO:
873 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
874 hw->phy.type = ixgbe_phy_tw_tyco;
876 case IXGBE_SFF_VENDOR_OUI_FTL:
877 hw->phy.type = ixgbe_phy_sfp_ftl;
879 case IXGBE_SFF_VENDOR_OUI_AVAGO:
880 hw->phy.type = ixgbe_phy_sfp_avago;
882 case IXGBE_SFF_VENDOR_OUI_INTEL:
883 hw->phy.type = ixgbe_phy_sfp_intel;
886 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
887 hw->phy.type = ixgbe_phy_tw_unknown;
889 hw->phy.type = ixgbe_phy_sfp_unknown;
894 /* All passive DA cables are supported */
895 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
896 status = IXGBE_SUCCESS;
900 /* 1G SFP modules are not supported */
901 if (comp_codes_10g == 0) {
902 hw->phy.type = ixgbe_phy_sfp_unsupported;
903 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
907 /* Anything else 82598-based is supported */
908 if (hw->mac.type == ixgbe_mac_82598EB) {
909 status = IXGBE_SUCCESS;
913 ixgbe_get_device_caps(hw, &enforce_sfp);
914 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
915 /* Make sure we're a supported PHY type */
916 if (hw->phy.type == ixgbe_phy_sfp_intel) {
917 status = IXGBE_SUCCESS;
919 DEBUGOUT("SFP+ module not supported\n");
920 hw->phy.type = ixgbe_phy_sfp_unsupported;
921 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
924 status = IXGBE_SUCCESS;
933 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
934 * @hw: pointer to hardware structure
935 * @list_offset: offset to the SFP ID list
936 * @data_offset: offset to the SFP data block
938 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
939 * so it returns the offsets to the phy init sequence block.
941 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
947 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
948 return IXGBE_ERR_SFP_NOT_SUPPORTED;
950 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
951 return IXGBE_ERR_SFP_NOT_PRESENT;
953 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
954 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
955 return IXGBE_ERR_SFP_NOT_SUPPORTED;
957 /* Read offset to PHY init contents */
958 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
960 if ((!*list_offset) || (*list_offset == 0xFFFF))
961 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
963 /* Shift offset to first ID word */
967 * Find the matching SFP ID in the EEPROM
968 * and program the init sequence
970 hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
972 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
973 if (sfp_id == hw->phy.sfp_type) {
975 hw->eeprom.ops.read(hw, *list_offset, data_offset);
976 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
977 DEBUGOUT("SFP+ module not supported\n");
978 return IXGBE_ERR_SFP_NOT_SUPPORTED;
984 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
985 return IXGBE_ERR_PHY;
989 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
990 DEBUGOUT("No matching SFP+ module found\n");
991 return IXGBE_ERR_SFP_NOT_SUPPORTED;
994 return IXGBE_SUCCESS;
998 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
999 * @hw: pointer to hardware structure
1000 * @byte_offset: EEPROM byte offset to read
1001 * @eeprom_data: value read
1003 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1005 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1008 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1010 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1011 IXGBE_I2C_EEPROM_DEV_ADDR,
1016 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1017 * @hw: pointer to hardware structure
1018 * @byte_offset: EEPROM byte offset to write
1019 * @eeprom_data: value to write
1021 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1023 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1026 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1028 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1029 IXGBE_I2C_EEPROM_DEV_ADDR,
1034 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1035 * @hw: pointer to hardware structure
1036 * @byte_offset: byte offset to read
1039 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1040 * a specified deivce address.
1042 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1043 u8 dev_addr, u8 *data)
1045 s32 status = IXGBE_SUCCESS;
1051 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1053 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1054 swfw_mask = IXGBE_GSSR_PHY1_SM;
1056 swfw_mask = IXGBE_GSSR_PHY0_SM;
1060 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
1061 status = IXGBE_ERR_SWFW_SYNC;
1065 ixgbe_i2c_start(hw);
1067 /* Device Address and write indication */
1068 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1069 if (status != IXGBE_SUCCESS)
1072 status = ixgbe_get_i2c_ack(hw);
1073 if (status != IXGBE_SUCCESS)
1076 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1077 if (status != IXGBE_SUCCESS)
1080 status = ixgbe_get_i2c_ack(hw);
1081 if (status != IXGBE_SUCCESS)
1084 ixgbe_i2c_start(hw);
1086 /* Device Address and read indication */
1087 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1088 if (status != IXGBE_SUCCESS)
1091 status = ixgbe_get_i2c_ack(hw);
1092 if (status != IXGBE_SUCCESS)
1095 status = ixgbe_clock_in_i2c_byte(hw, data);
1096 if (status != IXGBE_SUCCESS)
1099 status = ixgbe_clock_out_i2c_bit(hw, nack);
1100 if (status != IXGBE_SUCCESS)
1107 ixgbe_release_swfw_sync(hw, swfw_mask);
1109 ixgbe_i2c_bus_clear(hw);
1111 if (retry < max_retry)
1112 DEBUGOUT("I2C byte read error - Retrying.\n");
1114 DEBUGOUT("I2C byte read error.\n");
1116 } while (retry < max_retry);
1118 ixgbe_release_swfw_sync(hw, swfw_mask);
1125 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1126 * @hw: pointer to hardware structure
1127 * @byte_offset: byte offset to write
1128 * @data: value to write
1130 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1131 * a specified device address.
1133 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1134 u8 dev_addr, u8 data)
1136 s32 status = IXGBE_SUCCESS;
1141 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
1143 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1144 swfw_mask = IXGBE_GSSR_PHY1_SM;
1146 swfw_mask = IXGBE_GSSR_PHY0_SM;
1148 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
1149 status = IXGBE_ERR_SWFW_SYNC;
1150 goto write_byte_out;
1154 ixgbe_i2c_start(hw);
1156 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1157 if (status != IXGBE_SUCCESS)
1160 status = ixgbe_get_i2c_ack(hw);
1161 if (status != IXGBE_SUCCESS)
1164 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1165 if (status != IXGBE_SUCCESS)
1168 status = ixgbe_get_i2c_ack(hw);
1169 if (status != IXGBE_SUCCESS)
1172 status = ixgbe_clock_out_i2c_byte(hw, data);
1173 if (status != IXGBE_SUCCESS)
1176 status = ixgbe_get_i2c_ack(hw);
1177 if (status != IXGBE_SUCCESS)
1184 ixgbe_i2c_bus_clear(hw);
1186 if (retry < max_retry)
1187 DEBUGOUT("I2C byte write error - Retrying.\n");
1189 DEBUGOUT("I2C byte write error.\n");
1190 } while (retry < max_retry);
1192 ixgbe_release_swfw_sync(hw, swfw_mask);
1199 * ixgbe_i2c_start - Sets I2C start condition
1200 * @hw: pointer to hardware structure
1202 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1204 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1206 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1208 DEBUGFUNC("ixgbe_i2c_start");
1210 /* Start condition must begin with data and clock high */
1211 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1212 ixgbe_raise_i2c_clk(hw, &i2cctl);
1214 /* Setup time for start condition (4.7us) */
1215 usec_delay(IXGBE_I2C_T_SU_STA);
1217 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1219 /* Hold time for start condition (4us) */
1220 usec_delay(IXGBE_I2C_T_HD_STA);
1222 ixgbe_lower_i2c_clk(hw, &i2cctl);
1224 /* Minimum low period of clock is 4.7 us */
1225 usec_delay(IXGBE_I2C_T_LOW);
1230 * ixgbe_i2c_stop - Sets I2C stop condition
1231 * @hw: pointer to hardware structure
1233 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1235 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1237 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1239 DEBUGFUNC("ixgbe_i2c_stop");
1241 /* Stop condition must begin with data low and clock high */
1242 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1243 ixgbe_raise_i2c_clk(hw, &i2cctl);
1245 /* Setup time for stop condition (4us) */
1246 usec_delay(IXGBE_I2C_T_SU_STO);
1248 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1250 /* bus free time between stop and start (4.7us)*/
1251 usec_delay(IXGBE_I2C_T_BUF);
1255 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1256 * @hw: pointer to hardware structure
1257 * @data: data byte to clock in
1259 * Clocks in one byte data via I2C data/clock
1261 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1263 s32 status = IXGBE_SUCCESS;
1267 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
1269 for (i = 7; i >= 0; i--) {
1270 status = ixgbe_clock_in_i2c_bit(hw, &bit);
1273 if (status != IXGBE_SUCCESS)
1281 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1282 * @hw: pointer to hardware structure
1283 * @data: data byte clocked out
1285 * Clocks out one byte data via I2C data/clock
1287 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1289 s32 status = IXGBE_SUCCESS;
1294 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
1296 for (i = 7; i >= 0; i--) {
1297 bit = (data >> i) & 0x1;
1298 status = ixgbe_clock_out_i2c_bit(hw, bit);
1300 if (status != IXGBE_SUCCESS)
1304 /* Release SDA line (set high) */
1305 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1306 i2cctl |= IXGBE_I2C_DATA_OUT;
1307 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1313 * ixgbe_get_i2c_ack - Polls for I2C ACK
1314 * @hw: pointer to hardware structure
1316 * Clocks in/out one bit via I2C data/clock
1318 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1322 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1326 DEBUGFUNC("ixgbe_get_i2c_ack");
1328 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1330 if (status != IXGBE_SUCCESS)
1333 /* Minimum high period of clock is 4us */
1334 usec_delay(IXGBE_I2C_T_HIGH);
1336 /* Poll for ACK. Note that ACK in I2C spec is
1337 * transition from 1 to 0 */
1338 for (i = 0; i < timeout; i++) {
1339 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1340 ack = ixgbe_get_i2c_data(&i2cctl);
1348 DEBUGOUT("I2C ack was not received.\n");
1349 status = IXGBE_ERR_I2C;
1352 ixgbe_lower_i2c_clk(hw, &i2cctl);
1354 /* Minimum low period of clock is 4.7 us */
1355 usec_delay(IXGBE_I2C_T_LOW);
1362 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1363 * @hw: pointer to hardware structure
1364 * @data: read data value
1366 * Clocks in one bit via I2C data/clock
1368 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1371 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1373 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1375 /* Minimum high period of clock is 4us */
1376 usec_delay(IXGBE_I2C_T_HIGH);
1378 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1379 *data = ixgbe_get_i2c_data(&i2cctl);
1381 ixgbe_lower_i2c_clk(hw, &i2cctl);
1383 /* Minimum low period of clock is 4.7 us */
1384 usec_delay(IXGBE_I2C_T_LOW);
1390 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1391 * @hw: pointer to hardware structure
1392 * @data: data value to write
1394 * Clocks out one bit via I2C data/clock
1396 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1399 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1401 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1402 if (status == IXGBE_SUCCESS) {
1403 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1405 /* Minimum high period of clock is 4us */
1406 usec_delay(IXGBE_I2C_T_HIGH);
1408 ixgbe_lower_i2c_clk(hw, &i2cctl);
1410 /* Minimum low period of clock is 4.7 us.
1411 * This also takes care of the data hold time.
1413 usec_delay(IXGBE_I2C_T_LOW);
1415 status = IXGBE_ERR_I2C;
1416 DEBUGOUT1("I2C data was not set to %X\n", data);
1422 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1423 * @hw: pointer to hardware structure
1424 * @i2cctl: Current value of I2CCTL register
1426 * Raises the I2C clock line '0'->'1'
1428 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1430 s32 status = IXGBE_SUCCESS;
1432 *i2cctl |= IXGBE_I2C_CLK_OUT;
1434 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1436 /* SCL rise time (1000ns) */
1437 usec_delay(IXGBE_I2C_T_RISE);
1443 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1444 * @hw: pointer to hardware structure
1445 * @i2cctl: Current value of I2CCTL register
1447 * Lowers the I2C clock line '1'->'0'
1449 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1452 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1454 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1456 /* SCL fall time (300ns) */
1457 usec_delay(IXGBE_I2C_T_FALL);
1461 * ixgbe_set_i2c_data - Sets the I2C data bit
1462 * @hw: pointer to hardware structure
1463 * @i2cctl: Current value of I2CCTL register
1464 * @data: I2C data value (0 or 1) to set
1466 * Sets the I2C data bit
1468 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1470 s32 status = IXGBE_SUCCESS;
1473 *i2cctl |= IXGBE_I2C_DATA_OUT;
1475 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1477 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1479 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1480 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1482 /* Verify data was set correctly */
1483 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1484 if (data != ixgbe_get_i2c_data(i2cctl)) {
1485 status = IXGBE_ERR_I2C;
1486 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
1493 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1494 * @hw: pointer to hardware structure
1495 * @i2cctl: Current value of I2CCTL register
1497 * Returns the I2C data bit value
1499 static bool ixgbe_get_i2c_data(u32 *i2cctl)
1503 if (*i2cctl & IXGBE_I2C_DATA_IN)
1512 * ixgbe_i2c_bus_clear - Clears the I2C bus
1513 * @hw: pointer to hardware structure
1515 * Clears the I2C bus by sending nine clock pulses.
1516 * Used when data line is stuck low.
1518 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1520 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1523 DEBUGFUNC("ixgbe_i2c_bus_clear");
1525 ixgbe_i2c_start(hw);
1527 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1529 for (i = 0; i < 9; i++) {
1530 ixgbe_raise_i2c_clk(hw, &i2cctl);
1532 /* Min high period of clock is 4us */
1533 usec_delay(IXGBE_I2C_T_HIGH);
1535 ixgbe_lower_i2c_clk(hw, &i2cctl);
1537 /* Min low period of clock is 4.7us*/
1538 usec_delay(IXGBE_I2C_T_LOW);
1541 ixgbe_i2c_start(hw);
1543 /* Put the i2c bus back to default state */