2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/linker.h>
39 #include <sys/fcntl.h>
41 #include <sys/kernel.h>
42 #include <sys/queue.h>
43 #include <sys/sysctl.h>
44 #include <sys/endian.h>
48 #include <vm/vm_extern.h>
51 #include <machine/bus.h>
53 #include <machine/resource.h>
54 #include <machine/stdarg.h>
56 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
57 #include <machine/intr_machdep.h>
60 #include <sys/pciio.h>
61 #include <dev/pci/pcireg.h>
62 #include <dev/pci/pcivar.h>
63 #include <dev/pci/pci_private.h>
65 #include <dev/usb/controller/ehcireg.h>
66 #include <dev/usb/controller/ohcireg.h>
67 #include <dev/usb/controller/uhcireg.h>
73 #include <contrib/dev/acpica/include/acpi.h>
76 #define ACPI_PWR_FOR_SLEEP(x, y, z)
79 static pci_addr_t pci_mapbase(uint64_t mapreg);
80 static const char *pci_maptype(uint64_t mapreg);
81 static int pci_mapsize(uint64_t testval);
82 static int pci_maprange(uint64_t mapreg);
83 static void pci_fixancient(pcicfgregs *cfg);
84 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...);
86 static int pci_porten(device_t dev);
87 static int pci_memen(device_t dev);
88 static void pci_assign_interrupt(device_t bus, device_t dev,
90 static int pci_add_map(device_t bus, device_t dev, int reg,
91 struct resource_list *rl, int force, int prefetch);
92 static int pci_probe(device_t dev);
93 static int pci_attach(device_t dev);
94 static void pci_load_vendor_data(void);
95 static int pci_describe_parse_line(char **ptr, int *vendor,
96 int *device, char **desc);
97 static char *pci_describe_device(device_t dev);
98 static int pci_modevent(module_t mod, int what, void *arg);
99 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
101 static void pci_read_cap(device_t pcib, pcicfgregs *cfg);
102 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
103 int reg, uint32_t *data);
105 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
106 int reg, uint32_t data);
108 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
109 static void pci_disable_msi(device_t dev);
110 static void pci_enable_msi(device_t dev, uint64_t address,
112 static void pci_enable_msix(device_t dev, u_int index,
113 uint64_t address, uint32_t data);
114 static void pci_mask_msix(device_t dev, u_int index);
115 static void pci_unmask_msix(device_t dev, u_int index);
116 static int pci_msi_blacklisted(void);
117 static void pci_resume_msi(device_t dev);
118 static void pci_resume_msix(device_t dev);
119 static int pci_remap_intr_method(device_t bus, device_t dev,
122 static device_method_t pci_methods[] = {
123 /* Device interface */
124 DEVMETHOD(device_probe, pci_probe),
125 DEVMETHOD(device_attach, pci_attach),
126 DEVMETHOD(device_detach, bus_generic_detach),
127 DEVMETHOD(device_shutdown, bus_generic_shutdown),
128 DEVMETHOD(device_suspend, pci_suspend),
129 DEVMETHOD(device_resume, pci_resume),
132 DEVMETHOD(bus_print_child, pci_print_child),
133 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
134 DEVMETHOD(bus_read_ivar, pci_read_ivar),
135 DEVMETHOD(bus_write_ivar, pci_write_ivar),
136 DEVMETHOD(bus_driver_added, pci_driver_added),
137 DEVMETHOD(bus_setup_intr, pci_setup_intr),
138 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
140 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
141 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
142 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
143 DEVMETHOD(bus_delete_resource, pci_delete_resource),
144 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
145 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
146 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
147 DEVMETHOD(bus_activate_resource, pci_activate_resource),
148 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
149 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
150 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
151 DEVMETHOD(bus_remap_intr, pci_remap_intr_method),
154 DEVMETHOD(pci_read_config, pci_read_config_method),
155 DEVMETHOD(pci_write_config, pci_write_config_method),
156 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
157 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
158 DEVMETHOD(pci_enable_io, pci_enable_io_method),
159 DEVMETHOD(pci_disable_io, pci_disable_io_method),
160 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
161 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
162 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
163 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
164 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
165 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
166 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
167 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method),
168 DEVMETHOD(pci_remap_msix, pci_remap_msix_method),
169 DEVMETHOD(pci_release_msi, pci_release_msi_method),
170 DEVMETHOD(pci_msi_count, pci_msi_count_method),
171 DEVMETHOD(pci_msix_count, pci_msix_count_method),
176 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
178 static devclass_t pci_devclass;
179 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
180 MODULE_VERSION(pci, 1);
182 static char *pci_vendordata;
183 static size_t pci_vendordata_size;
187 uint32_t devid; /* Vendor/device of the card */
189 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
190 #define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */
191 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */
196 struct pci_quirk pci_quirks[] = {
197 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
198 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
199 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
200 /* As does the Serverworks OSB4 (the SMBus mapping register) */
201 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
204 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
205 * or the CMIC-SL (AKA ServerWorks GC_LE).
207 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
208 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
211 * MSI doesn't work on earlier Intel chipsets including
212 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
214 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
215 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
216 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
217 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
218 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
219 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
220 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
223 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
226 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
229 * Some virtualization environments emulate an older chipset
230 * but support MSI just fine. QEMU uses the Intel 82440.
232 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 },
237 /* map register information */
238 #define PCI_MAPMEM 0x01 /* memory map */
239 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
240 #define PCI_MAPPORT 0x04 /* port map */
242 struct devlist pci_devq;
243 uint32_t pci_generation;
244 uint32_t pci_numdevs = 0;
245 static int pcie_chipset, pcix_chipset;
248 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
250 static int pci_enable_io_modes = 1;
251 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
252 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
253 &pci_enable_io_modes, 1,
254 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
255 enable these bits correctly. We'd like to do this all the time, but there\n\
256 are some peripherals that this causes problems with.");
258 static int pci_do_power_nodriver = 0;
259 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
260 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
261 &pci_do_power_nodriver, 0,
262 "Place a function into D3 state when no driver attaches to it. 0 means\n\
263 disable. 1 means conservatively place devices into D3 state. 2 means\n\
264 agressively place devices into D3 state. 3 means put absolutely everything\n\
267 static int pci_do_power_resume = 1;
268 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
269 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
270 &pci_do_power_resume, 1,
271 "Transition from D3 -> D0 on resume.");
273 static int pci_do_msi = 1;
274 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
275 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
276 "Enable support for MSI interrupts");
278 static int pci_do_msix = 1;
279 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
280 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
281 "Enable support for MSI-X interrupts");
283 static int pci_honor_msi_blacklist = 1;
284 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
285 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
286 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI");
288 #if defined(__i386__) || defined(__amd64__)
289 static int pci_usb_takeover = 1;
291 static int pci_usb_takeover = 0;
293 TUNABLE_INT("hw.pci.usb_early_takeover", &pci_usb_takeover);
294 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RD | CTLFLAG_TUN,
295 &pci_usb_takeover, 1, "Enable early takeover of USB controllers.\n\
296 Disable this if you depend on BIOS emulation of USB devices, that is\n\
297 you use USB devices (like keyboard or mouse) but do not load USB drivers");
299 /* Find a device_t by bus/slot/function in domain 0 */
302 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
305 return (pci_find_dbsf(0, bus, slot, func));
308 /* Find a device_t by domain/bus/slot/function */
311 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
313 struct pci_devinfo *dinfo;
315 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
316 if ((dinfo->cfg.domain == domain) &&
317 (dinfo->cfg.bus == bus) &&
318 (dinfo->cfg.slot == slot) &&
319 (dinfo->cfg.func == func)) {
320 return (dinfo->cfg.dev);
327 /* Find a device_t by vendor/device ID */
330 pci_find_device(uint16_t vendor, uint16_t device)
332 struct pci_devinfo *dinfo;
334 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
335 if ((dinfo->cfg.vendor == vendor) &&
336 (dinfo->cfg.device == device)) {
337 return (dinfo->cfg.dev);
345 pci_find_class(uint8_t class, uint8_t subclass)
347 struct pci_devinfo *dinfo;
349 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
350 if (dinfo->cfg.baseclass == class &&
351 dinfo->cfg.subclass == subclass) {
352 return (dinfo->cfg.dev);
360 pci_printf(pcicfgregs *cfg, const char *fmt, ...)
365 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot,
368 retval += vprintf(fmt, ap);
373 /* return base address of memory or port map */
376 pci_mapbase(uint64_t mapreg)
379 if (PCI_BAR_MEM(mapreg))
380 return (mapreg & PCIM_BAR_MEM_BASE);
382 return (mapreg & PCIM_BAR_IO_BASE);
385 /* return map type of memory or port map */
388 pci_maptype(uint64_t mapreg)
391 if (PCI_BAR_IO(mapreg))
393 if (mapreg & PCIM_BAR_MEM_PREFETCH)
394 return ("Prefetchable Memory");
398 /* return log2 of map size decoded for memory or port map */
401 pci_mapsize(uint64_t testval)
405 testval = pci_mapbase(testval);
408 while ((testval & 1) == 0)
417 /* return log2 of address range supported by map register */
420 pci_maprange(uint64_t mapreg)
424 if (PCI_BAR_IO(mapreg))
427 switch (mapreg & PCIM_BAR_MEM_TYPE) {
428 case PCIM_BAR_MEM_32:
431 case PCIM_BAR_MEM_1MB:
434 case PCIM_BAR_MEM_64:
441 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
444 pci_fixancient(pcicfgregs *cfg)
446 if (cfg->hdrtype != 0)
449 /* PCI to PCI bridges use header type 1 */
450 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
454 /* extract header type specific config data */
457 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
459 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
460 switch (cfg->hdrtype) {
462 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
463 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
464 cfg->nummaps = PCI_MAXMAPS_0;
467 cfg->nummaps = PCI_MAXMAPS_1;
470 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
471 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
472 cfg->nummaps = PCI_MAXMAPS_2;
478 /* read configuration header into pcicfgregs structure */
480 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
482 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
483 pcicfgregs *cfg = NULL;
484 struct pci_devinfo *devlist_entry;
485 struct devlist *devlist_head;
487 devlist_head = &pci_devq;
489 devlist_entry = NULL;
491 if (REG(PCIR_DEVVENDOR, 4) != 0xfffffffful) {
492 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
493 if (devlist_entry == NULL)
496 cfg = &devlist_entry->cfg;
502 cfg->vendor = REG(PCIR_VENDOR, 2);
503 cfg->device = REG(PCIR_DEVICE, 2);
504 cfg->cmdreg = REG(PCIR_COMMAND, 2);
505 cfg->statreg = REG(PCIR_STATUS, 2);
506 cfg->baseclass = REG(PCIR_CLASS, 1);
507 cfg->subclass = REG(PCIR_SUBCLASS, 1);
508 cfg->progif = REG(PCIR_PROGIF, 1);
509 cfg->revid = REG(PCIR_REVID, 1);
510 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
511 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
512 cfg->lattimer = REG(PCIR_LATTIMER, 1);
513 cfg->intpin = REG(PCIR_INTPIN, 1);
514 cfg->intline = REG(PCIR_INTLINE, 1);
516 cfg->mingnt = REG(PCIR_MINGNT, 1);
517 cfg->maxlat = REG(PCIR_MAXLAT, 1);
519 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
520 cfg->hdrtype &= ~PCIM_MFDEV;
523 pci_hdrtypedata(pcib, b, s, f, cfg);
525 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
526 pci_read_cap(pcib, cfg);
528 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
530 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
531 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
532 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
533 devlist_entry->conf.pc_sel.pc_func = cfg->func;
534 devlist_entry->conf.pc_hdr = cfg->hdrtype;
536 devlist_entry->conf.pc_subvendor = cfg->subvendor;
537 devlist_entry->conf.pc_subdevice = cfg->subdevice;
538 devlist_entry->conf.pc_vendor = cfg->vendor;
539 devlist_entry->conf.pc_device = cfg->device;
541 devlist_entry->conf.pc_class = cfg->baseclass;
542 devlist_entry->conf.pc_subclass = cfg->subclass;
543 devlist_entry->conf.pc_progif = cfg->progif;
544 devlist_entry->conf.pc_revid = cfg->revid;
549 return (devlist_entry);
554 pci_read_cap(device_t pcib, pcicfgregs *cfg)
556 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
557 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
558 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
562 int ptr, nextptr, ptrptr;
564 switch (cfg->hdrtype & PCIM_HDRTYPE) {
567 ptrptr = PCIR_CAP_PTR;
570 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
573 return; /* no extended capabilities support */
575 nextptr = REG(ptrptr, 1); /* sanity check? */
578 * Read capability entries.
580 while (nextptr != 0) {
583 printf("illegal PCI extended capability offset %d\n",
587 /* Find the next entry */
589 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
591 /* Process this entry */
592 switch (REG(ptr + PCICAP_ID, 1)) {
593 case PCIY_PMG: /* PCI power management */
594 if (cfg->pp.pp_cap == 0) {
595 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
596 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS;
597 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR;
598 if ((nextptr - ptr) > PCIR_POWER_DATA)
599 cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
602 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
603 case PCIY_HT: /* HyperTransport */
604 /* Determine HT-specific capability type. */
605 val = REG(ptr + PCIR_HT_COMMAND, 2);
606 switch (val & PCIM_HTCMD_CAP_MASK) {
607 case PCIM_HTCAP_MSI_MAPPING:
608 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
609 /* Sanity check the mapping window. */
610 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI,
613 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO,
615 if (addr != MSI_INTEL_ADDR_BASE)
617 "HT Bridge at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n",
618 cfg->domain, cfg->bus,
619 cfg->slot, cfg->func,
622 addr = MSI_INTEL_ADDR_BASE;
624 cfg->ht.ht_msimap = ptr;
625 cfg->ht.ht_msictrl = val;
626 cfg->ht.ht_msiaddr = addr;
631 case PCIY_MSI: /* PCI MSI */
632 cfg->msi.msi_location = ptr;
633 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
634 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl &
635 PCIM_MSICTRL_MMC_MASK)>>1);
637 case PCIY_MSIX: /* PCI MSI-X */
638 cfg->msix.msix_location = ptr;
639 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
640 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl &
641 PCIM_MSIXCTRL_TABLE_SIZE) + 1;
642 val = REG(ptr + PCIR_MSIX_TABLE, 4);
643 cfg->msix.msix_table_bar = PCIR_BAR(val &
645 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
646 val = REG(ptr + PCIR_MSIX_PBA, 4);
647 cfg->msix.msix_pba_bar = PCIR_BAR(val &
649 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
651 case PCIY_VPD: /* PCI Vital Product Data */
652 cfg->vpd.vpd_reg = ptr;
655 /* Should always be true. */
656 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) {
657 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
658 cfg->subvendor = val & 0xffff;
659 cfg->subdevice = val >> 16;
662 case PCIY_PCIX: /* PCI-X */
664 * Assume we have a PCI-X chipset if we have
665 * at least one PCI-PCI bridge with a PCI-X
666 * capability. Note that some systems with
667 * PCI-express or HT chipsets might match on
668 * this check as well.
670 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1)
673 case PCIY_EXPRESS: /* PCI-express */
675 * Assume we have a PCI-express chipset if we have
676 * at least one PCI-express device.
684 /* REG and WREG use carry through to next functions */
688 * PCI Vital Product Data
691 #define PCI_VPD_TIMEOUT 1000000
694 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
696 int count = PCI_VPD_TIMEOUT;
698 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
700 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
702 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
705 DELAY(1); /* limit looping */
707 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
714 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
716 int count = PCI_VPD_TIMEOUT;
718 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
720 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
721 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
722 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
725 DELAY(1); /* limit looping */
732 #undef PCI_VPD_TIMEOUT
734 struct vpd_readstate {
744 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
749 if (vrs->bytesinval == 0) {
750 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
752 vrs->val = le32toh(reg);
754 byte = vrs->val & 0xff;
757 vrs->val = vrs->val >> 8;
758 byte = vrs->val & 0xff;
768 pci_read_vpd(device_t pcib, pcicfgregs *cfg)
770 struct vpd_readstate vrs;
775 int alloc, off; /* alloc/off for RO/W arrays */
781 /* init vpd reader */
789 name = remain = i = 0; /* shut up stupid gcc */
790 alloc = off = 0; /* shut up stupid gcc */
791 dflen = 0; /* shut up stupid gcc */
794 if (vpd_nextbyte(&vrs, &byte)) {
799 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
800 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
801 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
804 case 0: /* item name */
806 if (vpd_nextbyte(&vrs, &byte2)) {
811 if (vpd_nextbyte(&vrs, &byte2)) {
815 remain |= byte2 << 8;
816 if (remain > (0x7f*4 - vrs.off)) {
819 "pci%d:%d:%d:%d: invalid VPD data, remain %#x\n",
820 cfg->domain, cfg->bus, cfg->slot,
826 name = (byte >> 3) & 0xf;
829 case 0x2: /* String */
830 cfg->vpd.vpd_ident = malloc(remain + 1,
838 case 0x10: /* VPD-R */
841 cfg->vpd.vpd_ros = malloc(alloc *
842 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
846 case 0x11: /* VPD-W */
849 cfg->vpd.vpd_w = malloc(alloc *
850 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
854 default: /* Invalid data, abort */
860 case 1: /* Identifier String */
861 cfg->vpd.vpd_ident[i++] = byte;
864 cfg->vpd.vpd_ident[i] = '\0';
869 case 2: /* VPD-R Keyword Header */
871 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
872 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
873 M_DEVBUF, M_WAITOK | M_ZERO);
875 cfg->vpd.vpd_ros[off].keyword[0] = byte;
876 if (vpd_nextbyte(&vrs, &byte2)) {
880 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
881 if (vpd_nextbyte(&vrs, &byte2)) {
887 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
890 * if this happens, we can't trust the rest
894 "pci%d:%d:%d:%d: bad keyword length: %d\n",
895 cfg->domain, cfg->bus, cfg->slot,
900 } else if (dflen == 0) {
901 cfg->vpd.vpd_ros[off].value = malloc(1 *
902 sizeof(*cfg->vpd.vpd_ros[off].value),
904 cfg->vpd.vpd_ros[off].value[0] = '\x00';
906 cfg->vpd.vpd_ros[off].value = malloc(
908 sizeof(*cfg->vpd.vpd_ros[off].value),
912 /* keep in sync w/ state 3's transistions */
913 if (dflen == 0 && remain == 0)
921 case 3: /* VPD-R Keyword Value */
922 cfg->vpd.vpd_ros[off].value[i++] = byte;
923 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
924 "RV", 2) == 0 && cksumvalid == -1) {
930 "pci%d:%d:%d:%d: bad VPD cksum, remain %hhu\n",
931 cfg->domain, cfg->bus,
932 cfg->slot, cfg->func,
941 /* keep in sync w/ state 2's transistions */
943 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
944 if (dflen == 0 && remain == 0) {
945 cfg->vpd.vpd_rocnt = off;
946 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
947 off * sizeof(*cfg->vpd.vpd_ros),
948 M_DEVBUF, M_WAITOK | M_ZERO);
950 } else if (dflen == 0)
960 case 5: /* VPD-W Keyword Header */
962 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
963 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
964 M_DEVBUF, M_WAITOK | M_ZERO);
966 cfg->vpd.vpd_w[off].keyword[0] = byte;
967 if (vpd_nextbyte(&vrs, &byte2)) {
971 cfg->vpd.vpd_w[off].keyword[1] = byte2;
972 if (vpd_nextbyte(&vrs, &byte2)) {
976 cfg->vpd.vpd_w[off].len = dflen = byte2;
977 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
978 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) *
979 sizeof(*cfg->vpd.vpd_w[off].value),
983 /* keep in sync w/ state 6's transistions */
984 if (dflen == 0 && remain == 0)
992 case 6: /* VPD-W Keyword Value */
993 cfg->vpd.vpd_w[off].value[i++] = byte;
996 /* keep in sync w/ state 5's transistions */
998 cfg->vpd.vpd_w[off++].value[i++] = '\0';
999 if (dflen == 0 && remain == 0) {
1000 cfg->vpd.vpd_wcnt = off;
1001 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
1002 off * sizeof(*cfg->vpd.vpd_w),
1003 M_DEVBUF, M_WAITOK | M_ZERO);
1005 } else if (dflen == 0)
1010 printf("pci%d:%d:%d:%d: invalid state: %d\n",
1011 cfg->domain, cfg->bus, cfg->slot, cfg->func,
1018 if (cksumvalid == 0 || state < -1) {
1019 /* read-only data bad, clean up */
1020 if (cfg->vpd.vpd_ros != NULL) {
1021 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1022 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1023 free(cfg->vpd.vpd_ros, M_DEVBUF);
1024 cfg->vpd.vpd_ros = NULL;
1028 /* I/O error, clean up */
1029 printf("pci%d:%d:%d:%d: failed to read VPD data.\n",
1030 cfg->domain, cfg->bus, cfg->slot, cfg->func);
1031 if (cfg->vpd.vpd_ident != NULL) {
1032 free(cfg->vpd.vpd_ident, M_DEVBUF);
1033 cfg->vpd.vpd_ident = NULL;
1035 if (cfg->vpd.vpd_w != NULL) {
1036 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1037 free(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1038 free(cfg->vpd.vpd_w, M_DEVBUF);
1039 cfg->vpd.vpd_w = NULL;
1042 cfg->vpd.vpd_cached = 1;
1048 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1050 struct pci_devinfo *dinfo = device_get_ivars(child);
1051 pcicfgregs *cfg = &dinfo->cfg;
1053 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1054 pci_read_vpd(device_get_parent(dev), cfg);
1056 *identptr = cfg->vpd.vpd_ident;
1058 if (*identptr == NULL)
1065 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1068 struct pci_devinfo *dinfo = device_get_ivars(child);
1069 pcicfgregs *cfg = &dinfo->cfg;
1072 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1073 pci_read_vpd(device_get_parent(dev), cfg);
1075 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1076 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1077 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1078 *vptr = cfg->vpd.vpd_ros[i].value;
1087 * Find the requested extended capability and return the offset in
1088 * configuration space via the pointer provided. The function returns
1089 * 0 on success and error code otherwise.
1092 pci_find_extcap_method(device_t dev, device_t child, int capability,
1095 struct pci_devinfo *dinfo = device_get_ivars(child);
1096 pcicfgregs *cfg = &dinfo->cfg;
1101 * Check the CAP_LIST bit of the PCI status register first.
1103 status = pci_read_config(child, PCIR_STATUS, 2);
1104 if (!(status & PCIM_STATUS_CAPPRESENT))
1108 * Determine the start pointer of the capabilities list.
1110 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1116 ptr = PCIR_CAP_PTR_2;
1120 return (ENXIO); /* no extended capabilities support */
1122 ptr = pci_read_config(child, ptr, 1);
1125 * Traverse the capabilities list.
1128 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1133 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1140 * Support for MSI-X message interrupts.
1143 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
1145 struct pci_devinfo *dinfo = device_get_ivars(dev);
1146 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1149 KASSERT(msix->msix_table_len > index, ("bogus index"));
1150 offset = msix->msix_table_offset + index * 16;
1151 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1152 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1153 bus_write_4(msix->msix_table_res, offset + 8, data);
1155 /* Enable MSI -> HT mapping. */
1156 pci_ht_map_msi(dev, address);
1160 pci_mask_msix(device_t dev, u_int index)
1162 struct pci_devinfo *dinfo = device_get_ivars(dev);
1163 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1164 uint32_t offset, val;
1166 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1167 offset = msix->msix_table_offset + index * 16 + 12;
1168 val = bus_read_4(msix->msix_table_res, offset);
1169 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1170 val |= PCIM_MSIX_VCTRL_MASK;
1171 bus_write_4(msix->msix_table_res, offset, val);
1176 pci_unmask_msix(device_t dev, u_int index)
1178 struct pci_devinfo *dinfo = device_get_ivars(dev);
1179 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1180 uint32_t offset, val;
1182 KASSERT(msix->msix_table_len > index, ("bogus index"));
1183 offset = msix->msix_table_offset + index * 16 + 12;
1184 val = bus_read_4(msix->msix_table_res, offset);
1185 if (val & PCIM_MSIX_VCTRL_MASK) {
1186 val &= ~PCIM_MSIX_VCTRL_MASK;
1187 bus_write_4(msix->msix_table_res, offset, val);
1192 pci_pending_msix(device_t dev, u_int index)
1194 struct pci_devinfo *dinfo = device_get_ivars(dev);
1195 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1196 uint32_t offset, bit;
1198 KASSERT(msix->msix_table_len > index, ("bogus index"));
1199 offset = msix->msix_pba_offset + (index / 32) * 4;
1200 bit = 1 << index % 32;
1201 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1205 * Restore MSI-X registers and table during resume. If MSI-X is
1206 * enabled then walk the virtual table to restore the actual MSI-X
1210 pci_resume_msix(device_t dev)
1212 struct pci_devinfo *dinfo = device_get_ivars(dev);
1213 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1214 struct msix_table_entry *mte;
1215 struct msix_vector *mv;
1218 if (msix->msix_alloc > 0) {
1219 /* First, mask all vectors. */
1220 for (i = 0; i < msix->msix_msgnum; i++)
1221 pci_mask_msix(dev, i);
1223 /* Second, program any messages with at least one handler. */
1224 for (i = 0; i < msix->msix_table_len; i++) {
1225 mte = &msix->msix_table[i];
1226 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1228 mv = &msix->msix_vectors[mte->mte_vector - 1];
1229 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data);
1230 pci_unmask_msix(dev, i);
1233 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1234 msix->msix_ctrl, 2);
1238 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1239 * returned in *count. After this function returns, each message will be
1240 * available to the driver as SYS_RES_IRQ resources starting at rid 1.
1243 pci_alloc_msix_method(device_t dev, device_t child, int *count)
1245 struct pci_devinfo *dinfo = device_get_ivars(child);
1246 pcicfgregs *cfg = &dinfo->cfg;
1247 struct resource_list_entry *rle;
1248 int actual, error, i, irq, max;
1250 /* Don't let count == 0 get us into trouble. */
1254 /* If rid 0 is allocated, then fail. */
1255 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1256 if (rle != NULL && rle->res != NULL)
1259 /* Already have allocated messages? */
1260 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1263 /* If MSI is blacklisted for this system, fail. */
1264 if (pci_msi_blacklisted())
1267 /* MSI-X capability present? */
1268 if (cfg->msix.msix_location == 0 || !pci_do_msix)
1271 /* Make sure the appropriate BARs are mapped. */
1272 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1273 cfg->msix.msix_table_bar);
1274 if (rle == NULL || rle->res == NULL ||
1275 !(rman_get_flags(rle->res) & RF_ACTIVE))
1277 cfg->msix.msix_table_res = rle->res;
1278 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1279 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1280 cfg->msix.msix_pba_bar);
1281 if (rle == NULL || rle->res == NULL ||
1282 !(rman_get_flags(rle->res) & RF_ACTIVE))
1285 cfg->msix.msix_pba_res = rle->res;
1288 device_printf(child,
1289 "attempting to allocate %d MSI-X vectors (%d supported)\n",
1290 *count, cfg->msix.msix_msgnum);
1291 max = min(*count, cfg->msix.msix_msgnum);
1292 for (i = 0; i < max; i++) {
1293 /* Allocate a message. */
1294 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq);
1300 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1306 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
1308 device_printf(child, "using IRQ %lu for MSI-X\n",
1314 * Be fancy and try to print contiguous runs of
1315 * IRQ values as ranges. 'irq' is the previous IRQ.
1316 * 'run' is true if we are in a range.
1318 device_printf(child, "using IRQs %lu", rle->start);
1321 for (i = 1; i < actual; i++) {
1322 rle = resource_list_find(&dinfo->resources,
1323 SYS_RES_IRQ, i + 1);
1325 /* Still in a run? */
1326 if (rle->start == irq + 1) {
1332 /* Finish previous range. */
1338 /* Start new range. */
1339 printf(",%lu", rle->start);
1343 /* Unfinished range? */
1346 printf(" for MSI-X\n");
1350 /* Mask all vectors. */
1351 for (i = 0; i < cfg->msix.msix_msgnum; i++)
1352 pci_mask_msix(child, i);
1354 /* Allocate and initialize vector data and virtual table. */
1355 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual,
1356 M_DEVBUF, M_WAITOK | M_ZERO);
1357 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual,
1358 M_DEVBUF, M_WAITOK | M_ZERO);
1359 for (i = 0; i < actual; i++) {
1360 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1361 cfg->msix.msix_vectors[i].mv_irq = rle->start;
1362 cfg->msix.msix_table[i].mte_vector = i + 1;
1365 /* Update control register to enable MSI-X. */
1366 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1367 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1368 cfg->msix.msix_ctrl, 2);
1370 /* Update counts of alloc'd messages. */
1371 cfg->msix.msix_alloc = actual;
1372 cfg->msix.msix_table_len = actual;
1378 * By default, pci_alloc_msix() will assign the allocated IRQ
1379 * resources consecutively to the first N messages in the MSI-X table.
1380 * However, device drivers may want to use different layouts if they
1381 * either receive fewer messages than they asked for, or they wish to
1382 * populate the MSI-X table sparsely. This method allows the driver
1383 * to specify what layout it wants. It must be called after a
1384 * successful pci_alloc_msix() but before any of the associated
1385 * SYS_RES_IRQ resources are allocated via bus_alloc_resource().
1387 * The 'vectors' array contains 'count' message vectors. The array
1388 * maps directly to the MSI-X table in that index 0 in the array
1389 * specifies the vector for the first message in the MSI-X table, etc.
1390 * The vector value in each array index can either be 0 to indicate
1391 * that no vector should be assigned to a message slot, or it can be a
1392 * number from 1 to N (where N is the count returned from a
1393 * succcessful call to pci_alloc_msix()) to indicate which message
1394 * vector (IRQ) to be used for the corresponding message.
1396 * On successful return, each message with a non-zero vector will have
1397 * an associated SYS_RES_IRQ whose rid is equal to the array index +
1398 * 1. Additionally, if any of the IRQs allocated via the previous
1399 * call to pci_alloc_msix() are not used in the mapping, those IRQs
1400 * will be freed back to the system automatically.
1402 * For example, suppose a driver has a MSI-X table with 6 messages and
1403 * asks for 6 messages, but pci_alloc_msix() only returns a count of
1404 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and
1405 * C. After the call to pci_alloc_msix(), the device will be setup to
1406 * have an MSI-X table of ABC--- (where - means no vector assigned).
1407 * If the driver ten passes a vector array of { 1, 0, 1, 2, 0, 2 },
1408 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1409 * be freed back to the system. This device will also have valid
1410 * SYS_RES_IRQ rids of 1, 3, 4, and 6.
1412 * In any case, the SYS_RES_IRQ rid X will always map to the message
1413 * at MSI-X table index X - 1 and will only be valid if a vector is
1414 * assigned to that table entry.
1417 pci_remap_msix_method(device_t dev, device_t child, int count,
1418 const u_int *vectors)
1420 struct pci_devinfo *dinfo = device_get_ivars(child);
1421 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1422 struct resource_list_entry *rle;
1423 int i, irq, j, *used;
1426 * Have to have at least one message in the table but the
1427 * table can't be bigger than the actual MSI-X table in the
1430 if (count == 0 || count > msix->msix_msgnum)
1433 /* Sanity check the vectors. */
1434 for (i = 0; i < count; i++)
1435 if (vectors[i] > msix->msix_alloc)
1439 * Make sure there aren't any holes in the vectors to be used.
1440 * It's a big pain to support it, and it doesn't really make
1441 * sense anyway. Also, at least one vector must be used.
1443 used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK |
1445 for (i = 0; i < count; i++)
1446 if (vectors[i] != 0)
1447 used[vectors[i] - 1] = 1;
1448 for (i = 0; i < msix->msix_alloc - 1; i++)
1449 if (used[i] == 0 && used[i + 1] == 1) {
1450 free(used, M_DEVBUF);
1454 free(used, M_DEVBUF);
1458 /* Make sure none of the resources are allocated. */
1459 for (i = 0; i < msix->msix_table_len; i++) {
1460 if (msix->msix_table[i].mte_vector == 0)
1462 if (msix->msix_table[i].mte_handlers > 0)
1464 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1465 KASSERT(rle != NULL, ("missing resource"));
1466 if (rle->res != NULL)
1470 /* Free the existing resource list entries. */
1471 for (i = 0; i < msix->msix_table_len; i++) {
1472 if (msix->msix_table[i].mte_vector == 0)
1474 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1478 * Build the new virtual table keeping track of which vectors are
1481 free(msix->msix_table, M_DEVBUF);
1482 msix->msix_table = malloc(sizeof(struct msix_table_entry) * count,
1483 M_DEVBUF, M_WAITOK | M_ZERO);
1484 for (i = 0; i < count; i++)
1485 msix->msix_table[i].mte_vector = vectors[i];
1486 msix->msix_table_len = count;
1488 /* Free any unused IRQs and resize the vectors array if necessary. */
1489 j = msix->msix_alloc - 1;
1491 struct msix_vector *vec;
1493 while (used[j] == 0) {
1494 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1495 msix->msix_vectors[j].mv_irq);
1498 vec = malloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF,
1500 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
1502 free(msix->msix_vectors, M_DEVBUF);
1503 msix->msix_vectors = vec;
1504 msix->msix_alloc = j + 1;
1506 free(used, M_DEVBUF);
1508 /* Map the IRQs onto the rids. */
1509 for (i = 0; i < count; i++) {
1510 if (vectors[i] == 0)
1512 irq = msix->msix_vectors[vectors[i]].mv_irq;
1513 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1518 device_printf(child, "Remapped MSI-X IRQs as: ");
1519 for (i = 0; i < count; i++) {
1522 if (vectors[i] == 0)
1526 msix->msix_vectors[vectors[i]].mv_irq);
1535 pci_release_msix(device_t dev, device_t child)
1537 struct pci_devinfo *dinfo = device_get_ivars(child);
1538 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1539 struct resource_list_entry *rle;
1542 /* Do we have any messages to release? */
1543 if (msix->msix_alloc == 0)
1546 /* Make sure none of the resources are allocated. */
1547 for (i = 0; i < msix->msix_table_len; i++) {
1548 if (msix->msix_table[i].mte_vector == 0)
1550 if (msix->msix_table[i].mte_handlers > 0)
1552 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1553 KASSERT(rle != NULL, ("missing resource"));
1554 if (rle->res != NULL)
1558 /* Update control register to disable MSI-X. */
1559 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1560 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
1561 msix->msix_ctrl, 2);
1563 /* Free the resource list entries. */
1564 for (i = 0; i < msix->msix_table_len; i++) {
1565 if (msix->msix_table[i].mte_vector == 0)
1567 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1569 free(msix->msix_table, M_DEVBUF);
1570 msix->msix_table_len = 0;
1572 /* Release the IRQs. */
1573 for (i = 0; i < msix->msix_alloc; i++)
1574 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1575 msix->msix_vectors[i].mv_irq);
1576 free(msix->msix_vectors, M_DEVBUF);
1577 msix->msix_alloc = 0;
1582 * Return the max supported MSI-X messages this device supports.
1583 * Basically, assuming the MD code can alloc messages, this function
1584 * should return the maximum value that pci_alloc_msix() can return.
1585 * Thus, it is subject to the tunables, etc.
1588 pci_msix_count_method(device_t dev, device_t child)
1590 struct pci_devinfo *dinfo = device_get_ivars(child);
1591 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1593 if (pci_do_msix && msix->msix_location != 0)
1594 return (msix->msix_msgnum);
1599 * HyperTransport MSI mapping control
1602 pci_ht_map_msi(device_t dev, uint64_t addr)
1604 struct pci_devinfo *dinfo = device_get_ivars(dev);
1605 struct pcicfg_ht *ht = &dinfo->cfg.ht;
1610 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
1611 ht->ht_msiaddr >> 20 == addr >> 20) {
1612 /* Enable MSI -> HT mapping. */
1613 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1614 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1618 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
1619 /* Disable MSI -> HT mapping. */
1620 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
1621 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1627 pci_get_max_read_req(device_t dev)
1632 if (pci_find_cap(dev, PCIY_EXPRESS, &cap) != 0)
1634 val = pci_read_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, 2);
1635 val &= PCIM_EXP_CTL_MAX_READ_REQUEST;
1637 return (1 << (val + 7));
1641 pci_set_max_read_req(device_t dev, int size)
1646 if (pci_find_cap(dev, PCIY_EXPRESS, &cap) != 0)
1652 size = (1 << (fls(size) - 1));
1653 val = pci_read_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, 2);
1654 val &= ~PCIM_EXP_CTL_MAX_READ_REQUEST;
1655 val |= (fls(size) - 8) << 12;
1656 pci_write_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, val, 2);
1661 * Support for MSI message signalled interrupts.
1664 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
1666 struct pci_devinfo *dinfo = device_get_ivars(dev);
1667 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1669 /* Write data and address values. */
1670 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1671 address & 0xffffffff, 4);
1672 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1673 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1675 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1678 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1681 /* Enable MSI in the control register. */
1682 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1683 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1686 /* Enable MSI -> HT mapping. */
1687 pci_ht_map_msi(dev, address);
1691 pci_disable_msi(device_t dev)
1693 struct pci_devinfo *dinfo = device_get_ivars(dev);
1694 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1696 /* Disable MSI -> HT mapping. */
1697 pci_ht_map_msi(dev, 0);
1699 /* Disable MSI in the control register. */
1700 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1701 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1706 * Restore MSI registers during resume. If MSI is enabled then
1707 * restore the data and address registers in addition to the control
1711 pci_resume_msi(device_t dev)
1713 struct pci_devinfo *dinfo = device_get_ivars(dev);
1714 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1718 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1719 address = msi->msi_addr;
1720 data = msi->msi_data;
1721 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1722 address & 0xffffffff, 4);
1723 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1724 pci_write_config(dev, msi->msi_location +
1725 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1726 pci_write_config(dev, msi->msi_location +
1727 PCIR_MSI_DATA_64BIT, data, 2);
1729 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1732 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1737 pci_remap_intr_method(device_t bus, device_t dev, u_int irq)
1739 struct pci_devinfo *dinfo = device_get_ivars(dev);
1740 pcicfgregs *cfg = &dinfo->cfg;
1741 struct resource_list_entry *rle;
1742 struct msix_table_entry *mte;
1743 struct msix_vector *mv;
1749 * Handle MSI first. We try to find this IRQ among our list
1750 * of MSI IRQs. If we find it, we request updated address and
1751 * data registers and apply the results.
1753 if (cfg->msi.msi_alloc > 0) {
1755 /* If we don't have any active handlers, nothing to do. */
1756 if (cfg->msi.msi_handlers == 0)
1758 for (i = 0; i < cfg->msi.msi_alloc; i++) {
1759 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
1761 if (rle->start == irq) {
1762 error = PCIB_MAP_MSI(device_get_parent(bus),
1763 dev, irq, &addr, &data);
1766 pci_disable_msi(dev);
1767 dinfo->cfg.msi.msi_addr = addr;
1768 dinfo->cfg.msi.msi_data = data;
1769 pci_enable_msi(dev, addr, data);
1777 * For MSI-X, we check to see if we have this IRQ. If we do,
1778 * we request the updated mapping info. If that works, we go
1779 * through all the slots that use this IRQ and update them.
1781 if (cfg->msix.msix_alloc > 0) {
1782 for (i = 0; i < cfg->msix.msix_alloc; i++) {
1783 mv = &cfg->msix.msix_vectors[i];
1784 if (mv->mv_irq == irq) {
1785 error = PCIB_MAP_MSI(device_get_parent(bus),
1786 dev, irq, &addr, &data);
1789 mv->mv_address = addr;
1791 for (j = 0; j < cfg->msix.msix_table_len; j++) {
1792 mte = &cfg->msix.msix_table[j];
1793 if (mte->mte_vector != i + 1)
1795 if (mte->mte_handlers == 0)
1797 pci_mask_msix(dev, j);
1798 pci_enable_msix(dev, j, addr, data);
1799 pci_unmask_msix(dev, j);
1810 * Returns true if the specified device is blacklisted because MSI
1814 pci_msi_device_blacklisted(device_t dev)
1816 struct pci_quirk *q;
1818 if (!pci_honor_msi_blacklist)
1821 for (q = &pci_quirks[0]; q->devid; q++) {
1822 if (q->devid == pci_get_devid(dev) &&
1823 q->type == PCI_QUIRK_DISABLE_MSI)
1830 * Returns true if a specified chipset supports MSI when it is
1831 * emulated hardware in a virtual machine.
1834 pci_msi_vm_chipset(device_t dev)
1836 struct pci_quirk *q;
1838 for (q = &pci_quirks[0]; q->devid; q++) {
1839 if (q->devid == pci_get_devid(dev) &&
1840 q->type == PCI_QUIRK_ENABLE_MSI_VM)
1847 * Determine if MSI is blacklisted globally on this sytem. Currently,
1848 * we just check for blacklisted chipsets as represented by the
1849 * host-PCI bridge at device 0:0:0. In the future, it may become
1850 * necessary to check other system attributes, such as the kenv values
1851 * that give the motherboard manufacturer and model number.
1854 pci_msi_blacklisted(void)
1858 if (!pci_honor_msi_blacklist)
1861 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
1862 if (!(pcie_chipset || pcix_chipset)) {
1863 if (vm_guest != VM_GUEST_NO) {
1864 dev = pci_find_bsf(0, 0, 0);
1866 return (pci_msi_vm_chipset(dev) == 0);
1871 dev = pci_find_bsf(0, 0, 0);
1873 return (pci_msi_device_blacklisted(dev));
1878 * Attempt to allocate *count MSI messages. The actual number allocated is
1879 * returned in *count. After this function returns, each message will be
1880 * available to the driver as SYS_RES_IRQ resources starting at a rid 1.
1883 pci_alloc_msi_method(device_t dev, device_t child, int *count)
1885 struct pci_devinfo *dinfo = device_get_ivars(child);
1886 pcicfgregs *cfg = &dinfo->cfg;
1887 struct resource_list_entry *rle;
1888 int actual, error, i, irqs[32];
1891 /* Don't let count == 0 get us into trouble. */
1895 /* If rid 0 is allocated, then fail. */
1896 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1897 if (rle != NULL && rle->res != NULL)
1900 /* Already have allocated messages? */
1901 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1904 /* If MSI is blacklisted for this system, fail. */
1905 if (pci_msi_blacklisted())
1908 /* MSI capability present? */
1909 if (cfg->msi.msi_location == 0 || !pci_do_msi)
1913 device_printf(child,
1914 "attempting to allocate %d MSI vectors (%d supported)\n",
1915 *count, cfg->msi.msi_msgnum);
1917 /* Don't ask for more than the device supports. */
1918 actual = min(*count, cfg->msi.msi_msgnum);
1920 /* Don't ask for more than 32 messages. */
1921 actual = min(actual, 32);
1923 /* MSI requires power of 2 number of messages. */
1924 if (!powerof2(actual))
1928 /* Try to allocate N messages. */
1929 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
1941 * We now have N actual messages mapped onto SYS_RES_IRQ
1942 * resources in the irqs[] array, so add new resources
1943 * starting at rid 1.
1945 for (i = 0; i < actual; i++)
1946 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
1947 irqs[i], irqs[i], 1);
1951 device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
1956 * Be fancy and try to print contiguous runs
1957 * of IRQ values as ranges. 'run' is true if
1958 * we are in a range.
1960 device_printf(child, "using IRQs %d", irqs[0]);
1962 for (i = 1; i < actual; i++) {
1964 /* Still in a run? */
1965 if (irqs[i] == irqs[i - 1] + 1) {
1970 /* Finish previous range. */
1972 printf("-%d", irqs[i - 1]);
1976 /* Start new range. */
1977 printf(",%d", irqs[i]);
1980 /* Unfinished range? */
1982 printf("-%d", irqs[actual - 1]);
1983 printf(" for MSI\n");
1987 /* Update control register with actual count. */
1988 ctrl = cfg->msi.msi_ctrl;
1989 ctrl &= ~PCIM_MSICTRL_MME_MASK;
1990 ctrl |= (ffs(actual) - 1) << 4;
1991 cfg->msi.msi_ctrl = ctrl;
1992 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
1994 /* Update counts of alloc'd messages. */
1995 cfg->msi.msi_alloc = actual;
1996 cfg->msi.msi_handlers = 0;
2001 /* Release the MSI messages associated with this device. */
2003 pci_release_msi_method(device_t dev, device_t child)
2005 struct pci_devinfo *dinfo = device_get_ivars(child);
2006 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2007 struct resource_list_entry *rle;
2008 int error, i, irqs[32];
2010 /* Try MSI-X first. */
2011 error = pci_release_msix(dev, child);
2012 if (error != ENODEV)
2015 /* Do we have any messages to release? */
2016 if (msi->msi_alloc == 0)
2018 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
2020 /* Make sure none of the resources are allocated. */
2021 if (msi->msi_handlers > 0)
2023 for (i = 0; i < msi->msi_alloc; i++) {
2024 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2025 KASSERT(rle != NULL, ("missing MSI resource"));
2026 if (rle->res != NULL)
2028 irqs[i] = rle->start;
2031 /* Update control register with 0 count. */
2032 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
2033 ("%s: MSI still enabled", __func__));
2034 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
2035 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2038 /* Release the messages. */
2039 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
2040 for (i = 0; i < msi->msi_alloc; i++)
2041 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2043 /* Update alloc count. */
2051 * Return the max supported MSI messages this device supports.
2052 * Basically, assuming the MD code can alloc messages, this function
2053 * should return the maximum value that pci_alloc_msi() can return.
2054 * Thus, it is subject to the tunables, etc.
2057 pci_msi_count_method(device_t dev, device_t child)
2059 struct pci_devinfo *dinfo = device_get_ivars(child);
2060 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2062 if (pci_do_msi && msi->msi_location != 0)
2063 return (msi->msi_msgnum);
2067 /* free pcicfgregs structure and all depending data structures */
2070 pci_freecfg(struct pci_devinfo *dinfo)
2072 struct devlist *devlist_head;
2075 devlist_head = &pci_devq;
2077 if (dinfo->cfg.vpd.vpd_reg) {
2078 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2079 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2080 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2081 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2082 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2083 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2084 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2086 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2087 free(dinfo, M_DEVBUF);
2089 /* increment the generation count */
2092 /* we're losing one device */
2098 * PCI power manangement
2101 pci_set_powerstate_method(device_t dev, device_t child, int state)
2103 struct pci_devinfo *dinfo = device_get_ivars(child);
2104 pcicfgregs *cfg = &dinfo->cfg;
2106 int result, oldstate, highest, delay;
2108 if (cfg->pp.pp_cap == 0)
2109 return (EOPNOTSUPP);
2112 * Optimize a no state change request away. While it would be OK to
2113 * write to the hardware in theory, some devices have shown odd
2114 * behavior when going from D3 -> D3.
2116 oldstate = pci_get_powerstate(child);
2117 if (oldstate == state)
2121 * The PCI power management specification states that after a state
2122 * transition between PCI power states, system software must
2123 * guarantee a minimal delay before the function accesses the device.
2124 * Compute the worst case delay that we need to guarantee before we
2125 * access the device. Many devices will be responsive much more
2126 * quickly than this delay, but there are some that don't respond
2127 * instantly to state changes. Transitions to/from D3 state require
2128 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2129 * is done below with DELAY rather than a sleeper function because
2130 * this function can be called from contexts where we cannot sleep.
2132 highest = (oldstate > state) ? oldstate : state;
2133 if (highest == PCI_POWERSTATE_D3)
2135 else if (highest == PCI_POWERSTATE_D2)
2139 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2140 & ~PCIM_PSTAT_DMASK;
2143 case PCI_POWERSTATE_D0:
2144 status |= PCIM_PSTAT_D0;
2146 case PCI_POWERSTATE_D1:
2147 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2148 return (EOPNOTSUPP);
2149 status |= PCIM_PSTAT_D1;
2151 case PCI_POWERSTATE_D2:
2152 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2153 return (EOPNOTSUPP);
2154 status |= PCIM_PSTAT_D2;
2156 case PCI_POWERSTATE_D3:
2157 status |= PCIM_PSTAT_D3;
2164 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate,
2167 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2174 pci_get_powerstate_method(device_t dev, device_t child)
2176 struct pci_devinfo *dinfo = device_get_ivars(child);
2177 pcicfgregs *cfg = &dinfo->cfg;
2181 if (cfg->pp.pp_cap != 0) {
2182 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2183 switch (status & PCIM_PSTAT_DMASK) {
2185 result = PCI_POWERSTATE_D0;
2188 result = PCI_POWERSTATE_D1;
2191 result = PCI_POWERSTATE_D2;
2194 result = PCI_POWERSTATE_D3;
2197 result = PCI_POWERSTATE_UNKNOWN;
2201 /* No support, device is always at D0 */
2202 result = PCI_POWERSTATE_D0;
2208 * Some convenience functions for PCI device drivers.
2211 static __inline void
2212 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2216 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2218 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2221 static __inline void
2222 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2226 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2228 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2232 pci_enable_busmaster_method(device_t dev, device_t child)
2234 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2239 pci_disable_busmaster_method(device_t dev, device_t child)
2241 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2246 pci_enable_io_method(device_t dev, device_t child, int space)
2251 case SYS_RES_IOPORT:
2252 bit = PCIM_CMD_PORTEN;
2254 case SYS_RES_MEMORY:
2255 bit = PCIM_CMD_MEMEN;
2260 pci_set_command_bit(dev, child, bit);
2265 pci_disable_io_method(device_t dev, device_t child, int space)
2270 case SYS_RES_IOPORT:
2271 bit = PCIM_CMD_PORTEN;
2273 case SYS_RES_MEMORY:
2274 bit = PCIM_CMD_MEMEN;
2279 pci_clear_command_bit(dev, child, bit);
2284 * New style pci driver. Parent device is either a pci-host-bridge or a
2285 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2289 pci_print_verbose(struct pci_devinfo *dinfo)
2293 pcicfgregs *cfg = &dinfo->cfg;
2295 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2296 cfg->vendor, cfg->device, cfg->revid);
2297 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2298 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2299 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2300 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2302 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2303 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2304 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2305 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2306 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2307 if (cfg->intpin > 0)
2308 printf("\tintpin=%c, irq=%d\n",
2309 cfg->intpin +'a' -1, cfg->intline);
2310 if (cfg->pp.pp_cap) {
2313 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2314 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2315 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2316 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2317 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2318 status & PCIM_PSTAT_DMASK);
2320 if (cfg->msi.msi_location) {
2323 ctrl = cfg->msi.msi_ctrl;
2324 printf("\tMSI supports %d message%s%s%s\n",
2325 cfg->msi.msi_msgnum,
2326 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2327 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2328 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2330 if (cfg->msix.msix_location) {
2331 printf("\tMSI-X supports %d message%s ",
2332 cfg->msix.msix_msgnum,
2333 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2334 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2335 printf("in map 0x%x\n",
2336 cfg->msix.msix_table_bar);
2338 printf("in maps 0x%x and 0x%x\n",
2339 cfg->msix.msix_table_bar,
2340 cfg->msix.msix_pba_bar);
2346 pci_porten(device_t dev)
2348 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0;
2352 pci_memen(device_t dev)
2354 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0;
2358 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp)
2360 pci_addr_t map, testval;
2364 map = pci_read_config(dev, reg, 4);
2365 ln2range = pci_maprange(map);
2367 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
2370 * Disable decoding via the command register before
2371 * determining the BAR's length since we will be placing it in
2374 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2375 pci_write_config(dev, PCIR_COMMAND,
2376 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2);
2379 * Determine the BAR's length by writing all 1's. The bottom
2380 * log_2(size) bits of the BAR will stick as 0 when we read
2383 pci_write_config(dev, reg, 0xffffffff, 4);
2384 testval = pci_read_config(dev, reg, 4);
2385 if (ln2range == 64) {
2386 pci_write_config(dev, reg + 4, 0xffffffff, 4);
2387 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
2391 * Restore the original value of the BAR. We may have reprogrammed
2392 * the BAR of the low-level console device and when booting verbose,
2393 * we need the console device addressable.
2395 pci_write_config(dev, reg, map, 4);
2397 pci_write_config(dev, reg + 4, map >> 32, 4);
2398 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2401 *testvalp = testval;
2405 pci_write_bar(device_t dev, int reg, pci_addr_t base)
2410 map = pci_read_config(dev, reg, 4);
2411 ln2range = pci_maprange(map);
2412 pci_write_config(dev, reg, base, 4);
2414 pci_write_config(dev, reg + 4, base >> 32, 4);
2418 * Add a resource based on a pci map register. Return 1 if the map
2419 * register is a 32bit map register or 2 if it is a 64bit register.
2422 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl,
2423 int force, int prefetch)
2425 pci_addr_t base, map, testval;
2426 pci_addr_t start, end, count;
2427 int barlen, basezero, maprange, mapsize, type;
2429 struct resource *res;
2431 pci_read_bar(dev, reg, &map, &testval);
2432 if (PCI_BAR_MEM(map)) {
2433 type = SYS_RES_MEMORY;
2434 if (map & PCIM_BAR_MEM_PREFETCH)
2437 type = SYS_RES_IOPORT;
2438 mapsize = pci_mapsize(testval);
2439 base = pci_mapbase(map);
2440 #ifdef __PCI_BAR_ZERO_VALID
2443 basezero = base == 0;
2445 maprange = pci_maprange(map);
2446 barlen = maprange == 64 ? 2 : 1;
2449 * For I/O registers, if bottom bit is set, and the next bit up
2450 * isn't clear, we know we have a BAR that doesn't conform to the
2451 * spec, so ignore it. Also, sanity check the size of the data
2452 * areas to the type of memory involved. Memory must be at least
2453 * 16 bytes in size, while I/O ranges must be at least 4.
2455 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2457 if ((type == SYS_RES_MEMORY && mapsize < 4) ||
2458 (type == SYS_RES_IOPORT && mapsize < 2))
2462 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2463 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize);
2464 if (type == SYS_RES_IOPORT && !pci_porten(dev))
2465 printf(", port disabled\n");
2466 else if (type == SYS_RES_MEMORY && !pci_memen(dev))
2467 printf(", memory disabled\n");
2469 printf(", enabled\n");
2473 * If base is 0, then we have problems if this architecture does
2474 * not allow that. It is best to ignore such entries for the
2475 * moment. These will be allocated later if the driver specifically
2476 * requests them. However, some removable busses look better when
2477 * all resources are allocated, so allow '0' to be overriden.
2479 * Similarly treat maps whose values is the same as the test value
2480 * read back. These maps have had all f's written to them by the
2481 * BIOS in an attempt to disable the resources.
2483 if (!force && (basezero || map == testval))
2485 if ((u_long)base != base) {
2487 "pci%d:%d:%d:%d bar %#x too many address bits",
2488 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev),
2489 pci_get_function(dev), reg);
2494 * This code theoretically does the right thing, but has
2495 * undesirable side effects in some cases where peripherals
2496 * respond oddly to having these bits enabled. Let the user
2497 * be able to turn them off (since pci_enable_io_modes is 1 by
2500 if (pci_enable_io_modes) {
2501 /* Turn on resources that have been left off by a lazy BIOS */
2502 if (type == SYS_RES_IOPORT && !pci_porten(dev)) {
2503 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2504 cmd |= PCIM_CMD_PORTEN;
2505 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2507 if (type == SYS_RES_MEMORY && !pci_memen(dev)) {
2508 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2509 cmd |= PCIM_CMD_MEMEN;
2510 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2513 if (type == SYS_RES_IOPORT && !pci_porten(dev))
2515 if (type == SYS_RES_MEMORY && !pci_memen(dev))
2519 count = (pci_addr_t)1 << mapsize;
2520 if (basezero || base == pci_mapbase(testval)) {
2521 start = 0; /* Let the parent decide. */
2525 end = base + count - 1;
2527 resource_list_add(rl, type, reg, start, end, count);
2530 * Try to allocate the resource for this BAR from our parent
2531 * so that this resource range is already reserved. The
2532 * driver for this device will later inherit this resource in
2533 * pci_alloc_resource().
2535 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count,
2536 prefetch ? RF_PREFETCHABLE : 0);
2539 * If the allocation fails, clear the BAR and delete
2540 * the resource list entry to force
2541 * pci_alloc_resource() to allocate resources from the
2544 resource_list_delete(rl, type, reg);
2547 start = rman_get_start(res);
2548 rman_set_device(res, bus);
2550 pci_write_bar(dev, reg, start);
2555 * For ATA devices we need to decide early what addressing mode to use.
2556 * Legacy demands that the primary and secondary ATA ports sits on the
2557 * same addresses that old ISA hardware did. This dictates that we use
2558 * those addresses and ignore the BAR's if we cannot set PCI native
2562 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force,
2563 uint32_t prefetchmask)
2566 int rid, type, progif;
2568 /* if this device supports PCI native addressing use it */
2569 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2570 if ((progif & 0x8a) == 0x8a) {
2571 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2572 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
2573 printf("Trying ATA native PCI addressing mode\n");
2574 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2578 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2579 type = SYS_RES_IOPORT;
2580 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
2581 pci_add_map(bus, dev, PCIR_BAR(0), rl, force,
2582 prefetchmask & (1 << 0));
2583 pci_add_map(bus, dev, PCIR_BAR(1), rl, force,
2584 prefetchmask & (1 << 1));
2587 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
2588 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7,
2590 rman_set_device(r, bus);
2592 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
2593 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6,
2595 rman_set_device(r, bus);
2597 if (progif & PCIP_STORAGE_IDE_MODESEC) {
2598 pci_add_map(bus, dev, PCIR_BAR(2), rl, force,
2599 prefetchmask & (1 << 2));
2600 pci_add_map(bus, dev, PCIR_BAR(3), rl, force,
2601 prefetchmask & (1 << 3));
2604 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
2605 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177,
2607 rman_set_device(r, bus);
2609 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
2610 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376,
2612 rman_set_device(r, bus);
2614 pci_add_map(bus, dev, PCIR_BAR(4), rl, force,
2615 prefetchmask & (1 << 4));
2616 pci_add_map(bus, dev, PCIR_BAR(5), rl, force,
2617 prefetchmask & (1 << 5));
2621 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
2623 struct pci_devinfo *dinfo = device_get_ivars(dev);
2624 pcicfgregs *cfg = &dinfo->cfg;
2625 char tunable_name[64];
2628 /* Has to have an intpin to have an interrupt. */
2629 if (cfg->intpin == 0)
2632 /* Let the user override the IRQ with a tunable. */
2633 irq = PCI_INVALID_IRQ;
2634 snprintf(tunable_name, sizeof(tunable_name),
2635 "hw.pci%d.%d.%d.INT%c.irq",
2636 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
2637 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
2638 irq = PCI_INVALID_IRQ;
2641 * If we didn't get an IRQ via the tunable, then we either use the
2642 * IRQ value in the intline register or we ask the bus to route an
2643 * interrupt for us. If force_route is true, then we only use the
2644 * value in the intline register if the bus was unable to assign an
2647 if (!PCI_INTERRUPT_VALID(irq)) {
2648 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
2649 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
2650 if (!PCI_INTERRUPT_VALID(irq))
2654 /* If after all that we don't have an IRQ, just bail. */
2655 if (!PCI_INTERRUPT_VALID(irq))
2658 /* Update the config register if it changed. */
2659 if (irq != cfg->intline) {
2661 pci_write_config(dev, PCIR_INTLINE, irq, 1);
2664 /* Add this IRQ as rid 0 interrupt resource. */
2665 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
2668 /* Perform early OHCI takeover from SMM. */
2670 ohci_early_takeover(device_t self)
2672 struct resource *res;
2678 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
2682 ctl = bus_read_4(res, OHCI_CONTROL);
2683 if (ctl & OHCI_IR) {
2685 printf("ohci early: "
2686 "SMM active, request owner change\n");
2687 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR);
2688 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) {
2690 ctl = bus_read_4(res, OHCI_CONTROL);
2692 if (ctl & OHCI_IR) {
2694 printf("ohci early: "
2695 "SMM does not respond, resetting\n");
2696 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET);
2698 /* Disable interrupts */
2699 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
2702 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
2705 /* Perform early UHCI takeover from SMM. */
2707 uhci_early_takeover(device_t self)
2709 struct resource *res;
2713 * Set the PIRQD enable bit and switch off all the others. We don't
2714 * want legacy support to interfere with us XXX Does this also mean
2715 * that the BIOS won't touch the keyboard anymore if it is connected
2716 * to the ports of the root hub?
2718 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2);
2720 /* Disable interrupts */
2721 rid = PCI_UHCI_BASE_REG;
2722 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE);
2724 bus_write_2(res, UHCI_INTR, 0);
2725 bus_release_resource(self, SYS_RES_IOPORT, rid, res);
2729 /* Perform early EHCI takeover from SMM. */
2731 ehci_early_takeover(device_t self)
2733 struct resource *res;
2743 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
2747 cparams = bus_read_4(res, EHCI_HCCPARAMS);
2749 /* Synchronise with the BIOS if it owns the controller. */
2750 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0;
2751 eecp = EHCI_EECP_NEXT(eec)) {
2752 eec = pci_read_config(self, eecp, 4);
2753 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) {
2756 bios_sem = pci_read_config(self, eecp +
2757 EHCI_LEGSUP_BIOS_SEM, 1);
2758 if (bios_sem == 0) {
2762 printf("ehci early: "
2763 "SMM active, request owner change\n");
2765 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1);
2767 for (i = 0; (i < 100) && (bios_sem != 0); i++) {
2769 bios_sem = pci_read_config(self, eecp +
2770 EHCI_LEGSUP_BIOS_SEM, 1);
2773 if (bios_sem != 0) {
2775 printf("ehci early: "
2776 "SMM does not respond\n");
2778 /* Disable interrupts */
2779 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION));
2780 bus_write_4(res, offs + EHCI_USBINTR, 0);
2782 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
2786 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask)
2788 struct pci_devinfo *dinfo = device_get_ivars(dev);
2789 pcicfgregs *cfg = &dinfo->cfg;
2790 struct resource_list *rl = &dinfo->resources;
2791 struct pci_quirk *q;
2794 /* ATA devices needs special map treatment */
2795 if ((pci_get_class(dev) == PCIC_STORAGE) &&
2796 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
2797 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
2798 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
2799 !pci_read_config(dev, PCIR_BAR(2), 4))) )
2800 pci_ata_maps(bus, dev, rl, force, prefetchmask);
2802 for (i = 0; i < cfg->nummaps;)
2803 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force,
2804 prefetchmask & (1 << i));
2807 * Add additional, quirked resources.
2809 for (q = &pci_quirks[0]; q->devid; q++) {
2810 if (q->devid == ((cfg->device << 16) | cfg->vendor)
2811 && q->type == PCI_QUIRK_MAP_REG)
2812 pci_add_map(bus, dev, q->arg1, rl, force, 0);
2815 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2816 #ifdef __PCI_REROUTE_INTERRUPT
2818 * Try to re-route interrupts. Sometimes the BIOS or
2819 * firmware may leave bogus values in these registers.
2820 * If the re-route fails, then just stick with what we
2823 pci_assign_interrupt(bus, dev, 1);
2825 pci_assign_interrupt(bus, dev, 0);
2829 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS &&
2830 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) {
2831 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI)
2832 ehci_early_takeover(dev);
2833 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI)
2834 ohci_early_takeover(dev);
2835 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI)
2836 uhci_early_takeover(dev);
2841 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
2843 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
2844 device_t pcib = device_get_parent(dev);
2845 struct pci_devinfo *dinfo;
2847 int s, f, pcifunchigh;
2850 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
2851 ("dinfo_size too small"));
2852 maxslots = PCIB_MAXSLOTS(pcib);
2853 for (s = 0; s <= maxslots; s++) {
2857 hdrtype = REG(PCIR_HDRTYPE, 1);
2858 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
2860 if (hdrtype & PCIM_MFDEV)
2861 pcifunchigh = PCI_FUNCMAX;
2862 for (f = 0; f <= pcifunchigh; f++) {
2863 dinfo = pci_read_device(pcib, domain, busno, s, f,
2865 if (dinfo != NULL) {
2866 pci_add_child(dev, dinfo);
2874 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
2876 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
2877 device_set_ivars(dinfo->cfg.dev, dinfo);
2878 resource_list_init(&dinfo->resources);
2879 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
2880 pci_cfg_restore(dinfo->cfg.dev, dinfo);
2881 pci_print_verbose(dinfo);
2882 pci_add_resources(bus, dinfo->cfg.dev, 0, 0);
2886 pci_probe(device_t dev)
2889 device_set_desc(dev, "PCI bus");
2891 /* Allow other subclasses to override this driver. */
2892 return (BUS_PROBE_GENERIC);
2896 pci_attach(device_t dev)
2901 * Since there can be multiple independantly numbered PCI
2902 * busses on systems with multiple PCI domains, we can't use
2903 * the unit number to decide which bus we are probing. We ask
2904 * the parent pcib what our domain and bus numbers are.
2906 domain = pcib_get_domain(dev);
2907 busno = pcib_get_bus(dev);
2909 device_printf(dev, "domain=%d, physical bus=%d\n",
2911 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
2912 return (bus_generic_attach(dev));
2916 pci_suspend(device_t dev)
2918 int dstate, error, i, numdevs;
2919 device_t acpi_dev, child, *devlist;
2920 struct pci_devinfo *dinfo;
2923 * Save the PCI configuration space for each child and set the
2924 * device in the appropriate power state for this sleep state.
2927 if (pci_do_power_resume)
2928 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2929 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0)
2931 for (i = 0; i < numdevs; i++) {
2933 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2934 pci_cfg_save(child, dinfo, 0);
2937 /* Suspend devices before potentially powering them down. */
2938 error = bus_generic_suspend(dev);
2940 free(devlist, M_TEMP);
2945 * Always set the device to D3. If ACPI suggests a different
2946 * power state, use it instead. If ACPI is not present, the
2947 * firmware is responsible for managing device power. Skip
2948 * children who aren't attached since they are powered down
2949 * separately. Only manage type 0 devices for now.
2951 for (i = 0; acpi_dev && i < numdevs; i++) {
2953 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2954 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) {
2955 dstate = PCI_POWERSTATE_D3;
2956 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate);
2957 pci_set_powerstate(child, dstate);
2960 free(devlist, M_TEMP);
2965 pci_resume(device_t dev)
2967 int i, numdevs, error;
2968 device_t acpi_dev, child, *devlist;
2969 struct pci_devinfo *dinfo;
2972 * Set each child to D0 and restore its PCI configuration space.
2975 if (pci_do_power_resume)
2976 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2977 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0)
2979 for (i = 0; i < numdevs; i++) {
2981 * Notify ACPI we're going to D0 but ignore the result. If
2982 * ACPI is not present, the firmware is responsible for
2983 * managing device power. Only manage type 0 devices for now.
2986 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2987 if (acpi_dev && device_is_attached(child) &&
2988 dinfo->cfg.hdrtype == 0) {
2989 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL);
2990 pci_set_powerstate(child, PCI_POWERSTATE_D0);
2993 /* Now the device is powered up, restore its config space. */
2994 pci_cfg_restore(child, dinfo);
2996 free(devlist, M_TEMP);
2997 return (bus_generic_resume(dev));
3001 pci_load_vendor_data(void)
3003 caddr_t vendordata, info;
3005 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
3006 info = preload_search_info(vendordata, MODINFO_ADDR);
3007 pci_vendordata = *(char **)info;
3008 info = preload_search_info(vendordata, MODINFO_SIZE);
3009 pci_vendordata_size = *(size_t *)info;
3010 /* terminate the database */
3011 pci_vendordata[pci_vendordata_size] = '\n';
3016 pci_driver_added(device_t dev, driver_t *driver)
3021 struct pci_devinfo *dinfo;
3025 device_printf(dev, "driver added\n");
3026 DEVICE_IDENTIFY(driver, dev);
3027 if (device_get_children(dev, &devlist, &numdevs) != 0)
3029 for (i = 0; i < numdevs; i++) {
3031 if (device_get_state(child) != DS_NOTPRESENT)
3033 dinfo = device_get_ivars(child);
3034 pci_print_verbose(dinfo);
3036 pci_printf(&dinfo->cfg, "reprobing on driver added\n");
3037 pci_cfg_restore(child, dinfo);
3038 if (device_probe_and_attach(child) != 0)
3039 pci_cfg_save(child, dinfo, 1);
3041 free(devlist, M_TEMP);
3045 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
3046 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep)
3048 struct pci_devinfo *dinfo;
3049 struct msix_table_entry *mte;
3050 struct msix_vector *mv;
3056 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr,
3061 /* If this is not a direct child, just bail out. */
3062 if (device_get_parent(child) != dev) {
3067 rid = rman_get_rid(irq);
3069 /* Make sure that INTx is enabled */
3070 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3073 * Check to see if the interrupt is MSI or MSI-X.
3074 * Ask our parent to map the MSI and give
3075 * us the address and data register values.
3076 * If we fail for some reason, teardown the
3077 * interrupt handler.
3079 dinfo = device_get_ivars(child);
3080 if (dinfo->cfg.msi.msi_alloc > 0) {
3081 if (dinfo->cfg.msi.msi_addr == 0) {
3082 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
3083 ("MSI has handlers, but vectors not mapped"));
3084 error = PCIB_MAP_MSI(device_get_parent(dev),
3085 child, rman_get_start(irq), &addr, &data);
3088 dinfo->cfg.msi.msi_addr = addr;
3089 dinfo->cfg.msi.msi_data = data;
3091 if (dinfo->cfg.msi.msi_handlers == 0)
3092 pci_enable_msi(child, dinfo->cfg.msi.msi_addr,
3093 dinfo->cfg.msi.msi_data);
3094 dinfo->cfg.msi.msi_handlers++;
3096 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3097 ("No MSI or MSI-X interrupts allocated"));
3098 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3099 ("MSI-X index too high"));
3100 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3101 KASSERT(mte->mte_vector != 0, ("no message vector"));
3102 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
3103 KASSERT(mv->mv_irq == rman_get_start(irq),
3105 if (mv->mv_address == 0) {
3106 KASSERT(mte->mte_handlers == 0,
3107 ("MSI-X table entry has handlers, but vector not mapped"));
3108 error = PCIB_MAP_MSI(device_get_parent(dev),
3109 child, rman_get_start(irq), &addr, &data);
3112 mv->mv_address = addr;
3115 if (mte->mte_handlers == 0) {
3116 pci_enable_msix(child, rid - 1, mv->mv_address,
3118 pci_unmask_msix(child, rid - 1);
3120 mte->mte_handlers++;
3123 /* Make sure that INTx is disabled if we are using MSI/MSIX */
3124 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3127 (void)bus_generic_teardown_intr(dev, child, irq,
3137 pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
3140 struct msix_table_entry *mte;
3141 struct resource_list_entry *rle;
3142 struct pci_devinfo *dinfo;
3145 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
3148 /* If this isn't a direct child, just bail out */
3149 if (device_get_parent(child) != dev)
3150 return(bus_generic_teardown_intr(dev, child, irq, cookie));
3152 rid = rman_get_rid(irq);
3155 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3158 * Check to see if the interrupt is MSI or MSI-X. If so,
3159 * decrement the appropriate handlers count and mask the
3160 * MSI-X message, or disable MSI messages if the count
3163 dinfo = device_get_ivars(child);
3164 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
3165 if (rle->res != irq)
3167 if (dinfo->cfg.msi.msi_alloc > 0) {
3168 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
3169 ("MSI-X index too high"));
3170 if (dinfo->cfg.msi.msi_handlers == 0)
3172 dinfo->cfg.msi.msi_handlers--;
3173 if (dinfo->cfg.msi.msi_handlers == 0)
3174 pci_disable_msi(child);
3176 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3177 ("No MSI or MSI-X interrupts allocated"));
3178 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3179 ("MSI-X index too high"));
3180 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3181 if (mte->mte_handlers == 0)
3183 mte->mte_handlers--;
3184 if (mte->mte_handlers == 0)
3185 pci_mask_msix(child, rid - 1);
3188 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3191 ("%s: generic teardown failed for MSI/MSI-X", __func__));
3196 pci_print_child(device_t dev, device_t child)
3198 struct pci_devinfo *dinfo;
3199 struct resource_list *rl;
3202 dinfo = device_get_ivars(child);
3203 rl = &dinfo->resources;
3205 retval += bus_print_child_header(dev, child);
3207 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
3208 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
3209 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
3210 if (device_get_flags(dev))
3211 retval += printf(" flags %#x", device_get_flags(dev));
3213 retval += printf(" at device %d.%d", pci_get_slot(child),
3214 pci_get_function(child));
3216 retval += bus_print_child_footer(dev, child);
3226 } pci_nomatch_tab[] = {
3227 {PCIC_OLD, -1, "old"},
3228 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
3229 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
3230 {PCIC_STORAGE, -1, "mass storage"},
3231 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
3232 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
3233 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
3234 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
3235 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
3236 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"},
3237 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"},
3238 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"},
3239 {PCIC_NETWORK, -1, "network"},
3240 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
3241 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
3242 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
3243 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
3244 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
3245 {PCIC_DISPLAY, -1, "display"},
3246 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
3247 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
3248 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
3249 {PCIC_MULTIMEDIA, -1, "multimedia"},
3250 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
3251 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
3252 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
3253 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"},
3254 {PCIC_MEMORY, -1, "memory"},
3255 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
3256 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
3257 {PCIC_BRIDGE, -1, "bridge"},
3258 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
3259 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
3260 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
3261 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
3262 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
3263 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
3264 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
3265 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
3266 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
3267 {PCIC_SIMPLECOMM, -1, "simple comms"},
3268 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
3269 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
3270 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
3271 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
3272 {PCIC_BASEPERIPH, -1, "base peripheral"},
3273 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
3274 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
3275 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
3276 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
3277 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
3278 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"},
3279 {PCIC_INPUTDEV, -1, "input device"},
3280 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
3281 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
3282 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
3283 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
3284 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
3285 {PCIC_DOCKING, -1, "docking station"},
3286 {PCIC_PROCESSOR, -1, "processor"},
3287 {PCIC_SERIALBUS, -1, "serial bus"},
3288 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
3289 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
3290 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
3291 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
3292 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
3293 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
3294 {PCIC_WIRELESS, -1, "wireless controller"},
3295 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
3296 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
3297 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
3298 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
3299 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
3300 {PCIC_SATCOM, -1, "satellite communication"},
3301 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
3302 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
3303 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
3304 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
3305 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
3306 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
3307 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
3308 {PCIC_DASP, -1, "dasp"},
3309 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
3314 pci_probe_nomatch(device_t dev, device_t child)
3317 char *cp, *scp, *device;
3320 * Look for a listing for this device in a loaded device database.
3322 if ((device = pci_describe_device(child)) != NULL) {
3323 device_printf(dev, "<%s>", device);
3324 free(device, M_DEVBUF);
3327 * Scan the class/subclass descriptions for a general
3332 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
3333 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
3334 if (pci_nomatch_tab[i].subclass == -1) {
3335 cp = pci_nomatch_tab[i].desc;
3336 } else if (pci_nomatch_tab[i].subclass ==
3337 pci_get_subclass(child)) {
3338 scp = pci_nomatch_tab[i].desc;
3342 device_printf(dev, "<%s%s%s>",
3344 ((cp != NULL) && (scp != NULL)) ? ", " : "",
3347 printf(" at device %d.%d (no driver attached)\n",
3348 pci_get_slot(child), pci_get_function(child));
3349 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1);
3354 * Parse the PCI device database, if loaded, and return a pointer to a
3355 * description of the device.
3357 * The database is flat text formatted as follows:
3359 * Any line not in a valid format is ignored.
3360 * Lines are terminated with newline '\n' characters.
3362 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
3365 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
3366 * - devices cannot be listed without a corresponding VENDOR line.
3367 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
3368 * another TAB, then the device name.
3372 * Assuming (ptr) points to the beginning of a line in the database,
3373 * return the vendor or device and description of the next entry.
3374 * The value of (vendor) or (device) inappropriate for the entry type
3375 * is set to -1. Returns nonzero at the end of the database.
3377 * Note that this is slightly unrobust in the face of corrupt data;
3378 * we attempt to safeguard against this by spamming the end of the
3379 * database with a newline when we initialise.
3382 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
3391 left = pci_vendordata_size - (cp - pci_vendordata);
3399 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
3403 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
3406 /* skip to next line */
3407 while (*cp != '\n' && left > 0) {
3416 /* skip to next line */
3417 while (*cp != '\n' && left > 0) {
3421 if (*cp == '\n' && left > 0)
3428 pci_describe_device(device_t dev)
3431 char *desc, *vp, *dp, *line;
3433 desc = vp = dp = NULL;
3436 * If we have no vendor data, we can't do anything.
3438 if (pci_vendordata == NULL)
3442 * Scan the vendor data looking for this device
3444 line = pci_vendordata;
3445 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3448 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
3450 if (vendor == pci_get_vendor(dev))
3453 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3456 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
3464 if (device == pci_get_device(dev))
3468 snprintf(dp, 80, "0x%x", pci_get_device(dev));
3469 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
3471 sprintf(desc, "%s, %s", vp, dp);
3481 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
3483 struct pci_devinfo *dinfo;
3486 dinfo = device_get_ivars(child);
3490 case PCI_IVAR_ETHADDR:
3492 * The generic accessor doesn't deal with failure, so
3493 * we set the return value, then return an error.
3495 *((uint8_t **) result) = NULL;
3497 case PCI_IVAR_SUBVENDOR:
3498 *result = cfg->subvendor;
3500 case PCI_IVAR_SUBDEVICE:
3501 *result = cfg->subdevice;
3503 case PCI_IVAR_VENDOR:
3504 *result = cfg->vendor;
3506 case PCI_IVAR_DEVICE:
3507 *result = cfg->device;
3509 case PCI_IVAR_DEVID:
3510 *result = (cfg->device << 16) | cfg->vendor;
3512 case PCI_IVAR_CLASS:
3513 *result = cfg->baseclass;
3515 case PCI_IVAR_SUBCLASS:
3516 *result = cfg->subclass;
3518 case PCI_IVAR_PROGIF:
3519 *result = cfg->progif;
3521 case PCI_IVAR_REVID:
3522 *result = cfg->revid;
3524 case PCI_IVAR_INTPIN:
3525 *result = cfg->intpin;
3528 *result = cfg->intline;
3530 case PCI_IVAR_DOMAIN:
3531 *result = cfg->domain;
3537 *result = cfg->slot;
3539 case PCI_IVAR_FUNCTION:
3540 *result = cfg->func;
3542 case PCI_IVAR_CMDREG:
3543 *result = cfg->cmdreg;
3545 case PCI_IVAR_CACHELNSZ:
3546 *result = cfg->cachelnsz;
3548 case PCI_IVAR_MINGNT:
3549 *result = cfg->mingnt;
3551 case PCI_IVAR_MAXLAT:
3552 *result = cfg->maxlat;
3554 case PCI_IVAR_LATTIMER:
3555 *result = cfg->lattimer;
3564 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
3566 struct pci_devinfo *dinfo;
3568 dinfo = device_get_ivars(child);
3571 case PCI_IVAR_INTPIN:
3572 dinfo->cfg.intpin = value;
3574 case PCI_IVAR_ETHADDR:
3575 case PCI_IVAR_SUBVENDOR:
3576 case PCI_IVAR_SUBDEVICE:
3577 case PCI_IVAR_VENDOR:
3578 case PCI_IVAR_DEVICE:
3579 case PCI_IVAR_DEVID:
3580 case PCI_IVAR_CLASS:
3581 case PCI_IVAR_SUBCLASS:
3582 case PCI_IVAR_PROGIF:
3583 case PCI_IVAR_REVID:
3585 case PCI_IVAR_DOMAIN:
3588 case PCI_IVAR_FUNCTION:
3589 return (EINVAL); /* disallow for now */
3597 #include "opt_ddb.h"
3599 #include <ddb/ddb.h>
3600 #include <sys/cons.h>
3603 * List resources based on pci map registers, used for within ddb
3606 DB_SHOW_COMMAND(pciregs, db_pci_dump)
3608 struct pci_devinfo *dinfo;
3609 struct devlist *devlist_head;
3612 int i, error, none_count;
3615 /* get the head of the device queue */
3616 devlist_head = &pci_devq;
3619 * Go through the list of devices and print out devices
3621 for (error = 0, i = 0,
3622 dinfo = STAILQ_FIRST(devlist_head);
3623 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
3624 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
3626 /* Populate pd_name and pd_unit */
3629 name = device_get_name(dinfo->cfg.dev);
3632 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
3633 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
3634 (name && *name) ? name : "none",
3635 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
3637 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
3638 p->pc_sel.pc_func, (p->pc_class << 16) |
3639 (p->pc_subclass << 8) | p->pc_progif,
3640 (p->pc_subdevice << 16) | p->pc_subvendor,
3641 (p->pc_device << 16) | p->pc_vendor,
3642 p->pc_revid, p->pc_hdr);
3647 static struct resource *
3648 pci_alloc_map(device_t dev, device_t child, int type, int *rid,
3649 u_long start, u_long end, u_long count, u_int flags)
3651 struct pci_devinfo *dinfo = device_get_ivars(child);
3652 struct resource_list *rl = &dinfo->resources;
3653 struct resource_list_entry *rle;
3654 struct resource *res;
3655 pci_addr_t map, testval;
3659 * Weed out the bogons, and figure out how large the BAR/map
3660 * is. Bars that read back 0 here are bogus and unimplemented.
3661 * Note: atapci in legacy mode are special and handled elsewhere
3662 * in the code. If you have a atapci device in legacy mode and
3663 * it fails here, that other code is broken.
3666 pci_read_bar(child, *rid, &map, &testval);
3668 /* Ignore a BAR with a base of 0. */
3669 if (pci_mapbase(testval) == 0)
3672 if (PCI_BAR_MEM(testval)) {
3673 if (type != SYS_RES_MEMORY) {
3676 "child %s requested type %d for rid %#x,"
3677 " but the BAR says it is an memio\n",
3678 device_get_nameunit(child), type, *rid);
3682 if (type != SYS_RES_IOPORT) {
3685 "child %s requested type %d for rid %#x,"
3686 " but the BAR says it is an ioport\n",
3687 device_get_nameunit(child), type, *rid);
3693 * For real BARs, we need to override the size that
3694 * the driver requests, because that's what the BAR
3695 * actually uses and we would otherwise have a
3696 * situation where we might allocate the excess to
3697 * another driver, which won't work.
3699 mapsize = pci_mapsize(testval);
3700 count = (pci_addr_t)1 << mapsize;
3701 if (RF_ALIGNMENT(flags) < mapsize)
3702 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
3703 if (PCI_BAR_MEM(testval) && (testval & PCIM_BAR_MEM_PREFETCH))
3704 flags |= RF_PREFETCHABLE;
3707 * Allocate enough resource, and then write back the
3708 * appropriate bar for that resource.
3710 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
3711 start, end, count, flags & ~RF_ACTIVE);
3713 device_printf(child,
3714 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
3715 count, *rid, type, start, end);
3718 rman_set_device(res, dev);
3719 resource_list_add(rl, type, *rid, start, end, count);
3720 rle = resource_list_find(rl, type, *rid);
3722 panic("pci_alloc_map: unexpectedly can't find resource.");
3724 rle->start = rman_get_start(res);
3725 rle->end = rman_get_end(res);
3728 device_printf(child,
3729 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
3730 count, *rid, type, rman_get_start(res));
3731 map = rman_get_start(res);
3732 pci_write_bar(child, *rid, map);
3739 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
3740 u_long start, u_long end, u_long count, u_int flags)
3742 struct pci_devinfo *dinfo = device_get_ivars(child);
3743 struct resource_list *rl = &dinfo->resources;
3744 struct resource_list_entry *rle;
3745 struct resource *res;
3746 pcicfgregs *cfg = &dinfo->cfg;
3748 if (device_get_parent(child) != dev)
3749 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
3750 type, rid, start, end, count, flags));
3753 * Perform lazy resource allocation
3758 * Can't alloc legacy interrupt once MSI messages have
3761 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
3762 cfg->msix.msix_alloc > 0))
3766 * If the child device doesn't have an interrupt
3767 * routed and is deserving of an interrupt, try to
3770 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
3772 pci_assign_interrupt(dev, child, 0);
3774 case SYS_RES_IOPORT:
3775 case SYS_RES_MEMORY:
3778 * PCI-PCI bridge I/O window resources are not BARs.
3779 * For those allocations just pass the request up the
3782 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) {
3784 case PCIR_IOBASEL_1:
3785 case PCIR_MEMBASE_1:
3786 case PCIR_PMBASEL_1:
3788 * XXX: Should we bother creating a resource
3791 return (bus_generic_alloc_resource(dev, child,
3792 type, rid, start, end, count, flags));
3796 /* Allocate resources for this BAR if needed. */
3797 rle = resource_list_find(rl, type, *rid);
3799 res = pci_alloc_map(dev, child, type, rid, start, end,
3803 rle = resource_list_find(rl, type, *rid);
3807 * If the resource belongs to the bus, then give it to
3808 * the child. We need to activate it if requested
3809 * since the bus always allocates inactive resources.
3811 if (rle != NULL && rle->res != NULL &&
3812 rman_get_device(rle->res) == dev) {
3814 device_printf(child,
3815 "Reserved %#lx bytes for rid %#x type %d at %#lx\n",
3816 rman_get_size(rle->res), *rid, type,
3817 rman_get_start(rle->res));
3818 rman_set_device(rle->res, child);
3819 if ((flags & RF_ACTIVE) &&
3820 bus_activate_resource(child, type, *rid,
3826 return (resource_list_alloc(rl, dev, child, type, rid,
3827 start, end, count, flags));
3831 pci_release_resource(device_t dev, device_t child, int type, int rid,
3836 if (device_get_parent(child) != dev)
3837 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
3841 * For BARs we don't actually want to release the resource.
3842 * Instead, we deactivate the resource if needed and then give
3843 * ownership of the BAR back to the bus.
3846 case SYS_RES_IOPORT:
3847 case SYS_RES_MEMORY:
3848 if (rman_get_device(r) != child)
3850 if (rman_get_flags(r) & RF_ACTIVE) {
3851 error = bus_deactivate_resource(child, type, rid, r);
3855 rman_set_device(r, dev);
3858 return (bus_generic_rl_release_resource(dev, child, type, rid, r));
3862 pci_activate_resource(device_t dev, device_t child, int type, int rid,
3867 error = bus_generic_activate_resource(dev, child, type, rid, r);
3871 /* Enable decoding in the command register when activating BARs. */
3872 if (device_get_parent(child) == dev) {
3874 case SYS_RES_IOPORT:
3875 case SYS_RES_MEMORY:
3876 error = PCI_ENABLE_IO(dev, child, type);
3884 pci_delete_resource(device_t dev, device_t child, int type, int rid)
3886 struct pci_devinfo *dinfo;
3887 struct resource_list *rl;
3888 struct resource_list_entry *rle;
3890 if (device_get_parent(child) != dev)
3893 dinfo = device_get_ivars(child);
3894 rl = &dinfo->resources;
3895 rle = resource_list_find(rl, type, rid);
3900 if (rman_get_device(rle->res) != dev ||
3901 rman_get_flags(rle->res) & RF_ACTIVE) {
3902 device_printf(dev, "delete_resource: "
3903 "Resource still owned by child, oops. "
3904 "(type=%d, rid=%d, addr=%lx)\n",
3905 rle->type, rle->rid,
3906 rman_get_start(rle->res));
3910 #ifndef __PCI_BAR_ZERO_VALID
3912 * If this is a BAR, clear the BAR so it stops
3913 * decoding before releasing the resource.
3916 case SYS_RES_IOPORT:
3917 case SYS_RES_MEMORY:
3918 pci_write_bar(child, rid, 0);
3922 bus_release_resource(dev, type, rid, rle->res);
3924 resource_list_delete(rl, type, rid);
3927 struct resource_list *
3928 pci_get_resource_list (device_t dev, device_t child)
3930 struct pci_devinfo *dinfo = device_get_ivars(child);
3932 return (&dinfo->resources);
3936 pci_read_config_method(device_t dev, device_t child, int reg, int width)
3938 struct pci_devinfo *dinfo = device_get_ivars(child);
3939 pcicfgregs *cfg = &dinfo->cfg;
3941 return (PCIB_READ_CONFIG(device_get_parent(dev),
3942 cfg->bus, cfg->slot, cfg->func, reg, width));
3946 pci_write_config_method(device_t dev, device_t child, int reg,
3947 uint32_t val, int width)
3949 struct pci_devinfo *dinfo = device_get_ivars(child);
3950 pcicfgregs *cfg = &dinfo->cfg;
3952 PCIB_WRITE_CONFIG(device_get_parent(dev),
3953 cfg->bus, cfg->slot, cfg->func, reg, val, width);
3957 pci_child_location_str_method(device_t dev, device_t child, char *buf,
3961 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
3962 pci_get_function(child));
3967 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
3970 struct pci_devinfo *dinfo;
3973 dinfo = device_get_ivars(child);
3975 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
3976 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
3977 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
3983 pci_assign_interrupt_method(device_t dev, device_t child)
3985 struct pci_devinfo *dinfo = device_get_ivars(child);
3986 pcicfgregs *cfg = &dinfo->cfg;
3988 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
3993 pci_modevent(module_t mod, int what, void *arg)
3995 static struct cdev *pci_cdev;
3999 STAILQ_INIT(&pci_devq);
4001 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644,
4003 pci_load_vendor_data();
4007 destroy_dev(pci_cdev);
4015 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
4020 * Only do header type 0 devices. Type 1 devices are bridges,
4021 * which we know need special treatment. Type 2 devices are
4022 * cardbus bridges which also require special treatment.
4023 * Other types are unknown, and we err on the side of safety
4026 if (dinfo->cfg.hdrtype != 0)
4030 * Restore the device to full power mode. We must do this
4031 * before we restore the registers because moving from D3 to
4032 * D0 will cause the chip's BARs and some other registers to
4033 * be reset to some unknown power on reset values. Cut down
4034 * the noise on boot by doing nothing if we are already in
4037 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
4038 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4040 for (i = 0; i < dinfo->cfg.nummaps; i++)
4041 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
4042 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
4043 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
4044 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
4045 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
4046 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
4047 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
4048 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
4049 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
4050 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
4051 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
4053 /* Restore MSI and MSI-X configurations if they are present. */
4054 if (dinfo->cfg.msi.msi_location != 0)
4055 pci_resume_msi(dev);
4056 if (dinfo->cfg.msix.msix_location != 0)
4057 pci_resume_msix(dev);
4061 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
4068 * Only do header type 0 devices. Type 1 devices are bridges, which
4069 * we know need special treatment. Type 2 devices are cardbus bridges
4070 * which also require special treatment. Other types are unknown, and
4071 * we err on the side of safety by ignoring them. Powering down
4072 * bridges should not be undertaken lightly.
4074 if (dinfo->cfg.hdrtype != 0)
4076 for (i = 0; i < dinfo->cfg.nummaps; i++)
4077 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
4078 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
4081 * Some drivers apparently write to these registers w/o updating our
4082 * cached copy. No harm happens if we update the copy, so do so here
4083 * so we can restore them. The COMMAND register is modified by the
4084 * bus w/o updating the cache. This should represent the normally
4085 * writable portion of the 'defined' part of type 0 headers. In
4086 * theory we also need to save/restore the PCI capability structures
4087 * we know about, but apart from power we don't know any that are
4090 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
4091 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4092 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
4093 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
4094 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
4095 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
4096 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
4097 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
4098 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
4099 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
4100 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
4101 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
4102 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
4103 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
4104 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
4107 * don't set the state for display devices, base peripherals and
4108 * memory devices since bad things happen when they are powered down.
4109 * We should (a) have drivers that can easily detach and (b) use
4110 * generic drivers for these devices so that some device actually
4111 * attaches. We need to make sure that when we implement (a) we don't
4112 * power the device down on a reattach.
4114 cls = pci_get_class(dev);
4117 switch (pci_do_power_nodriver)
4119 case 0: /* NO powerdown at all */
4121 case 1: /* Conservative about what to power down */
4122 if (cls == PCIC_STORAGE)
4125 case 2: /* Agressive about what to power down */
4126 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
4127 cls == PCIC_BASEPERIPH)
4130 case 3: /* Power down everything */
4134 * PCI spec says we can only go into D3 state from D0 state.
4135 * Transition from D[12] into D0 before going to D3 state.
4137 ps = pci_get_powerstate(dev);
4138 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
4139 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4140 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
4141 pci_set_powerstate(dev, PCI_POWERSTATE_D3);