2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/linker.h>
39 #include <sys/fcntl.h>
41 #include <sys/kernel.h>
42 #include <sys/queue.h>
43 #include <sys/sysctl.h>
44 #include <sys/endian.h>
48 #include <vm/vm_extern.h>
51 #include <machine/bus.h>
53 #include <machine/resource.h>
54 #include <machine/stdarg.h>
56 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
57 #include <machine/intr_machdep.h>
60 #include <sys/pciio.h>
61 #include <dev/pci/pcireg.h>
62 #include <dev/pci/pcivar.h>
63 #include <dev/pci/pci_private.h>
65 #include <dev/usb/controller/ehcireg.h>
66 #include <dev/usb/controller/ohcireg.h>
67 #include <dev/usb/controller/uhcireg.h>
73 #include <contrib/dev/acpica/include/acpi.h>
76 #define ACPI_PWR_FOR_SLEEP(x, y, z)
79 static pci_addr_t pci_mapbase(uint64_t mapreg);
80 static const char *pci_maptype(uint64_t mapreg);
81 static int pci_mapsize(uint64_t testval);
82 static int pci_maprange(uint64_t mapreg);
83 static void pci_fixancient(pcicfgregs *cfg);
84 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...);
86 static int pci_porten(device_t dev);
87 static int pci_memen(device_t dev);
88 static void pci_assign_interrupt(device_t bus, device_t dev,
90 static int pci_add_map(device_t bus, device_t dev, int reg,
91 struct resource_list *rl, int force, int prefetch);
92 static int pci_probe(device_t dev);
93 static int pci_attach(device_t dev);
94 static void pci_load_vendor_data(void);
95 static int pci_describe_parse_line(char **ptr, int *vendor,
96 int *device, char **desc);
97 static char *pci_describe_device(device_t dev);
98 static int pci_modevent(module_t mod, int what, void *arg);
99 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
101 static void pci_read_cap(device_t pcib, pcicfgregs *cfg);
102 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
103 int reg, uint32_t *data);
105 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
106 int reg, uint32_t data);
108 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
109 static void pci_disable_msi(device_t dev);
110 static void pci_enable_msi(device_t dev, uint64_t address,
112 static void pci_enable_msix(device_t dev, u_int index,
113 uint64_t address, uint32_t data);
114 static void pci_mask_msix(device_t dev, u_int index);
115 static void pci_unmask_msix(device_t dev, u_int index);
116 static int pci_msi_blacklisted(void);
117 static void pci_resume_msi(device_t dev);
118 static void pci_resume_msix(device_t dev);
119 static int pci_remap_intr_method(device_t bus, device_t dev,
122 static device_method_t pci_methods[] = {
123 /* Device interface */
124 DEVMETHOD(device_probe, pci_probe),
125 DEVMETHOD(device_attach, pci_attach),
126 DEVMETHOD(device_detach, bus_generic_detach),
127 DEVMETHOD(device_shutdown, bus_generic_shutdown),
128 DEVMETHOD(device_suspend, pci_suspend),
129 DEVMETHOD(device_resume, pci_resume),
132 DEVMETHOD(bus_print_child, pci_print_child),
133 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
134 DEVMETHOD(bus_read_ivar, pci_read_ivar),
135 DEVMETHOD(bus_write_ivar, pci_write_ivar),
136 DEVMETHOD(bus_driver_added, pci_driver_added),
137 DEVMETHOD(bus_setup_intr, pci_setup_intr),
138 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
140 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
141 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
142 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
143 DEVMETHOD(bus_delete_resource, pci_delete_resource),
144 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
145 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
146 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
147 DEVMETHOD(bus_activate_resource, pci_activate_resource),
148 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
149 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
150 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
151 DEVMETHOD(bus_remap_intr, pci_remap_intr_method),
154 DEVMETHOD(pci_read_config, pci_read_config_method),
155 DEVMETHOD(pci_write_config, pci_write_config_method),
156 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
157 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
158 DEVMETHOD(pci_enable_io, pci_enable_io_method),
159 DEVMETHOD(pci_disable_io, pci_disable_io_method),
160 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
161 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
162 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
163 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
164 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
165 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
166 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
167 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method),
168 DEVMETHOD(pci_remap_msix, pci_remap_msix_method),
169 DEVMETHOD(pci_release_msi, pci_release_msi_method),
170 DEVMETHOD(pci_msi_count, pci_msi_count_method),
171 DEVMETHOD(pci_msix_count, pci_msix_count_method),
176 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
178 static devclass_t pci_devclass;
179 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
180 MODULE_VERSION(pci, 1);
182 static char *pci_vendordata;
183 static size_t pci_vendordata_size;
186 uint32_t devid; /* Vendor/device of the card */
188 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
189 #define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */
190 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */
191 #define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */
196 static const struct pci_quirk const pci_quirks[] = {
197 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
198 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
199 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
200 /* As does the Serverworks OSB4 (the SMBus mapping register) */
201 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
204 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
205 * or the CMIC-SL (AKA ServerWorks GC_LE).
207 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
208 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
211 * MSI doesn't work on earlier Intel chipsets including
212 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
214 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
215 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
216 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
217 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
218 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
219 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
220 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
223 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
226 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
229 * MSI-X doesn't work with at least LSI SAS1068E passed through by
232 { 0x079015ad, PCI_QUIRK_DISABLE_MSI, 0, 0 },
235 * Some virtualization environments emulate an older chipset
236 * but support MSI just fine. QEMU uses the Intel 82440.
238 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 },
241 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus
242 * controller depending on SoftPciRst register (PM_IO 0x55 [7]).
243 * It prevents us from attaching hpet(4) when the bit is unset.
244 * Note this quirk only affects SB600 revision A13 and earlier.
245 * For SB600 A21 and later, firmware must set the bit to hide it.
246 * For SB700 and later, it is unused and hardcoded to zero.
248 { 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 },
253 /* map register information */
254 #define PCI_MAPMEM 0x01 /* memory map */
255 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
256 #define PCI_MAPPORT 0x04 /* port map */
258 struct devlist pci_devq;
259 uint32_t pci_generation;
260 uint32_t pci_numdevs = 0;
261 static int pcie_chipset, pcix_chipset;
264 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
266 static int pci_enable_io_modes = 1;
267 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
268 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
269 &pci_enable_io_modes, 1,
270 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
271 enable these bits correctly. We'd like to do this all the time, but there\n\
272 are some peripherals that this causes problems with.");
274 static int pci_do_power_nodriver = 0;
275 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
276 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
277 &pci_do_power_nodriver, 0,
278 "Place a function into D3 state when no driver attaches to it. 0 means\n\
279 disable. 1 means conservatively place devices into D3 state. 2 means\n\
280 agressively place devices into D3 state. 3 means put absolutely everything\n\
283 static int pci_do_power_resume = 1;
284 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
285 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
286 &pci_do_power_resume, 1,
287 "Transition from D3 -> D0 on resume.");
289 static int pci_do_msi = 1;
290 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
291 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
292 "Enable support for MSI interrupts");
294 static int pci_do_msix = 1;
295 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
296 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
297 "Enable support for MSI-X interrupts");
299 static int pci_honor_msi_blacklist = 1;
300 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
301 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
302 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI");
304 #if defined(__i386__) || defined(__amd64__)
305 static int pci_usb_takeover = 1;
307 static int pci_usb_takeover = 0;
309 TUNABLE_INT("hw.pci.usb_early_takeover", &pci_usb_takeover);
310 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RD | CTLFLAG_TUN,
311 &pci_usb_takeover, 1, "Enable early takeover of USB controllers.\n\
312 Disable this if you depend on BIOS emulation of USB devices, that is\n\
313 you use USB devices (like keyboard or mouse) but do not load USB drivers");
315 /* Find a device_t by bus/slot/function in domain 0 */
318 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
321 return (pci_find_dbsf(0, bus, slot, func));
324 /* Find a device_t by domain/bus/slot/function */
327 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
329 struct pci_devinfo *dinfo;
331 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
332 if ((dinfo->cfg.domain == domain) &&
333 (dinfo->cfg.bus == bus) &&
334 (dinfo->cfg.slot == slot) &&
335 (dinfo->cfg.func == func)) {
336 return (dinfo->cfg.dev);
343 /* Find a device_t by vendor/device ID */
346 pci_find_device(uint16_t vendor, uint16_t device)
348 struct pci_devinfo *dinfo;
350 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
351 if ((dinfo->cfg.vendor == vendor) &&
352 (dinfo->cfg.device == device)) {
353 return (dinfo->cfg.dev);
361 pci_find_class(uint8_t class, uint8_t subclass)
363 struct pci_devinfo *dinfo;
365 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
366 if (dinfo->cfg.baseclass == class &&
367 dinfo->cfg.subclass == subclass) {
368 return (dinfo->cfg.dev);
376 pci_printf(pcicfgregs *cfg, const char *fmt, ...)
381 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot,
384 retval += vprintf(fmt, ap);
389 /* return base address of memory or port map */
392 pci_mapbase(uint64_t mapreg)
395 if (PCI_BAR_MEM(mapreg))
396 return (mapreg & PCIM_BAR_MEM_BASE);
398 return (mapreg & PCIM_BAR_IO_BASE);
401 /* return map type of memory or port map */
404 pci_maptype(uint64_t mapreg)
407 if (PCI_BAR_IO(mapreg))
409 if (mapreg & PCIM_BAR_MEM_PREFETCH)
410 return ("Prefetchable Memory");
414 /* return log2 of map size decoded for memory or port map */
417 pci_mapsize(uint64_t testval)
421 testval = pci_mapbase(testval);
424 while ((testval & 1) == 0)
433 /* return log2 of address range supported by map register */
436 pci_maprange(uint64_t mapreg)
440 if (PCI_BAR_IO(mapreg))
443 switch (mapreg & PCIM_BAR_MEM_TYPE) {
444 case PCIM_BAR_MEM_32:
447 case PCIM_BAR_MEM_1MB:
450 case PCIM_BAR_MEM_64:
457 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
460 pci_fixancient(pcicfgregs *cfg)
462 if (cfg->hdrtype != 0)
465 /* PCI to PCI bridges use header type 1 */
466 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
470 /* extract header type specific config data */
473 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
475 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
476 switch (cfg->hdrtype) {
478 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
479 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
480 cfg->nummaps = PCI_MAXMAPS_0;
483 cfg->nummaps = PCI_MAXMAPS_1;
486 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
487 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
488 cfg->nummaps = PCI_MAXMAPS_2;
494 /* read configuration header into pcicfgregs structure */
496 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
498 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
499 pcicfgregs *cfg = NULL;
500 struct pci_devinfo *devlist_entry;
501 struct devlist *devlist_head;
503 devlist_head = &pci_devq;
505 devlist_entry = NULL;
507 if (REG(PCIR_DEVVENDOR, 4) != 0xfffffffful) {
508 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
509 if (devlist_entry == NULL)
512 cfg = &devlist_entry->cfg;
518 cfg->vendor = REG(PCIR_VENDOR, 2);
519 cfg->device = REG(PCIR_DEVICE, 2);
520 cfg->cmdreg = REG(PCIR_COMMAND, 2);
521 cfg->statreg = REG(PCIR_STATUS, 2);
522 cfg->baseclass = REG(PCIR_CLASS, 1);
523 cfg->subclass = REG(PCIR_SUBCLASS, 1);
524 cfg->progif = REG(PCIR_PROGIF, 1);
525 cfg->revid = REG(PCIR_REVID, 1);
526 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
527 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
528 cfg->lattimer = REG(PCIR_LATTIMER, 1);
529 cfg->intpin = REG(PCIR_INTPIN, 1);
530 cfg->intline = REG(PCIR_INTLINE, 1);
532 cfg->mingnt = REG(PCIR_MINGNT, 1);
533 cfg->maxlat = REG(PCIR_MAXLAT, 1);
535 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
536 cfg->hdrtype &= ~PCIM_MFDEV;
539 pci_hdrtypedata(pcib, b, s, f, cfg);
541 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
542 pci_read_cap(pcib, cfg);
544 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
546 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
547 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
548 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
549 devlist_entry->conf.pc_sel.pc_func = cfg->func;
550 devlist_entry->conf.pc_hdr = cfg->hdrtype;
552 devlist_entry->conf.pc_subvendor = cfg->subvendor;
553 devlist_entry->conf.pc_subdevice = cfg->subdevice;
554 devlist_entry->conf.pc_vendor = cfg->vendor;
555 devlist_entry->conf.pc_device = cfg->device;
557 devlist_entry->conf.pc_class = cfg->baseclass;
558 devlist_entry->conf.pc_subclass = cfg->subclass;
559 devlist_entry->conf.pc_progif = cfg->progif;
560 devlist_entry->conf.pc_revid = cfg->revid;
565 return (devlist_entry);
570 pci_read_cap(device_t pcib, pcicfgregs *cfg)
572 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
573 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
574 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
578 int ptr, nextptr, ptrptr;
580 switch (cfg->hdrtype & PCIM_HDRTYPE) {
583 ptrptr = PCIR_CAP_PTR;
586 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
589 return; /* no extended capabilities support */
591 nextptr = REG(ptrptr, 1); /* sanity check? */
594 * Read capability entries.
596 while (nextptr != 0) {
599 printf("illegal PCI extended capability offset %d\n",
603 /* Find the next entry */
605 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
607 /* Process this entry */
608 switch (REG(ptr + PCICAP_ID, 1)) {
609 case PCIY_PMG: /* PCI power management */
610 if (cfg->pp.pp_cap == 0) {
611 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
612 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS;
613 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR;
614 if ((nextptr - ptr) > PCIR_POWER_DATA)
615 cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
618 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
619 case PCIY_HT: /* HyperTransport */
620 /* Determine HT-specific capability type. */
621 val = REG(ptr + PCIR_HT_COMMAND, 2);
622 switch (val & PCIM_HTCMD_CAP_MASK) {
623 case PCIM_HTCAP_MSI_MAPPING:
624 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
625 /* Sanity check the mapping window. */
626 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI,
629 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO,
631 if (addr != MSI_INTEL_ADDR_BASE)
633 "HT Bridge at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n",
634 cfg->domain, cfg->bus,
635 cfg->slot, cfg->func,
638 addr = MSI_INTEL_ADDR_BASE;
640 cfg->ht.ht_msimap = ptr;
641 cfg->ht.ht_msictrl = val;
642 cfg->ht.ht_msiaddr = addr;
647 case PCIY_MSI: /* PCI MSI */
648 cfg->msi.msi_location = ptr;
649 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
650 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl &
651 PCIM_MSICTRL_MMC_MASK)>>1);
653 case PCIY_MSIX: /* PCI MSI-X */
654 cfg->msix.msix_location = ptr;
655 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
656 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl &
657 PCIM_MSIXCTRL_TABLE_SIZE) + 1;
658 val = REG(ptr + PCIR_MSIX_TABLE, 4);
659 cfg->msix.msix_table_bar = PCIR_BAR(val &
661 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
662 val = REG(ptr + PCIR_MSIX_PBA, 4);
663 cfg->msix.msix_pba_bar = PCIR_BAR(val &
665 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
667 case PCIY_VPD: /* PCI Vital Product Data */
668 cfg->vpd.vpd_reg = ptr;
671 /* Should always be true. */
672 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) {
673 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
674 cfg->subvendor = val & 0xffff;
675 cfg->subdevice = val >> 16;
678 case PCIY_PCIX: /* PCI-X */
680 * Assume we have a PCI-X chipset if we have
681 * at least one PCI-PCI bridge with a PCI-X
682 * capability. Note that some systems with
683 * PCI-express or HT chipsets might match on
684 * this check as well.
686 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1)
689 case PCIY_EXPRESS: /* PCI-express */
691 * Assume we have a PCI-express chipset if we have
692 * at least one PCI-express device.
700 /* REG and WREG use carry through to next functions */
704 * PCI Vital Product Data
707 #define PCI_VPD_TIMEOUT 1000000
710 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
712 int count = PCI_VPD_TIMEOUT;
714 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
716 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
718 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
721 DELAY(1); /* limit looping */
723 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
730 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
732 int count = PCI_VPD_TIMEOUT;
734 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
736 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
737 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
738 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
741 DELAY(1); /* limit looping */
748 #undef PCI_VPD_TIMEOUT
750 struct vpd_readstate {
760 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
765 if (vrs->bytesinval == 0) {
766 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
768 vrs->val = le32toh(reg);
770 byte = vrs->val & 0xff;
773 vrs->val = vrs->val >> 8;
774 byte = vrs->val & 0xff;
784 pci_read_vpd(device_t pcib, pcicfgregs *cfg)
786 struct vpd_readstate vrs;
791 int alloc, off; /* alloc/off for RO/W arrays */
797 /* init vpd reader */
805 name = remain = i = 0; /* shut up stupid gcc */
806 alloc = off = 0; /* shut up stupid gcc */
807 dflen = 0; /* shut up stupid gcc */
810 if (vpd_nextbyte(&vrs, &byte)) {
815 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
816 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
817 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
820 case 0: /* item name */
822 if (vpd_nextbyte(&vrs, &byte2)) {
827 if (vpd_nextbyte(&vrs, &byte2)) {
831 remain |= byte2 << 8;
832 if (remain > (0x7f*4 - vrs.off)) {
835 "pci%d:%d:%d:%d: invalid VPD data, remain %#x\n",
836 cfg->domain, cfg->bus, cfg->slot,
842 name = (byte >> 3) & 0xf;
845 case 0x2: /* String */
846 cfg->vpd.vpd_ident = malloc(remain + 1,
854 case 0x10: /* VPD-R */
857 cfg->vpd.vpd_ros = malloc(alloc *
858 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
862 case 0x11: /* VPD-W */
865 cfg->vpd.vpd_w = malloc(alloc *
866 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
870 default: /* Invalid data, abort */
876 case 1: /* Identifier String */
877 cfg->vpd.vpd_ident[i++] = byte;
880 cfg->vpd.vpd_ident[i] = '\0';
885 case 2: /* VPD-R Keyword Header */
887 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
888 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
889 M_DEVBUF, M_WAITOK | M_ZERO);
891 cfg->vpd.vpd_ros[off].keyword[0] = byte;
892 if (vpd_nextbyte(&vrs, &byte2)) {
896 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
897 if (vpd_nextbyte(&vrs, &byte2)) {
903 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
906 * if this happens, we can't trust the rest
910 "pci%d:%d:%d:%d: bad keyword length: %d\n",
911 cfg->domain, cfg->bus, cfg->slot,
916 } else if (dflen == 0) {
917 cfg->vpd.vpd_ros[off].value = malloc(1 *
918 sizeof(*cfg->vpd.vpd_ros[off].value),
920 cfg->vpd.vpd_ros[off].value[0] = '\x00';
922 cfg->vpd.vpd_ros[off].value = malloc(
924 sizeof(*cfg->vpd.vpd_ros[off].value),
928 /* keep in sync w/ state 3's transistions */
929 if (dflen == 0 && remain == 0)
937 case 3: /* VPD-R Keyword Value */
938 cfg->vpd.vpd_ros[off].value[i++] = byte;
939 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
940 "RV", 2) == 0 && cksumvalid == -1) {
946 "pci%d:%d:%d:%d: bad VPD cksum, remain %hhu\n",
947 cfg->domain, cfg->bus,
948 cfg->slot, cfg->func,
957 /* keep in sync w/ state 2's transistions */
959 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
960 if (dflen == 0 && remain == 0) {
961 cfg->vpd.vpd_rocnt = off;
962 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
963 off * sizeof(*cfg->vpd.vpd_ros),
964 M_DEVBUF, M_WAITOK | M_ZERO);
966 } else if (dflen == 0)
976 case 5: /* VPD-W Keyword Header */
978 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
979 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
980 M_DEVBUF, M_WAITOK | M_ZERO);
982 cfg->vpd.vpd_w[off].keyword[0] = byte;
983 if (vpd_nextbyte(&vrs, &byte2)) {
987 cfg->vpd.vpd_w[off].keyword[1] = byte2;
988 if (vpd_nextbyte(&vrs, &byte2)) {
992 cfg->vpd.vpd_w[off].len = dflen = byte2;
993 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
994 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) *
995 sizeof(*cfg->vpd.vpd_w[off].value),
999 /* keep in sync w/ state 6's transistions */
1000 if (dflen == 0 && remain == 0)
1002 else if (dflen == 0)
1008 case 6: /* VPD-W Keyword Value */
1009 cfg->vpd.vpd_w[off].value[i++] = byte;
1012 /* keep in sync w/ state 5's transistions */
1014 cfg->vpd.vpd_w[off++].value[i++] = '\0';
1015 if (dflen == 0 && remain == 0) {
1016 cfg->vpd.vpd_wcnt = off;
1017 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
1018 off * sizeof(*cfg->vpd.vpd_w),
1019 M_DEVBUF, M_WAITOK | M_ZERO);
1021 } else if (dflen == 0)
1026 printf("pci%d:%d:%d:%d: invalid state: %d\n",
1027 cfg->domain, cfg->bus, cfg->slot, cfg->func,
1034 if (cksumvalid == 0 || state < -1) {
1035 /* read-only data bad, clean up */
1036 if (cfg->vpd.vpd_ros != NULL) {
1037 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1038 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1039 free(cfg->vpd.vpd_ros, M_DEVBUF);
1040 cfg->vpd.vpd_ros = NULL;
1044 /* I/O error, clean up */
1045 printf("pci%d:%d:%d:%d: failed to read VPD data.\n",
1046 cfg->domain, cfg->bus, cfg->slot, cfg->func);
1047 if (cfg->vpd.vpd_ident != NULL) {
1048 free(cfg->vpd.vpd_ident, M_DEVBUF);
1049 cfg->vpd.vpd_ident = NULL;
1051 if (cfg->vpd.vpd_w != NULL) {
1052 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1053 free(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1054 free(cfg->vpd.vpd_w, M_DEVBUF);
1055 cfg->vpd.vpd_w = NULL;
1058 cfg->vpd.vpd_cached = 1;
1064 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1066 struct pci_devinfo *dinfo = device_get_ivars(child);
1067 pcicfgregs *cfg = &dinfo->cfg;
1069 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1070 pci_read_vpd(device_get_parent(dev), cfg);
1072 *identptr = cfg->vpd.vpd_ident;
1074 if (*identptr == NULL)
1081 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1084 struct pci_devinfo *dinfo = device_get_ivars(child);
1085 pcicfgregs *cfg = &dinfo->cfg;
1088 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1089 pci_read_vpd(device_get_parent(dev), cfg);
1091 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1092 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1093 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1094 *vptr = cfg->vpd.vpd_ros[i].value;
1103 * Find the requested extended capability and return the offset in
1104 * configuration space via the pointer provided. The function returns
1105 * 0 on success and error code otherwise.
1108 pci_find_extcap_method(device_t dev, device_t child, int capability,
1111 struct pci_devinfo *dinfo = device_get_ivars(child);
1112 pcicfgregs *cfg = &dinfo->cfg;
1117 * Check the CAP_LIST bit of the PCI status register first.
1119 status = pci_read_config(child, PCIR_STATUS, 2);
1120 if (!(status & PCIM_STATUS_CAPPRESENT))
1124 * Determine the start pointer of the capabilities list.
1126 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1132 ptr = PCIR_CAP_PTR_2;
1136 return (ENXIO); /* no extended capabilities support */
1138 ptr = pci_read_config(child, ptr, 1);
1141 * Traverse the capabilities list.
1144 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1149 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1156 * Support for MSI-X message interrupts.
1159 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
1161 struct pci_devinfo *dinfo = device_get_ivars(dev);
1162 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1165 KASSERT(msix->msix_table_len > index, ("bogus index"));
1166 offset = msix->msix_table_offset + index * 16;
1167 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1168 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1169 bus_write_4(msix->msix_table_res, offset + 8, data);
1171 /* Enable MSI -> HT mapping. */
1172 pci_ht_map_msi(dev, address);
1176 pci_mask_msix(device_t dev, u_int index)
1178 struct pci_devinfo *dinfo = device_get_ivars(dev);
1179 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1180 uint32_t offset, val;
1182 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1183 offset = msix->msix_table_offset + index * 16 + 12;
1184 val = bus_read_4(msix->msix_table_res, offset);
1185 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1186 val |= PCIM_MSIX_VCTRL_MASK;
1187 bus_write_4(msix->msix_table_res, offset, val);
1192 pci_unmask_msix(device_t dev, u_int index)
1194 struct pci_devinfo *dinfo = device_get_ivars(dev);
1195 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1196 uint32_t offset, val;
1198 KASSERT(msix->msix_table_len > index, ("bogus index"));
1199 offset = msix->msix_table_offset + index * 16 + 12;
1200 val = bus_read_4(msix->msix_table_res, offset);
1201 if (val & PCIM_MSIX_VCTRL_MASK) {
1202 val &= ~PCIM_MSIX_VCTRL_MASK;
1203 bus_write_4(msix->msix_table_res, offset, val);
1208 pci_pending_msix(device_t dev, u_int index)
1210 struct pci_devinfo *dinfo = device_get_ivars(dev);
1211 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1212 uint32_t offset, bit;
1214 KASSERT(msix->msix_table_len > index, ("bogus index"));
1215 offset = msix->msix_pba_offset + (index / 32) * 4;
1216 bit = 1 << index % 32;
1217 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1221 * Restore MSI-X registers and table during resume. If MSI-X is
1222 * enabled then walk the virtual table to restore the actual MSI-X
1226 pci_resume_msix(device_t dev)
1228 struct pci_devinfo *dinfo = device_get_ivars(dev);
1229 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1230 struct msix_table_entry *mte;
1231 struct msix_vector *mv;
1234 if (msix->msix_alloc > 0) {
1235 /* First, mask all vectors. */
1236 for (i = 0; i < msix->msix_msgnum; i++)
1237 pci_mask_msix(dev, i);
1239 /* Second, program any messages with at least one handler. */
1240 for (i = 0; i < msix->msix_table_len; i++) {
1241 mte = &msix->msix_table[i];
1242 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1244 mv = &msix->msix_vectors[mte->mte_vector - 1];
1245 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data);
1246 pci_unmask_msix(dev, i);
1249 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1250 msix->msix_ctrl, 2);
1254 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1255 * returned in *count. After this function returns, each message will be
1256 * available to the driver as SYS_RES_IRQ resources starting at rid 1.
1259 pci_alloc_msix_method(device_t dev, device_t child, int *count)
1261 struct pci_devinfo *dinfo = device_get_ivars(child);
1262 pcicfgregs *cfg = &dinfo->cfg;
1263 struct resource_list_entry *rle;
1264 int actual, error, i, irq, max;
1266 /* Don't let count == 0 get us into trouble. */
1270 /* If rid 0 is allocated, then fail. */
1271 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1272 if (rle != NULL && rle->res != NULL)
1275 /* Already have allocated messages? */
1276 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1279 /* If MSI is blacklisted for this system, fail. */
1280 if (pci_msi_blacklisted())
1283 /* MSI-X capability present? */
1284 if (cfg->msix.msix_location == 0 || !pci_do_msix)
1287 /* Make sure the appropriate BARs are mapped. */
1288 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1289 cfg->msix.msix_table_bar);
1290 if (rle == NULL || rle->res == NULL ||
1291 !(rman_get_flags(rle->res) & RF_ACTIVE))
1293 cfg->msix.msix_table_res = rle->res;
1294 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1295 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1296 cfg->msix.msix_pba_bar);
1297 if (rle == NULL || rle->res == NULL ||
1298 !(rman_get_flags(rle->res) & RF_ACTIVE))
1301 cfg->msix.msix_pba_res = rle->res;
1304 device_printf(child,
1305 "attempting to allocate %d MSI-X vectors (%d supported)\n",
1306 *count, cfg->msix.msix_msgnum);
1307 max = min(*count, cfg->msix.msix_msgnum);
1308 for (i = 0; i < max; i++) {
1309 /* Allocate a message. */
1310 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq);
1316 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1322 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
1324 device_printf(child, "using IRQ %lu for MSI-X\n",
1330 * Be fancy and try to print contiguous runs of
1331 * IRQ values as ranges. 'irq' is the previous IRQ.
1332 * 'run' is true if we are in a range.
1334 device_printf(child, "using IRQs %lu", rle->start);
1337 for (i = 1; i < actual; i++) {
1338 rle = resource_list_find(&dinfo->resources,
1339 SYS_RES_IRQ, i + 1);
1341 /* Still in a run? */
1342 if (rle->start == irq + 1) {
1348 /* Finish previous range. */
1354 /* Start new range. */
1355 printf(",%lu", rle->start);
1359 /* Unfinished range? */
1362 printf(" for MSI-X\n");
1366 /* Mask all vectors. */
1367 for (i = 0; i < cfg->msix.msix_msgnum; i++)
1368 pci_mask_msix(child, i);
1370 /* Allocate and initialize vector data and virtual table. */
1371 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual,
1372 M_DEVBUF, M_WAITOK | M_ZERO);
1373 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual,
1374 M_DEVBUF, M_WAITOK | M_ZERO);
1375 for (i = 0; i < actual; i++) {
1376 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1377 cfg->msix.msix_vectors[i].mv_irq = rle->start;
1378 cfg->msix.msix_table[i].mte_vector = i + 1;
1381 /* Update control register to enable MSI-X. */
1382 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1383 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1384 cfg->msix.msix_ctrl, 2);
1386 /* Update counts of alloc'd messages. */
1387 cfg->msix.msix_alloc = actual;
1388 cfg->msix.msix_table_len = actual;
1394 * By default, pci_alloc_msix() will assign the allocated IRQ
1395 * resources consecutively to the first N messages in the MSI-X table.
1396 * However, device drivers may want to use different layouts if they
1397 * either receive fewer messages than they asked for, or they wish to
1398 * populate the MSI-X table sparsely. This method allows the driver
1399 * to specify what layout it wants. It must be called after a
1400 * successful pci_alloc_msix() but before any of the associated
1401 * SYS_RES_IRQ resources are allocated via bus_alloc_resource().
1403 * The 'vectors' array contains 'count' message vectors. The array
1404 * maps directly to the MSI-X table in that index 0 in the array
1405 * specifies the vector for the first message in the MSI-X table, etc.
1406 * The vector value in each array index can either be 0 to indicate
1407 * that no vector should be assigned to a message slot, or it can be a
1408 * number from 1 to N (where N is the count returned from a
1409 * succcessful call to pci_alloc_msix()) to indicate which message
1410 * vector (IRQ) to be used for the corresponding message.
1412 * On successful return, each message with a non-zero vector will have
1413 * an associated SYS_RES_IRQ whose rid is equal to the array index +
1414 * 1. Additionally, if any of the IRQs allocated via the previous
1415 * call to pci_alloc_msix() are not used in the mapping, those IRQs
1416 * will be freed back to the system automatically.
1418 * For example, suppose a driver has a MSI-X table with 6 messages and
1419 * asks for 6 messages, but pci_alloc_msix() only returns a count of
1420 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and
1421 * C. After the call to pci_alloc_msix(), the device will be setup to
1422 * have an MSI-X table of ABC--- (where - means no vector assigned).
1423 * If the driver ten passes a vector array of { 1, 0, 1, 2, 0, 2 },
1424 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1425 * be freed back to the system. This device will also have valid
1426 * SYS_RES_IRQ rids of 1, 3, 4, and 6.
1428 * In any case, the SYS_RES_IRQ rid X will always map to the message
1429 * at MSI-X table index X - 1 and will only be valid if a vector is
1430 * assigned to that table entry.
1433 pci_remap_msix_method(device_t dev, device_t child, int count,
1434 const u_int *vectors)
1436 struct pci_devinfo *dinfo = device_get_ivars(child);
1437 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1438 struct resource_list_entry *rle;
1439 int i, irq, j, *used;
1442 * Have to have at least one message in the table but the
1443 * table can't be bigger than the actual MSI-X table in the
1446 if (count == 0 || count > msix->msix_msgnum)
1449 /* Sanity check the vectors. */
1450 for (i = 0; i < count; i++)
1451 if (vectors[i] > msix->msix_alloc)
1455 * Make sure there aren't any holes in the vectors to be used.
1456 * It's a big pain to support it, and it doesn't really make
1457 * sense anyway. Also, at least one vector must be used.
1459 used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK |
1461 for (i = 0; i < count; i++)
1462 if (vectors[i] != 0)
1463 used[vectors[i] - 1] = 1;
1464 for (i = 0; i < msix->msix_alloc - 1; i++)
1465 if (used[i] == 0 && used[i + 1] == 1) {
1466 free(used, M_DEVBUF);
1470 free(used, M_DEVBUF);
1474 /* Make sure none of the resources are allocated. */
1475 for (i = 0; i < msix->msix_table_len; i++) {
1476 if (msix->msix_table[i].mte_vector == 0)
1478 if (msix->msix_table[i].mte_handlers > 0)
1480 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1481 KASSERT(rle != NULL, ("missing resource"));
1482 if (rle->res != NULL)
1486 /* Free the existing resource list entries. */
1487 for (i = 0; i < msix->msix_table_len; i++) {
1488 if (msix->msix_table[i].mte_vector == 0)
1490 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1494 * Build the new virtual table keeping track of which vectors are
1497 free(msix->msix_table, M_DEVBUF);
1498 msix->msix_table = malloc(sizeof(struct msix_table_entry) * count,
1499 M_DEVBUF, M_WAITOK | M_ZERO);
1500 for (i = 0; i < count; i++)
1501 msix->msix_table[i].mte_vector = vectors[i];
1502 msix->msix_table_len = count;
1504 /* Free any unused IRQs and resize the vectors array if necessary. */
1505 j = msix->msix_alloc - 1;
1507 struct msix_vector *vec;
1509 while (used[j] == 0) {
1510 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1511 msix->msix_vectors[j].mv_irq);
1514 vec = malloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF,
1516 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
1518 free(msix->msix_vectors, M_DEVBUF);
1519 msix->msix_vectors = vec;
1520 msix->msix_alloc = j + 1;
1522 free(used, M_DEVBUF);
1524 /* Map the IRQs onto the rids. */
1525 for (i = 0; i < count; i++) {
1526 if (vectors[i] == 0)
1528 irq = msix->msix_vectors[vectors[i]].mv_irq;
1529 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1534 device_printf(child, "Remapped MSI-X IRQs as: ");
1535 for (i = 0; i < count; i++) {
1538 if (vectors[i] == 0)
1542 msix->msix_vectors[vectors[i]].mv_irq);
1551 pci_release_msix(device_t dev, device_t child)
1553 struct pci_devinfo *dinfo = device_get_ivars(child);
1554 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1555 struct resource_list_entry *rle;
1558 /* Do we have any messages to release? */
1559 if (msix->msix_alloc == 0)
1562 /* Make sure none of the resources are allocated. */
1563 for (i = 0; i < msix->msix_table_len; i++) {
1564 if (msix->msix_table[i].mte_vector == 0)
1566 if (msix->msix_table[i].mte_handlers > 0)
1568 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1569 KASSERT(rle != NULL, ("missing resource"));
1570 if (rle->res != NULL)
1574 /* Update control register to disable MSI-X. */
1575 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1576 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
1577 msix->msix_ctrl, 2);
1579 /* Free the resource list entries. */
1580 for (i = 0; i < msix->msix_table_len; i++) {
1581 if (msix->msix_table[i].mte_vector == 0)
1583 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1585 free(msix->msix_table, M_DEVBUF);
1586 msix->msix_table_len = 0;
1588 /* Release the IRQs. */
1589 for (i = 0; i < msix->msix_alloc; i++)
1590 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1591 msix->msix_vectors[i].mv_irq);
1592 free(msix->msix_vectors, M_DEVBUF);
1593 msix->msix_alloc = 0;
1598 * Return the max supported MSI-X messages this device supports.
1599 * Basically, assuming the MD code can alloc messages, this function
1600 * should return the maximum value that pci_alloc_msix() can return.
1601 * Thus, it is subject to the tunables, etc.
1604 pci_msix_count_method(device_t dev, device_t child)
1606 struct pci_devinfo *dinfo = device_get_ivars(child);
1607 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1609 if (pci_do_msix && msix->msix_location != 0)
1610 return (msix->msix_msgnum);
1615 * HyperTransport MSI mapping control
1618 pci_ht_map_msi(device_t dev, uint64_t addr)
1620 struct pci_devinfo *dinfo = device_get_ivars(dev);
1621 struct pcicfg_ht *ht = &dinfo->cfg.ht;
1626 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
1627 ht->ht_msiaddr >> 20 == addr >> 20) {
1628 /* Enable MSI -> HT mapping. */
1629 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1630 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1634 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
1635 /* Disable MSI -> HT mapping. */
1636 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
1637 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1643 pci_get_max_read_req(device_t dev)
1648 if (pci_find_cap(dev, PCIY_EXPRESS, &cap) != 0)
1650 val = pci_read_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, 2);
1651 val &= PCIM_EXP_CTL_MAX_READ_REQUEST;
1653 return (1 << (val + 7));
1657 pci_set_max_read_req(device_t dev, int size)
1662 if (pci_find_cap(dev, PCIY_EXPRESS, &cap) != 0)
1668 size = (1 << (fls(size) - 1));
1669 val = pci_read_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, 2);
1670 val &= ~PCIM_EXP_CTL_MAX_READ_REQUEST;
1671 val |= (fls(size) - 8) << 12;
1672 pci_write_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, val, 2);
1677 * Support for MSI message signalled interrupts.
1680 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
1682 struct pci_devinfo *dinfo = device_get_ivars(dev);
1683 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1685 /* Write data and address values. */
1686 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1687 address & 0xffffffff, 4);
1688 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1689 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1691 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1694 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1697 /* Enable MSI in the control register. */
1698 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1699 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1702 /* Enable MSI -> HT mapping. */
1703 pci_ht_map_msi(dev, address);
1707 pci_disable_msi(device_t dev)
1709 struct pci_devinfo *dinfo = device_get_ivars(dev);
1710 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1712 /* Disable MSI -> HT mapping. */
1713 pci_ht_map_msi(dev, 0);
1715 /* Disable MSI in the control register. */
1716 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1717 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1722 * Restore MSI registers during resume. If MSI is enabled then
1723 * restore the data and address registers in addition to the control
1727 pci_resume_msi(device_t dev)
1729 struct pci_devinfo *dinfo = device_get_ivars(dev);
1730 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1734 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1735 address = msi->msi_addr;
1736 data = msi->msi_data;
1737 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1738 address & 0xffffffff, 4);
1739 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1740 pci_write_config(dev, msi->msi_location +
1741 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1742 pci_write_config(dev, msi->msi_location +
1743 PCIR_MSI_DATA_64BIT, data, 2);
1745 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1748 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1753 pci_remap_intr_method(device_t bus, device_t dev, u_int irq)
1755 struct pci_devinfo *dinfo = device_get_ivars(dev);
1756 pcicfgregs *cfg = &dinfo->cfg;
1757 struct resource_list_entry *rle;
1758 struct msix_table_entry *mte;
1759 struct msix_vector *mv;
1765 * Handle MSI first. We try to find this IRQ among our list
1766 * of MSI IRQs. If we find it, we request updated address and
1767 * data registers and apply the results.
1769 if (cfg->msi.msi_alloc > 0) {
1771 /* If we don't have any active handlers, nothing to do. */
1772 if (cfg->msi.msi_handlers == 0)
1774 for (i = 0; i < cfg->msi.msi_alloc; i++) {
1775 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
1777 if (rle->start == irq) {
1778 error = PCIB_MAP_MSI(device_get_parent(bus),
1779 dev, irq, &addr, &data);
1782 pci_disable_msi(dev);
1783 dinfo->cfg.msi.msi_addr = addr;
1784 dinfo->cfg.msi.msi_data = data;
1785 pci_enable_msi(dev, addr, data);
1793 * For MSI-X, we check to see if we have this IRQ. If we do,
1794 * we request the updated mapping info. If that works, we go
1795 * through all the slots that use this IRQ and update them.
1797 if (cfg->msix.msix_alloc > 0) {
1798 for (i = 0; i < cfg->msix.msix_alloc; i++) {
1799 mv = &cfg->msix.msix_vectors[i];
1800 if (mv->mv_irq == irq) {
1801 error = PCIB_MAP_MSI(device_get_parent(bus),
1802 dev, irq, &addr, &data);
1805 mv->mv_address = addr;
1807 for (j = 0; j < cfg->msix.msix_table_len; j++) {
1808 mte = &cfg->msix.msix_table[j];
1809 if (mte->mte_vector != i + 1)
1811 if (mte->mte_handlers == 0)
1813 pci_mask_msix(dev, j);
1814 pci_enable_msix(dev, j, addr, data);
1815 pci_unmask_msix(dev, j);
1826 * Returns true if the specified device is blacklisted because MSI
1830 pci_msi_device_blacklisted(device_t dev)
1832 const struct pci_quirk *q;
1834 if (!pci_honor_msi_blacklist)
1837 for (q = &pci_quirks[0]; q->devid; q++) {
1838 if (q->devid == pci_get_devid(dev) &&
1839 q->type == PCI_QUIRK_DISABLE_MSI)
1846 * Returns true if a specified chipset supports MSI when it is
1847 * emulated hardware in a virtual machine.
1850 pci_msi_vm_chipset(device_t dev)
1852 const struct pci_quirk *q;
1854 for (q = &pci_quirks[0]; q->devid; q++) {
1855 if (q->devid == pci_get_devid(dev) &&
1856 q->type == PCI_QUIRK_ENABLE_MSI_VM)
1863 * Determine if MSI is blacklisted globally on this sytem. Currently,
1864 * we just check for blacklisted chipsets as represented by the
1865 * host-PCI bridge at device 0:0:0. In the future, it may become
1866 * necessary to check other system attributes, such as the kenv values
1867 * that give the motherboard manufacturer and model number.
1870 pci_msi_blacklisted(void)
1874 if (!pci_honor_msi_blacklist)
1877 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
1878 if (!(pcie_chipset || pcix_chipset)) {
1879 if (vm_guest != VM_GUEST_NO) {
1880 dev = pci_find_bsf(0, 0, 0);
1882 return (pci_msi_vm_chipset(dev) == 0);
1887 dev = pci_find_bsf(0, 0, 0);
1889 return (pci_msi_device_blacklisted(dev));
1894 * Attempt to allocate *count MSI messages. The actual number allocated is
1895 * returned in *count. After this function returns, each message will be
1896 * available to the driver as SYS_RES_IRQ resources starting at a rid 1.
1899 pci_alloc_msi_method(device_t dev, device_t child, int *count)
1901 struct pci_devinfo *dinfo = device_get_ivars(child);
1902 pcicfgregs *cfg = &dinfo->cfg;
1903 struct resource_list_entry *rle;
1904 int actual, error, i, irqs[32];
1907 /* Don't let count == 0 get us into trouble. */
1911 /* If rid 0 is allocated, then fail. */
1912 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1913 if (rle != NULL && rle->res != NULL)
1916 /* Already have allocated messages? */
1917 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1920 /* If MSI is blacklisted for this system, fail. */
1921 if (pci_msi_blacklisted())
1924 /* MSI capability present? */
1925 if (cfg->msi.msi_location == 0 || !pci_do_msi)
1929 device_printf(child,
1930 "attempting to allocate %d MSI vectors (%d supported)\n",
1931 *count, cfg->msi.msi_msgnum);
1933 /* Don't ask for more than the device supports. */
1934 actual = min(*count, cfg->msi.msi_msgnum);
1936 /* Don't ask for more than 32 messages. */
1937 actual = min(actual, 32);
1939 /* MSI requires power of 2 number of messages. */
1940 if (!powerof2(actual))
1944 /* Try to allocate N messages. */
1945 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
1957 * We now have N actual messages mapped onto SYS_RES_IRQ
1958 * resources in the irqs[] array, so add new resources
1959 * starting at rid 1.
1961 for (i = 0; i < actual; i++)
1962 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
1963 irqs[i], irqs[i], 1);
1967 device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
1972 * Be fancy and try to print contiguous runs
1973 * of IRQ values as ranges. 'run' is true if
1974 * we are in a range.
1976 device_printf(child, "using IRQs %d", irqs[0]);
1978 for (i = 1; i < actual; i++) {
1980 /* Still in a run? */
1981 if (irqs[i] == irqs[i - 1] + 1) {
1986 /* Finish previous range. */
1988 printf("-%d", irqs[i - 1]);
1992 /* Start new range. */
1993 printf(",%d", irqs[i]);
1996 /* Unfinished range? */
1998 printf("-%d", irqs[actual - 1]);
1999 printf(" for MSI\n");
2003 /* Update control register with actual count. */
2004 ctrl = cfg->msi.msi_ctrl;
2005 ctrl &= ~PCIM_MSICTRL_MME_MASK;
2006 ctrl |= (ffs(actual) - 1) << 4;
2007 cfg->msi.msi_ctrl = ctrl;
2008 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
2010 /* Update counts of alloc'd messages. */
2011 cfg->msi.msi_alloc = actual;
2012 cfg->msi.msi_handlers = 0;
2017 /* Release the MSI messages associated with this device. */
2019 pci_release_msi_method(device_t dev, device_t child)
2021 struct pci_devinfo *dinfo = device_get_ivars(child);
2022 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2023 struct resource_list_entry *rle;
2024 int error, i, irqs[32];
2026 /* Try MSI-X first. */
2027 error = pci_release_msix(dev, child);
2028 if (error != ENODEV)
2031 /* Do we have any messages to release? */
2032 if (msi->msi_alloc == 0)
2034 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
2036 /* Make sure none of the resources are allocated. */
2037 if (msi->msi_handlers > 0)
2039 for (i = 0; i < msi->msi_alloc; i++) {
2040 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2041 KASSERT(rle != NULL, ("missing MSI resource"));
2042 if (rle->res != NULL)
2044 irqs[i] = rle->start;
2047 /* Update control register with 0 count. */
2048 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
2049 ("%s: MSI still enabled", __func__));
2050 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
2051 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2054 /* Release the messages. */
2055 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
2056 for (i = 0; i < msi->msi_alloc; i++)
2057 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2059 /* Update alloc count. */
2067 * Return the max supported MSI messages this device supports.
2068 * Basically, assuming the MD code can alloc messages, this function
2069 * should return the maximum value that pci_alloc_msi() can return.
2070 * Thus, it is subject to the tunables, etc.
2073 pci_msi_count_method(device_t dev, device_t child)
2075 struct pci_devinfo *dinfo = device_get_ivars(child);
2076 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2078 if (pci_do_msi && msi->msi_location != 0)
2079 return (msi->msi_msgnum);
2083 /* free pcicfgregs structure and all depending data structures */
2086 pci_freecfg(struct pci_devinfo *dinfo)
2088 struct devlist *devlist_head;
2091 devlist_head = &pci_devq;
2093 if (dinfo->cfg.vpd.vpd_reg) {
2094 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2095 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2096 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2097 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2098 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2099 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2100 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2102 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2103 free(dinfo, M_DEVBUF);
2105 /* increment the generation count */
2108 /* we're losing one device */
2114 * PCI power manangement
2117 pci_set_powerstate_method(device_t dev, device_t child, int state)
2119 struct pci_devinfo *dinfo = device_get_ivars(child);
2120 pcicfgregs *cfg = &dinfo->cfg;
2122 int result, oldstate, highest, delay;
2124 if (cfg->pp.pp_cap == 0)
2125 return (EOPNOTSUPP);
2128 * Optimize a no state change request away. While it would be OK to
2129 * write to the hardware in theory, some devices have shown odd
2130 * behavior when going from D3 -> D3.
2132 oldstate = pci_get_powerstate(child);
2133 if (oldstate == state)
2137 * The PCI power management specification states that after a state
2138 * transition between PCI power states, system software must
2139 * guarantee a minimal delay before the function accesses the device.
2140 * Compute the worst case delay that we need to guarantee before we
2141 * access the device. Many devices will be responsive much more
2142 * quickly than this delay, but there are some that don't respond
2143 * instantly to state changes. Transitions to/from D3 state require
2144 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2145 * is done below with DELAY rather than a sleeper function because
2146 * this function can be called from contexts where we cannot sleep.
2148 highest = (oldstate > state) ? oldstate : state;
2149 if (highest == PCI_POWERSTATE_D3)
2151 else if (highest == PCI_POWERSTATE_D2)
2155 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2156 & ~PCIM_PSTAT_DMASK;
2159 case PCI_POWERSTATE_D0:
2160 status |= PCIM_PSTAT_D0;
2162 case PCI_POWERSTATE_D1:
2163 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2164 return (EOPNOTSUPP);
2165 status |= PCIM_PSTAT_D1;
2167 case PCI_POWERSTATE_D2:
2168 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2169 return (EOPNOTSUPP);
2170 status |= PCIM_PSTAT_D2;
2172 case PCI_POWERSTATE_D3:
2173 status |= PCIM_PSTAT_D3;
2180 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate,
2183 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2190 pci_get_powerstate_method(device_t dev, device_t child)
2192 struct pci_devinfo *dinfo = device_get_ivars(child);
2193 pcicfgregs *cfg = &dinfo->cfg;
2197 if (cfg->pp.pp_cap != 0) {
2198 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2199 switch (status & PCIM_PSTAT_DMASK) {
2201 result = PCI_POWERSTATE_D0;
2204 result = PCI_POWERSTATE_D1;
2207 result = PCI_POWERSTATE_D2;
2210 result = PCI_POWERSTATE_D3;
2213 result = PCI_POWERSTATE_UNKNOWN;
2217 /* No support, device is always at D0 */
2218 result = PCI_POWERSTATE_D0;
2224 * Some convenience functions for PCI device drivers.
2227 static __inline void
2228 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2232 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2234 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2237 static __inline void
2238 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2242 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2244 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2248 pci_enable_busmaster_method(device_t dev, device_t child)
2250 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2255 pci_disable_busmaster_method(device_t dev, device_t child)
2257 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2262 pci_enable_io_method(device_t dev, device_t child, int space)
2267 case SYS_RES_IOPORT:
2268 bit = PCIM_CMD_PORTEN;
2270 case SYS_RES_MEMORY:
2271 bit = PCIM_CMD_MEMEN;
2276 pci_set_command_bit(dev, child, bit);
2281 pci_disable_io_method(device_t dev, device_t child, int space)
2286 case SYS_RES_IOPORT:
2287 bit = PCIM_CMD_PORTEN;
2289 case SYS_RES_MEMORY:
2290 bit = PCIM_CMD_MEMEN;
2295 pci_clear_command_bit(dev, child, bit);
2300 * New style pci driver. Parent device is either a pci-host-bridge or a
2301 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2305 pci_print_verbose(struct pci_devinfo *dinfo)
2309 pcicfgregs *cfg = &dinfo->cfg;
2311 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2312 cfg->vendor, cfg->device, cfg->revid);
2313 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2314 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2315 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2316 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2318 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2319 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2320 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2321 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2322 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2323 if (cfg->intpin > 0)
2324 printf("\tintpin=%c, irq=%d\n",
2325 cfg->intpin +'a' -1, cfg->intline);
2326 if (cfg->pp.pp_cap) {
2329 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2330 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2331 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2332 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2333 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2334 status & PCIM_PSTAT_DMASK);
2336 if (cfg->msi.msi_location) {
2339 ctrl = cfg->msi.msi_ctrl;
2340 printf("\tMSI supports %d message%s%s%s\n",
2341 cfg->msi.msi_msgnum,
2342 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2343 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2344 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2346 if (cfg->msix.msix_location) {
2347 printf("\tMSI-X supports %d message%s ",
2348 cfg->msix.msix_msgnum,
2349 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2350 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2351 printf("in map 0x%x\n",
2352 cfg->msix.msix_table_bar);
2354 printf("in maps 0x%x and 0x%x\n",
2355 cfg->msix.msix_table_bar,
2356 cfg->msix.msix_pba_bar);
2362 pci_porten(device_t dev)
2364 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0;
2368 pci_memen(device_t dev)
2370 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0;
2374 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp)
2376 pci_addr_t map, testval;
2380 map = pci_read_config(dev, reg, 4);
2381 ln2range = pci_maprange(map);
2383 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
2386 * Disable decoding via the command register before
2387 * determining the BAR's length since we will be placing it in
2390 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2391 pci_write_config(dev, PCIR_COMMAND,
2392 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2);
2395 * Determine the BAR's length by writing all 1's. The bottom
2396 * log_2(size) bits of the BAR will stick as 0 when we read
2399 pci_write_config(dev, reg, 0xffffffff, 4);
2400 testval = pci_read_config(dev, reg, 4);
2401 if (ln2range == 64) {
2402 pci_write_config(dev, reg + 4, 0xffffffff, 4);
2403 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
2407 * Restore the original value of the BAR. We may have reprogrammed
2408 * the BAR of the low-level console device and when booting verbose,
2409 * we need the console device addressable.
2411 pci_write_config(dev, reg, map, 4);
2413 pci_write_config(dev, reg + 4, map >> 32, 4);
2414 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2417 *testvalp = testval;
2421 pci_write_bar(device_t dev, int reg, pci_addr_t base)
2426 map = pci_read_config(dev, reg, 4);
2427 ln2range = pci_maprange(map);
2428 pci_write_config(dev, reg, base, 4);
2430 pci_write_config(dev, reg + 4, base >> 32, 4);
2434 * Add a resource based on a pci map register. Return 1 if the map
2435 * register is a 32bit map register or 2 if it is a 64bit register.
2438 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl,
2439 int force, int prefetch)
2441 pci_addr_t base, map, testval;
2442 pci_addr_t start, end, count;
2443 int barlen, basezero, maprange, mapsize, type;
2445 struct resource *res;
2447 pci_read_bar(dev, reg, &map, &testval);
2448 if (PCI_BAR_MEM(map)) {
2449 type = SYS_RES_MEMORY;
2450 if (map & PCIM_BAR_MEM_PREFETCH)
2453 type = SYS_RES_IOPORT;
2454 mapsize = pci_mapsize(testval);
2455 base = pci_mapbase(map);
2456 #ifdef __PCI_BAR_ZERO_VALID
2459 basezero = base == 0;
2461 maprange = pci_maprange(map);
2462 barlen = maprange == 64 ? 2 : 1;
2465 * For I/O registers, if bottom bit is set, and the next bit up
2466 * isn't clear, we know we have a BAR that doesn't conform to the
2467 * spec, so ignore it. Also, sanity check the size of the data
2468 * areas to the type of memory involved. Memory must be at least
2469 * 16 bytes in size, while I/O ranges must be at least 4.
2471 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2473 if ((type == SYS_RES_MEMORY && mapsize < 4) ||
2474 (type == SYS_RES_IOPORT && mapsize < 2))
2478 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2479 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize);
2480 if (type == SYS_RES_IOPORT && !pci_porten(dev))
2481 printf(", port disabled\n");
2482 else if (type == SYS_RES_MEMORY && !pci_memen(dev))
2483 printf(", memory disabled\n");
2485 printf(", enabled\n");
2489 * If base is 0, then we have problems if this architecture does
2490 * not allow that. It is best to ignore such entries for the
2491 * moment. These will be allocated later if the driver specifically
2492 * requests them. However, some removable busses look better when
2493 * all resources are allocated, so allow '0' to be overriden.
2495 * Similarly treat maps whose values is the same as the test value
2496 * read back. These maps have had all f's written to them by the
2497 * BIOS in an attempt to disable the resources.
2499 if (!force && (basezero || map == testval))
2501 if ((u_long)base != base) {
2503 "pci%d:%d:%d:%d bar %#x too many address bits",
2504 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev),
2505 pci_get_function(dev), reg);
2510 * This code theoretically does the right thing, but has
2511 * undesirable side effects in some cases where peripherals
2512 * respond oddly to having these bits enabled. Let the user
2513 * be able to turn them off (since pci_enable_io_modes is 1 by
2516 if (pci_enable_io_modes) {
2517 /* Turn on resources that have been left off by a lazy BIOS */
2518 if (type == SYS_RES_IOPORT && !pci_porten(dev)) {
2519 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2520 cmd |= PCIM_CMD_PORTEN;
2521 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2523 if (type == SYS_RES_MEMORY && !pci_memen(dev)) {
2524 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2525 cmd |= PCIM_CMD_MEMEN;
2526 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2529 if (type == SYS_RES_IOPORT && !pci_porten(dev))
2531 if (type == SYS_RES_MEMORY && !pci_memen(dev))
2535 count = (pci_addr_t)1 << mapsize;
2536 if (basezero || base == pci_mapbase(testval)) {
2537 start = 0; /* Let the parent decide. */
2541 end = base + count - 1;
2543 resource_list_add(rl, type, reg, start, end, count);
2546 * Try to allocate the resource for this BAR from our parent
2547 * so that this resource range is already reserved. The
2548 * driver for this device will later inherit this resource in
2549 * pci_alloc_resource().
2551 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count,
2552 prefetch ? RF_PREFETCHABLE : 0);
2555 * If the allocation fails, clear the BAR and delete
2556 * the resource list entry to force
2557 * pci_alloc_resource() to allocate resources from the
2560 resource_list_delete(rl, type, reg);
2563 start = rman_get_start(res);
2564 rman_set_device(res, bus);
2566 pci_write_bar(dev, reg, start);
2571 * For ATA devices we need to decide early what addressing mode to use.
2572 * Legacy demands that the primary and secondary ATA ports sits on the
2573 * same addresses that old ISA hardware did. This dictates that we use
2574 * those addresses and ignore the BAR's if we cannot set PCI native
2578 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force,
2579 uint32_t prefetchmask)
2582 int rid, type, progif;
2584 /* if this device supports PCI native addressing use it */
2585 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2586 if ((progif & 0x8a) == 0x8a) {
2587 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2588 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
2589 printf("Trying ATA native PCI addressing mode\n");
2590 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2594 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2595 type = SYS_RES_IOPORT;
2596 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
2597 pci_add_map(bus, dev, PCIR_BAR(0), rl, force,
2598 prefetchmask & (1 << 0));
2599 pci_add_map(bus, dev, PCIR_BAR(1), rl, force,
2600 prefetchmask & (1 << 1));
2603 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
2604 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7,
2606 rman_set_device(r, bus);
2608 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
2609 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6,
2611 rman_set_device(r, bus);
2613 if (progif & PCIP_STORAGE_IDE_MODESEC) {
2614 pci_add_map(bus, dev, PCIR_BAR(2), rl, force,
2615 prefetchmask & (1 << 2));
2616 pci_add_map(bus, dev, PCIR_BAR(3), rl, force,
2617 prefetchmask & (1 << 3));
2620 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
2621 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177,
2623 rman_set_device(r, bus);
2625 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
2626 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376,
2628 rman_set_device(r, bus);
2630 pci_add_map(bus, dev, PCIR_BAR(4), rl, force,
2631 prefetchmask & (1 << 4));
2632 pci_add_map(bus, dev, PCIR_BAR(5), rl, force,
2633 prefetchmask & (1 << 5));
2637 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
2639 struct pci_devinfo *dinfo = device_get_ivars(dev);
2640 pcicfgregs *cfg = &dinfo->cfg;
2641 char tunable_name[64];
2644 /* Has to have an intpin to have an interrupt. */
2645 if (cfg->intpin == 0)
2648 /* Let the user override the IRQ with a tunable. */
2649 irq = PCI_INVALID_IRQ;
2650 snprintf(tunable_name, sizeof(tunable_name),
2651 "hw.pci%d.%d.%d.INT%c.irq",
2652 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
2653 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
2654 irq = PCI_INVALID_IRQ;
2657 * If we didn't get an IRQ via the tunable, then we either use the
2658 * IRQ value in the intline register or we ask the bus to route an
2659 * interrupt for us. If force_route is true, then we only use the
2660 * value in the intline register if the bus was unable to assign an
2663 if (!PCI_INTERRUPT_VALID(irq)) {
2664 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
2665 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
2666 if (!PCI_INTERRUPT_VALID(irq))
2670 /* If after all that we don't have an IRQ, just bail. */
2671 if (!PCI_INTERRUPT_VALID(irq))
2674 /* Update the config register if it changed. */
2675 if (irq != cfg->intline) {
2677 pci_write_config(dev, PCIR_INTLINE, irq, 1);
2680 /* Add this IRQ as rid 0 interrupt resource. */
2681 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
2684 /* Perform early OHCI takeover from SMM. */
2686 ohci_early_takeover(device_t self)
2688 struct resource *res;
2694 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
2698 ctl = bus_read_4(res, OHCI_CONTROL);
2699 if (ctl & OHCI_IR) {
2701 printf("ohci early: "
2702 "SMM active, request owner change\n");
2703 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR);
2704 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) {
2706 ctl = bus_read_4(res, OHCI_CONTROL);
2708 if (ctl & OHCI_IR) {
2710 printf("ohci early: "
2711 "SMM does not respond, resetting\n");
2712 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET);
2714 /* Disable interrupts */
2715 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
2718 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
2721 /* Perform early UHCI takeover from SMM. */
2723 uhci_early_takeover(device_t self)
2725 struct resource *res;
2729 * Set the PIRQD enable bit and switch off all the others. We don't
2730 * want legacy support to interfere with us XXX Does this also mean
2731 * that the BIOS won't touch the keyboard anymore if it is connected
2732 * to the ports of the root hub?
2734 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2);
2736 /* Disable interrupts */
2737 rid = PCI_UHCI_BASE_REG;
2738 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE);
2740 bus_write_2(res, UHCI_INTR, 0);
2741 bus_release_resource(self, SYS_RES_IOPORT, rid, res);
2745 /* Perform early EHCI takeover from SMM. */
2747 ehci_early_takeover(device_t self)
2749 struct resource *res;
2759 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
2763 cparams = bus_read_4(res, EHCI_HCCPARAMS);
2765 /* Synchronise with the BIOS if it owns the controller. */
2766 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0;
2767 eecp = EHCI_EECP_NEXT(eec)) {
2768 eec = pci_read_config(self, eecp, 4);
2769 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) {
2772 bios_sem = pci_read_config(self, eecp +
2773 EHCI_LEGSUP_BIOS_SEM, 1);
2774 if (bios_sem == 0) {
2778 printf("ehci early: "
2779 "SMM active, request owner change\n");
2781 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1);
2783 for (i = 0; (i < 100) && (bios_sem != 0); i++) {
2785 bios_sem = pci_read_config(self, eecp +
2786 EHCI_LEGSUP_BIOS_SEM, 1);
2789 if (bios_sem != 0) {
2791 printf("ehci early: "
2792 "SMM does not respond\n");
2794 /* Disable interrupts */
2795 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION));
2796 bus_write_4(res, offs + EHCI_USBINTR, 0);
2798 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
2802 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask)
2804 struct pci_devinfo *dinfo;
2806 struct resource_list *rl;
2807 const struct pci_quirk *q;
2811 dinfo = device_get_ivars(dev);
2813 rl = &dinfo->resources;
2814 devid = (cfg->device << 16) | cfg->vendor;
2816 /* ATA devices needs special map treatment */
2817 if ((pci_get_class(dev) == PCIC_STORAGE) &&
2818 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
2819 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
2820 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
2821 !pci_read_config(dev, PCIR_BAR(2), 4))) )
2822 pci_ata_maps(bus, dev, rl, force, prefetchmask);
2824 for (i = 0; i < cfg->nummaps;) {
2826 * Skip quirked resources.
2828 for (q = &pci_quirks[0]; q->devid != 0; q++)
2829 if (q->devid == devid &&
2830 q->type == PCI_QUIRK_UNMAP_REG &&
2831 q->arg1 == PCIR_BAR(i))
2833 if (q->devid != 0) {
2837 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force,
2838 prefetchmask & (1 << i));
2842 * Add additional, quirked resources.
2844 for (q = &pci_quirks[0]; q->devid != 0; q++)
2845 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG)
2846 pci_add_map(bus, dev, q->arg1, rl, force, 0);
2848 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2849 #ifdef __PCI_REROUTE_INTERRUPT
2851 * Try to re-route interrupts. Sometimes the BIOS or
2852 * firmware may leave bogus values in these registers.
2853 * If the re-route fails, then just stick with what we
2856 pci_assign_interrupt(bus, dev, 1);
2858 pci_assign_interrupt(bus, dev, 0);
2862 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS &&
2863 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) {
2864 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI)
2865 ehci_early_takeover(dev);
2866 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI)
2867 ohci_early_takeover(dev);
2868 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI)
2869 uhci_early_takeover(dev);
2874 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
2876 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
2877 device_t pcib = device_get_parent(dev);
2878 struct pci_devinfo *dinfo;
2880 int s, f, pcifunchigh;
2883 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
2884 ("dinfo_size too small"));
2885 maxslots = PCIB_MAXSLOTS(pcib);
2886 for (s = 0; s <= maxslots; s++) {
2890 hdrtype = REG(PCIR_HDRTYPE, 1);
2891 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
2893 if (hdrtype & PCIM_MFDEV)
2894 pcifunchigh = PCI_FUNCMAX;
2895 for (f = 0; f <= pcifunchigh; f++) {
2896 dinfo = pci_read_device(pcib, domain, busno, s, f,
2898 if (dinfo != NULL) {
2899 pci_add_child(dev, dinfo);
2907 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
2909 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
2910 device_set_ivars(dinfo->cfg.dev, dinfo);
2911 resource_list_init(&dinfo->resources);
2912 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
2913 pci_cfg_restore(dinfo->cfg.dev, dinfo);
2914 pci_print_verbose(dinfo);
2915 pci_add_resources(bus, dinfo->cfg.dev, 0, 0);
2919 pci_probe(device_t dev)
2922 device_set_desc(dev, "PCI bus");
2924 /* Allow other subclasses to override this driver. */
2925 return (BUS_PROBE_GENERIC);
2929 pci_attach(device_t dev)
2934 * Since there can be multiple independantly numbered PCI
2935 * busses on systems with multiple PCI domains, we can't use
2936 * the unit number to decide which bus we are probing. We ask
2937 * the parent pcib what our domain and bus numbers are.
2939 domain = pcib_get_domain(dev);
2940 busno = pcib_get_bus(dev);
2942 device_printf(dev, "domain=%d, physical bus=%d\n",
2944 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
2945 return (bus_generic_attach(dev));
2949 pci_suspend(device_t dev)
2951 int dstate, error, i, numdevs;
2952 device_t acpi_dev, child, *devlist;
2953 struct pci_devinfo *dinfo;
2956 * Save the PCI configuration space for each child and set the
2957 * device in the appropriate power state for this sleep state.
2960 if (pci_do_power_resume)
2961 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2962 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0)
2964 for (i = 0; i < numdevs; i++) {
2966 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2967 pci_cfg_save(child, dinfo, 0);
2970 /* Suspend devices before potentially powering them down. */
2971 error = bus_generic_suspend(dev);
2973 free(devlist, M_TEMP);
2978 * Always set the device to D3. If ACPI suggests a different
2979 * power state, use it instead. If ACPI is not present, the
2980 * firmware is responsible for managing device power. Skip
2981 * children who aren't attached since they are powered down
2982 * separately. Only manage type 0 devices for now.
2984 for (i = 0; acpi_dev && i < numdevs; i++) {
2986 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2987 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) {
2988 dstate = PCI_POWERSTATE_D3;
2989 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate);
2990 pci_set_powerstate(child, dstate);
2993 free(devlist, M_TEMP);
2998 pci_resume(device_t dev)
3000 int i, numdevs, error;
3001 device_t acpi_dev, child, *devlist;
3002 struct pci_devinfo *dinfo;
3005 * Set each child to D0 and restore its PCI configuration space.
3008 if (pci_do_power_resume)
3009 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
3010 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0)
3012 for (i = 0; i < numdevs; i++) {
3014 * Notify ACPI we're going to D0 but ignore the result. If
3015 * ACPI is not present, the firmware is responsible for
3016 * managing device power. Only manage type 0 devices for now.
3019 dinfo = (struct pci_devinfo *) device_get_ivars(child);
3020 if (acpi_dev && device_is_attached(child) &&
3021 dinfo->cfg.hdrtype == 0) {
3022 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL);
3023 pci_set_powerstate(child, PCI_POWERSTATE_D0);
3026 /* Now the device is powered up, restore its config space. */
3027 pci_cfg_restore(child, dinfo);
3029 free(devlist, M_TEMP);
3030 return (bus_generic_resume(dev));
3034 pci_load_vendor_data(void)
3036 caddr_t vendordata, info;
3038 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
3039 info = preload_search_info(vendordata, MODINFO_ADDR);
3040 pci_vendordata = *(char **)info;
3041 info = preload_search_info(vendordata, MODINFO_SIZE);
3042 pci_vendordata_size = *(size_t *)info;
3043 /* terminate the database */
3044 pci_vendordata[pci_vendordata_size] = '\n';
3049 pci_driver_added(device_t dev, driver_t *driver)
3054 struct pci_devinfo *dinfo;
3058 device_printf(dev, "driver added\n");
3059 DEVICE_IDENTIFY(driver, dev);
3060 if (device_get_children(dev, &devlist, &numdevs) != 0)
3062 for (i = 0; i < numdevs; i++) {
3064 if (device_get_state(child) != DS_NOTPRESENT)
3066 dinfo = device_get_ivars(child);
3067 pci_print_verbose(dinfo);
3069 pci_printf(&dinfo->cfg, "reprobing on driver added\n");
3070 pci_cfg_restore(child, dinfo);
3071 if (device_probe_and_attach(child) != 0)
3072 pci_cfg_save(child, dinfo, 1);
3074 free(devlist, M_TEMP);
3078 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
3079 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep)
3081 struct pci_devinfo *dinfo;
3082 struct msix_table_entry *mte;
3083 struct msix_vector *mv;
3089 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr,
3094 /* If this is not a direct child, just bail out. */
3095 if (device_get_parent(child) != dev) {
3100 rid = rman_get_rid(irq);
3102 /* Make sure that INTx is enabled */
3103 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3106 * Check to see if the interrupt is MSI or MSI-X.
3107 * Ask our parent to map the MSI and give
3108 * us the address and data register values.
3109 * If we fail for some reason, teardown the
3110 * interrupt handler.
3112 dinfo = device_get_ivars(child);
3113 if (dinfo->cfg.msi.msi_alloc > 0) {
3114 if (dinfo->cfg.msi.msi_addr == 0) {
3115 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
3116 ("MSI has handlers, but vectors not mapped"));
3117 error = PCIB_MAP_MSI(device_get_parent(dev),
3118 child, rman_get_start(irq), &addr, &data);
3121 dinfo->cfg.msi.msi_addr = addr;
3122 dinfo->cfg.msi.msi_data = data;
3124 if (dinfo->cfg.msi.msi_handlers == 0)
3125 pci_enable_msi(child, dinfo->cfg.msi.msi_addr,
3126 dinfo->cfg.msi.msi_data);
3127 dinfo->cfg.msi.msi_handlers++;
3129 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3130 ("No MSI or MSI-X interrupts allocated"));
3131 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3132 ("MSI-X index too high"));
3133 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3134 KASSERT(mte->mte_vector != 0, ("no message vector"));
3135 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
3136 KASSERT(mv->mv_irq == rman_get_start(irq),
3138 if (mv->mv_address == 0) {
3139 KASSERT(mte->mte_handlers == 0,
3140 ("MSI-X table entry has handlers, but vector not mapped"));
3141 error = PCIB_MAP_MSI(device_get_parent(dev),
3142 child, rman_get_start(irq), &addr, &data);
3145 mv->mv_address = addr;
3148 if (mte->mte_handlers == 0) {
3149 pci_enable_msix(child, rid - 1, mv->mv_address,
3151 pci_unmask_msix(child, rid - 1);
3153 mte->mte_handlers++;
3156 /* Make sure that INTx is disabled if we are using MSI/MSIX */
3157 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3160 (void)bus_generic_teardown_intr(dev, child, irq,
3170 pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
3173 struct msix_table_entry *mte;
3174 struct resource_list_entry *rle;
3175 struct pci_devinfo *dinfo;
3178 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
3181 /* If this isn't a direct child, just bail out */
3182 if (device_get_parent(child) != dev)
3183 return(bus_generic_teardown_intr(dev, child, irq, cookie));
3185 rid = rman_get_rid(irq);
3188 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3191 * Check to see if the interrupt is MSI or MSI-X. If so,
3192 * decrement the appropriate handlers count and mask the
3193 * MSI-X message, or disable MSI messages if the count
3196 dinfo = device_get_ivars(child);
3197 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
3198 if (rle->res != irq)
3200 if (dinfo->cfg.msi.msi_alloc > 0) {
3201 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
3202 ("MSI-X index too high"));
3203 if (dinfo->cfg.msi.msi_handlers == 0)
3205 dinfo->cfg.msi.msi_handlers--;
3206 if (dinfo->cfg.msi.msi_handlers == 0)
3207 pci_disable_msi(child);
3209 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3210 ("No MSI or MSI-X interrupts allocated"));
3211 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3212 ("MSI-X index too high"));
3213 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3214 if (mte->mte_handlers == 0)
3216 mte->mte_handlers--;
3217 if (mte->mte_handlers == 0)
3218 pci_mask_msix(child, rid - 1);
3221 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3224 ("%s: generic teardown failed for MSI/MSI-X", __func__));
3229 pci_print_child(device_t dev, device_t child)
3231 struct pci_devinfo *dinfo;
3232 struct resource_list *rl;
3235 dinfo = device_get_ivars(child);
3236 rl = &dinfo->resources;
3238 retval += bus_print_child_header(dev, child);
3240 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
3241 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
3242 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
3243 if (device_get_flags(dev))
3244 retval += printf(" flags %#x", device_get_flags(dev));
3246 retval += printf(" at device %d.%d", pci_get_slot(child),
3247 pci_get_function(child));
3249 retval += bus_print_child_footer(dev, child);
3259 } pci_nomatch_tab[] = {
3260 {PCIC_OLD, -1, "old"},
3261 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
3262 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
3263 {PCIC_STORAGE, -1, "mass storage"},
3264 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
3265 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
3266 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
3267 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
3268 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
3269 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"},
3270 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"},
3271 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"},
3272 {PCIC_NETWORK, -1, "network"},
3273 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
3274 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
3275 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
3276 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
3277 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
3278 {PCIC_DISPLAY, -1, "display"},
3279 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
3280 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
3281 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
3282 {PCIC_MULTIMEDIA, -1, "multimedia"},
3283 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
3284 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
3285 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
3286 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"},
3287 {PCIC_MEMORY, -1, "memory"},
3288 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
3289 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
3290 {PCIC_BRIDGE, -1, "bridge"},
3291 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
3292 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
3293 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
3294 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
3295 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
3296 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
3297 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
3298 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
3299 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
3300 {PCIC_SIMPLECOMM, -1, "simple comms"},
3301 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
3302 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
3303 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
3304 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
3305 {PCIC_BASEPERIPH, -1, "base peripheral"},
3306 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
3307 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
3308 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
3309 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
3310 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
3311 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"},
3312 {PCIC_INPUTDEV, -1, "input device"},
3313 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
3314 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
3315 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
3316 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
3317 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
3318 {PCIC_DOCKING, -1, "docking station"},
3319 {PCIC_PROCESSOR, -1, "processor"},
3320 {PCIC_SERIALBUS, -1, "serial bus"},
3321 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
3322 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
3323 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
3324 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
3325 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
3326 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
3327 {PCIC_WIRELESS, -1, "wireless controller"},
3328 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
3329 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
3330 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
3331 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
3332 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
3333 {PCIC_SATCOM, -1, "satellite communication"},
3334 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
3335 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
3336 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
3337 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
3338 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
3339 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
3340 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
3341 {PCIC_DASP, -1, "dasp"},
3342 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
3347 pci_probe_nomatch(device_t dev, device_t child)
3350 char *cp, *scp, *device;
3353 * Look for a listing for this device in a loaded device database.
3355 if ((device = pci_describe_device(child)) != NULL) {
3356 device_printf(dev, "<%s>", device);
3357 free(device, M_DEVBUF);
3360 * Scan the class/subclass descriptions for a general
3365 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
3366 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
3367 if (pci_nomatch_tab[i].subclass == -1) {
3368 cp = pci_nomatch_tab[i].desc;
3369 } else if (pci_nomatch_tab[i].subclass ==
3370 pci_get_subclass(child)) {
3371 scp = pci_nomatch_tab[i].desc;
3375 device_printf(dev, "<%s%s%s>",
3377 ((cp != NULL) && (scp != NULL)) ? ", " : "",
3380 printf(" at device %d.%d (no driver attached)\n",
3381 pci_get_slot(child), pci_get_function(child));
3382 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1);
3387 * Parse the PCI device database, if loaded, and return a pointer to a
3388 * description of the device.
3390 * The database is flat text formatted as follows:
3392 * Any line not in a valid format is ignored.
3393 * Lines are terminated with newline '\n' characters.
3395 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
3398 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
3399 * - devices cannot be listed without a corresponding VENDOR line.
3400 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
3401 * another TAB, then the device name.
3405 * Assuming (ptr) points to the beginning of a line in the database,
3406 * return the vendor or device and description of the next entry.
3407 * The value of (vendor) or (device) inappropriate for the entry type
3408 * is set to -1. Returns nonzero at the end of the database.
3410 * Note that this is slightly unrobust in the face of corrupt data;
3411 * we attempt to safeguard against this by spamming the end of the
3412 * database with a newline when we initialise.
3415 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
3424 left = pci_vendordata_size - (cp - pci_vendordata);
3432 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
3436 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
3439 /* skip to next line */
3440 while (*cp != '\n' && left > 0) {
3449 /* skip to next line */
3450 while (*cp != '\n' && left > 0) {
3454 if (*cp == '\n' && left > 0)
3461 pci_describe_device(device_t dev)
3464 char *desc, *vp, *dp, *line;
3466 desc = vp = dp = NULL;
3469 * If we have no vendor data, we can't do anything.
3471 if (pci_vendordata == NULL)
3475 * Scan the vendor data looking for this device
3477 line = pci_vendordata;
3478 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3481 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
3483 if (vendor == pci_get_vendor(dev))
3486 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3489 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
3497 if (device == pci_get_device(dev))
3501 snprintf(dp, 80, "0x%x", pci_get_device(dev));
3502 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
3504 sprintf(desc, "%s, %s", vp, dp);
3514 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
3516 struct pci_devinfo *dinfo;
3519 dinfo = device_get_ivars(child);
3523 case PCI_IVAR_ETHADDR:
3525 * The generic accessor doesn't deal with failure, so
3526 * we set the return value, then return an error.
3528 *((uint8_t **) result) = NULL;
3530 case PCI_IVAR_SUBVENDOR:
3531 *result = cfg->subvendor;
3533 case PCI_IVAR_SUBDEVICE:
3534 *result = cfg->subdevice;
3536 case PCI_IVAR_VENDOR:
3537 *result = cfg->vendor;
3539 case PCI_IVAR_DEVICE:
3540 *result = cfg->device;
3542 case PCI_IVAR_DEVID:
3543 *result = (cfg->device << 16) | cfg->vendor;
3545 case PCI_IVAR_CLASS:
3546 *result = cfg->baseclass;
3548 case PCI_IVAR_SUBCLASS:
3549 *result = cfg->subclass;
3551 case PCI_IVAR_PROGIF:
3552 *result = cfg->progif;
3554 case PCI_IVAR_REVID:
3555 *result = cfg->revid;
3557 case PCI_IVAR_INTPIN:
3558 *result = cfg->intpin;
3561 *result = cfg->intline;
3563 case PCI_IVAR_DOMAIN:
3564 *result = cfg->domain;
3570 *result = cfg->slot;
3572 case PCI_IVAR_FUNCTION:
3573 *result = cfg->func;
3575 case PCI_IVAR_CMDREG:
3576 *result = cfg->cmdreg;
3578 case PCI_IVAR_CACHELNSZ:
3579 *result = cfg->cachelnsz;
3581 case PCI_IVAR_MINGNT:
3582 *result = cfg->mingnt;
3584 case PCI_IVAR_MAXLAT:
3585 *result = cfg->maxlat;
3587 case PCI_IVAR_LATTIMER:
3588 *result = cfg->lattimer;
3597 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
3599 struct pci_devinfo *dinfo;
3601 dinfo = device_get_ivars(child);
3604 case PCI_IVAR_INTPIN:
3605 dinfo->cfg.intpin = value;
3607 case PCI_IVAR_ETHADDR:
3608 case PCI_IVAR_SUBVENDOR:
3609 case PCI_IVAR_SUBDEVICE:
3610 case PCI_IVAR_VENDOR:
3611 case PCI_IVAR_DEVICE:
3612 case PCI_IVAR_DEVID:
3613 case PCI_IVAR_CLASS:
3614 case PCI_IVAR_SUBCLASS:
3615 case PCI_IVAR_PROGIF:
3616 case PCI_IVAR_REVID:
3618 case PCI_IVAR_DOMAIN:
3621 case PCI_IVAR_FUNCTION:
3622 return (EINVAL); /* disallow for now */
3629 #include "opt_ddb.h"
3631 #include <ddb/ddb.h>
3632 #include <sys/cons.h>
3635 * List resources based on pci map registers, used for within ddb
3638 DB_SHOW_COMMAND(pciregs, db_pci_dump)
3640 struct pci_devinfo *dinfo;
3641 struct devlist *devlist_head;
3644 int i, error, none_count;
3647 /* get the head of the device queue */
3648 devlist_head = &pci_devq;
3651 * Go through the list of devices and print out devices
3653 for (error = 0, i = 0,
3654 dinfo = STAILQ_FIRST(devlist_head);
3655 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
3656 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
3658 /* Populate pd_name and pd_unit */
3661 name = device_get_name(dinfo->cfg.dev);
3664 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
3665 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
3666 (name && *name) ? name : "none",
3667 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
3669 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
3670 p->pc_sel.pc_func, (p->pc_class << 16) |
3671 (p->pc_subclass << 8) | p->pc_progif,
3672 (p->pc_subdevice << 16) | p->pc_subvendor,
3673 (p->pc_device << 16) | p->pc_vendor,
3674 p->pc_revid, p->pc_hdr);
3679 static struct resource *
3680 pci_alloc_map(device_t dev, device_t child, int type, int *rid,
3681 u_long start, u_long end, u_long count, u_int flags)
3683 struct pci_devinfo *dinfo = device_get_ivars(child);
3684 struct resource_list *rl = &dinfo->resources;
3685 struct resource_list_entry *rle;
3686 struct resource *res;
3687 pci_addr_t map, testval;
3691 * Weed out the bogons, and figure out how large the BAR/map
3692 * is. Bars that read back 0 here are bogus and unimplemented.
3693 * Note: atapci in legacy mode are special and handled elsewhere
3694 * in the code. If you have a atapci device in legacy mode and
3695 * it fails here, that other code is broken.
3698 pci_read_bar(child, *rid, &map, &testval);
3700 /* Ignore a BAR with a base of 0. */
3701 if (pci_mapbase(testval) == 0)
3704 if (PCI_BAR_MEM(testval)) {
3705 if (type != SYS_RES_MEMORY) {
3708 "child %s requested type %d for rid %#x,"
3709 " but the BAR says it is an memio\n",
3710 device_get_nameunit(child), type, *rid);
3714 if (type != SYS_RES_IOPORT) {
3717 "child %s requested type %d for rid %#x,"
3718 " but the BAR says it is an ioport\n",
3719 device_get_nameunit(child), type, *rid);
3725 * For real BARs, we need to override the size that
3726 * the driver requests, because that's what the BAR
3727 * actually uses and we would otherwise have a
3728 * situation where we might allocate the excess to
3729 * another driver, which won't work.
3731 mapsize = pci_mapsize(testval);
3732 count = (pci_addr_t)1 << mapsize;
3733 if (RF_ALIGNMENT(flags) < mapsize)
3734 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
3735 if (PCI_BAR_MEM(testval) && (testval & PCIM_BAR_MEM_PREFETCH))
3736 flags |= RF_PREFETCHABLE;
3739 * Allocate enough resource, and then write back the
3740 * appropriate bar for that resource.
3742 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
3743 start, end, count, flags & ~RF_ACTIVE);
3745 device_printf(child,
3746 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
3747 count, *rid, type, start, end);
3750 rman_set_device(res, dev);
3751 resource_list_add(rl, type, *rid, start, end, count);
3752 rle = resource_list_find(rl, type, *rid);
3754 panic("pci_alloc_map: unexpectedly can't find resource.");
3756 rle->start = rman_get_start(res);
3757 rle->end = rman_get_end(res);
3760 device_printf(child,
3761 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
3762 count, *rid, type, rman_get_start(res));
3763 map = rman_get_start(res);
3764 pci_write_bar(child, *rid, map);
3770 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
3771 u_long start, u_long end, u_long count, u_int flags)
3773 struct pci_devinfo *dinfo = device_get_ivars(child);
3774 struct resource_list *rl = &dinfo->resources;
3775 struct resource_list_entry *rle;
3776 struct resource *res;
3777 pcicfgregs *cfg = &dinfo->cfg;
3779 if (device_get_parent(child) != dev)
3780 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
3781 type, rid, start, end, count, flags));
3784 * Perform lazy resource allocation
3789 * Can't alloc legacy interrupt once MSI messages have
3792 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
3793 cfg->msix.msix_alloc > 0))
3797 * If the child device doesn't have an interrupt
3798 * routed and is deserving of an interrupt, try to
3801 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
3803 pci_assign_interrupt(dev, child, 0);
3805 case SYS_RES_IOPORT:
3806 case SYS_RES_MEMORY:
3809 * PCI-PCI bridge I/O window resources are not BARs.
3810 * For those allocations just pass the request up the
3813 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) {
3815 case PCIR_IOBASEL_1:
3816 case PCIR_MEMBASE_1:
3817 case PCIR_PMBASEL_1:
3819 * XXX: Should we bother creating a resource
3822 return (bus_generic_alloc_resource(dev, child,
3823 type, rid, start, end, count, flags));
3827 /* Allocate resources for this BAR if needed. */
3828 rle = resource_list_find(rl, type, *rid);
3830 res = pci_alloc_map(dev, child, type, rid, start, end,
3834 rle = resource_list_find(rl, type, *rid);
3838 * If the resource belongs to the bus, then give it to
3839 * the child. We need to activate it if requested
3840 * since the bus always allocates inactive resources.
3842 if (rle != NULL && rle->res != NULL &&
3843 rman_get_device(rle->res) == dev) {
3845 device_printf(child,
3846 "Reserved %#lx bytes for rid %#x type %d at %#lx\n",
3847 rman_get_size(rle->res), *rid, type,
3848 rman_get_start(rle->res));
3849 rman_set_device(rle->res, child);
3850 if ((flags & RF_ACTIVE) &&
3851 bus_activate_resource(child, type, *rid,
3857 return (resource_list_alloc(rl, dev, child, type, rid,
3858 start, end, count, flags));
3862 pci_release_resource(device_t dev, device_t child, int type, int rid,
3867 if (device_get_parent(child) != dev)
3868 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
3872 * For BARs we don't actually want to release the resource.
3873 * Instead, we deactivate the resource if needed and then give
3874 * ownership of the BAR back to the bus.
3877 case SYS_RES_IOPORT:
3878 case SYS_RES_MEMORY:
3879 if (rman_get_device(r) != child)
3881 if (rman_get_flags(r) & RF_ACTIVE) {
3882 error = bus_deactivate_resource(child, type, rid, r);
3886 rman_set_device(r, dev);
3889 return (bus_generic_rl_release_resource(dev, child, type, rid, r));
3893 pci_activate_resource(device_t dev, device_t child, int type, int rid,
3898 error = bus_generic_activate_resource(dev, child, type, rid, r);
3902 /* Enable decoding in the command register when activating BARs. */
3903 if (device_get_parent(child) == dev) {
3905 case SYS_RES_IOPORT:
3906 case SYS_RES_MEMORY:
3907 error = PCI_ENABLE_IO(dev, child, type);
3915 pci_delete_resource(device_t dev, device_t child, int type, int rid)
3917 struct pci_devinfo *dinfo;
3918 struct resource_list *rl;
3919 struct resource_list_entry *rle;
3921 if (device_get_parent(child) != dev)
3924 dinfo = device_get_ivars(child);
3925 rl = &dinfo->resources;
3926 rle = resource_list_find(rl, type, rid);
3931 if (rman_get_device(rle->res) != dev ||
3932 rman_get_flags(rle->res) & RF_ACTIVE) {
3933 device_printf(dev, "delete_resource: "
3934 "Resource still owned by child, oops. "
3935 "(type=%d, rid=%d, addr=%lx)\n",
3936 rle->type, rle->rid,
3937 rman_get_start(rle->res));
3941 #ifndef __PCI_BAR_ZERO_VALID
3943 * If this is a BAR, clear the BAR so it stops
3944 * decoding before releasing the resource.
3947 case SYS_RES_IOPORT:
3948 case SYS_RES_MEMORY:
3949 pci_write_bar(child, rid, 0);
3953 bus_release_resource(dev, type, rid, rle->res);
3955 resource_list_delete(rl, type, rid);
3958 struct resource_list *
3959 pci_get_resource_list (device_t dev, device_t child)
3961 struct pci_devinfo *dinfo = device_get_ivars(child);
3963 return (&dinfo->resources);
3967 pci_read_config_method(device_t dev, device_t child, int reg, int width)
3969 struct pci_devinfo *dinfo = device_get_ivars(child);
3970 pcicfgregs *cfg = &dinfo->cfg;
3972 return (PCIB_READ_CONFIG(device_get_parent(dev),
3973 cfg->bus, cfg->slot, cfg->func, reg, width));
3977 pci_write_config_method(device_t dev, device_t child, int reg,
3978 uint32_t val, int width)
3980 struct pci_devinfo *dinfo = device_get_ivars(child);
3981 pcicfgregs *cfg = &dinfo->cfg;
3983 PCIB_WRITE_CONFIG(device_get_parent(dev),
3984 cfg->bus, cfg->slot, cfg->func, reg, val, width);
3988 pci_child_location_str_method(device_t dev, device_t child, char *buf,
3992 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
3993 pci_get_function(child));
3998 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
4001 struct pci_devinfo *dinfo;
4004 dinfo = device_get_ivars(child);
4006 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
4007 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
4008 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
4014 pci_assign_interrupt_method(device_t dev, device_t child)
4016 struct pci_devinfo *dinfo = device_get_ivars(child);
4017 pcicfgregs *cfg = &dinfo->cfg;
4019 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
4024 pci_modevent(module_t mod, int what, void *arg)
4026 static struct cdev *pci_cdev;
4030 STAILQ_INIT(&pci_devq);
4032 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644,
4034 pci_load_vendor_data();
4038 destroy_dev(pci_cdev);
4046 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
4051 * Only do header type 0 devices. Type 1 devices are bridges,
4052 * which we know need special treatment. Type 2 devices are
4053 * cardbus bridges which also require special treatment.
4054 * Other types are unknown, and we err on the side of safety
4057 if (dinfo->cfg.hdrtype != 0)
4061 * Restore the device to full power mode. We must do this
4062 * before we restore the registers because moving from D3 to
4063 * D0 will cause the chip's BARs and some other registers to
4064 * be reset to some unknown power on reset values. Cut down
4065 * the noise on boot by doing nothing if we are already in
4068 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
4069 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4071 for (i = 0; i < dinfo->cfg.nummaps; i++)
4072 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
4073 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
4074 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
4075 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
4076 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
4077 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
4078 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
4079 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
4080 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
4081 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
4082 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
4084 /* Restore MSI and MSI-X configurations if they are present. */
4085 if (dinfo->cfg.msi.msi_location != 0)
4086 pci_resume_msi(dev);
4087 if (dinfo->cfg.msix.msix_location != 0)
4088 pci_resume_msix(dev);
4092 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
4099 * Only do header type 0 devices. Type 1 devices are bridges, which
4100 * we know need special treatment. Type 2 devices are cardbus bridges
4101 * which also require special treatment. Other types are unknown, and
4102 * we err on the side of safety by ignoring them. Powering down
4103 * bridges should not be undertaken lightly.
4105 if (dinfo->cfg.hdrtype != 0)
4107 for (i = 0; i < dinfo->cfg.nummaps; i++)
4108 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
4109 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
4112 * Some drivers apparently write to these registers w/o updating our
4113 * cached copy. No harm happens if we update the copy, so do so here
4114 * so we can restore them. The COMMAND register is modified by the
4115 * bus w/o updating the cache. This should represent the normally
4116 * writable portion of the 'defined' part of type 0 headers. In
4117 * theory we also need to save/restore the PCI capability structures
4118 * we know about, but apart from power we don't know any that are
4121 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
4122 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4123 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
4124 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
4125 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
4126 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
4127 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
4128 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
4129 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
4130 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
4131 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
4132 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
4133 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
4134 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
4135 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
4138 * don't set the state for display devices, base peripherals and
4139 * memory devices since bad things happen when they are powered down.
4140 * We should (a) have drivers that can easily detach and (b) use
4141 * generic drivers for these devices so that some device actually
4142 * attaches. We need to make sure that when we implement (a) we don't
4143 * power the device down on a reattach.
4145 cls = pci_get_class(dev);
4148 switch (pci_do_power_nodriver)
4150 case 0: /* NO powerdown at all */
4152 case 1: /* Conservative about what to power down */
4153 if (cls == PCIC_STORAGE)
4156 case 2: /* Agressive about what to power down */
4157 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
4158 cls == PCIC_BASEPERIPH)
4161 case 3: /* Power down everything */
4165 * PCI spec says we can only go into D3 state from D0 state.
4166 * Transition from D[12] into D0 before going to D3 state.
4168 ps = pci_get_powerstate(dev);
4169 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
4170 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4171 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
4172 pci_set_powerstate(dev, PCI_POWERSTATE_D3);