2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/linker.h>
39 #include <sys/fcntl.h>
41 #include <sys/kernel.h>
42 #include <sys/queue.h>
43 #include <sys/sysctl.h>
44 #include <sys/endian.h>
48 #include <vm/vm_extern.h>
51 #include <machine/bus.h>
53 #include <machine/resource.h>
54 #include <machine/stdarg.h>
56 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
57 #include <machine/intr_machdep.h>
60 #include <sys/pciio.h>
61 #include <dev/pci/pcireg.h>
62 #include <dev/pci/pcivar.h>
63 #include <dev/pci/pci_private.h>
65 #include <dev/usb/controller/ehcireg.h>
66 #include <dev/usb/controller/ohcireg.h>
67 #include <dev/usb/controller/uhcireg.h>
73 #include <contrib/dev/acpica/include/acpi.h>
76 #define ACPI_PWR_FOR_SLEEP(x, y, z)
79 static pci_addr_t pci_mapbase(uint64_t mapreg);
80 static const char *pci_maptype(uint64_t mapreg);
81 static int pci_mapsize(uint64_t testval);
82 static int pci_maprange(uint64_t mapreg);
83 static void pci_fixancient(pcicfgregs *cfg);
84 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...);
86 static int pci_porten(device_t dev);
87 static int pci_memen(device_t dev);
88 static void pci_assign_interrupt(device_t bus, device_t dev,
90 static int pci_add_map(device_t bus, device_t dev, int reg,
91 struct resource_list *rl, int force, int prefetch);
92 static int pci_probe(device_t dev);
93 static int pci_attach(device_t dev);
94 static void pci_load_vendor_data(void);
95 static int pci_describe_parse_line(char **ptr, int *vendor,
96 int *device, char **desc);
97 static char *pci_describe_device(device_t dev);
98 static int pci_modevent(module_t mod, int what, void *arg);
99 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
101 static void pci_read_cap(device_t pcib, pcicfgregs *cfg);
102 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
103 int reg, uint32_t *data);
105 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
106 int reg, uint32_t data);
108 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
109 static void pci_disable_msi(device_t dev);
110 static void pci_enable_msi(device_t dev, uint64_t address,
112 static void pci_enable_msix(device_t dev, u_int index,
113 uint64_t address, uint32_t data);
114 static void pci_mask_msix(device_t dev, u_int index);
115 static void pci_unmask_msix(device_t dev, u_int index);
116 static int pci_msi_blacklisted(void);
117 static void pci_resume_msi(device_t dev);
118 static void pci_resume_msix(device_t dev);
119 static int pci_remap_intr_method(device_t bus, device_t dev,
122 static device_method_t pci_methods[] = {
123 /* Device interface */
124 DEVMETHOD(device_probe, pci_probe),
125 DEVMETHOD(device_attach, pci_attach),
126 DEVMETHOD(device_detach, bus_generic_detach),
127 DEVMETHOD(device_shutdown, bus_generic_shutdown),
128 DEVMETHOD(device_suspend, pci_suspend),
129 DEVMETHOD(device_resume, pci_resume),
132 DEVMETHOD(bus_print_child, pci_print_child),
133 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
134 DEVMETHOD(bus_read_ivar, pci_read_ivar),
135 DEVMETHOD(bus_write_ivar, pci_write_ivar),
136 DEVMETHOD(bus_driver_added, pci_driver_added),
137 DEVMETHOD(bus_setup_intr, pci_setup_intr),
138 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
140 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
141 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
142 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
143 DEVMETHOD(bus_delete_resource, pci_delete_resource),
144 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
145 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
146 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
147 DEVMETHOD(bus_activate_resource, pci_activate_resource),
148 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
149 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
150 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
151 DEVMETHOD(bus_remap_intr, pci_remap_intr_method),
154 DEVMETHOD(pci_read_config, pci_read_config_method),
155 DEVMETHOD(pci_write_config, pci_write_config_method),
156 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
157 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
158 DEVMETHOD(pci_enable_io, pci_enable_io_method),
159 DEVMETHOD(pci_disable_io, pci_disable_io_method),
160 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
161 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
162 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
163 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
164 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
165 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
166 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
167 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method),
168 DEVMETHOD(pci_remap_msix, pci_remap_msix_method),
169 DEVMETHOD(pci_release_msi, pci_release_msi_method),
170 DEVMETHOD(pci_msi_count, pci_msi_count_method),
171 DEVMETHOD(pci_msix_count, pci_msix_count_method),
176 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
178 static devclass_t pci_devclass;
179 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
180 MODULE_VERSION(pci, 1);
182 static char *pci_vendordata;
183 static size_t pci_vendordata_size;
187 uint32_t devid; /* Vendor/device of the card */
189 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
190 #define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */
191 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */
196 struct pci_quirk pci_quirks[] = {
197 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
198 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
199 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
200 /* As does the Serverworks OSB4 (the SMBus mapping register) */
201 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
204 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
205 * or the CMIC-SL (AKA ServerWorks GC_LE).
207 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
208 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
211 * MSI doesn't work on earlier Intel chipsets including
212 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
214 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
215 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
216 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
217 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
218 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
219 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
220 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
223 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
226 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
229 * Some virtualization environments emulate an older chipset
230 * but support MSI just fine. QEMU uses the Intel 82440.
232 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 },
237 /* map register information */
238 #define PCI_MAPMEM 0x01 /* memory map */
239 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
240 #define PCI_MAPPORT 0x04 /* port map */
242 struct devlist pci_devq;
243 uint32_t pci_generation;
244 uint32_t pci_numdevs = 0;
245 static int pcie_chipset, pcix_chipset;
248 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
250 static int pci_enable_io_modes = 1;
251 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
252 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
253 &pci_enable_io_modes, 1,
254 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
255 enable these bits correctly. We'd like to do this all the time, but there\n\
256 are some peripherals that this causes problems with.");
258 static int pci_do_power_nodriver = 0;
259 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
260 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
261 &pci_do_power_nodriver, 0,
262 "Place a function into D3 state when no driver attaches to it. 0 means\n\
263 disable. 1 means conservatively place devices into D3 state. 2 means\n\
264 agressively place devices into D3 state. 3 means put absolutely everything\n\
267 static int pci_do_power_resume = 1;
268 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
269 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
270 &pci_do_power_resume, 1,
271 "Transition from D3 -> D0 on resume.");
273 static int pci_do_msi = 1;
274 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
275 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
276 "Enable support for MSI interrupts");
278 static int pci_do_msix = 1;
279 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
280 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
281 "Enable support for MSI-X interrupts");
283 static int pci_honor_msi_blacklist = 1;
284 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
285 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
286 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI");
288 #if defined(__i386__) || defined(__amd64__)
289 static int pci_usb_takeover = 1;
291 static int pci_usb_takeover = 0;
293 TUNABLE_INT("hw.pci.usb_early_takeover", &pci_usb_takeover);
294 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RD | CTLFLAG_TUN,
295 &pci_usb_takeover, 1, "Enable early takeover of USB controllers.\n\
296 Disable this if you depend on BIOS emulation of USB devices, that is\n\
297 you use USB devices (like keyboard or mouse) but do not load USB drivers");
299 /* Find a device_t by bus/slot/function in domain 0 */
302 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
305 return (pci_find_dbsf(0, bus, slot, func));
308 /* Find a device_t by domain/bus/slot/function */
311 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
313 struct pci_devinfo *dinfo;
315 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
316 if ((dinfo->cfg.domain == domain) &&
317 (dinfo->cfg.bus == bus) &&
318 (dinfo->cfg.slot == slot) &&
319 (dinfo->cfg.func == func)) {
320 return (dinfo->cfg.dev);
327 /* Find a device_t by vendor/device ID */
330 pci_find_device(uint16_t vendor, uint16_t device)
332 struct pci_devinfo *dinfo;
334 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
335 if ((dinfo->cfg.vendor == vendor) &&
336 (dinfo->cfg.device == device)) {
337 return (dinfo->cfg.dev);
345 pci_printf(pcicfgregs *cfg, const char *fmt, ...)
350 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot,
353 retval += vprintf(fmt, ap);
358 /* return base address of memory or port map */
361 pci_mapbase(uint64_t mapreg)
364 if (PCI_BAR_MEM(mapreg))
365 return (mapreg & PCIM_BAR_MEM_BASE);
367 return (mapreg & PCIM_BAR_IO_BASE);
370 /* return map type of memory or port map */
373 pci_maptype(uint64_t mapreg)
376 if (PCI_BAR_IO(mapreg))
378 if (mapreg & PCIM_BAR_MEM_PREFETCH)
379 return ("Prefetchable Memory");
383 /* return log2 of map size decoded for memory or port map */
386 pci_mapsize(uint64_t testval)
390 testval = pci_mapbase(testval);
393 while ((testval & 1) == 0)
402 /* return log2 of address range supported by map register */
405 pci_maprange(uint64_t mapreg)
409 if (PCI_BAR_IO(mapreg))
412 switch (mapreg & PCIM_BAR_MEM_TYPE) {
413 case PCIM_BAR_MEM_32:
416 case PCIM_BAR_MEM_1MB:
419 case PCIM_BAR_MEM_64:
426 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
429 pci_fixancient(pcicfgregs *cfg)
431 if (cfg->hdrtype != 0)
434 /* PCI to PCI bridges use header type 1 */
435 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
439 /* extract header type specific config data */
442 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
444 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
445 switch (cfg->hdrtype) {
447 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
448 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
449 cfg->nummaps = PCI_MAXMAPS_0;
452 cfg->nummaps = PCI_MAXMAPS_1;
455 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
456 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
457 cfg->nummaps = PCI_MAXMAPS_2;
463 /* read configuration header into pcicfgregs structure */
465 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
467 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
468 pcicfgregs *cfg = NULL;
469 struct pci_devinfo *devlist_entry;
470 struct devlist *devlist_head;
472 devlist_head = &pci_devq;
474 devlist_entry = NULL;
476 if (REG(PCIR_DEVVENDOR, 4) != 0xfffffffful) {
477 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
478 if (devlist_entry == NULL)
481 cfg = &devlist_entry->cfg;
487 cfg->vendor = REG(PCIR_VENDOR, 2);
488 cfg->device = REG(PCIR_DEVICE, 2);
489 cfg->cmdreg = REG(PCIR_COMMAND, 2);
490 cfg->statreg = REG(PCIR_STATUS, 2);
491 cfg->baseclass = REG(PCIR_CLASS, 1);
492 cfg->subclass = REG(PCIR_SUBCLASS, 1);
493 cfg->progif = REG(PCIR_PROGIF, 1);
494 cfg->revid = REG(PCIR_REVID, 1);
495 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
496 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
497 cfg->lattimer = REG(PCIR_LATTIMER, 1);
498 cfg->intpin = REG(PCIR_INTPIN, 1);
499 cfg->intline = REG(PCIR_INTLINE, 1);
501 cfg->mingnt = REG(PCIR_MINGNT, 1);
502 cfg->maxlat = REG(PCIR_MAXLAT, 1);
504 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
505 cfg->hdrtype &= ~PCIM_MFDEV;
508 pci_hdrtypedata(pcib, b, s, f, cfg);
510 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
511 pci_read_cap(pcib, cfg);
513 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
515 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
516 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
517 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
518 devlist_entry->conf.pc_sel.pc_func = cfg->func;
519 devlist_entry->conf.pc_hdr = cfg->hdrtype;
521 devlist_entry->conf.pc_subvendor = cfg->subvendor;
522 devlist_entry->conf.pc_subdevice = cfg->subdevice;
523 devlist_entry->conf.pc_vendor = cfg->vendor;
524 devlist_entry->conf.pc_device = cfg->device;
526 devlist_entry->conf.pc_class = cfg->baseclass;
527 devlist_entry->conf.pc_subclass = cfg->subclass;
528 devlist_entry->conf.pc_progif = cfg->progif;
529 devlist_entry->conf.pc_revid = cfg->revid;
534 return (devlist_entry);
539 pci_read_cap(device_t pcib, pcicfgregs *cfg)
541 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
542 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
543 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
547 int ptr, nextptr, ptrptr;
549 switch (cfg->hdrtype & PCIM_HDRTYPE) {
552 ptrptr = PCIR_CAP_PTR;
555 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
558 return; /* no extended capabilities support */
560 nextptr = REG(ptrptr, 1); /* sanity check? */
563 * Read capability entries.
565 while (nextptr != 0) {
568 printf("illegal PCI extended capability offset %d\n",
572 /* Find the next entry */
574 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
576 /* Process this entry */
577 switch (REG(ptr + PCICAP_ID, 1)) {
578 case PCIY_PMG: /* PCI power management */
579 if (cfg->pp.pp_cap == 0) {
580 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
581 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS;
582 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR;
583 if ((nextptr - ptr) > PCIR_POWER_DATA)
584 cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
587 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
588 case PCIY_HT: /* HyperTransport */
589 /* Determine HT-specific capability type. */
590 val = REG(ptr + PCIR_HT_COMMAND, 2);
591 switch (val & PCIM_HTCMD_CAP_MASK) {
592 case PCIM_HTCAP_MSI_MAPPING:
593 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
594 /* Sanity check the mapping window. */
595 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI,
598 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO,
600 if (addr != MSI_INTEL_ADDR_BASE)
602 "HT Bridge at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n",
603 cfg->domain, cfg->bus,
604 cfg->slot, cfg->func,
607 addr = MSI_INTEL_ADDR_BASE;
609 cfg->ht.ht_msimap = ptr;
610 cfg->ht.ht_msictrl = val;
611 cfg->ht.ht_msiaddr = addr;
616 case PCIY_MSI: /* PCI MSI */
617 cfg->msi.msi_location = ptr;
618 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
619 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl &
620 PCIM_MSICTRL_MMC_MASK)>>1);
622 case PCIY_MSIX: /* PCI MSI-X */
623 cfg->msix.msix_location = ptr;
624 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
625 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl &
626 PCIM_MSIXCTRL_TABLE_SIZE) + 1;
627 val = REG(ptr + PCIR_MSIX_TABLE, 4);
628 cfg->msix.msix_table_bar = PCIR_BAR(val &
630 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
631 val = REG(ptr + PCIR_MSIX_PBA, 4);
632 cfg->msix.msix_pba_bar = PCIR_BAR(val &
634 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
636 case PCIY_VPD: /* PCI Vital Product Data */
637 cfg->vpd.vpd_reg = ptr;
640 /* Should always be true. */
641 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) {
642 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
643 cfg->subvendor = val & 0xffff;
644 cfg->subdevice = val >> 16;
647 case PCIY_PCIX: /* PCI-X */
649 * Assume we have a PCI-X chipset if we have
650 * at least one PCI-PCI bridge with a PCI-X
651 * capability. Note that some systems with
652 * PCI-express or HT chipsets might match on
653 * this check as well.
655 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1)
658 case PCIY_EXPRESS: /* PCI-express */
660 * Assume we have a PCI-express chipset if we have
661 * at least one PCI-express device.
669 /* REG and WREG use carry through to next functions */
673 * PCI Vital Product Data
676 #define PCI_VPD_TIMEOUT 1000000
679 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
681 int count = PCI_VPD_TIMEOUT;
683 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
685 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
687 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
690 DELAY(1); /* limit looping */
692 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
699 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
701 int count = PCI_VPD_TIMEOUT;
703 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
705 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
706 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
707 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
710 DELAY(1); /* limit looping */
717 #undef PCI_VPD_TIMEOUT
719 struct vpd_readstate {
729 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
734 if (vrs->bytesinval == 0) {
735 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
737 vrs->val = le32toh(reg);
739 byte = vrs->val & 0xff;
742 vrs->val = vrs->val >> 8;
743 byte = vrs->val & 0xff;
753 pci_read_vpd(device_t pcib, pcicfgregs *cfg)
755 struct vpd_readstate vrs;
760 int alloc, off; /* alloc/off for RO/W arrays */
766 /* init vpd reader */
774 name = remain = i = 0; /* shut up stupid gcc */
775 alloc = off = 0; /* shut up stupid gcc */
776 dflen = 0; /* shut up stupid gcc */
779 if (vpd_nextbyte(&vrs, &byte)) {
784 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
785 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
786 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
789 case 0: /* item name */
791 if (vpd_nextbyte(&vrs, &byte2)) {
796 if (vpd_nextbyte(&vrs, &byte2)) {
800 remain |= byte2 << 8;
801 if (remain > (0x7f*4 - vrs.off)) {
804 "pci%d:%d:%d:%d: invalid VPD data, remain %#x\n",
805 cfg->domain, cfg->bus, cfg->slot,
811 name = (byte >> 3) & 0xf;
814 case 0x2: /* String */
815 cfg->vpd.vpd_ident = malloc(remain + 1,
823 case 0x10: /* VPD-R */
826 cfg->vpd.vpd_ros = malloc(alloc *
827 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
831 case 0x11: /* VPD-W */
834 cfg->vpd.vpd_w = malloc(alloc *
835 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
839 default: /* Invalid data, abort */
845 case 1: /* Identifier String */
846 cfg->vpd.vpd_ident[i++] = byte;
849 cfg->vpd.vpd_ident[i] = '\0';
854 case 2: /* VPD-R Keyword Header */
856 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
857 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
858 M_DEVBUF, M_WAITOK | M_ZERO);
860 cfg->vpd.vpd_ros[off].keyword[0] = byte;
861 if (vpd_nextbyte(&vrs, &byte2)) {
865 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
866 if (vpd_nextbyte(&vrs, &byte2)) {
872 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
875 * if this happens, we can't trust the rest
879 "pci%d:%d:%d:%d: bad keyword length: %d\n",
880 cfg->domain, cfg->bus, cfg->slot,
885 } else if (dflen == 0) {
886 cfg->vpd.vpd_ros[off].value = malloc(1 *
887 sizeof(*cfg->vpd.vpd_ros[off].value),
889 cfg->vpd.vpd_ros[off].value[0] = '\x00';
891 cfg->vpd.vpd_ros[off].value = malloc(
893 sizeof(*cfg->vpd.vpd_ros[off].value),
897 /* keep in sync w/ state 3's transistions */
898 if (dflen == 0 && remain == 0)
906 case 3: /* VPD-R Keyword Value */
907 cfg->vpd.vpd_ros[off].value[i++] = byte;
908 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
909 "RV", 2) == 0 && cksumvalid == -1) {
915 "pci%d:%d:%d:%d: bad VPD cksum, remain %hhu\n",
916 cfg->domain, cfg->bus,
917 cfg->slot, cfg->func,
926 /* keep in sync w/ state 2's transistions */
928 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
929 if (dflen == 0 && remain == 0) {
930 cfg->vpd.vpd_rocnt = off;
931 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
932 off * sizeof(*cfg->vpd.vpd_ros),
933 M_DEVBUF, M_WAITOK | M_ZERO);
935 } else if (dflen == 0)
945 case 5: /* VPD-W Keyword Header */
947 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
948 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
949 M_DEVBUF, M_WAITOK | M_ZERO);
951 cfg->vpd.vpd_w[off].keyword[0] = byte;
952 if (vpd_nextbyte(&vrs, &byte2)) {
956 cfg->vpd.vpd_w[off].keyword[1] = byte2;
957 if (vpd_nextbyte(&vrs, &byte2)) {
961 cfg->vpd.vpd_w[off].len = dflen = byte2;
962 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
963 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) *
964 sizeof(*cfg->vpd.vpd_w[off].value),
968 /* keep in sync w/ state 6's transistions */
969 if (dflen == 0 && remain == 0)
977 case 6: /* VPD-W Keyword Value */
978 cfg->vpd.vpd_w[off].value[i++] = byte;
981 /* keep in sync w/ state 5's transistions */
983 cfg->vpd.vpd_w[off++].value[i++] = '\0';
984 if (dflen == 0 && remain == 0) {
985 cfg->vpd.vpd_wcnt = off;
986 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
987 off * sizeof(*cfg->vpd.vpd_w),
988 M_DEVBUF, M_WAITOK | M_ZERO);
990 } else if (dflen == 0)
995 printf("pci%d:%d:%d:%d: invalid state: %d\n",
996 cfg->domain, cfg->bus, cfg->slot, cfg->func,
1003 if (cksumvalid == 0 || state < -1) {
1004 /* read-only data bad, clean up */
1005 if (cfg->vpd.vpd_ros != NULL) {
1006 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1007 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1008 free(cfg->vpd.vpd_ros, M_DEVBUF);
1009 cfg->vpd.vpd_ros = NULL;
1013 /* I/O error, clean up */
1014 printf("pci%d:%d:%d:%d: failed to read VPD data.\n",
1015 cfg->domain, cfg->bus, cfg->slot, cfg->func);
1016 if (cfg->vpd.vpd_ident != NULL) {
1017 free(cfg->vpd.vpd_ident, M_DEVBUF);
1018 cfg->vpd.vpd_ident = NULL;
1020 if (cfg->vpd.vpd_w != NULL) {
1021 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1022 free(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1023 free(cfg->vpd.vpd_w, M_DEVBUF);
1024 cfg->vpd.vpd_w = NULL;
1027 cfg->vpd.vpd_cached = 1;
1033 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1035 struct pci_devinfo *dinfo = device_get_ivars(child);
1036 pcicfgregs *cfg = &dinfo->cfg;
1038 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1039 pci_read_vpd(device_get_parent(dev), cfg);
1041 *identptr = cfg->vpd.vpd_ident;
1043 if (*identptr == NULL)
1050 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1053 struct pci_devinfo *dinfo = device_get_ivars(child);
1054 pcicfgregs *cfg = &dinfo->cfg;
1057 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1058 pci_read_vpd(device_get_parent(dev), cfg);
1060 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1061 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1062 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1063 *vptr = cfg->vpd.vpd_ros[i].value;
1066 if (i != cfg->vpd.vpd_rocnt)
1074 * Find the requested extended capability and return the offset in
1075 * configuration space via the pointer provided. The function returns
1076 * 0 on success and error code otherwise.
1079 pci_find_extcap_method(device_t dev, device_t child, int capability,
1082 struct pci_devinfo *dinfo = device_get_ivars(child);
1083 pcicfgregs *cfg = &dinfo->cfg;
1088 * Check the CAP_LIST bit of the PCI status register first.
1090 status = pci_read_config(child, PCIR_STATUS, 2);
1091 if (!(status & PCIM_STATUS_CAPPRESENT))
1095 * Determine the start pointer of the capabilities list.
1097 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1103 ptr = PCIR_CAP_PTR_2;
1107 return (ENXIO); /* no extended capabilities support */
1109 ptr = pci_read_config(child, ptr, 1);
1112 * Traverse the capabilities list.
1115 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1120 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1127 * Support for MSI-X message interrupts.
1130 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
1132 struct pci_devinfo *dinfo = device_get_ivars(dev);
1133 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1136 KASSERT(msix->msix_table_len > index, ("bogus index"));
1137 offset = msix->msix_table_offset + index * 16;
1138 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1139 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1140 bus_write_4(msix->msix_table_res, offset + 8, data);
1142 /* Enable MSI -> HT mapping. */
1143 pci_ht_map_msi(dev, address);
1147 pci_mask_msix(device_t dev, u_int index)
1149 struct pci_devinfo *dinfo = device_get_ivars(dev);
1150 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1151 uint32_t offset, val;
1153 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1154 offset = msix->msix_table_offset + index * 16 + 12;
1155 val = bus_read_4(msix->msix_table_res, offset);
1156 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1157 val |= PCIM_MSIX_VCTRL_MASK;
1158 bus_write_4(msix->msix_table_res, offset, val);
1163 pci_unmask_msix(device_t dev, u_int index)
1165 struct pci_devinfo *dinfo = device_get_ivars(dev);
1166 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1167 uint32_t offset, val;
1169 KASSERT(msix->msix_table_len > index, ("bogus index"));
1170 offset = msix->msix_table_offset + index * 16 + 12;
1171 val = bus_read_4(msix->msix_table_res, offset);
1172 if (val & PCIM_MSIX_VCTRL_MASK) {
1173 val &= ~PCIM_MSIX_VCTRL_MASK;
1174 bus_write_4(msix->msix_table_res, offset, val);
1179 pci_pending_msix(device_t dev, u_int index)
1181 struct pci_devinfo *dinfo = device_get_ivars(dev);
1182 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1183 uint32_t offset, bit;
1185 KASSERT(msix->msix_table_len > index, ("bogus index"));
1186 offset = msix->msix_pba_offset + (index / 32) * 4;
1187 bit = 1 << index % 32;
1188 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1192 * Restore MSI-X registers and table during resume. If MSI-X is
1193 * enabled then walk the virtual table to restore the actual MSI-X
1197 pci_resume_msix(device_t dev)
1199 struct pci_devinfo *dinfo = device_get_ivars(dev);
1200 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1201 struct msix_table_entry *mte;
1202 struct msix_vector *mv;
1205 if (msix->msix_alloc > 0) {
1206 /* First, mask all vectors. */
1207 for (i = 0; i < msix->msix_msgnum; i++)
1208 pci_mask_msix(dev, i);
1210 /* Second, program any messages with at least one handler. */
1211 for (i = 0; i < msix->msix_table_len; i++) {
1212 mte = &msix->msix_table[i];
1213 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1215 mv = &msix->msix_vectors[mte->mte_vector - 1];
1216 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data);
1217 pci_unmask_msix(dev, i);
1220 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1221 msix->msix_ctrl, 2);
1225 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1226 * returned in *count. After this function returns, each message will be
1227 * available to the driver as SYS_RES_IRQ resources starting at rid 1.
1230 pci_alloc_msix_method(device_t dev, device_t child, int *count)
1232 struct pci_devinfo *dinfo = device_get_ivars(child);
1233 pcicfgregs *cfg = &dinfo->cfg;
1234 struct resource_list_entry *rle;
1235 int actual, error, i, irq, max;
1237 /* Don't let count == 0 get us into trouble. */
1241 /* If rid 0 is allocated, then fail. */
1242 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1243 if (rle != NULL && rle->res != NULL)
1246 /* Already have allocated messages? */
1247 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1250 /* If MSI is blacklisted for this system, fail. */
1251 if (pci_msi_blacklisted())
1254 /* MSI-X capability present? */
1255 if (cfg->msix.msix_location == 0 || !pci_do_msix)
1258 /* Make sure the appropriate BARs are mapped. */
1259 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1260 cfg->msix.msix_table_bar);
1261 if (rle == NULL || rle->res == NULL ||
1262 !(rman_get_flags(rle->res) & RF_ACTIVE))
1264 cfg->msix.msix_table_res = rle->res;
1265 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1266 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1267 cfg->msix.msix_pba_bar);
1268 if (rle == NULL || rle->res == NULL ||
1269 !(rman_get_flags(rle->res) & RF_ACTIVE))
1272 cfg->msix.msix_pba_res = rle->res;
1275 device_printf(child,
1276 "attempting to allocate %d MSI-X vectors (%d supported)\n",
1277 *count, cfg->msix.msix_msgnum);
1278 max = min(*count, cfg->msix.msix_msgnum);
1279 for (i = 0; i < max; i++) {
1280 /* Allocate a message. */
1281 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq);
1284 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1290 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
1292 device_printf(child, "using IRQ %lu for MSI-X\n",
1298 * Be fancy and try to print contiguous runs of
1299 * IRQ values as ranges. 'irq' is the previous IRQ.
1300 * 'run' is true if we are in a range.
1302 device_printf(child, "using IRQs %lu", rle->start);
1305 for (i = 1; i < actual; i++) {
1306 rle = resource_list_find(&dinfo->resources,
1307 SYS_RES_IRQ, i + 1);
1309 /* Still in a run? */
1310 if (rle->start == irq + 1) {
1316 /* Finish previous range. */
1322 /* Start new range. */
1323 printf(",%lu", rle->start);
1327 /* Unfinished range? */
1330 printf(" for MSI-X\n");
1334 /* Mask all vectors. */
1335 for (i = 0; i < cfg->msix.msix_msgnum; i++)
1336 pci_mask_msix(child, i);
1338 /* Allocate and initialize vector data and virtual table. */
1339 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual,
1340 M_DEVBUF, M_WAITOK | M_ZERO);
1341 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual,
1342 M_DEVBUF, M_WAITOK | M_ZERO);
1343 for (i = 0; i < actual; i++) {
1344 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1345 cfg->msix.msix_vectors[i].mv_irq = rle->start;
1346 cfg->msix.msix_table[i].mte_vector = i + 1;
1349 /* Update control register to enable MSI-X. */
1350 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1351 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1352 cfg->msix.msix_ctrl, 2);
1354 /* Update counts of alloc'd messages. */
1355 cfg->msix.msix_alloc = actual;
1356 cfg->msix.msix_table_len = actual;
1362 * By default, pci_alloc_msix() will assign the allocated IRQ
1363 * resources consecutively to the first N messages in the MSI-X table.
1364 * However, device drivers may want to use different layouts if they
1365 * either receive fewer messages than they asked for, or they wish to
1366 * populate the MSI-X table sparsely. This method allows the driver
1367 * to specify what layout it wants. It must be called after a
1368 * successful pci_alloc_msix() but before any of the associated
1369 * SYS_RES_IRQ resources are allocated via bus_alloc_resource().
1371 * The 'vectors' array contains 'count' message vectors. The array
1372 * maps directly to the MSI-X table in that index 0 in the array
1373 * specifies the vector for the first message in the MSI-X table, etc.
1374 * The vector value in each array index can either be 0 to indicate
1375 * that no vector should be assigned to a message slot, or it can be a
1376 * number from 1 to N (where N is the count returned from a
1377 * succcessful call to pci_alloc_msix()) to indicate which message
1378 * vector (IRQ) to be used for the corresponding message.
1380 * On successful return, each message with a non-zero vector will have
1381 * an associated SYS_RES_IRQ whose rid is equal to the array index +
1382 * 1. Additionally, if any of the IRQs allocated via the previous
1383 * call to pci_alloc_msix() are not used in the mapping, those IRQs
1384 * will be freed back to the system automatically.
1386 * For example, suppose a driver has a MSI-X table with 6 messages and
1387 * asks for 6 messages, but pci_alloc_msix() only returns a count of
1388 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and
1389 * C. After the call to pci_alloc_msix(), the device will be setup to
1390 * have an MSI-X table of ABC--- (where - means no vector assigned).
1391 * If the driver ten passes a vector array of { 1, 0, 1, 2, 0, 2 },
1392 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1393 * be freed back to the system. This device will also have valid
1394 * SYS_RES_IRQ rids of 1, 3, 4, and 6.
1396 * In any case, the SYS_RES_IRQ rid X will always map to the message
1397 * at MSI-X table index X - 1 and will only be valid if a vector is
1398 * assigned to that table entry.
1401 pci_remap_msix_method(device_t dev, device_t child, int count,
1402 const u_int *vectors)
1404 struct pci_devinfo *dinfo = device_get_ivars(child);
1405 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1406 struct resource_list_entry *rle;
1407 int i, irq, j, *used;
1410 * Have to have at least one message in the table but the
1411 * table can't be bigger than the actual MSI-X table in the
1414 if (count == 0 || count > msix->msix_msgnum)
1417 /* Sanity check the vectors. */
1418 for (i = 0; i < count; i++)
1419 if (vectors[i] > msix->msix_alloc)
1423 * Make sure there aren't any holes in the vectors to be used.
1424 * It's a big pain to support it, and it doesn't really make
1425 * sense anyway. Also, at least one vector must be used.
1427 used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK |
1429 for (i = 0; i < count; i++)
1430 if (vectors[i] != 0)
1431 used[vectors[i] - 1] = 1;
1432 for (i = 0; i < msix->msix_alloc - 1; i++)
1433 if (used[i] == 0 && used[i + 1] == 1) {
1434 free(used, M_DEVBUF);
1438 free(used, M_DEVBUF);
1442 /* Make sure none of the resources are allocated. */
1443 for (i = 0; i < msix->msix_table_len; i++) {
1444 if (msix->msix_table[i].mte_vector == 0)
1446 if (msix->msix_table[i].mte_handlers > 0)
1448 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1449 KASSERT(rle != NULL, ("missing resource"));
1450 if (rle->res != NULL)
1454 /* Free the existing resource list entries. */
1455 for (i = 0; i < msix->msix_table_len; i++) {
1456 if (msix->msix_table[i].mte_vector == 0)
1458 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1462 * Build the new virtual table keeping track of which vectors are
1465 free(msix->msix_table, M_DEVBUF);
1466 msix->msix_table = malloc(sizeof(struct msix_table_entry) * count,
1467 M_DEVBUF, M_WAITOK | M_ZERO);
1468 for (i = 0; i < count; i++)
1469 msix->msix_table[i].mte_vector = vectors[i];
1470 msix->msix_table_len = count;
1472 /* Free any unused IRQs and resize the vectors array if necessary. */
1473 j = msix->msix_alloc - 1;
1475 struct msix_vector *vec;
1477 while (used[j] == 0) {
1478 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1479 msix->msix_vectors[j].mv_irq);
1482 vec = malloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF,
1484 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
1486 free(msix->msix_vectors, M_DEVBUF);
1487 msix->msix_vectors = vec;
1488 msix->msix_alloc = j + 1;
1490 free(used, M_DEVBUF);
1492 /* Map the IRQs onto the rids. */
1493 for (i = 0; i < count; i++) {
1494 if (vectors[i] == 0)
1496 irq = msix->msix_vectors[vectors[i]].mv_irq;
1497 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1502 device_printf(child, "Remapped MSI-X IRQs as: ");
1503 for (i = 0; i < count; i++) {
1506 if (vectors[i] == 0)
1510 msix->msix_vectors[vectors[i]].mv_irq);
1519 pci_release_msix(device_t dev, device_t child)
1521 struct pci_devinfo *dinfo = device_get_ivars(child);
1522 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1523 struct resource_list_entry *rle;
1526 /* Do we have any messages to release? */
1527 if (msix->msix_alloc == 0)
1530 /* Make sure none of the resources are allocated. */
1531 for (i = 0; i < msix->msix_table_len; i++) {
1532 if (msix->msix_table[i].mte_vector == 0)
1534 if (msix->msix_table[i].mte_handlers > 0)
1536 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1537 KASSERT(rle != NULL, ("missing resource"));
1538 if (rle->res != NULL)
1542 /* Update control register to disable MSI-X. */
1543 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1544 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
1545 msix->msix_ctrl, 2);
1547 /* Free the resource list entries. */
1548 for (i = 0; i < msix->msix_table_len; i++) {
1549 if (msix->msix_table[i].mte_vector == 0)
1551 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1553 free(msix->msix_table, M_DEVBUF);
1554 msix->msix_table_len = 0;
1556 /* Release the IRQs. */
1557 for (i = 0; i < msix->msix_alloc; i++)
1558 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1559 msix->msix_vectors[i].mv_irq);
1560 free(msix->msix_vectors, M_DEVBUF);
1561 msix->msix_alloc = 0;
1566 * Return the max supported MSI-X messages this device supports.
1567 * Basically, assuming the MD code can alloc messages, this function
1568 * should return the maximum value that pci_alloc_msix() can return.
1569 * Thus, it is subject to the tunables, etc.
1572 pci_msix_count_method(device_t dev, device_t child)
1574 struct pci_devinfo *dinfo = device_get_ivars(child);
1575 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1577 if (pci_do_msix && msix->msix_location != 0)
1578 return (msix->msix_msgnum);
1583 * HyperTransport MSI mapping control
1586 pci_ht_map_msi(device_t dev, uint64_t addr)
1588 struct pci_devinfo *dinfo = device_get_ivars(dev);
1589 struct pcicfg_ht *ht = &dinfo->cfg.ht;
1594 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
1595 ht->ht_msiaddr >> 20 == addr >> 20) {
1596 /* Enable MSI -> HT mapping. */
1597 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1598 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1602 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
1603 /* Disable MSI -> HT mapping. */
1604 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
1605 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1611 pci_get_max_read_req(device_t dev)
1616 if (pci_find_cap(dev, PCIY_EXPRESS, &cap) != 0)
1618 val = pci_read_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, 2);
1619 val &= PCIM_EXP_CTL_MAX_READ_REQUEST;
1621 return (1 << (val + 7));
1625 pci_set_max_read_req(device_t dev, int size)
1630 if (pci_find_cap(dev, PCIY_EXPRESS, &cap) != 0)
1636 size = (1 << (fls(size) - 1));
1637 val = pci_read_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, 2);
1638 val &= ~PCIM_EXP_CTL_MAX_READ_REQUEST;
1639 val |= (fls(size) - 8) << 12;
1640 pci_write_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, val, 2);
1645 * Support for MSI message signalled interrupts.
1648 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
1650 struct pci_devinfo *dinfo = device_get_ivars(dev);
1651 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1653 /* Write data and address values. */
1654 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1655 address & 0xffffffff, 4);
1656 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1657 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1659 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1662 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1665 /* Enable MSI in the control register. */
1666 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1667 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1670 /* Enable MSI -> HT mapping. */
1671 pci_ht_map_msi(dev, address);
1675 pci_disable_msi(device_t dev)
1677 struct pci_devinfo *dinfo = device_get_ivars(dev);
1678 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1680 /* Disable MSI -> HT mapping. */
1681 pci_ht_map_msi(dev, 0);
1683 /* Disable MSI in the control register. */
1684 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1685 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1690 * Restore MSI registers during resume. If MSI is enabled then
1691 * restore the data and address registers in addition to the control
1695 pci_resume_msi(device_t dev)
1697 struct pci_devinfo *dinfo = device_get_ivars(dev);
1698 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1702 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1703 address = msi->msi_addr;
1704 data = msi->msi_data;
1705 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1706 address & 0xffffffff, 4);
1707 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1708 pci_write_config(dev, msi->msi_location +
1709 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1710 pci_write_config(dev, msi->msi_location +
1711 PCIR_MSI_DATA_64BIT, data, 2);
1713 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1716 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1721 pci_remap_intr_method(device_t bus, device_t dev, u_int irq)
1723 struct pci_devinfo *dinfo = device_get_ivars(dev);
1724 pcicfgregs *cfg = &dinfo->cfg;
1725 struct resource_list_entry *rle;
1726 struct msix_table_entry *mte;
1727 struct msix_vector *mv;
1733 * Handle MSI first. We try to find this IRQ among our list
1734 * of MSI IRQs. If we find it, we request updated address and
1735 * data registers and apply the results.
1737 if (cfg->msi.msi_alloc > 0) {
1739 /* If we don't have any active handlers, nothing to do. */
1740 if (cfg->msi.msi_handlers == 0)
1742 for (i = 0; i < cfg->msi.msi_alloc; i++) {
1743 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
1745 if (rle->start == irq) {
1746 error = PCIB_MAP_MSI(device_get_parent(bus),
1747 dev, irq, &addr, &data);
1750 pci_disable_msi(dev);
1751 dinfo->cfg.msi.msi_addr = addr;
1752 dinfo->cfg.msi.msi_data = data;
1753 pci_enable_msi(dev, addr, data);
1761 * For MSI-X, we check to see if we have this IRQ. If we do,
1762 * we request the updated mapping info. If that works, we go
1763 * through all the slots that use this IRQ and update them.
1765 if (cfg->msix.msix_alloc > 0) {
1766 for (i = 0; i < cfg->msix.msix_alloc; i++) {
1767 mv = &cfg->msix.msix_vectors[i];
1768 if (mv->mv_irq == irq) {
1769 error = PCIB_MAP_MSI(device_get_parent(bus),
1770 dev, irq, &addr, &data);
1773 mv->mv_address = addr;
1775 for (j = 0; j < cfg->msix.msix_table_len; j++) {
1776 mte = &cfg->msix.msix_table[j];
1777 if (mte->mte_vector != i + 1)
1779 if (mte->mte_handlers == 0)
1781 pci_mask_msix(dev, j);
1782 pci_enable_msix(dev, j, addr, data);
1783 pci_unmask_msix(dev, j);
1794 * Returns true if the specified device is blacklisted because MSI
1798 pci_msi_device_blacklisted(device_t dev)
1800 struct pci_quirk *q;
1802 if (!pci_honor_msi_blacklist)
1805 for (q = &pci_quirks[0]; q->devid; q++) {
1806 if (q->devid == pci_get_devid(dev) &&
1807 q->type == PCI_QUIRK_DISABLE_MSI)
1814 * Returns true if a specified chipset supports MSI when it is
1815 * emulated hardware in a virtual machine.
1818 pci_msi_vm_chipset(device_t dev)
1820 struct pci_quirk *q;
1822 for (q = &pci_quirks[0]; q->devid; q++) {
1823 if (q->devid == pci_get_devid(dev) &&
1824 q->type == PCI_QUIRK_ENABLE_MSI_VM)
1831 * Determine if MSI is blacklisted globally on this sytem. Currently,
1832 * we just check for blacklisted chipsets as represented by the
1833 * host-PCI bridge at device 0:0:0. In the future, it may become
1834 * necessary to check other system attributes, such as the kenv values
1835 * that give the motherboard manufacturer and model number.
1838 pci_msi_blacklisted(void)
1842 if (!pci_honor_msi_blacklist)
1845 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
1846 if (!(pcie_chipset || pcix_chipset)) {
1847 if (vm_guest != VM_GUEST_NO) {
1848 dev = pci_find_bsf(0, 0, 0);
1850 return (pci_msi_vm_chipset(dev) == 0);
1855 dev = pci_find_bsf(0, 0, 0);
1857 return (pci_msi_device_blacklisted(dev));
1862 * Attempt to allocate *count MSI messages. The actual number allocated is
1863 * returned in *count. After this function returns, each message will be
1864 * available to the driver as SYS_RES_IRQ resources starting at a rid 1.
1867 pci_alloc_msi_method(device_t dev, device_t child, int *count)
1869 struct pci_devinfo *dinfo = device_get_ivars(child);
1870 pcicfgregs *cfg = &dinfo->cfg;
1871 struct resource_list_entry *rle;
1872 int actual, error, i, irqs[32];
1875 /* Don't let count == 0 get us into trouble. */
1879 /* If rid 0 is allocated, then fail. */
1880 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1881 if (rle != NULL && rle->res != NULL)
1884 /* Already have allocated messages? */
1885 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1888 /* If MSI is blacklisted for this system, fail. */
1889 if (pci_msi_blacklisted())
1892 /* MSI capability present? */
1893 if (cfg->msi.msi_location == 0 || !pci_do_msi)
1897 device_printf(child,
1898 "attempting to allocate %d MSI vectors (%d supported)\n",
1899 *count, cfg->msi.msi_msgnum);
1901 /* Don't ask for more than the device supports. */
1902 actual = min(*count, cfg->msi.msi_msgnum);
1904 /* Don't ask for more than 32 messages. */
1905 actual = min(actual, 32);
1907 /* MSI requires power of 2 number of messages. */
1908 if (!powerof2(actual))
1912 /* Try to allocate N messages. */
1913 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
1925 * We now have N actual messages mapped onto SYS_RES_IRQ
1926 * resources in the irqs[] array, so add new resources
1927 * starting at rid 1.
1929 for (i = 0; i < actual; i++)
1930 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
1931 irqs[i], irqs[i], 1);
1935 device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
1940 * Be fancy and try to print contiguous runs
1941 * of IRQ values as ranges. 'run' is true if
1942 * we are in a range.
1944 device_printf(child, "using IRQs %d", irqs[0]);
1946 for (i = 1; i < actual; i++) {
1948 /* Still in a run? */
1949 if (irqs[i] == irqs[i - 1] + 1) {
1954 /* Finish previous range. */
1956 printf("-%d", irqs[i - 1]);
1960 /* Start new range. */
1961 printf(",%d", irqs[i]);
1964 /* Unfinished range? */
1966 printf("-%d", irqs[actual - 1]);
1967 printf(" for MSI\n");
1971 /* Update control register with actual count. */
1972 ctrl = cfg->msi.msi_ctrl;
1973 ctrl &= ~PCIM_MSICTRL_MME_MASK;
1974 ctrl |= (ffs(actual) - 1) << 4;
1975 cfg->msi.msi_ctrl = ctrl;
1976 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
1978 /* Update counts of alloc'd messages. */
1979 cfg->msi.msi_alloc = actual;
1980 cfg->msi.msi_handlers = 0;
1985 /* Release the MSI messages associated with this device. */
1987 pci_release_msi_method(device_t dev, device_t child)
1989 struct pci_devinfo *dinfo = device_get_ivars(child);
1990 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1991 struct resource_list_entry *rle;
1992 int error, i, irqs[32];
1994 /* Try MSI-X first. */
1995 error = pci_release_msix(dev, child);
1996 if (error != ENODEV)
1999 /* Do we have any messages to release? */
2000 if (msi->msi_alloc == 0)
2002 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
2004 /* Make sure none of the resources are allocated. */
2005 if (msi->msi_handlers > 0)
2007 for (i = 0; i < msi->msi_alloc; i++) {
2008 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2009 KASSERT(rle != NULL, ("missing MSI resource"));
2010 if (rle->res != NULL)
2012 irqs[i] = rle->start;
2015 /* Update control register with 0 count. */
2016 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
2017 ("%s: MSI still enabled", __func__));
2018 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
2019 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2022 /* Release the messages. */
2023 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
2024 for (i = 0; i < msi->msi_alloc; i++)
2025 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2027 /* Update alloc count. */
2035 * Return the max supported MSI messages this device supports.
2036 * Basically, assuming the MD code can alloc messages, this function
2037 * should return the maximum value that pci_alloc_msi() can return.
2038 * Thus, it is subject to the tunables, etc.
2041 pci_msi_count_method(device_t dev, device_t child)
2043 struct pci_devinfo *dinfo = device_get_ivars(child);
2044 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2046 if (pci_do_msi && msi->msi_location != 0)
2047 return (msi->msi_msgnum);
2051 /* free pcicfgregs structure and all depending data structures */
2054 pci_freecfg(struct pci_devinfo *dinfo)
2056 struct devlist *devlist_head;
2059 devlist_head = &pci_devq;
2061 if (dinfo->cfg.vpd.vpd_reg) {
2062 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2063 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2064 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2065 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2066 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2067 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2068 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2070 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2071 free(dinfo, M_DEVBUF);
2073 /* increment the generation count */
2076 /* we're losing one device */
2082 * PCI power manangement
2085 pci_set_powerstate_method(device_t dev, device_t child, int state)
2087 struct pci_devinfo *dinfo = device_get_ivars(child);
2088 pcicfgregs *cfg = &dinfo->cfg;
2090 int result, oldstate, highest, delay;
2092 if (cfg->pp.pp_cap == 0)
2093 return (EOPNOTSUPP);
2096 * Optimize a no state change request away. While it would be OK to
2097 * write to the hardware in theory, some devices have shown odd
2098 * behavior when going from D3 -> D3.
2100 oldstate = pci_get_powerstate(child);
2101 if (oldstate == state)
2105 * The PCI power management specification states that after a state
2106 * transition between PCI power states, system software must
2107 * guarantee a minimal delay before the function accesses the device.
2108 * Compute the worst case delay that we need to guarantee before we
2109 * access the device. Many devices will be responsive much more
2110 * quickly than this delay, but there are some that don't respond
2111 * instantly to state changes. Transitions to/from D3 state require
2112 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2113 * is done below with DELAY rather than a sleeper function because
2114 * this function can be called from contexts where we cannot sleep.
2116 highest = (oldstate > state) ? oldstate : state;
2117 if (highest == PCI_POWERSTATE_D3)
2119 else if (highest == PCI_POWERSTATE_D2)
2123 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2124 & ~PCIM_PSTAT_DMASK;
2127 case PCI_POWERSTATE_D0:
2128 status |= PCIM_PSTAT_D0;
2130 case PCI_POWERSTATE_D1:
2131 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2132 return (EOPNOTSUPP);
2133 status |= PCIM_PSTAT_D1;
2135 case PCI_POWERSTATE_D2:
2136 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2137 return (EOPNOTSUPP);
2138 status |= PCIM_PSTAT_D2;
2140 case PCI_POWERSTATE_D3:
2141 status |= PCIM_PSTAT_D3;
2148 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate,
2151 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2158 pci_get_powerstate_method(device_t dev, device_t child)
2160 struct pci_devinfo *dinfo = device_get_ivars(child);
2161 pcicfgregs *cfg = &dinfo->cfg;
2165 if (cfg->pp.pp_cap != 0) {
2166 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2167 switch (status & PCIM_PSTAT_DMASK) {
2169 result = PCI_POWERSTATE_D0;
2172 result = PCI_POWERSTATE_D1;
2175 result = PCI_POWERSTATE_D2;
2178 result = PCI_POWERSTATE_D3;
2181 result = PCI_POWERSTATE_UNKNOWN;
2185 /* No support, device is always at D0 */
2186 result = PCI_POWERSTATE_D0;
2192 * Some convenience functions for PCI device drivers.
2195 static __inline void
2196 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2200 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2202 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2205 static __inline void
2206 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2210 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2212 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2216 pci_enable_busmaster_method(device_t dev, device_t child)
2218 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2223 pci_disable_busmaster_method(device_t dev, device_t child)
2225 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2230 pci_enable_io_method(device_t dev, device_t child, int space)
2235 case SYS_RES_IOPORT:
2236 bit = PCIM_CMD_PORTEN;
2238 case SYS_RES_MEMORY:
2239 bit = PCIM_CMD_MEMEN;
2244 pci_set_command_bit(dev, child, bit);
2249 pci_disable_io_method(device_t dev, device_t child, int space)
2254 case SYS_RES_IOPORT:
2255 bit = PCIM_CMD_PORTEN;
2257 case SYS_RES_MEMORY:
2258 bit = PCIM_CMD_MEMEN;
2263 pci_clear_command_bit(dev, child, bit);
2268 * New style pci driver. Parent device is either a pci-host-bridge or a
2269 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2273 pci_print_verbose(struct pci_devinfo *dinfo)
2277 pcicfgregs *cfg = &dinfo->cfg;
2279 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2280 cfg->vendor, cfg->device, cfg->revid);
2281 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2282 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2283 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2284 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2286 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2287 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2288 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2289 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2290 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2291 if (cfg->intpin > 0)
2292 printf("\tintpin=%c, irq=%d\n",
2293 cfg->intpin +'a' -1, cfg->intline);
2294 if (cfg->pp.pp_cap) {
2297 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2298 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2299 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2300 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2301 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2302 status & PCIM_PSTAT_DMASK);
2304 if (cfg->msi.msi_location) {
2307 ctrl = cfg->msi.msi_ctrl;
2308 printf("\tMSI supports %d message%s%s%s\n",
2309 cfg->msi.msi_msgnum,
2310 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2311 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2312 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2314 if (cfg->msix.msix_location) {
2315 printf("\tMSI-X supports %d message%s ",
2316 cfg->msix.msix_msgnum,
2317 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2318 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2319 printf("in map 0x%x\n",
2320 cfg->msix.msix_table_bar);
2322 printf("in maps 0x%x and 0x%x\n",
2323 cfg->msix.msix_table_bar,
2324 cfg->msix.msix_pba_bar);
2330 pci_porten(device_t dev)
2332 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0;
2336 pci_memen(device_t dev)
2338 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0;
2342 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp)
2344 pci_addr_t map, testval;
2348 map = pci_read_config(dev, reg, 4);
2349 ln2range = pci_maprange(map);
2351 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
2354 * Disable decoding via the command register before
2355 * determining the BAR's length since we will be placing it in
2358 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2359 pci_write_config(dev, PCIR_COMMAND,
2360 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2);
2363 * Determine the BAR's length by writing all 1's. The bottom
2364 * log_2(size) bits of the BAR will stick as 0 when we read
2367 pci_write_config(dev, reg, 0xffffffff, 4);
2368 testval = pci_read_config(dev, reg, 4);
2369 if (ln2range == 64) {
2370 pci_write_config(dev, reg + 4, 0xffffffff, 4);
2371 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
2375 * Restore the original value of the BAR. We may have reprogrammed
2376 * the BAR of the low-level console device and when booting verbose,
2377 * we need the console device addressable.
2379 pci_write_config(dev, reg, map, 4);
2381 pci_write_config(dev, reg + 4, map >> 32, 4);
2382 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2385 *testvalp = testval;
2389 pci_write_bar(device_t dev, int reg, pci_addr_t base)
2394 map = pci_read_config(dev, reg, 4);
2395 ln2range = pci_maprange(map);
2396 pci_write_config(dev, reg, base, 4);
2398 pci_write_config(dev, reg + 4, base >> 32, 4);
2402 * Add a resource based on a pci map register. Return 1 if the map
2403 * register is a 32bit map register or 2 if it is a 64bit register.
2406 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl,
2407 int force, int prefetch)
2409 pci_addr_t base, map, testval;
2410 pci_addr_t start, end, count;
2411 int barlen, basezero, maprange, mapsize, type;
2413 struct resource *res;
2415 pci_read_bar(dev, reg, &map, &testval);
2416 if (PCI_BAR_MEM(map)) {
2417 type = SYS_RES_MEMORY;
2418 if (map & PCIM_BAR_MEM_PREFETCH)
2421 type = SYS_RES_IOPORT;
2422 mapsize = pci_mapsize(testval);
2423 base = pci_mapbase(map);
2424 #ifdef __PCI_BAR_ZERO_VALID
2427 basezero = base == 0;
2429 maprange = pci_maprange(map);
2430 barlen = maprange == 64 ? 2 : 1;
2433 * For I/O registers, if bottom bit is set, and the next bit up
2434 * isn't clear, we know we have a BAR that doesn't conform to the
2435 * spec, so ignore it. Also, sanity check the size of the data
2436 * areas to the type of memory involved. Memory must be at least
2437 * 16 bytes in size, while I/O ranges must be at least 4.
2439 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2441 if ((type == SYS_RES_MEMORY && mapsize < 4) ||
2442 (type == SYS_RES_IOPORT && mapsize < 2))
2446 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2447 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize);
2448 if (type == SYS_RES_IOPORT && !pci_porten(dev))
2449 printf(", port disabled\n");
2450 else if (type == SYS_RES_MEMORY && !pci_memen(dev))
2451 printf(", memory disabled\n");
2453 printf(", enabled\n");
2457 * If base is 0, then we have problems if this architecture does
2458 * not allow that. It is best to ignore such entries for the
2459 * moment. These will be allocated later if the driver specifically
2460 * requests them. However, some removable busses look better when
2461 * all resources are allocated, so allow '0' to be overriden.
2463 * Similarly treat maps whose values is the same as the test value
2464 * read back. These maps have had all f's written to them by the
2465 * BIOS in an attempt to disable the resources.
2467 if (!force && (basezero || map == testval))
2469 if ((u_long)base != base) {
2471 "pci%d:%d:%d:%d bar %#x too many address bits",
2472 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev),
2473 pci_get_function(dev), reg);
2478 * This code theoretically does the right thing, but has
2479 * undesirable side effects in some cases where peripherals
2480 * respond oddly to having these bits enabled. Let the user
2481 * be able to turn them off (since pci_enable_io_modes is 1 by
2484 if (pci_enable_io_modes) {
2485 /* Turn on resources that have been left off by a lazy BIOS */
2486 if (type == SYS_RES_IOPORT && !pci_porten(dev)) {
2487 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2488 cmd |= PCIM_CMD_PORTEN;
2489 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2491 if (type == SYS_RES_MEMORY && !pci_memen(dev)) {
2492 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2493 cmd |= PCIM_CMD_MEMEN;
2494 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2497 if (type == SYS_RES_IOPORT && !pci_porten(dev))
2499 if (type == SYS_RES_MEMORY && !pci_memen(dev))
2503 count = (pci_addr_t)1 << mapsize;
2504 if (basezero || base == pci_mapbase(testval)) {
2505 start = 0; /* Let the parent decide. */
2509 end = base + count - 1;
2511 resource_list_add(rl, type, reg, start, end, count);
2514 * Try to allocate the resource for this BAR from our parent
2515 * so that this resource range is already reserved. The
2516 * driver for this device will later inherit this resource in
2517 * pci_alloc_resource().
2519 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count,
2520 prefetch ? RF_PREFETCHABLE : 0);
2523 * If the allocation fails, clear the BAR and delete
2524 * the resource list entry to force
2525 * pci_alloc_resource() to allocate resources from the
2528 resource_list_delete(rl, type, reg);
2531 start = rman_get_start(res);
2532 rman_set_device(res, bus);
2534 pci_write_bar(dev, reg, start);
2539 * For ATA devices we need to decide early what addressing mode to use.
2540 * Legacy demands that the primary and secondary ATA ports sits on the
2541 * same addresses that old ISA hardware did. This dictates that we use
2542 * those addresses and ignore the BAR's if we cannot set PCI native
2546 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force,
2547 uint32_t prefetchmask)
2550 int rid, type, progif;
2552 /* if this device supports PCI native addressing use it */
2553 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2554 if ((progif & 0x8a) == 0x8a) {
2555 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2556 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
2557 printf("Trying ATA native PCI addressing mode\n");
2558 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2562 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2563 type = SYS_RES_IOPORT;
2564 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
2565 pci_add_map(bus, dev, PCIR_BAR(0), rl, force,
2566 prefetchmask & (1 << 0));
2567 pci_add_map(bus, dev, PCIR_BAR(1), rl, force,
2568 prefetchmask & (1 << 1));
2571 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
2572 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7,
2574 rman_set_device(r, bus);
2576 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
2577 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6,
2579 rman_set_device(r, bus);
2581 if (progif & PCIP_STORAGE_IDE_MODESEC) {
2582 pci_add_map(bus, dev, PCIR_BAR(2), rl, force,
2583 prefetchmask & (1 << 2));
2584 pci_add_map(bus, dev, PCIR_BAR(3), rl, force,
2585 prefetchmask & (1 << 3));
2588 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
2589 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177,
2591 rman_set_device(r, bus);
2593 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
2594 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376,
2596 rman_set_device(r, bus);
2598 pci_add_map(bus, dev, PCIR_BAR(4), rl, force,
2599 prefetchmask & (1 << 4));
2600 pci_add_map(bus, dev, PCIR_BAR(5), rl, force,
2601 prefetchmask & (1 << 5));
2605 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
2607 struct pci_devinfo *dinfo = device_get_ivars(dev);
2608 pcicfgregs *cfg = &dinfo->cfg;
2609 char tunable_name[64];
2612 /* Has to have an intpin to have an interrupt. */
2613 if (cfg->intpin == 0)
2616 /* Let the user override the IRQ with a tunable. */
2617 irq = PCI_INVALID_IRQ;
2618 snprintf(tunable_name, sizeof(tunable_name),
2619 "hw.pci%d.%d.%d.INT%c.irq",
2620 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
2621 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
2622 irq = PCI_INVALID_IRQ;
2625 * If we didn't get an IRQ via the tunable, then we either use the
2626 * IRQ value in the intline register or we ask the bus to route an
2627 * interrupt for us. If force_route is true, then we only use the
2628 * value in the intline register if the bus was unable to assign an
2631 if (!PCI_INTERRUPT_VALID(irq)) {
2632 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
2633 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
2634 if (!PCI_INTERRUPT_VALID(irq))
2638 /* If after all that we don't have an IRQ, just bail. */
2639 if (!PCI_INTERRUPT_VALID(irq))
2642 /* Update the config register if it changed. */
2643 if (irq != cfg->intline) {
2645 pci_write_config(dev, PCIR_INTLINE, irq, 1);
2648 /* Add this IRQ as rid 0 interrupt resource. */
2649 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
2652 /* Perform early OHCI takeover from SMM. */
2654 ohci_early_takeover(device_t self)
2656 struct resource *res;
2662 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
2666 ctl = bus_read_4(res, OHCI_CONTROL);
2667 if (ctl & OHCI_IR) {
2669 printf("ohci early: "
2670 "SMM active, request owner change\n");
2671 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR);
2672 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) {
2674 ctl = bus_read_4(res, OHCI_CONTROL);
2676 if (ctl & OHCI_IR) {
2678 printf("ohci early: "
2679 "SMM does not respond, resetting\n");
2680 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET);
2682 /* Disable interrupts */
2683 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
2686 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
2689 /* Perform early UHCI takeover from SMM. */
2691 uhci_early_takeover(device_t self)
2693 struct resource *res;
2697 * Set the PIRQD enable bit and switch off all the others. We don't
2698 * want legacy support to interfere with us XXX Does this also mean
2699 * that the BIOS won't touch the keyboard anymore if it is connected
2700 * to the ports of the root hub?
2702 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2);
2704 /* Disable interrupts */
2705 rid = PCI_UHCI_BASE_REG;
2706 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE);
2708 bus_write_2(res, UHCI_INTR, 0);
2709 bus_release_resource(self, SYS_RES_IOPORT, rid, res);
2713 /* Perform early EHCI takeover from SMM. */
2715 ehci_early_takeover(device_t self)
2717 struct resource *res;
2727 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
2731 cparams = bus_read_4(res, EHCI_HCCPARAMS);
2733 /* Synchronise with the BIOS if it owns the controller. */
2734 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0;
2735 eecp = EHCI_EECP_NEXT(eec)) {
2736 eec = pci_read_config(self, eecp, 4);
2737 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) {
2740 bios_sem = pci_read_config(self, eecp +
2741 EHCI_LEGSUP_BIOS_SEM, 1);
2742 if (bios_sem == 0) {
2746 printf("ehci early: "
2747 "SMM active, request owner change\n");
2749 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1);
2751 for (i = 0; (i < 100) && (bios_sem != 0); i++) {
2753 bios_sem = pci_read_config(self, eecp +
2754 EHCI_LEGSUP_BIOS_SEM, 1);
2757 if (bios_sem != 0) {
2759 printf("ehci early: "
2760 "SMM does not respond\n");
2762 /* Disable interrupts */
2763 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION));
2764 bus_write_4(res, offs + EHCI_USBINTR, 0);
2766 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
2770 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask)
2772 struct pci_devinfo *dinfo = device_get_ivars(dev);
2773 pcicfgregs *cfg = &dinfo->cfg;
2774 struct resource_list *rl = &dinfo->resources;
2775 struct pci_quirk *q;
2778 /* ATA devices needs special map treatment */
2779 if ((pci_get_class(dev) == PCIC_STORAGE) &&
2780 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
2781 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
2782 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
2783 !pci_read_config(dev, PCIR_BAR(2), 4))) )
2784 pci_ata_maps(bus, dev, rl, force, prefetchmask);
2786 for (i = 0; i < cfg->nummaps;)
2787 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force,
2788 prefetchmask & (1 << i));
2791 * Add additional, quirked resources.
2793 for (q = &pci_quirks[0]; q->devid; q++) {
2794 if (q->devid == ((cfg->device << 16) | cfg->vendor)
2795 && q->type == PCI_QUIRK_MAP_REG)
2796 pci_add_map(bus, dev, q->arg1, rl, force, 0);
2799 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2800 #ifdef __PCI_REROUTE_INTERRUPT
2802 * Try to re-route interrupts. Sometimes the BIOS or
2803 * firmware may leave bogus values in these registers.
2804 * If the re-route fails, then just stick with what we
2807 pci_assign_interrupt(bus, dev, 1);
2809 pci_assign_interrupt(bus, dev, 0);
2813 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS &&
2814 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) {
2815 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI)
2816 ehci_early_takeover(dev);
2817 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI)
2818 ohci_early_takeover(dev);
2819 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI)
2820 uhci_early_takeover(dev);
2825 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
2827 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
2828 device_t pcib = device_get_parent(dev);
2829 struct pci_devinfo *dinfo;
2831 int s, f, pcifunchigh;
2834 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
2835 ("dinfo_size too small"));
2836 maxslots = PCIB_MAXSLOTS(pcib);
2837 for (s = 0; s <= maxslots; s++) {
2841 hdrtype = REG(PCIR_HDRTYPE, 1);
2842 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
2844 if (hdrtype & PCIM_MFDEV)
2845 pcifunchigh = PCI_FUNCMAX;
2846 for (f = 0; f <= pcifunchigh; f++) {
2847 dinfo = pci_read_device(pcib, domain, busno, s, f,
2849 if (dinfo != NULL) {
2850 pci_add_child(dev, dinfo);
2858 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
2860 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
2861 device_set_ivars(dinfo->cfg.dev, dinfo);
2862 resource_list_init(&dinfo->resources);
2863 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
2864 pci_cfg_restore(dinfo->cfg.dev, dinfo);
2865 pci_print_verbose(dinfo);
2866 pci_add_resources(bus, dinfo->cfg.dev, 0, 0);
2870 pci_probe(device_t dev)
2873 device_set_desc(dev, "PCI bus");
2875 /* Allow other subclasses to override this driver. */
2876 return (BUS_PROBE_GENERIC);
2880 pci_attach(device_t dev)
2885 * Since there can be multiple independantly numbered PCI
2886 * busses on systems with multiple PCI domains, we can't use
2887 * the unit number to decide which bus we are probing. We ask
2888 * the parent pcib what our domain and bus numbers are.
2890 domain = pcib_get_domain(dev);
2891 busno = pcib_get_bus(dev);
2893 device_printf(dev, "domain=%d, physical bus=%d\n",
2895 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
2896 return (bus_generic_attach(dev));
2900 pci_suspend(device_t dev)
2902 int dstate, error, i, numdevs;
2903 device_t acpi_dev, child, *devlist;
2904 struct pci_devinfo *dinfo;
2907 * Save the PCI configuration space for each child and set the
2908 * device in the appropriate power state for this sleep state.
2911 if (pci_do_power_resume)
2912 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2913 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0)
2915 for (i = 0; i < numdevs; i++) {
2917 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2918 pci_cfg_save(child, dinfo, 0);
2921 /* Suspend devices before potentially powering them down. */
2922 error = bus_generic_suspend(dev);
2924 free(devlist, M_TEMP);
2929 * Always set the device to D3. If ACPI suggests a different
2930 * power state, use it instead. If ACPI is not present, the
2931 * firmware is responsible for managing device power. Skip
2932 * children who aren't attached since they are powered down
2933 * separately. Only manage type 0 devices for now.
2935 for (i = 0; acpi_dev && i < numdevs; i++) {
2937 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2938 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) {
2939 dstate = PCI_POWERSTATE_D3;
2940 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate);
2941 pci_set_powerstate(child, dstate);
2944 free(devlist, M_TEMP);
2949 pci_resume(device_t dev)
2951 int i, numdevs, error;
2952 device_t acpi_dev, child, *devlist;
2953 struct pci_devinfo *dinfo;
2956 * Set each child to D0 and restore its PCI configuration space.
2959 if (pci_do_power_resume)
2960 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2961 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0)
2963 for (i = 0; i < numdevs; i++) {
2965 * Notify ACPI we're going to D0 but ignore the result. If
2966 * ACPI is not present, the firmware is responsible for
2967 * managing device power. Only manage type 0 devices for now.
2970 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2971 if (acpi_dev && device_is_attached(child) &&
2972 dinfo->cfg.hdrtype == 0) {
2973 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL);
2974 pci_set_powerstate(child, PCI_POWERSTATE_D0);
2977 /* Now the device is powered up, restore its config space. */
2978 pci_cfg_restore(child, dinfo);
2980 free(devlist, M_TEMP);
2981 return (bus_generic_resume(dev));
2985 pci_load_vendor_data(void)
2987 caddr_t vendordata, info;
2989 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
2990 info = preload_search_info(vendordata, MODINFO_ADDR);
2991 pci_vendordata = *(char **)info;
2992 info = preload_search_info(vendordata, MODINFO_SIZE);
2993 pci_vendordata_size = *(size_t *)info;
2994 /* terminate the database */
2995 pci_vendordata[pci_vendordata_size] = '\n';
3000 pci_driver_added(device_t dev, driver_t *driver)
3005 struct pci_devinfo *dinfo;
3009 device_printf(dev, "driver added\n");
3010 DEVICE_IDENTIFY(driver, dev);
3011 if (device_get_children(dev, &devlist, &numdevs) != 0)
3013 for (i = 0; i < numdevs; i++) {
3015 if (device_get_state(child) != DS_NOTPRESENT)
3017 dinfo = device_get_ivars(child);
3018 pci_print_verbose(dinfo);
3020 pci_printf(&dinfo->cfg, "reprobing on driver added\n");
3021 pci_cfg_restore(child, dinfo);
3022 if (device_probe_and_attach(child) != 0)
3023 pci_cfg_save(child, dinfo, 1);
3025 free(devlist, M_TEMP);
3029 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
3030 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep)
3032 struct pci_devinfo *dinfo;
3033 struct msix_table_entry *mte;
3034 struct msix_vector *mv;
3040 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr,
3045 /* If this is not a direct child, just bail out. */
3046 if (device_get_parent(child) != dev) {
3051 rid = rman_get_rid(irq);
3053 /* Make sure that INTx is enabled */
3054 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3057 * Check to see if the interrupt is MSI or MSI-X.
3058 * Ask our parent to map the MSI and give
3059 * us the address and data register values.
3060 * If we fail for some reason, teardown the
3061 * interrupt handler.
3063 dinfo = device_get_ivars(child);
3064 if (dinfo->cfg.msi.msi_alloc > 0) {
3065 if (dinfo->cfg.msi.msi_addr == 0) {
3066 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
3067 ("MSI has handlers, but vectors not mapped"));
3068 error = PCIB_MAP_MSI(device_get_parent(dev),
3069 child, rman_get_start(irq), &addr, &data);
3072 dinfo->cfg.msi.msi_addr = addr;
3073 dinfo->cfg.msi.msi_data = data;
3075 if (dinfo->cfg.msi.msi_handlers == 0)
3076 pci_enable_msi(child, dinfo->cfg.msi.msi_addr,
3077 dinfo->cfg.msi.msi_data);
3078 dinfo->cfg.msi.msi_handlers++;
3080 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3081 ("No MSI or MSI-X interrupts allocated"));
3082 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3083 ("MSI-X index too high"));
3084 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3085 KASSERT(mte->mte_vector != 0, ("no message vector"));
3086 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
3087 KASSERT(mv->mv_irq == rman_get_start(irq),
3089 if (mv->mv_address == 0) {
3090 KASSERT(mte->mte_handlers == 0,
3091 ("MSI-X table entry has handlers, but vector not mapped"));
3092 error = PCIB_MAP_MSI(device_get_parent(dev),
3093 child, rman_get_start(irq), &addr, &data);
3096 mv->mv_address = addr;
3099 if (mte->mte_handlers == 0) {
3100 pci_enable_msix(child, rid - 1, mv->mv_address,
3102 pci_unmask_msix(child, rid - 1);
3104 mte->mte_handlers++;
3107 /* Make sure that INTx is disabled if we are using MSI/MSIX */
3108 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3111 (void)bus_generic_teardown_intr(dev, child, irq,
3121 pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
3124 struct msix_table_entry *mte;
3125 struct resource_list_entry *rle;
3126 struct pci_devinfo *dinfo;
3129 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
3132 /* If this isn't a direct child, just bail out */
3133 if (device_get_parent(child) != dev)
3134 return(bus_generic_teardown_intr(dev, child, irq, cookie));
3136 rid = rman_get_rid(irq);
3139 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3142 * Check to see if the interrupt is MSI or MSI-X. If so,
3143 * decrement the appropriate handlers count and mask the
3144 * MSI-X message, or disable MSI messages if the count
3147 dinfo = device_get_ivars(child);
3148 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
3149 if (rle->res != irq)
3151 if (dinfo->cfg.msi.msi_alloc > 0) {
3152 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
3153 ("MSI-X index too high"));
3154 if (dinfo->cfg.msi.msi_handlers == 0)
3156 dinfo->cfg.msi.msi_handlers--;
3157 if (dinfo->cfg.msi.msi_handlers == 0)
3158 pci_disable_msi(child);
3160 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3161 ("No MSI or MSI-X interrupts allocated"));
3162 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3163 ("MSI-X index too high"));
3164 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3165 if (mte->mte_handlers == 0)
3167 mte->mte_handlers--;
3168 if (mte->mte_handlers == 0)
3169 pci_mask_msix(child, rid - 1);
3172 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3175 ("%s: generic teardown failed for MSI/MSI-X", __func__));
3180 pci_print_child(device_t dev, device_t child)
3182 struct pci_devinfo *dinfo;
3183 struct resource_list *rl;
3186 dinfo = device_get_ivars(child);
3187 rl = &dinfo->resources;
3189 retval += bus_print_child_header(dev, child);
3191 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
3192 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
3193 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
3194 if (device_get_flags(dev))
3195 retval += printf(" flags %#x", device_get_flags(dev));
3197 retval += printf(" at device %d.%d", pci_get_slot(child),
3198 pci_get_function(child));
3200 retval += bus_print_child_footer(dev, child);
3210 } pci_nomatch_tab[] = {
3211 {PCIC_OLD, -1, "old"},
3212 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
3213 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
3214 {PCIC_STORAGE, -1, "mass storage"},
3215 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
3216 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
3217 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
3218 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
3219 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
3220 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"},
3221 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"},
3222 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"},
3223 {PCIC_NETWORK, -1, "network"},
3224 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
3225 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
3226 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
3227 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
3228 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
3229 {PCIC_DISPLAY, -1, "display"},
3230 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
3231 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
3232 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
3233 {PCIC_MULTIMEDIA, -1, "multimedia"},
3234 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
3235 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
3236 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
3237 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"},
3238 {PCIC_MEMORY, -1, "memory"},
3239 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
3240 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
3241 {PCIC_BRIDGE, -1, "bridge"},
3242 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
3243 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
3244 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
3245 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
3246 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
3247 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
3248 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
3249 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
3250 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
3251 {PCIC_SIMPLECOMM, -1, "simple comms"},
3252 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
3253 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
3254 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
3255 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
3256 {PCIC_BASEPERIPH, -1, "base peripheral"},
3257 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
3258 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
3259 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
3260 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
3261 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
3262 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"},
3263 {PCIC_INPUTDEV, -1, "input device"},
3264 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
3265 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
3266 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
3267 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
3268 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
3269 {PCIC_DOCKING, -1, "docking station"},
3270 {PCIC_PROCESSOR, -1, "processor"},
3271 {PCIC_SERIALBUS, -1, "serial bus"},
3272 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
3273 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
3274 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
3275 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
3276 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
3277 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
3278 {PCIC_WIRELESS, -1, "wireless controller"},
3279 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
3280 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
3281 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
3282 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
3283 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
3284 {PCIC_SATCOM, -1, "satellite communication"},
3285 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
3286 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
3287 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
3288 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
3289 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
3290 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
3291 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
3292 {PCIC_DASP, -1, "dasp"},
3293 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
3298 pci_probe_nomatch(device_t dev, device_t child)
3301 char *cp, *scp, *device;
3304 * Look for a listing for this device in a loaded device database.
3306 if ((device = pci_describe_device(child)) != NULL) {
3307 device_printf(dev, "<%s>", device);
3308 free(device, M_DEVBUF);
3311 * Scan the class/subclass descriptions for a general
3316 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
3317 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
3318 if (pci_nomatch_tab[i].subclass == -1) {
3319 cp = pci_nomatch_tab[i].desc;
3320 } else if (pci_nomatch_tab[i].subclass ==
3321 pci_get_subclass(child)) {
3322 scp = pci_nomatch_tab[i].desc;
3326 device_printf(dev, "<%s%s%s>",
3328 ((cp != NULL) && (scp != NULL)) ? ", " : "",
3331 printf(" at device %d.%d (no driver attached)\n",
3332 pci_get_slot(child), pci_get_function(child));
3333 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1);
3338 * Parse the PCI device database, if loaded, and return a pointer to a
3339 * description of the device.
3341 * The database is flat text formatted as follows:
3343 * Any line not in a valid format is ignored.
3344 * Lines are terminated with newline '\n' characters.
3346 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
3349 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
3350 * - devices cannot be listed without a corresponding VENDOR line.
3351 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
3352 * another TAB, then the device name.
3356 * Assuming (ptr) points to the beginning of a line in the database,
3357 * return the vendor or device and description of the next entry.
3358 * The value of (vendor) or (device) inappropriate for the entry type
3359 * is set to -1. Returns nonzero at the end of the database.
3361 * Note that this is slightly unrobust in the face of corrupt data;
3362 * we attempt to safeguard against this by spamming the end of the
3363 * database with a newline when we initialise.
3366 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
3375 left = pci_vendordata_size - (cp - pci_vendordata);
3383 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
3387 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
3390 /* skip to next line */
3391 while (*cp != '\n' && left > 0) {
3400 /* skip to next line */
3401 while (*cp != '\n' && left > 0) {
3405 if (*cp == '\n' && left > 0)
3412 pci_describe_device(device_t dev)
3415 char *desc, *vp, *dp, *line;
3417 desc = vp = dp = NULL;
3420 * If we have no vendor data, we can't do anything.
3422 if (pci_vendordata == NULL)
3426 * Scan the vendor data looking for this device
3428 line = pci_vendordata;
3429 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3432 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
3434 if (vendor == pci_get_vendor(dev))
3437 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3440 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
3448 if (device == pci_get_device(dev))
3452 snprintf(dp, 80, "0x%x", pci_get_device(dev));
3453 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
3455 sprintf(desc, "%s, %s", vp, dp);
3465 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
3467 struct pci_devinfo *dinfo;
3470 dinfo = device_get_ivars(child);
3474 case PCI_IVAR_ETHADDR:
3476 * The generic accessor doesn't deal with failure, so
3477 * we set the return value, then return an error.
3479 *((uint8_t **) result) = NULL;
3481 case PCI_IVAR_SUBVENDOR:
3482 *result = cfg->subvendor;
3484 case PCI_IVAR_SUBDEVICE:
3485 *result = cfg->subdevice;
3487 case PCI_IVAR_VENDOR:
3488 *result = cfg->vendor;
3490 case PCI_IVAR_DEVICE:
3491 *result = cfg->device;
3493 case PCI_IVAR_DEVID:
3494 *result = (cfg->device << 16) | cfg->vendor;
3496 case PCI_IVAR_CLASS:
3497 *result = cfg->baseclass;
3499 case PCI_IVAR_SUBCLASS:
3500 *result = cfg->subclass;
3502 case PCI_IVAR_PROGIF:
3503 *result = cfg->progif;
3505 case PCI_IVAR_REVID:
3506 *result = cfg->revid;
3508 case PCI_IVAR_INTPIN:
3509 *result = cfg->intpin;
3512 *result = cfg->intline;
3514 case PCI_IVAR_DOMAIN:
3515 *result = cfg->domain;
3521 *result = cfg->slot;
3523 case PCI_IVAR_FUNCTION:
3524 *result = cfg->func;
3526 case PCI_IVAR_CMDREG:
3527 *result = cfg->cmdreg;
3529 case PCI_IVAR_CACHELNSZ:
3530 *result = cfg->cachelnsz;
3532 case PCI_IVAR_MINGNT:
3533 *result = cfg->mingnt;
3535 case PCI_IVAR_MAXLAT:
3536 *result = cfg->maxlat;
3538 case PCI_IVAR_LATTIMER:
3539 *result = cfg->lattimer;
3548 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
3550 struct pci_devinfo *dinfo;
3552 dinfo = device_get_ivars(child);
3555 case PCI_IVAR_INTPIN:
3556 dinfo->cfg.intpin = value;
3558 case PCI_IVAR_ETHADDR:
3559 case PCI_IVAR_SUBVENDOR:
3560 case PCI_IVAR_SUBDEVICE:
3561 case PCI_IVAR_VENDOR:
3562 case PCI_IVAR_DEVICE:
3563 case PCI_IVAR_DEVID:
3564 case PCI_IVAR_CLASS:
3565 case PCI_IVAR_SUBCLASS:
3566 case PCI_IVAR_PROGIF:
3567 case PCI_IVAR_REVID:
3569 case PCI_IVAR_DOMAIN:
3572 case PCI_IVAR_FUNCTION:
3573 return (EINVAL); /* disallow for now */
3581 #include "opt_ddb.h"
3583 #include <ddb/ddb.h>
3584 #include <sys/cons.h>
3587 * List resources based on pci map registers, used for within ddb
3590 DB_SHOW_COMMAND(pciregs, db_pci_dump)
3592 struct pci_devinfo *dinfo;
3593 struct devlist *devlist_head;
3596 int i, error, none_count;
3599 /* get the head of the device queue */
3600 devlist_head = &pci_devq;
3603 * Go through the list of devices and print out devices
3605 for (error = 0, i = 0,
3606 dinfo = STAILQ_FIRST(devlist_head);
3607 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
3608 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
3610 /* Populate pd_name and pd_unit */
3613 name = device_get_name(dinfo->cfg.dev);
3616 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
3617 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
3618 (name && *name) ? name : "none",
3619 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
3621 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
3622 p->pc_sel.pc_func, (p->pc_class << 16) |
3623 (p->pc_subclass << 8) | p->pc_progif,
3624 (p->pc_subdevice << 16) | p->pc_subvendor,
3625 (p->pc_device << 16) | p->pc_vendor,
3626 p->pc_revid, p->pc_hdr);
3631 static struct resource *
3632 pci_alloc_map(device_t dev, device_t child, int type, int *rid,
3633 u_long start, u_long end, u_long count, u_int flags)
3635 struct pci_devinfo *dinfo = device_get_ivars(child);
3636 struct resource_list *rl = &dinfo->resources;
3637 struct resource_list_entry *rle;
3638 struct resource *res;
3639 pci_addr_t map, testval;
3643 * Weed out the bogons, and figure out how large the BAR/map
3644 * is. Bars that read back 0 here are bogus and unimplemented.
3645 * Note: atapci in legacy mode are special and handled elsewhere
3646 * in the code. If you have a atapci device in legacy mode and
3647 * it fails here, that other code is broken.
3650 pci_read_bar(child, *rid, &map, &testval);
3652 /* Ignore a BAR with a base of 0. */
3653 if (pci_mapbase(testval) == 0)
3656 if (PCI_BAR_MEM(testval)) {
3657 if (type != SYS_RES_MEMORY) {
3660 "child %s requested type %d for rid %#x,"
3661 " but the BAR says it is an memio\n",
3662 device_get_nameunit(child), type, *rid);
3666 if (type != SYS_RES_IOPORT) {
3669 "child %s requested type %d for rid %#x,"
3670 " but the BAR says it is an ioport\n",
3671 device_get_nameunit(child), type, *rid);
3677 * For real BARs, we need to override the size that
3678 * the driver requests, because that's what the BAR
3679 * actually uses and we would otherwise have a
3680 * situation where we might allocate the excess to
3681 * another driver, which won't work.
3683 mapsize = pci_mapsize(testval);
3684 count = (pci_addr_t)1 << mapsize;
3685 if (RF_ALIGNMENT(flags) < mapsize)
3686 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
3687 if (PCI_BAR_MEM(testval) && (testval & PCIM_BAR_MEM_PREFETCH))
3688 flags |= RF_PREFETCHABLE;
3691 * Allocate enough resource, and then write back the
3692 * appropriate bar for that resource.
3694 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
3695 start, end, count, flags & ~RF_ACTIVE);
3697 device_printf(child,
3698 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
3699 count, *rid, type, start, end);
3702 rman_set_device(res, dev);
3703 resource_list_add(rl, type, *rid, start, end, count);
3704 rle = resource_list_find(rl, type, *rid);
3706 panic("pci_alloc_map: unexpectedly can't find resource.");
3708 rle->start = rman_get_start(res);
3709 rle->end = rman_get_end(res);
3712 device_printf(child,
3713 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
3714 count, *rid, type, rman_get_start(res));
3715 map = rman_get_start(res);
3716 pci_write_bar(child, *rid, map);
3723 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
3724 u_long start, u_long end, u_long count, u_int flags)
3726 struct pci_devinfo *dinfo = device_get_ivars(child);
3727 struct resource_list *rl = &dinfo->resources;
3728 struct resource_list_entry *rle;
3729 struct resource *res;
3730 pcicfgregs *cfg = &dinfo->cfg;
3732 if (device_get_parent(child) != dev)
3733 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
3734 type, rid, start, end, count, flags));
3737 * Perform lazy resource allocation
3742 * Can't alloc legacy interrupt once MSI messages have
3745 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
3746 cfg->msix.msix_alloc > 0))
3750 * If the child device doesn't have an interrupt
3751 * routed and is deserving of an interrupt, try to
3754 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
3756 pci_assign_interrupt(dev, child, 0);
3758 case SYS_RES_IOPORT:
3759 case SYS_RES_MEMORY:
3760 /* Allocate resources for this BAR if needed. */
3761 rle = resource_list_find(rl, type, *rid);
3763 res = pci_alloc_map(dev, child, type, rid, start, end,
3767 rle = resource_list_find(rl, type, *rid);
3771 * If the resource belongs to the bus, then give it to
3772 * the child. We need to activate it if requested
3773 * since the bus always allocates inactive resources.
3775 if (rle != NULL && rle->res != NULL &&
3776 rman_get_device(rle->res) == dev) {
3778 device_printf(child,
3779 "Reserved %#lx bytes for rid %#x type %d at %#lx\n",
3780 rman_get_size(rle->res), *rid, type,
3781 rman_get_start(rle->res));
3782 rman_set_device(rle->res, child);
3783 if ((flags & RF_ACTIVE) &&
3784 bus_activate_resource(child, type, *rid,
3790 return (resource_list_alloc(rl, dev, child, type, rid,
3791 start, end, count, flags));
3795 pci_release_resource(device_t dev, device_t child, int type, int rid,
3800 if (device_get_parent(child) != dev)
3801 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
3805 * For BARs we don't actually want to release the resource.
3806 * Instead, we deactivate the resource if needed and then give
3807 * ownership of the BAR back to the bus.
3810 case SYS_RES_IOPORT:
3811 case SYS_RES_MEMORY:
3812 if (rman_get_device(r) != child)
3814 if (rman_get_flags(r) & RF_ACTIVE) {
3815 error = bus_deactivate_resource(child, type, rid, r);
3819 rman_set_device(r, dev);
3822 return (bus_generic_rl_release_resource(dev, child, type, rid, r));
3826 pci_activate_resource(device_t dev, device_t child, int type, int rid,
3831 error = bus_generic_activate_resource(dev, child, type, rid, r);
3835 /* Enable decoding in the command register when activating BARs. */
3836 if (device_get_parent(child) == dev) {
3838 case SYS_RES_IOPORT:
3839 case SYS_RES_MEMORY:
3840 error = PCI_ENABLE_IO(dev, child, type);
3848 pci_delete_resource(device_t dev, device_t child, int type, int rid)
3850 struct pci_devinfo *dinfo;
3851 struct resource_list *rl;
3852 struct resource_list_entry *rle;
3854 if (device_get_parent(child) != dev)
3857 dinfo = device_get_ivars(child);
3858 rl = &dinfo->resources;
3859 rle = resource_list_find(rl, type, rid);
3864 if (rman_get_device(rle->res) != dev ||
3865 rman_get_flags(rle->res) & RF_ACTIVE) {
3866 device_printf(dev, "delete_resource: "
3867 "Resource still owned by child, oops. "
3868 "(type=%d, rid=%d, addr=%lx)\n",
3869 rle->type, rle->rid,
3870 rman_get_start(rle->res));
3874 #ifndef __PCI_BAR_ZERO_VALID
3876 * If this is a BAR, clear the BAR so it stops
3877 * decoding before releasing the resource.
3880 case SYS_RES_IOPORT:
3881 case SYS_RES_MEMORY:
3882 pci_write_bar(child, rid, 0);
3886 bus_release_resource(dev, type, rid, rle->res);
3888 resource_list_delete(rl, type, rid);
3891 struct resource_list *
3892 pci_get_resource_list (device_t dev, device_t child)
3894 struct pci_devinfo *dinfo = device_get_ivars(child);
3896 return (&dinfo->resources);
3900 pci_read_config_method(device_t dev, device_t child, int reg, int width)
3902 struct pci_devinfo *dinfo = device_get_ivars(child);
3903 pcicfgregs *cfg = &dinfo->cfg;
3905 return (PCIB_READ_CONFIG(device_get_parent(dev),
3906 cfg->bus, cfg->slot, cfg->func, reg, width));
3910 pci_write_config_method(device_t dev, device_t child, int reg,
3911 uint32_t val, int width)
3913 struct pci_devinfo *dinfo = device_get_ivars(child);
3914 pcicfgregs *cfg = &dinfo->cfg;
3916 PCIB_WRITE_CONFIG(device_get_parent(dev),
3917 cfg->bus, cfg->slot, cfg->func, reg, val, width);
3921 pci_child_location_str_method(device_t dev, device_t child, char *buf,
3925 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
3926 pci_get_function(child));
3931 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
3934 struct pci_devinfo *dinfo;
3937 dinfo = device_get_ivars(child);
3939 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
3940 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
3941 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
3947 pci_assign_interrupt_method(device_t dev, device_t child)
3949 struct pci_devinfo *dinfo = device_get_ivars(child);
3950 pcicfgregs *cfg = &dinfo->cfg;
3952 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
3957 pci_modevent(module_t mod, int what, void *arg)
3959 static struct cdev *pci_cdev;
3963 STAILQ_INIT(&pci_devq);
3965 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644,
3967 pci_load_vendor_data();
3971 destroy_dev(pci_cdev);
3979 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
3984 * Only do header type 0 devices. Type 1 devices are bridges,
3985 * which we know need special treatment. Type 2 devices are
3986 * cardbus bridges which also require special treatment.
3987 * Other types are unknown, and we err on the side of safety
3990 if (dinfo->cfg.hdrtype != 0)
3994 * Restore the device to full power mode. We must do this
3995 * before we restore the registers because moving from D3 to
3996 * D0 will cause the chip's BARs and some other registers to
3997 * be reset to some unknown power on reset values. Cut down
3998 * the noise on boot by doing nothing if we are already in
4001 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
4002 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4004 for (i = 0; i < dinfo->cfg.nummaps; i++)
4005 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
4006 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
4007 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
4008 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
4009 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
4010 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
4011 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
4012 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
4013 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
4014 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
4015 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
4017 /* Restore MSI and MSI-X configurations if they are present. */
4018 if (dinfo->cfg.msi.msi_location != 0)
4019 pci_resume_msi(dev);
4020 if (dinfo->cfg.msix.msix_location != 0)
4021 pci_resume_msix(dev);
4025 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
4032 * Only do header type 0 devices. Type 1 devices are bridges, which
4033 * we know need special treatment. Type 2 devices are cardbus bridges
4034 * which also require special treatment. Other types are unknown, and
4035 * we err on the side of safety by ignoring them. Powering down
4036 * bridges should not be undertaken lightly.
4038 if (dinfo->cfg.hdrtype != 0)
4040 for (i = 0; i < dinfo->cfg.nummaps; i++)
4041 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
4042 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
4045 * Some drivers apparently write to these registers w/o updating our
4046 * cached copy. No harm happens if we update the copy, so do so here
4047 * so we can restore them. The COMMAND register is modified by the
4048 * bus w/o updating the cache. This should represent the normally
4049 * writable portion of the 'defined' part of type 0 headers. In
4050 * theory we also need to save/restore the PCI capability structures
4051 * we know about, but apart from power we don't know any that are
4054 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
4055 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4056 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
4057 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
4058 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
4059 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
4060 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
4061 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
4062 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
4063 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
4064 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
4065 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
4066 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
4067 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
4068 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
4071 * don't set the state for display devices, base peripherals and
4072 * memory devices since bad things happen when they are powered down.
4073 * We should (a) have drivers that can easily detach and (b) use
4074 * generic drivers for these devices so that some device actually
4075 * attaches. We need to make sure that when we implement (a) we don't
4076 * power the device down on a reattach.
4078 cls = pci_get_class(dev);
4081 switch (pci_do_power_nodriver)
4083 case 0: /* NO powerdown at all */
4085 case 1: /* Conservative about what to power down */
4086 if (cls == PCIC_STORAGE)
4089 case 2: /* Agressive about what to power down */
4090 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
4091 cls == PCIC_BASEPERIPH)
4094 case 3: /* Power down everything */
4098 * PCI spec says we can only go into D3 state from D0 state.
4099 * Transition from D[12] into D0 before going to D3 state.
4101 ps = pci_get_powerstate(dev);
4102 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
4103 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4104 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
4105 pci_set_powerstate(dev, PCI_POWERSTATE_D3);