2 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia.
3 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia.
4 * Copyright (C) 2002 by John Baldwin <jhb@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * Cirrus Logic CD180 -based RISCom/8 board definitions
35 /* Oscillator frequency - 19660.08Mhz / 2 */
36 #define RC_OSCFREQ 9830400
38 #define RC_BRD(s) ((s) == 0 ? 0 : \
39 (((RC_OSCFREQ + (s) / 2) / (s)) + CD180_CTICKS/2) / CD180_CTICKS)
41 /* Riscom/8 board ISA I/O mapping */
42 #define RC_IOMAP(r) ((((r) & 07) << 1) | (((r) & ~07) << 7))
45 #define RC_OUT(sc, addr, value) \
46 bus_space_write_1((sc)->sc_bt, (sc)->sc_bh, RC_IOMAP(addr), (value))
47 #define RC_IN(sc, addr) \
48 bus_space_read_1((sc)->sc_bt, (sc)->sc_bh, RC_IOMAP(addr))
50 /* Riscom on-board registers (mapping assumed) */
51 #define RC_RIREG 0x100 /* Ring Indicator Register (read-only) */
52 #define RC_DTREG 0x100 /* DTR Register (write-only) */
53 #define RC_BSR 0x101 /* Board Status Register (read-only) */
54 #define RC_CTOUT 0x101 /* Clear Timeout (write-only) */
56 /* Board Status Register */
57 #define RC_BSR_TOUT 0x08 /* Timeout */
58 #define RC_BSR_RXINT 0x04 /* Receiver Interrupt */
59 #define RC_BSR_TXINT 0x02 /* Transmitter Interrupt */
60 #define RC_BSR_MOINT 0x01 /* Modem Control Interrupt */
62 /* Interrupt groups */
63 #define RC_MODEMGRP 0x01 /* Modem interrupt group */
64 #define RC_RXGRP 0x02 /* Receiver interrupt group */
65 #define RC_TXGRP 0x04 /* Transmitter interrupt group */
67 /* Priority Interrupt Level definitions */
68 #define RC_PILR_MODEM (0x80 | RC_MODEMGRP)
69 #define RC_PILR_RX (0x80 | RC_RXGRP )
70 #define RC_PILR_TX (0x80 | RC_TXGRP )