2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Networking Software Engineer
45 * This driver is designed to support RealTek's next generation of
46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
51 * with the older 8139 family, however it also supports a special
52 * C+ mode of operation that provides several new performance enhancing
53 * features. These include:
55 * o Descriptor based DMA mechanism. Each descriptor represents
56 * a single packet fragment. Data buffers may be aligned on
61 * o TCP/IP checksum offload for both RX and TX
63 * o High and normal priority transmit DMA rings
65 * o VLAN tag insertion and extraction
67 * o TCP large send (segmentation offload)
69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
70 * programming API is fairly straightforward. The RX filtering, EEPROM
71 * access and PHY access is the same as it is on the older 8139 series
74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
75 * same programming API and feature set as the 8139C+ with the following
76 * differences and additions:
82 * o GMII and TBI ports/registers for interfacing with copper
85 * o RX and TX DMA rings can have up to 1024 descriptors
86 * (the 8139C+ allows a maximum of 64)
88 * o Slight differences in register layout from the 8139C+
90 * The TX start and timer interrupt registers are at different locations
91 * on the 8169 than they are on the 8139C+. Also, the status word in the
92 * RX descriptor has a slightly different bit layout. The 8169 does not
93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
97 * (the 'S' stands for 'single-chip'). These devices have the same
98 * programming API as the older 8169, but also have some vendor-specific
99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
102 * This driver takes advantage of the RX and TX checksum offload and
103 * VLAN tag insertion/extraction features. It also implements TX
104 * interrupt moderation using the timer interrupt registers, which
105 * significantly reduces TX interrupt load. There is also support
106 * for jumbo frames, however the 8169/8169S/8110S can not transmit
107 * jumbo frames larger than 7440, so the max MTU possible with this
108 * driver is 7422 bytes.
111 #ifdef HAVE_KERNEL_OPTION_HEADERS
112 #include "opt_device_polling.h"
115 #include <sys/param.h>
116 #include <sys/endian.h>
117 #include <sys/systm.h>
118 #include <sys/sockio.h>
119 #include <sys/mbuf.h>
120 #include <sys/malloc.h>
121 #include <sys/module.h>
122 #include <sys/kernel.h>
123 #include <sys/socket.h>
124 #include <sys/lock.h>
125 #include <sys/mutex.h>
126 #include <sys/sysctl.h>
127 #include <sys/taskqueue.h>
130 #include <net/if_arp.h>
131 #include <net/ethernet.h>
132 #include <net/if_dl.h>
133 #include <net/if_media.h>
134 #include <net/if_types.h>
135 #include <net/if_vlan_var.h>
139 #include <machine/bus.h>
140 #include <machine/resource.h>
142 #include <sys/rman.h>
144 #include <dev/mii/mii.h>
145 #include <dev/mii/miivar.h>
147 #include <dev/pci/pcireg.h>
148 #include <dev/pci/pcivar.h>
150 #include <pci/if_rlreg.h>
152 MODULE_DEPEND(re, pci, 1, 1, 1);
153 MODULE_DEPEND(re, ether, 1, 1, 1);
154 MODULE_DEPEND(re, miibus, 1, 1, 1);
156 /* "device miibus" required. See GENERIC if you get errors here. */
157 #include "miibus_if.h"
160 static int intr_filter = 0;
161 TUNABLE_INT("hw.re.intr_filter", &intr_filter);
162 static int msi_disable = 0;
163 TUNABLE_INT("hw.re.msi_disable", &msi_disable);
164 static int msix_disable = 0;
165 TUNABLE_INT("hw.re.msix_disable", &msix_disable);
166 static int prefer_iomap = 0;
167 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap);
169 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
172 * Various supported device vendors/types and their names.
174 static const struct rl_type re_devs[] = {
175 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0,
176 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
177 { DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0,
178 "D-Link DGE-530(T) Gigabit Ethernet Adapter" },
179 { RT_VENDORID, RT_DEVICEID_8139, 0,
180 "RealTek 8139C+ 10/100BaseTX" },
181 { RT_VENDORID, RT_DEVICEID_8101E, 0,
182 "RealTek 810xE PCIe 10/100baseTX" },
183 { RT_VENDORID, RT_DEVICEID_8168, 0,
184 "RealTek 8168/8111 B/C/CP/D/DP/E/F PCIe Gigabit Ethernet" },
185 { RT_VENDORID, RT_DEVICEID_8169, 0,
186 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" },
187 { RT_VENDORID, RT_DEVICEID_8169SC, 0,
188 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
189 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0,
190 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" },
191 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0,
192 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" },
193 { USR_VENDORID, USR_DEVICEID_997902, 0,
194 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" }
197 static const struct rl_hwrev re_hwrevs[] = {
198 { RL_HWREV_8139, RL_8139, "", RL_MTU },
199 { RL_HWREV_8139A, RL_8139, "A", RL_MTU },
200 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU },
201 { RL_HWREV_8139B, RL_8139, "B", RL_MTU },
202 { RL_HWREV_8130, RL_8139, "8130", RL_MTU },
203 { RL_HWREV_8139C, RL_8139, "C", RL_MTU },
204 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU },
205 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU },
206 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU },
207 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU },
208 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU },
209 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU },
210 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU },
211 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU },
212 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU },
213 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU },
214 { RL_HWREV_8100, RL_8139, "8100", RL_MTU },
215 { RL_HWREV_8101, RL_8139, "8101", RL_MTU },
216 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU },
217 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU },
218 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU },
219 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU },
220 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU },
221 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU },
222 { RL_HWREV_8401E, RL_8169, "8401E", RL_MTU },
223 { RL_HWREV_8402, RL_8169, "8402", RL_MTU },
224 { RL_HWREV_8105E, RL_8169, "8105E", RL_MTU },
225 { RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU },
226 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU },
227 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU },
228 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K },
229 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K },
230 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K },
231 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K },
232 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K },
233 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K},
234 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K},
235 { RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K},
236 { RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K},
240 static int re_probe (device_t);
241 static int re_attach (device_t);
242 static int re_detach (device_t);
244 static int re_encap (struct rl_softc *, struct mbuf **);
246 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int);
247 static int re_allocmem (device_t, struct rl_softc *);
248 static __inline void re_discard_rxbuf
249 (struct rl_softc *, int);
250 static int re_newbuf (struct rl_softc *, int);
251 static int re_jumbo_newbuf (struct rl_softc *, int);
252 static int re_rx_list_init (struct rl_softc *);
253 static int re_jrx_list_init (struct rl_softc *);
254 static int re_tx_list_init (struct rl_softc *);
256 static __inline void re_fixup_rx
259 static int re_rxeof (struct rl_softc *, int *);
260 static void re_txeof (struct rl_softc *);
261 #ifdef DEVICE_POLLING
262 static int re_poll (struct ifnet *, enum poll_cmd, int);
263 static int re_poll_locked (struct ifnet *, enum poll_cmd, int);
265 static int re_intr (void *);
266 static void re_intr_msi (void *);
267 static void re_tick (void *);
268 static void re_int_task (void *, int);
269 static void re_start (struct ifnet *);
270 static void re_start_locked (struct ifnet *);
271 static int re_ioctl (struct ifnet *, u_long, caddr_t);
272 static void re_init (void *);
273 static void re_init_locked (struct rl_softc *);
274 static void re_stop (struct rl_softc *);
275 static void re_watchdog (struct rl_softc *);
276 static int re_suspend (device_t);
277 static int re_resume (device_t);
278 static int re_shutdown (device_t);
279 static int re_ifmedia_upd (struct ifnet *);
280 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *);
282 static void re_eeprom_putbyte (struct rl_softc *, int);
283 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *);
284 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int);
285 static int re_gmii_readreg (device_t, int, int);
286 static int re_gmii_writereg (device_t, int, int, int);
288 static int re_miibus_readreg (device_t, int, int);
289 static int re_miibus_writereg (device_t, int, int, int);
290 static void re_miibus_statchg (device_t);
292 static void re_set_jumbo (struct rl_softc *, int);
293 static void re_set_rxmode (struct rl_softc *);
294 static void re_reset (struct rl_softc *);
295 static void re_setwol (struct rl_softc *);
296 static void re_clrwol (struct rl_softc *);
297 static void re_set_linkspeed (struct rl_softc *);
300 static int re_diag (struct rl_softc *);
303 static void re_add_sysctls (struct rl_softc *);
304 static int re_sysctl_stats (SYSCTL_HANDLER_ARGS);
305 static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int);
306 static int sysctl_hw_re_int_mod (SYSCTL_HANDLER_ARGS);
308 static device_method_t re_methods[] = {
309 /* Device interface */
310 DEVMETHOD(device_probe, re_probe),
311 DEVMETHOD(device_attach, re_attach),
312 DEVMETHOD(device_detach, re_detach),
313 DEVMETHOD(device_suspend, re_suspend),
314 DEVMETHOD(device_resume, re_resume),
315 DEVMETHOD(device_shutdown, re_shutdown),
318 DEVMETHOD(miibus_readreg, re_miibus_readreg),
319 DEVMETHOD(miibus_writereg, re_miibus_writereg),
320 DEVMETHOD(miibus_statchg, re_miibus_statchg),
325 static driver_t re_driver = {
328 sizeof(struct rl_softc)
331 static devclass_t re_devclass;
333 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0);
334 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
337 CSR_WRITE_1(sc, RL_EECMD, \
338 CSR_READ_1(sc, RL_EECMD) | x)
341 CSR_WRITE_1(sc, RL_EECMD, \
342 CSR_READ_1(sc, RL_EECMD) & ~x)
345 * Send a read command and address to the EEPROM, check for ACK.
348 re_eeprom_putbyte(struct rl_softc *sc, int addr)
352 d = addr | (RL_9346_READ << sc->rl_eewidth);
355 * Feed in each bit and strobe the clock.
358 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) {
360 EE_SET(RL_EE_DATAIN);
362 EE_CLR(RL_EE_DATAIN);
373 * Read a word of data stored in the EEPROM at address 'addr.'
376 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest)
382 * Send address of word we want to read.
384 re_eeprom_putbyte(sc, addr);
387 * Start reading bits from EEPROM.
389 for (i = 0x8000; i; i >>= 1) {
392 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
402 * Read a sequence of words from the EEPROM.
405 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt)
408 u_int16_t word = 0, *ptr;
410 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
414 for (i = 0; i < cnt; i++) {
415 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL);
416 re_eeprom_getword(sc, off + i, &word);
417 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL);
418 ptr = (u_int16_t *)(dest + (i * 2));
422 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
426 re_gmii_readreg(device_t dev, int phy, int reg)
432 sc = device_get_softc(dev);
434 /* Let the rgephy driver read the GMEDIASTAT register */
436 if (reg == RL_GMEDIASTAT) {
437 rval = CSR_READ_1(sc, RL_GMEDIASTAT);
441 CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
443 for (i = 0; i < RL_PHY_TIMEOUT; i++) {
444 rval = CSR_READ_4(sc, RL_PHYAR);
445 if (rval & RL_PHYAR_BUSY)
450 if (i == RL_PHY_TIMEOUT) {
451 device_printf(sc->rl_dev, "PHY read failed\n");
456 * Controller requires a 20us delay to process next MDIO request.
460 return (rval & RL_PHYAR_PHYDATA);
464 re_gmii_writereg(device_t dev, int phy, int reg, int data)
470 sc = device_get_softc(dev);
472 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
473 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
475 for (i = 0; i < RL_PHY_TIMEOUT; i++) {
476 rval = CSR_READ_4(sc, RL_PHYAR);
477 if (!(rval & RL_PHYAR_BUSY))
482 if (i == RL_PHY_TIMEOUT) {
483 device_printf(sc->rl_dev, "PHY write failed\n");
488 * Controller requires a 20us delay to process next MDIO request.
496 re_miibus_readreg(device_t dev, int phy, int reg)
500 u_int16_t re8139_reg = 0;
502 sc = device_get_softc(dev);
504 if (sc->rl_type == RL_8169) {
505 rval = re_gmii_readreg(dev, phy, reg);
511 re8139_reg = RL_BMCR;
514 re8139_reg = RL_BMSR;
517 re8139_reg = RL_ANAR;
520 re8139_reg = RL_ANER;
523 re8139_reg = RL_LPAR;
529 * Allow the rlphy driver to read the media status
530 * register. If we have a link partner which does not
531 * support NWAY, this is the register which will tell
532 * us the results of parallel detection.
535 rval = CSR_READ_1(sc, RL_MEDIASTAT);
538 device_printf(sc->rl_dev, "bad phy register\n");
541 rval = CSR_READ_2(sc, re8139_reg);
542 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) {
543 /* 8139C+ has different bit layout. */
544 rval &= ~(BMCR_LOOP | BMCR_ISO);
550 re_miibus_writereg(device_t dev, int phy, int reg, int data)
553 u_int16_t re8139_reg = 0;
556 sc = device_get_softc(dev);
558 if (sc->rl_type == RL_8169) {
559 rval = re_gmii_writereg(dev, phy, reg, data);
565 re8139_reg = RL_BMCR;
566 if (sc->rl_type == RL_8139CPLUS) {
567 /* 8139C+ has different bit layout. */
568 data &= ~(BMCR_LOOP | BMCR_ISO);
572 re8139_reg = RL_BMSR;
575 re8139_reg = RL_ANAR;
578 re8139_reg = RL_ANER;
581 re8139_reg = RL_LPAR;
588 device_printf(sc->rl_dev, "bad phy register\n");
591 CSR_WRITE_2(sc, re8139_reg, data);
596 re_miibus_statchg(device_t dev)
600 struct mii_data *mii;
602 sc = device_get_softc(dev);
603 mii = device_get_softc(sc->rl_miibus);
605 if (mii == NULL || ifp == NULL ||
606 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
609 sc->rl_flags &= ~RL_FLAG_LINK;
610 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
611 (IFM_ACTIVE | IFM_AVALID)) {
612 switch (IFM_SUBTYPE(mii->mii_media_active)) {
615 sc->rl_flags |= RL_FLAG_LINK;
618 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0)
620 sc->rl_flags |= RL_FLAG_LINK;
627 * RealTek controllers does not provide any interface to
628 * Tx/Rx MACs for resolved speed, duplex and flow-control
634 * Set the RX configuration and 64-bit multicast hash filter.
637 re_set_rxmode(struct rl_softc *sc)
640 struct ifmultiaddr *ifma;
641 uint32_t hashes[2] = { 0, 0 };
648 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD;
650 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
651 if (ifp->if_flags & IFF_PROMISC)
652 rxfilt |= RL_RXCFG_RX_ALLPHYS;
654 * Unlike other hardwares, we have to explicitly set
655 * RL_RXCFG_RX_MULTI to receive multicast frames in
658 rxfilt |= RL_RXCFG_RX_MULTI;
659 hashes[0] = hashes[1] = 0xffffffff;
664 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
665 if (ifma->ifma_addr->sa_family != AF_LINK)
667 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
668 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
670 hashes[0] |= (1 << h);
672 hashes[1] |= (1 << (h - 32));
674 if_maddr_runlock(ifp);
676 if (hashes[0] != 0 || hashes[1] != 0) {
678 * For some unfathomable reason, RealTek decided to
679 * reverse the order of the multicast hash registers
680 * in the PCI Express parts. This means we have to
681 * write the hash pattern in reverse order for those
684 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) {
685 h = bswap32(hashes[0]);
686 hashes[0] = bswap32(hashes[1]);
689 rxfilt |= RL_RXCFG_RX_MULTI;
693 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
694 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
695 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
699 re_reset(struct rl_softc *sc)
705 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
707 for (i = 0; i < RL_TIMEOUT; i++) {
709 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
713 device_printf(sc->rl_dev, "reset never completed!\n");
715 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0)
716 CSR_WRITE_1(sc, 0x82, 1);
717 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S)
718 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0);
724 * The following routine is designed to test for a defect on some
725 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
726 * lines connected to the bus, however for a 32-bit only card, they
727 * should be pulled high. The result of this defect is that the
728 * NIC will not work right if you plug it into a 64-bit slot: DMA
729 * operations will be done with 64-bit transfers, which will fail
730 * because the 64-bit data lines aren't connected.
732 * There's no way to work around this (short of talking a soldering
733 * iron to the board), however we can detect it. The method we use
734 * here is to put the NIC into digital loopback mode, set the receiver
735 * to promiscuous mode, and then try to send a frame. We then compare
736 * the frame data we sent to what was received. If the data matches,
737 * then the NIC is working correctly, otherwise we know the user has
738 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
739 * slot. In the latter case, there's no way the NIC can work correctly,
740 * so we print out a message on the console and abort the device attach.
744 re_diag(struct rl_softc *sc)
746 struct ifnet *ifp = sc->rl_ifp;
748 struct ether_header *eh;
749 struct rl_desc *cur_rx;
752 int total_len, i, error = 0, phyaddr;
753 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
754 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
756 /* Allocate a single mbuf */
757 MGETHDR(m0, M_DONTWAIT, MT_DATA);
764 * Initialize the NIC in test mode. This sets the chip up
765 * so that it can send and receive frames, but performs the
766 * following special functions:
767 * - Puts receiver in promiscuous mode
768 * - Enables digital loopback mode
769 * - Leaves interrupts turned off
772 ifp->if_flags |= IFF_PROMISC;
774 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
776 sc->rl_flags |= RL_FLAG_LINK;
777 if (sc->rl_type == RL_8169)
782 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET);
783 for (i = 0; i < RL_TIMEOUT; i++) {
784 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR);
785 if (!(status & BMCR_RESET))
789 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP);
790 CSR_WRITE_2(sc, RL_ISR, RL_INTRS);
794 /* Put some data in the mbuf */
796 eh = mtod(m0, struct ether_header *);
797 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN);
798 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN);
799 eh->ether_type = htons(ETHERTYPE_IP);
800 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
803 * Queue the packet, start transmission.
804 * Note: IF_HANDOFF() ultimately calls re_start() for us.
807 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
809 /* XXX: re_diag must not be called when in ALTQ mode */
810 IF_HANDOFF(&ifp->if_snd, m0, ifp);
814 /* Wait for it to propagate through the chip */
817 for (i = 0; i < RL_TIMEOUT; i++) {
818 status = CSR_READ_2(sc, RL_ISR);
819 CSR_WRITE_2(sc, RL_ISR, status);
820 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) ==
821 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK))
826 if (i == RL_TIMEOUT) {
827 device_printf(sc->rl_dev,
828 "diagnostic failed, failed to receive packet in"
835 * The packet should have been dumped into the first
836 * entry in the RX DMA ring. Grab it from there.
839 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
840 sc->rl_ldata.rl_rx_list_map,
841 BUS_DMASYNC_POSTREAD);
842 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag,
843 sc->rl_ldata.rl_rx_desc[0].rx_dmamap,
844 BUS_DMASYNC_POSTREAD);
845 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
846 sc->rl_ldata.rl_rx_desc[0].rx_dmamap);
848 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m;
849 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL;
850 eh = mtod(m0, struct ether_header *);
852 cur_rx = &sc->rl_ldata.rl_rx_list[0];
853 total_len = RL_RXBYTES(cur_rx);
854 rxstat = le32toh(cur_rx->rl_cmdstat);
856 if (total_len != ETHER_MIN_LEN) {
857 device_printf(sc->rl_dev,
858 "diagnostic failed, received short packet\n");
863 /* Test that the received packet data matches what we sent. */
865 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) ||
866 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) ||
867 ntohs(eh->ether_type) != ETHERTYPE_IP) {
868 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n");
869 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n",
870 dst, ":", src, ":", ETHERTYPE_IP);
871 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n",
872 eh->ether_dhost, ":", eh->ether_shost, ":",
873 ntohs(eh->ether_type));
874 device_printf(sc->rl_dev, "You may have a defective 32-bit "
875 "NIC plugged into a 64-bit PCI slot.\n");
876 device_printf(sc->rl_dev, "Please re-install the NIC in a "
877 "32-bit slot for proper operation.\n");
878 device_printf(sc->rl_dev, "Read the re(4) man page for more "
884 /* Turn interface off, release resources */
887 sc->rl_flags &= ~RL_FLAG_LINK;
888 ifp->if_flags &= ~IFF_PROMISC;
901 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
902 * IDs against our list and return a device name if we find a match.
905 re_probe(device_t dev)
907 const struct rl_type *t;
908 uint16_t devid, vendor;
909 uint16_t revid, sdevid;
912 vendor = pci_get_vendor(dev);
913 devid = pci_get_device(dev);
914 revid = pci_get_revid(dev);
915 sdevid = pci_get_subdevice(dev);
917 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) {
918 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) {
920 * Only attach to rev. 3 of the Linksys EG1032 adapter.
921 * Rev. 2 is supported by sk(4).
927 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
929 /* 8139, let rl(4) take care of this device. */
935 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) {
936 if (vendor == t->rl_vid && devid == t->rl_did) {
937 device_set_desc(dev, t->rl_name);
938 return (BUS_PROBE_DEFAULT);
946 * Map a single buffer address.
950 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
957 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
959 *addr = segs->ds_addr;
963 re_allocmem(device_t dev, struct rl_softc *sc)
966 bus_size_t rx_list_size, tx_list_size;
970 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc);
971 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc);
974 * Allocate the parent bus DMA tag appropriate for PCI.
975 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD
976 * register should be set. However some RealTek chips are known
977 * to be buggy on DAC handling, therefore disable DAC by limiting
978 * DMA address space to 32bit. PCIe variants of RealTek chips
979 * may not have the limitation.
981 lowaddr = BUS_SPACE_MAXADDR;
982 if ((sc->rl_flags & RL_FLAG_PCIE) == 0)
983 lowaddr = BUS_SPACE_MAXADDR_32BIT;
984 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
985 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL,
986 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
987 NULL, NULL, &sc->rl_parent_tag);
989 device_printf(dev, "could not allocate parent DMA tag\n");
994 * Allocate map for TX mbufs.
996 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0,
997 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
998 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0,
999 NULL, NULL, &sc->rl_ldata.rl_tx_mtag);
1001 device_printf(dev, "could not allocate TX DMA tag\n");
1006 * Allocate map for RX mbufs.
1009 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
1010 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t),
1011 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1012 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL,
1013 &sc->rl_ldata.rl_jrx_mtag);
1016 "could not allocate jumbo RX DMA tag\n");
1020 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0,
1021 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1022 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag);
1024 device_printf(dev, "could not allocate RX DMA tag\n");
1029 * Allocate map for TX descriptor list.
1031 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1032 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1033 NULL, tx_list_size, 1, tx_list_size, 0,
1034 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag);
1036 device_printf(dev, "could not allocate TX DMA ring tag\n");
1040 /* Allocate DMA'able memory for the TX ring */
1042 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag,
1043 (void **)&sc->rl_ldata.rl_tx_list,
1044 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1045 &sc->rl_ldata.rl_tx_list_map);
1047 device_printf(dev, "could not allocate TX DMA ring\n");
1051 /* Load the map for the TX ring. */
1053 sc->rl_ldata.rl_tx_list_addr = 0;
1054 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag,
1055 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list,
1056 tx_list_size, re_dma_map_addr,
1057 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT);
1058 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) {
1059 device_printf(dev, "could not load TX DMA ring\n");
1063 /* Create DMA maps for TX buffers */
1065 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
1066 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0,
1067 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap);
1069 device_printf(dev, "could not create DMA map for TX\n");
1075 * Allocate map for RX descriptor list.
1077 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1078 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1079 NULL, rx_list_size, 1, rx_list_size, 0,
1080 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag);
1082 device_printf(dev, "could not create RX DMA ring tag\n");
1086 /* Allocate DMA'able memory for the RX ring */
1088 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag,
1089 (void **)&sc->rl_ldata.rl_rx_list,
1090 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1091 &sc->rl_ldata.rl_rx_list_map);
1093 device_printf(dev, "could not allocate RX DMA ring\n");
1097 /* Load the map for the RX ring. */
1099 sc->rl_ldata.rl_rx_list_addr = 0;
1100 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag,
1101 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list,
1102 rx_list_size, re_dma_map_addr,
1103 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT);
1104 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) {
1105 device_printf(dev, "could not load RX DMA ring\n");
1109 /* Create DMA maps for RX buffers */
1111 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
1112 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0,
1113 &sc->rl_ldata.rl_jrx_sparemap);
1116 "could not create spare DMA map for jumbo RX\n");
1119 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1120 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0,
1121 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap);
1124 "could not create DMA map for jumbo RX\n");
1129 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0,
1130 &sc->rl_ldata.rl_rx_sparemap);
1132 device_printf(dev, "could not create spare DMA map for RX\n");
1135 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1136 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0,
1137 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap);
1139 device_printf(dev, "could not create DMA map for RX\n");
1144 /* Create DMA map for statistics. */
1145 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0,
1146 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1147 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL,
1148 &sc->rl_ldata.rl_stag);
1150 device_printf(dev, "could not create statistics DMA tag\n");
1153 /* Allocate DMA'able memory for statistics. */
1154 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag,
1155 (void **)&sc->rl_ldata.rl_stats,
1156 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1157 &sc->rl_ldata.rl_smap);
1160 "could not allocate statistics DMA memory\n");
1163 /* Load the map for statistics. */
1164 sc->rl_ldata.rl_stats_addr = 0;
1165 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap,
1166 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr,
1167 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT);
1168 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) {
1169 device_printf(dev, "could not load statistics DMA memory\n");
1177 * Attach the interface. Allocate softc structures, do ifmedia
1178 * setup and ethernet/BPF attach.
1181 re_attach(device_t dev)
1183 u_char eaddr[ETHER_ADDR_LEN];
1184 u_int16_t as[ETHER_ADDR_LEN / 2];
1185 struct rl_softc *sc;
1187 const struct rl_hwrev *hw_rev;
1190 u_int16_t devid, re_did = 0;
1191 int error = 0, i, phy, rid;
1192 int msic, msixc, reg;
1195 sc = device_get_softc(dev);
1198 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1200 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
1203 * Map control/status registers.
1205 pci_enable_busmaster(dev);
1207 devid = pci_get_device(dev);
1209 * Prefer memory space register mapping over IO space.
1210 * Because RTL8169SC does not seem to work when memory mapping
1211 * is used always activate io mapping.
1213 if (devid == RT_DEVICEID_8169SC)
1215 if (prefer_iomap == 0) {
1216 sc->rl_res_id = PCIR_BAR(1);
1217 sc->rl_res_type = SYS_RES_MEMORY;
1218 /* RTL8168/8101E seems to use different BARs. */
1219 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E)
1220 sc->rl_res_id = PCIR_BAR(2);
1222 sc->rl_res_id = PCIR_BAR(0);
1223 sc->rl_res_type = SYS_RES_IOPORT;
1225 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
1226 &sc->rl_res_id, RF_ACTIVE);
1227 if (sc->rl_res == NULL && prefer_iomap == 0) {
1228 sc->rl_res_id = PCIR_BAR(0);
1229 sc->rl_res_type = SYS_RES_IOPORT;
1230 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
1231 &sc->rl_res_id, RF_ACTIVE);
1233 if (sc->rl_res == NULL) {
1234 device_printf(dev, "couldn't map ports/memory\n");
1239 sc->rl_btag = rman_get_bustag(sc->rl_res);
1240 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
1242 msic = pci_msi_count(dev);
1243 msixc = pci_msix_count(dev);
1244 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
1245 sc->rl_flags |= RL_FLAG_PCIE;
1246 sc->rl_expcap = reg;
1249 device_printf(dev, "MSI count : %d\n", msic);
1250 device_printf(dev, "MSI-X count : %d\n", msixc);
1252 if (msix_disable > 0)
1254 if (msi_disable > 0)
1256 /* Prefer MSI-X to MSI. */
1260 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1262 if (sc->rl_res_pba == NULL) {
1263 device_printf(sc->rl_dev,
1264 "could not allocate MSI-X PBA resource\n");
1266 if (sc->rl_res_pba != NULL &&
1267 pci_alloc_msix(dev, &msixc) == 0) {
1269 device_printf(dev, "Using %d MSI-X message\n",
1271 sc->rl_flags |= RL_FLAG_MSIX;
1273 pci_release_msi(dev);
1275 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) {
1276 if (sc->rl_res_pba != NULL)
1277 bus_release_resource(dev, SYS_RES_MEMORY, rid,
1279 sc->rl_res_pba = NULL;
1283 /* Prefer MSI to INTx. */
1284 if (msixc == 0 && msic > 0) {
1286 if (pci_alloc_msi(dev, &msic) == 0) {
1287 if (msic == RL_MSI_MESSAGES) {
1288 device_printf(dev, "Using %d MSI message\n",
1290 sc->rl_flags |= RL_FLAG_MSI;
1291 /* Explicitly set MSI enable bit. */
1292 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1293 cfg = CSR_READ_1(sc, RL_CFG2);
1295 CSR_WRITE_1(sc, RL_CFG2, cfg);
1296 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1298 pci_release_msi(dev);
1300 if ((sc->rl_flags & RL_FLAG_MSI) == 0)
1304 /* Allocate interrupt */
1305 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) {
1307 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1308 RF_SHAREABLE | RF_ACTIVE);
1309 if (sc->rl_irq[0] == NULL) {
1310 device_printf(dev, "couldn't allocate IRQ resources\n");
1315 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) {
1316 sc->rl_irq[i] = bus_alloc_resource_any(dev,
1317 SYS_RES_IRQ, &rid, RF_ACTIVE);
1318 if (sc->rl_irq[i] == NULL) {
1320 "couldn't llocate IRQ resources for "
1321 "message %d\n", rid);
1328 if ((sc->rl_flags & RL_FLAG_MSI) == 0) {
1329 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1330 cfg = CSR_READ_1(sc, RL_CFG2);
1331 if ((cfg & RL_CFG2_MSI) != 0) {
1332 device_printf(dev, "turning off MSI enable bit.\n");
1333 cfg &= ~RL_CFG2_MSI;
1334 CSR_WRITE_1(sc, RL_CFG2, cfg);
1336 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1339 /* Disable ASPM L0S/L1. */
1340 if (sc->rl_expcap != 0) {
1341 cap = pci_read_config(dev, sc->rl_expcap +
1343 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) {
1344 ctl = pci_read_config(dev, sc->rl_expcap +
1346 if ((ctl & 0x0003) != 0) {
1348 pci_write_config(dev, sc->rl_expcap +
1349 PCIER_LINK_CTL, ctl, 2);
1350 device_printf(dev, "ASPM disabled\n");
1353 device_printf(dev, "no ASPM capability\n");
1357 hwrev = CSR_READ_4(sc, RL_TXCFG);
1358 switch (hwrev & 0x70000000) {
1361 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000);
1362 hwrev &= (RL_TXCFG_HWREV | 0x80000000);
1365 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000);
1366 hwrev &= RL_TXCFG_HWREV;
1369 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000);
1370 while (hw_rev->rl_desc != NULL) {
1371 if (hw_rev->rl_rev == hwrev) {
1372 sc->rl_type = hw_rev->rl_type;
1373 sc->rl_hwrev = hw_rev;
1378 if (hw_rev->rl_desc == NULL) {
1379 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev);
1384 switch (hw_rev->rl_rev) {
1385 case RL_HWREV_8139CPLUS:
1386 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD;
1388 case RL_HWREV_8100E:
1389 case RL_HWREV_8101E:
1390 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER;
1392 case RL_HWREV_8102E:
1393 case RL_HWREV_8102EL:
1394 case RL_HWREV_8102EL_SPIN1:
1395 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 |
1396 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP |
1399 case RL_HWREV_8103E:
1400 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 |
1401 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP |
1402 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP;
1404 case RL_HWREV_8401E:
1405 case RL_HWREV_8105E:
1406 case RL_HWREV_8105E_SPIN1:
1407 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1408 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1409 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD;
1412 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1413 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1414 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD |
1415 RL_FLAG_CMDSTOP_WAIT_TXQ;
1417 case RL_HWREV_8168B_SPIN1:
1418 case RL_HWREV_8168B_SPIN2:
1419 sc->rl_flags |= RL_FLAG_WOLRXENB;
1421 case RL_HWREV_8168B_SPIN3:
1422 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT;
1424 case RL_HWREV_8168C_SPIN2:
1425 sc->rl_flags |= RL_FLAG_MACSLEEP;
1427 case RL_HWREV_8168C:
1428 if ((hwrev & 0x00700000) == 0x00200000)
1429 sc->rl_flags |= RL_FLAG_MACSLEEP;
1431 case RL_HWREV_8168CP:
1432 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1433 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
1434 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK;
1436 case RL_HWREV_8168D:
1437 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1438 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1439 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
1440 RL_FLAG_WOL_MANLINK;
1442 case RL_HWREV_8168DP:
1443 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1444 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD |
1445 RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK;
1447 case RL_HWREV_8168E:
1448 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1449 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1450 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
1451 RL_FLAG_WOL_MANLINK;
1453 case RL_HWREV_8168E_VL:
1454 case RL_HWREV_8168F:
1456 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1457 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
1458 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
1459 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK;
1461 case RL_HWREV_8169_8110SB:
1462 case RL_HWREV_8169_8110SBL:
1463 case RL_HWREV_8169_8110SC:
1464 case RL_HWREV_8169_8110SCE:
1465 sc->rl_flags |= RL_FLAG_PHYWAKE;
1468 case RL_HWREV_8169S:
1469 case RL_HWREV_8110S:
1470 sc->rl_flags |= RL_FLAG_MACRESET;
1476 if (sc->rl_hwrev->rl_rev == RL_HWREV_8139CPLUS) {
1477 sc->rl_cfg0 = RL_8139_CFG0;
1478 sc->rl_cfg1 = RL_8139_CFG1;
1480 sc->rl_cfg3 = RL_8139_CFG3;
1481 sc->rl_cfg4 = RL_8139_CFG4;
1482 sc->rl_cfg5 = RL_8139_CFG5;
1484 sc->rl_cfg0 = RL_CFG0;
1485 sc->rl_cfg1 = RL_CFG1;
1486 sc->rl_cfg2 = RL_CFG2;
1487 sc->rl_cfg3 = RL_CFG3;
1488 sc->rl_cfg4 = RL_CFG4;
1489 sc->rl_cfg5 = RL_CFG5;
1492 /* Reset the adapter. */
1498 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1499 cfg = CSR_READ_1(sc, sc->rl_cfg1);
1501 CSR_WRITE_1(sc, sc->rl_cfg1, cfg);
1502 cfg = CSR_READ_1(sc, sc->rl_cfg5);
1503 cfg &= RL_CFG5_PME_STS;
1504 CSR_WRITE_1(sc, sc->rl_cfg5, cfg);
1505 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1507 if ((sc->rl_flags & RL_FLAG_PAR) != 0) {
1509 * XXX Should have a better way to extract station
1510 * address from EEPROM.
1512 for (i = 0; i < ETHER_ADDR_LEN; i++)
1513 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
1515 sc->rl_eewidth = RL_9356_ADDR_LEN;
1516 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
1517 if (re_did != 0x8129)
1518 sc->rl_eewidth = RL_9346_ADDR_LEN;
1521 * Get station address from the EEPROM.
1523 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3);
1524 for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
1525 as[i] = le16toh(as[i]);
1526 bcopy(as, eaddr, ETHER_ADDR_LEN);
1529 if (sc->rl_type == RL_8169) {
1530 /* Set RX length mask and number of descriptors. */
1531 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN;
1532 sc->rl_txstart = RL_GTXSTART;
1533 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT;
1534 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT;
1536 /* Set RX length mask and number of descriptors. */
1537 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN;
1538 sc->rl_txstart = RL_TXSTART;
1539 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT;
1540 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT;
1543 error = re_allocmem(dev, sc);
1548 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
1550 device_printf(dev, "can not if_alloc()\n");
1555 /* Take controller out of deep sleep mode. */
1556 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
1557 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
1558 CSR_WRITE_1(sc, RL_GPIO,
1559 CSR_READ_1(sc, RL_GPIO) | 0x01);
1561 CSR_WRITE_1(sc, RL_GPIO,
1562 CSR_READ_1(sc, RL_GPIO) & ~0x01);
1565 /* Take PHY out of power down mode. */
1566 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) {
1567 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80);
1568 if (hw_rev->rl_rev == RL_HWREV_8401E)
1569 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08);
1571 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) {
1572 re_gmii_writereg(dev, 1, 0x1f, 0);
1573 re_gmii_writereg(dev, 1, 0x0e, 0);
1577 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1578 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1579 ifp->if_ioctl = re_ioctl;
1580 ifp->if_start = re_start;
1582 * RTL8168/8111C generates wrong IP checksummed frame if the
1583 * packet has IP options so disable TX IP checksum offloading.
1585 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C ||
1586 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2 ||
1587 sc->rl_hwrev->rl_rev == RL_HWREV_8168CP)
1588 ifp->if_hwassist = CSUM_TCP | CSUM_UDP;
1590 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP;
1591 ifp->if_hwassist |= CSUM_TSO;
1592 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4;
1593 ifp->if_capenable = ifp->if_capabilities;
1594 ifp->if_init = re_init;
1595 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN);
1596 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN;
1597 IFQ_SET_READY(&ifp->if_snd);
1599 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc);
1601 #define RE_PHYAD_INTERNAL 0
1604 phy = RE_PHYAD_INTERNAL;
1605 if (sc->rl_type == RL_8169)
1607 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd,
1608 re_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, MIIF_DOPAUSE);
1610 device_printf(dev, "attaching PHYs failed\n");
1615 * Call MI attach routine.
1617 ether_ifattach(ifp, eaddr);
1619 /* VLAN capability setup */
1620 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
1621 if (ifp->if_capabilities & IFCAP_HWCSUM)
1622 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
1623 /* Enable WOL if PM is supported. */
1624 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0)
1625 ifp->if_capabilities |= IFCAP_WOL;
1626 ifp->if_capenable = ifp->if_capabilities;
1627 ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST);
1629 * Don't enable TSO by default. It is known to generate
1630 * corrupted TCP segments(bad TCP options) under certain
1633 ifp->if_hwassist &= ~CSUM_TSO;
1634 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO);
1635 #ifdef DEVICE_POLLING
1636 ifp->if_capabilities |= IFCAP_POLLING;
1639 * Tell the upper layer(s) we support long frames.
1640 * Must appear after the call to ether_ifattach() because
1641 * ether_ifattach() sets ifi_hdrlen to the default value.
1643 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1647 * Perform hardware diagnostic on the original RTL8169.
1648 * Some 32-bit cards were incorrectly wired and would
1649 * malfunction if plugged into a 64-bit slot.
1652 if (hwrev == RL_HWREV_8169) {
1653 error = re_diag(sc);
1656 "attach aborted due to hardware diag failure\n");
1657 ether_ifdetach(ifp);
1663 #ifdef RE_TX_MODERATION
1666 /* Hook interrupt last to avoid having to lock softc */
1667 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 &&
1669 error = bus_setup_intr(dev, sc->rl_irq[0],
1670 INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc,
1671 &sc->rl_intrhand[0]);
1673 error = bus_setup_intr(dev, sc->rl_irq[0],
1674 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc,
1675 &sc->rl_intrhand[0]);
1678 device_printf(dev, "couldn't set up irq\n");
1679 ether_ifdetach(ifp);
1691 * Shutdown hardware and free up resources. This can be called any
1692 * time after the mutex has been initialized. It is called in both
1693 * the error case in attach and the normal detach case so it needs
1694 * to be careful about only freeing resources that have actually been
1698 re_detach(device_t dev)
1700 struct rl_softc *sc;
1704 sc = device_get_softc(dev);
1706 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized"));
1708 /* These should only be active if attach succeeded */
1709 if (device_is_attached(dev)) {
1710 #ifdef DEVICE_POLLING
1711 if (ifp->if_capenable & IFCAP_POLLING)
1712 ether_poll_deregister(ifp);
1720 callout_drain(&sc->rl_stat_callout);
1721 taskqueue_drain(taskqueue_fast, &sc->rl_inttask);
1723 * Force off the IFF_UP flag here, in case someone
1724 * still had a BPF descriptor attached to this
1725 * interface. If they do, ether_ifdetach() will cause
1726 * the BPF code to try and clear the promisc mode
1727 * flag, which will bubble down to re_ioctl(),
1728 * which will try to call re_init() again. This will
1729 * turn the NIC back on and restart the MII ticker,
1730 * which will panic the system when the kernel tries
1731 * to invoke the re_tick() function that isn't there
1734 ifp->if_flags &= ~IFF_UP;
1735 ether_ifdetach(ifp);
1738 device_delete_child(dev, sc->rl_miibus);
1739 bus_generic_detach(dev);
1742 * The rest is resource deallocation, so we should already be
1746 if (sc->rl_intrhand[0] != NULL) {
1747 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
1748 sc->rl_intrhand[0] = NULL;
1752 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0)
1756 if (sc->rl_irq[0] != NULL) {
1757 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]);
1758 sc->rl_irq[0] = NULL;
1760 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0)
1761 pci_release_msi(dev);
1762 if (sc->rl_res_pba) {
1764 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba);
1767 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id,
1770 /* Unload and free the RX DMA ring memory and map */
1772 if (sc->rl_ldata.rl_rx_list_tag) {
1773 if (sc->rl_ldata.rl_rx_list_map)
1774 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag,
1775 sc->rl_ldata.rl_rx_list_map);
1776 if (sc->rl_ldata.rl_rx_list_map && sc->rl_ldata.rl_rx_list)
1777 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag,
1778 sc->rl_ldata.rl_rx_list,
1779 sc->rl_ldata.rl_rx_list_map);
1780 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag);
1783 /* Unload and free the TX DMA ring memory and map */
1785 if (sc->rl_ldata.rl_tx_list_tag) {
1786 if (sc->rl_ldata.rl_tx_list_map)
1787 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag,
1788 sc->rl_ldata.rl_tx_list_map);
1789 if (sc->rl_ldata.rl_tx_list_map && sc->rl_ldata.rl_tx_list)
1790 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag,
1791 sc->rl_ldata.rl_tx_list,
1792 sc->rl_ldata.rl_tx_list_map);
1793 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag);
1796 /* Destroy all the RX and TX buffer maps */
1798 if (sc->rl_ldata.rl_tx_mtag) {
1799 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
1800 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap)
1801 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag,
1802 sc->rl_ldata.rl_tx_desc[i].tx_dmamap);
1804 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag);
1806 if (sc->rl_ldata.rl_rx_mtag) {
1807 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1808 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap)
1809 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag,
1810 sc->rl_ldata.rl_rx_desc[i].rx_dmamap);
1812 if (sc->rl_ldata.rl_rx_sparemap)
1813 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag,
1814 sc->rl_ldata.rl_rx_sparemap);
1815 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag);
1817 if (sc->rl_ldata.rl_jrx_mtag) {
1818 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1819 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap)
1820 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag,
1821 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap);
1823 if (sc->rl_ldata.rl_jrx_sparemap)
1824 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag,
1825 sc->rl_ldata.rl_jrx_sparemap);
1826 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag);
1828 /* Unload and free the stats buffer and map */
1830 if (sc->rl_ldata.rl_stag) {
1831 if (sc->rl_ldata.rl_smap)
1832 bus_dmamap_unload(sc->rl_ldata.rl_stag,
1833 sc->rl_ldata.rl_smap);
1834 if (sc->rl_ldata.rl_smap && sc->rl_ldata.rl_stats)
1835 bus_dmamem_free(sc->rl_ldata.rl_stag,
1836 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap);
1837 bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
1840 if (sc->rl_parent_tag)
1841 bus_dma_tag_destroy(sc->rl_parent_tag);
1843 mtx_destroy(&sc->rl_mtx);
1848 static __inline void
1849 re_discard_rxbuf(struct rl_softc *sc, int idx)
1851 struct rl_desc *desc;
1852 struct rl_rxdesc *rxd;
1855 if (sc->rl_ifp->if_mtu > RL_MTU &&
1856 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0)
1857 rxd = &sc->rl_ldata.rl_jrx_desc[idx];
1859 rxd = &sc->rl_ldata.rl_rx_desc[idx];
1860 desc = &sc->rl_ldata.rl_rx_list[idx];
1861 desc->rl_vlanctl = 0;
1862 cmdstat = rxd->rx_size;
1863 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1864 cmdstat |= RL_RDESC_CMD_EOR;
1865 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
1869 re_newbuf(struct rl_softc *sc, int idx)
1872 struct rl_rxdesc *rxd;
1873 bus_dma_segment_t segs[1];
1875 struct rl_desc *desc;
1879 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1883 m->m_len = m->m_pkthdr.len = MCLBYTES;
1886 * This is part of an evil trick to deal with non-x86 platforms.
1887 * The RealTek chip requires RX buffers to be aligned on 64-bit
1888 * boundaries, but that will hose non-x86 machines. To get around
1889 * this, we leave some empty space at the start of each buffer
1890 * and for non-x86 hosts, we copy the buffer back six bytes
1891 * to achieve word alignment. This is slightly more efficient
1892 * than allocating a new buffer, copying the contents, and
1893 * discarding the old buffer.
1895 m_adj(m, RE_ETHER_ALIGN);
1897 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag,
1898 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT);
1903 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs));
1905 rxd = &sc->rl_ldata.rl_rx_desc[idx];
1906 if (rxd->rx_m != NULL) {
1907 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap,
1908 BUS_DMASYNC_POSTREAD);
1909 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap);
1913 map = rxd->rx_dmamap;
1914 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap;
1915 rxd->rx_size = segs[0].ds_len;
1916 sc->rl_ldata.rl_rx_sparemap = map;
1917 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap,
1918 BUS_DMASYNC_PREREAD);
1920 desc = &sc->rl_ldata.rl_rx_list[idx];
1921 desc->rl_vlanctl = 0;
1922 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr));
1923 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr));
1924 cmdstat = segs[0].ds_len;
1925 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1926 cmdstat |= RL_RDESC_CMD_EOR;
1927 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
1933 re_jumbo_newbuf(struct rl_softc *sc, int idx)
1936 struct rl_rxdesc *rxd;
1937 bus_dma_segment_t segs[1];
1939 struct rl_desc *desc;
1943 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1946 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1948 m_adj(m, RE_ETHER_ALIGN);
1950 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag,
1951 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT);
1956 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs));
1958 rxd = &sc->rl_ldata.rl_jrx_desc[idx];
1959 if (rxd->rx_m != NULL) {
1960 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap,
1961 BUS_DMASYNC_POSTREAD);
1962 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap);
1966 map = rxd->rx_dmamap;
1967 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap;
1968 rxd->rx_size = segs[0].ds_len;
1969 sc->rl_ldata.rl_jrx_sparemap = map;
1970 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap,
1971 BUS_DMASYNC_PREREAD);
1973 desc = &sc->rl_ldata.rl_rx_list[idx];
1974 desc->rl_vlanctl = 0;
1975 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr));
1976 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr));
1977 cmdstat = segs[0].ds_len;
1978 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1979 cmdstat |= RL_RDESC_CMD_EOR;
1980 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
1986 static __inline void
1987 re_fixup_rx(struct mbuf *m)
1990 uint16_t *src, *dst;
1992 src = mtod(m, uint16_t *);
1993 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src;
1995 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1998 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN;
2003 re_tx_list_init(struct rl_softc *sc)
2005 struct rl_desc *desc;
2010 bzero(sc->rl_ldata.rl_tx_list,
2011 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc));
2012 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++)
2013 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL;
2015 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1];
2016 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR);
2018 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2019 sc->rl_ldata.rl_tx_list_map,
2020 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2022 sc->rl_ldata.rl_tx_prodidx = 0;
2023 sc->rl_ldata.rl_tx_considx = 0;
2024 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt;
2030 re_rx_list_init(struct rl_softc *sc)
2034 bzero(sc->rl_ldata.rl_rx_list,
2035 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc));
2036 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
2037 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL;
2038 if ((error = re_newbuf(sc, i)) != 0)
2042 /* Flush the RX descriptors */
2044 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2045 sc->rl_ldata.rl_rx_list_map,
2046 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2048 sc->rl_ldata.rl_rx_prodidx = 0;
2049 sc->rl_head = sc->rl_tail = NULL;
2050 sc->rl_int_rx_act = 0;
2056 re_jrx_list_init(struct rl_softc *sc)
2060 bzero(sc->rl_ldata.rl_rx_list,
2061 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc));
2062 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
2063 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL;
2064 if ((error = re_jumbo_newbuf(sc, i)) != 0)
2068 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2069 sc->rl_ldata.rl_rx_list_map,
2070 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2072 sc->rl_ldata.rl_rx_prodidx = 0;
2073 sc->rl_head = sc->rl_tail = NULL;
2074 sc->rl_int_rx_act = 0;
2080 * RX handler for C+ and 8169. For the gigE chips, we support
2081 * the reception of jumbo frames that have been fragmented
2082 * across multiple 2K mbuf cluster buffers.
2085 re_rxeof(struct rl_softc *sc, int *rx_npktsp)
2089 int i, rxerr, total_len;
2090 struct rl_desc *cur_rx;
2091 u_int32_t rxstat, rxvlan;
2092 int jumbo, maxpkt = 16, rx_npkts = 0;
2097 if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0)
2102 /* Invalidate the descriptor memory */
2104 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2105 sc->rl_ldata.rl_rx_list_map,
2106 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2108 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0;
2109 i = RL_RX_DESC_NXT(sc, i)) {
2110 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
2112 cur_rx = &sc->rl_ldata.rl_rx_list[i];
2113 rxstat = le32toh(cur_rx->rl_cmdstat);
2114 if ((rxstat & RL_RDESC_STAT_OWN) != 0)
2116 total_len = rxstat & sc->rl_rxlenmask;
2117 rxvlan = le32toh(cur_rx->rl_vlanctl);
2119 m = sc->rl_ldata.rl_jrx_desc[i].rx_m;
2121 m = sc->rl_ldata.rl_rx_desc[i].rx_m;
2123 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
2124 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) !=
2125 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) {
2127 * RTL8168C or later controllers do not
2128 * support multi-fragment packet.
2130 re_discard_rxbuf(sc, i);
2132 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) {
2133 if (re_newbuf(sc, i) != 0) {
2135 * If this is part of a multi-fragment packet,
2136 * discard all the pieces.
2138 if (sc->rl_head != NULL) {
2139 m_freem(sc->rl_head);
2140 sc->rl_head = sc->rl_tail = NULL;
2142 re_discard_rxbuf(sc, i);
2145 m->m_len = RE_RX_DESC_BUFLEN;
2146 if (sc->rl_head == NULL)
2147 sc->rl_head = sc->rl_tail = m;
2149 m->m_flags &= ~M_PKTHDR;
2150 sc->rl_tail->m_next = m;
2157 * NOTE: for the 8139C+, the frame length field
2158 * is always 12 bits in size, but for the gigE chips,
2159 * it is 13 bits (since the max RX frame length is 16K).
2160 * Unfortunately, all 32 bits in the status word
2161 * were already used, so to make room for the extra
2162 * length bit, RealTek took out the 'frame alignment
2163 * error' bit and shifted the other status bits
2164 * over one slot. The OWN, EOR, FS and LS bits are
2165 * still in the same places. We have already extracted
2166 * the frame length and checked the OWN bit, so rather
2167 * than using an alternate bit mapping, we shift the
2168 * status bits one space to the right so we can evaluate
2169 * them using the 8169 status as though it was in the
2170 * same format as that of the 8139C+.
2172 if (sc->rl_type == RL_8169)
2176 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be
2177 * set, but if CRC is clear, it will still be a valid frame.
2179 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) {
2181 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 &&
2183 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)
2188 * If this is part of a multi-fragment packet,
2189 * discard all the pieces.
2191 if (sc->rl_head != NULL) {
2192 m_freem(sc->rl_head);
2193 sc->rl_head = sc->rl_tail = NULL;
2195 re_discard_rxbuf(sc, i);
2201 * If allocating a replacement mbuf fails,
2202 * reload the current one.
2205 rxerr = re_jumbo_newbuf(sc, i);
2207 rxerr = re_newbuf(sc, i);
2210 if (sc->rl_head != NULL) {
2211 m_freem(sc->rl_head);
2212 sc->rl_head = sc->rl_tail = NULL;
2214 re_discard_rxbuf(sc, i);
2218 if (sc->rl_head != NULL) {
2220 m->m_len = total_len;
2222 m->m_len = total_len % RE_RX_DESC_BUFLEN;
2224 m->m_len = RE_RX_DESC_BUFLEN;
2227 * Special case: if there's 4 bytes or less
2228 * in this buffer, the mbuf can be discarded:
2229 * the last 4 bytes is the CRC, which we don't
2230 * care about anyway.
2232 if (m->m_len <= ETHER_CRC_LEN) {
2233 sc->rl_tail->m_len -=
2234 (ETHER_CRC_LEN - m->m_len);
2237 m->m_len -= ETHER_CRC_LEN;
2238 m->m_flags &= ~M_PKTHDR;
2239 sc->rl_tail->m_next = m;
2242 sc->rl_head = sc->rl_tail = NULL;
2243 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
2245 m->m_pkthdr.len = m->m_len =
2246 (total_len - ETHER_CRC_LEN);
2252 m->m_pkthdr.rcvif = ifp;
2254 /* Do RX checksumming if enabled */
2256 if (ifp->if_capenable & IFCAP_RXCSUM) {
2257 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
2258 /* Check IP header checksum */
2259 if (rxstat & RL_RDESC_STAT_PROTOID)
2260 m->m_pkthdr.csum_flags |=
2262 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD))
2263 m->m_pkthdr.csum_flags |=
2266 /* Check TCP/UDP checksum */
2267 if ((RL_TCPPKT(rxstat) &&
2268 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
2269 (RL_UDPPKT(rxstat) &&
2270 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
2271 m->m_pkthdr.csum_flags |=
2272 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2273 m->m_pkthdr.csum_data = 0xffff;
2277 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP
2279 if ((rxstat & RL_RDESC_STAT_PROTOID) &&
2280 (rxvlan & RL_RDESC_IPV4))
2281 m->m_pkthdr.csum_flags |=
2283 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) &&
2284 (rxvlan & RL_RDESC_IPV4))
2285 m->m_pkthdr.csum_flags |=
2287 if (((rxstat & RL_RDESC_STAT_TCP) &&
2288 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
2289 ((rxstat & RL_RDESC_STAT_UDP) &&
2290 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
2291 m->m_pkthdr.csum_flags |=
2292 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2293 m->m_pkthdr.csum_data = 0xffff;
2298 if (rxvlan & RL_RDESC_VLANCTL_TAG) {
2299 m->m_pkthdr.ether_vtag =
2300 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA));
2301 m->m_flags |= M_VLANTAG;
2304 (*ifp->if_input)(ifp, m);
2309 /* Flush the RX DMA ring */
2311 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2312 sc->rl_ldata.rl_rx_list_map,
2313 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2315 sc->rl_ldata.rl_rx_prodidx = i;
2317 if (rx_npktsp != NULL)
2318 *rx_npktsp = rx_npkts;
2326 re_txeof(struct rl_softc *sc)
2329 struct rl_txdesc *txd;
2333 cons = sc->rl_ldata.rl_tx_considx;
2334 if (cons == sc->rl_ldata.rl_tx_prodidx)
2338 /* Invalidate the TX descriptor list */
2339 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2340 sc->rl_ldata.rl_tx_list_map,
2341 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2343 for (; cons != sc->rl_ldata.rl_tx_prodidx;
2344 cons = RL_TX_DESC_NXT(sc, cons)) {
2345 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat);
2346 if (txstat & RL_TDESC_STAT_OWN)
2349 * We only stash mbufs in the last descriptor
2350 * in a fragment chain, which also happens to
2351 * be the only place where the TX status bits
2354 if (txstat & RL_TDESC_CMD_EOF) {
2355 txd = &sc->rl_ldata.rl_tx_desc[cons];
2356 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
2357 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2358 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag,
2360 KASSERT(txd->tx_m != NULL,
2361 ("%s: freeing NULL mbufs!", __func__));
2364 if (txstat & (RL_TDESC_STAT_EXCESSCOL|
2365 RL_TDESC_STAT_COLCNT))
2366 ifp->if_collisions++;
2367 if (txstat & RL_TDESC_STAT_TXERRSUM)
2372 sc->rl_ldata.rl_tx_free++;
2373 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2375 sc->rl_ldata.rl_tx_considx = cons;
2377 /* No changes made to the TX ring, so no flush needed */
2379 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) {
2380 #ifdef RE_TX_MODERATION
2382 * If not all descriptors have been reaped yet, reload
2383 * the timer so that we will eventually get another
2384 * interrupt that will cause us to re-enter this routine.
2385 * This is done in case the transmitter has gone idle.
2387 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2390 sc->rl_watchdog_timer = 0;
2396 struct rl_softc *sc;
2397 struct mii_data *mii;
2403 mii = device_get_softc(sc->rl_miibus);
2405 if ((sc->rl_flags & RL_FLAG_LINK) == 0)
2406 re_miibus_statchg(sc->rl_dev);
2408 * Reclaim transmitted frames here. Technically it is not
2409 * necessary to do here but it ensures periodic reclamation
2410 * regardless of Tx completion interrupt which seems to be
2411 * lost on PCIe based controllers under certain situations.
2415 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
2418 #ifdef DEVICE_POLLING
2420 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2422 struct rl_softc *sc = ifp->if_softc;
2426 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2427 rx_npkts = re_poll_locked(ifp, cmd, count);
2433 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
2435 struct rl_softc *sc = ifp->if_softc;
2440 sc->rxcycles = count;
2441 re_rxeof(sc, &rx_npkts);
2444 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2445 re_start_locked(ifp);
2447 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
2450 status = CSR_READ_2(sc, RL_ISR);
2451 if (status == 0xffff)
2454 CSR_WRITE_2(sc, RL_ISR, status);
2455 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2456 (sc->rl_flags & RL_FLAG_PCIE))
2457 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2460 * XXX check behaviour on receiver stalls.
2463 if (status & RL_ISR_SYSTEM_ERR) {
2464 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2470 #endif /* DEVICE_POLLING */
2475 struct rl_softc *sc;
2480 status = CSR_READ_2(sc, RL_ISR);
2481 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0)
2482 return (FILTER_STRAY);
2483 CSR_WRITE_2(sc, RL_IMR, 0);
2485 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
2487 return (FILTER_HANDLED);
2491 re_int_task(void *arg, int npending)
2493 struct rl_softc *sc;
2503 status = CSR_READ_2(sc, RL_ISR);
2504 CSR_WRITE_2(sc, RL_ISR, status);
2506 if (sc->suspended ||
2507 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2512 #ifdef DEVICE_POLLING
2513 if (ifp->if_capenable & IFCAP_POLLING) {
2519 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW))
2520 rval = re_rxeof(sc, NULL);
2523 * Some chips will ignore a second TX request issued
2524 * while an existing transmission is in progress. If
2525 * the transmitter goes idle but there are still
2526 * packets waiting to be sent, we need to restart the
2527 * channel here to flush them out. This only seems to
2528 * be required with the PCIe devices.
2530 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2531 (sc->rl_flags & RL_FLAG_PCIE))
2532 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2534 #ifdef RE_TX_MODERATION
2535 RL_ISR_TIMEOUT_EXPIRED|
2539 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL))
2542 if (status & RL_ISR_SYSTEM_ERR) {
2543 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2547 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2548 re_start_locked(ifp);
2552 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) {
2553 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
2557 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2561 re_intr_msi(void *xsc)
2563 struct rl_softc *sc;
2565 uint16_t intrs, status;
2571 #ifdef DEVICE_POLLING
2572 if (ifp->if_capenable & IFCAP_POLLING) {
2577 /* Disable interrupts. */
2578 CSR_WRITE_2(sc, RL_IMR, 0);
2579 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2584 intrs = RL_INTRS_CPLUS;
2585 status = CSR_READ_2(sc, RL_ISR);
2586 CSR_WRITE_2(sc, RL_ISR, status);
2587 if (sc->rl_int_rx_act > 0) {
2588 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW |
2590 status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW |
2594 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR |
2595 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) {
2597 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2598 if (sc->rl_int_rx_mod != 0 &&
2599 (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR |
2600 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) {
2601 /* Rearm one-shot timer. */
2602 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2603 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR |
2604 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN);
2605 sc->rl_int_rx_act = 1;
2607 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR |
2608 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN;
2609 sc->rl_int_rx_act = 0;
2615 * Some chips will ignore a second TX request issued
2616 * while an existing transmission is in progress. If
2617 * the transmitter goes idle but there are still
2618 * packets waiting to be sent, we need to restart the
2619 * channel here to flush them out. This only seems to
2620 * be required with the PCIe devices.
2622 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2623 (sc->rl_flags & RL_FLAG_PCIE))
2624 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2625 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL))
2628 if (status & RL_ISR_SYSTEM_ERR) {
2629 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2633 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2634 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2635 re_start_locked(ifp);
2636 CSR_WRITE_2(sc, RL_IMR, intrs);
2642 re_encap(struct rl_softc *sc, struct mbuf **m_head)
2644 struct rl_txdesc *txd, *txd_last;
2645 bus_dma_segment_t segs[RL_NTXSEGS];
2648 struct rl_desc *desc;
2650 int i, error, ei, si;
2652 uint32_t cmdstat, csum_flags, vlanctl;
2655 M_ASSERTPKTHDR((*m_head));
2658 * With some of the RealTek chips, using the checksum offload
2659 * support in conjunction with the autopadding feature results
2660 * in the transmission of corrupt frames. For example, if we
2661 * need to send a really small IP fragment that's less than 60
2662 * bytes in size, and IP header checksumming is enabled, the
2663 * resulting ethernet frame that appears on the wire will
2664 * have garbled payload. To work around this, if TX IP checksum
2665 * offload is enabled, we always manually pad short frames out
2666 * to the minimum ethernet frame size.
2668 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 &&
2669 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN &&
2670 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) {
2671 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len;
2672 if (M_WRITABLE(*m_head) == 0) {
2673 /* Get a writable copy. */
2674 m_new = m_dup(*m_head, M_DONTWAIT);
2676 if (m_new == NULL) {
2682 if ((*m_head)->m_next != NULL ||
2683 M_TRAILINGSPACE(*m_head) < padlen) {
2684 m_new = m_defrag(*m_head, M_DONTWAIT);
2685 if (m_new == NULL) {
2694 * Manually pad short frames, and zero the pad space
2695 * to avoid leaking data.
2697 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen);
2698 m_new->m_pkthdr.len += padlen;
2699 m_new->m_len = m_new->m_pkthdr.len;
2703 prod = sc->rl_ldata.rl_tx_prodidx;
2704 txd = &sc->rl_ldata.rl_tx_desc[prod];
2705 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
2706 *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
2707 if (error == EFBIG) {
2708 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS);
2709 if (m_new == NULL) {
2715 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag,
2716 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
2722 } else if (error != 0)
2730 /* Check for number of available descriptors. */
2731 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) {
2732 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap);
2736 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
2737 BUS_DMASYNC_PREWRITE);
2740 * Set up checksum offload. Note: checksum offload bits must
2741 * appear in all descriptors of a multi-descriptor transmit
2742 * attempt. This is according to testing done with an 8169
2743 * chip. This is a requirement.
2747 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2748 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) {
2749 csum_flags |= RL_TDESC_CMD_LGSEND;
2750 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
2751 RL_TDESC_CMD_MSSVALV2_SHIFT);
2753 csum_flags |= RL_TDESC_CMD_LGSEND |
2754 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
2755 RL_TDESC_CMD_MSSVAL_SHIFT);
2759 * Unconditionally enable IP checksum if TCP or UDP
2760 * checksum is required. Otherwise, TCP/UDP checksum
2761 * does't make effects.
2763 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) {
2764 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
2765 csum_flags |= RL_TDESC_CMD_IPCSUM;
2766 if (((*m_head)->m_pkthdr.csum_flags &
2768 csum_flags |= RL_TDESC_CMD_TCPCSUM;
2769 if (((*m_head)->m_pkthdr.csum_flags &
2771 csum_flags |= RL_TDESC_CMD_UDPCSUM;
2773 vlanctl |= RL_TDESC_CMD_IPCSUMV2;
2774 if (((*m_head)->m_pkthdr.csum_flags &
2776 vlanctl |= RL_TDESC_CMD_TCPCSUMV2;
2777 if (((*m_head)->m_pkthdr.csum_flags &
2779 vlanctl |= RL_TDESC_CMD_UDPCSUMV2;
2785 * Set up hardware VLAN tagging. Note: vlan tag info must
2786 * appear in all descriptors of a multi-descriptor
2787 * transmission attempt.
2789 if ((*m_head)->m_flags & M_VLANTAG)
2790 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) |
2791 RL_TDESC_VLANCTL_TAG;
2794 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) {
2795 desc = &sc->rl_ldata.rl_tx_list[prod];
2796 desc->rl_vlanctl = htole32(vlanctl);
2797 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr));
2798 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr));
2799 cmdstat = segs[i].ds_len;
2801 cmdstat |= RL_TDESC_CMD_OWN;
2802 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1)
2803 cmdstat |= RL_TDESC_CMD_EOR;
2804 desc->rl_cmdstat = htole32(cmdstat | csum_flags);
2805 sc->rl_ldata.rl_tx_free--;
2807 /* Update producer index. */
2808 sc->rl_ldata.rl_tx_prodidx = prod;
2810 /* Set EOF on the last descriptor. */
2811 ei = RL_TX_DESC_PRV(sc, prod);
2812 desc = &sc->rl_ldata.rl_tx_list[ei];
2813 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF);
2815 desc = &sc->rl_ldata.rl_tx_list[si];
2816 /* Set SOF and transfer ownership of packet to the chip. */
2817 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF);
2820 * Insure that the map for this transmission
2821 * is placed at the array index of the last descriptor
2822 * in this chain. (Swap last and first dmamaps.)
2824 txd_last = &sc->rl_ldata.rl_tx_desc[ei];
2825 map = txd->tx_dmamap;
2826 txd->tx_dmamap = txd_last->tx_dmamap;
2827 txd_last->tx_dmamap = map;
2828 txd_last->tx_m = *m_head;
2834 re_start(struct ifnet *ifp)
2836 struct rl_softc *sc;
2840 re_start_locked(ifp);
2845 * Main transmit routine for C+ and gigE NICs.
2848 re_start_locked(struct ifnet *ifp)
2850 struct rl_softc *sc;
2851 struct mbuf *m_head;
2856 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2857 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0)
2860 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2861 sc->rl_ldata.rl_tx_free > 1;) {
2862 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2866 if (re_encap(sc, &m_head) != 0) {
2869 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2870 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2875 * If there's a BPF listener, bounce a copy of this frame
2878 ETHER_BPF_MTAP(ifp, m_head);
2884 #ifdef RE_TX_MODERATION
2885 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt)
2886 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2891 /* Flush the TX descriptors */
2893 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2894 sc->rl_ldata.rl_tx_list_map,
2895 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2897 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2899 #ifdef RE_TX_MODERATION
2901 * Use the countdown timer for interrupt moderation.
2902 * 'TX done' interrupts are disabled. Instead, we reset the
2903 * countdown timer, which will begin counting until it hits
2904 * the value in the TIMERINT register, and then trigger an
2905 * interrupt. Each time we write to the TIMERCNT register,
2906 * the timer count is reset to 0.
2908 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2912 * Set a timeout in case the chip goes out to lunch.
2914 sc->rl_watchdog_timer = 5;
2918 re_set_jumbo(struct rl_softc *sc, int jumbo)
2921 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) {
2922 pci_set_max_read_req(sc->rl_dev, 4096);
2926 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
2928 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) |
2930 switch (sc->rl_hwrev->rl_rev) {
2931 case RL_HWREV_8168DP:
2933 case RL_HWREV_8168E:
2934 CSR_WRITE_1(sc, sc->rl_cfg4,
2935 CSR_READ_1(sc, sc->rl_cfg4) | 0x01);
2938 CSR_WRITE_1(sc, sc->rl_cfg4,
2939 CSR_READ_1(sc, sc->rl_cfg4) | RL_CFG4_JUMBO_EN1);
2942 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) &
2943 ~RL_CFG3_JUMBO_EN0);
2944 switch (sc->rl_hwrev->rl_rev) {
2945 case RL_HWREV_8168DP:
2947 case RL_HWREV_8168E:
2948 CSR_WRITE_1(sc, sc->rl_cfg4,
2949 CSR_READ_1(sc, sc->rl_cfg4) & ~0x01);
2952 CSR_WRITE_1(sc, sc->rl_cfg4,
2953 CSR_READ_1(sc, sc->rl_cfg4) & ~RL_CFG4_JUMBO_EN1);
2956 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2958 switch (sc->rl_hwrev->rl_rev) {
2959 case RL_HWREV_8168DP:
2960 pci_set_max_read_req(sc->rl_dev, 4096);
2964 pci_set_max_read_req(sc->rl_dev, 512);
2966 pci_set_max_read_req(sc->rl_dev, 4096);
2973 struct rl_softc *sc = xsc;
2981 re_init_locked(struct rl_softc *sc)
2983 struct ifnet *ifp = sc->rl_ifp;
2984 struct mii_data *mii;
2988 uint32_t align_dummy;
2989 u_char eaddr[ETHER_ADDR_LEN];
2994 mii = device_get_softc(sc->rl_miibus);
2996 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3000 * Cancel pending I/O and free all RX/TX buffers.
3004 /* Put controller into known state. */
3008 * For C+ mode, initialize the RX descriptors and mbufs.
3010 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
3011 if (ifp->if_mtu > RL_MTU) {
3012 if (re_jrx_list_init(sc) != 0) {
3013 device_printf(sc->rl_dev,
3014 "no memory for jumbo RX buffers\n");
3018 /* Disable checksum offloading for jumbo frames. */
3019 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_TSO4);
3020 ifp->if_hwassist &= ~(RE_CSUM_FEATURES | CSUM_TSO);
3022 if (re_rx_list_init(sc) != 0) {
3023 device_printf(sc->rl_dev,
3024 "no memory for RX buffers\n");
3029 re_set_jumbo(sc, ifp->if_mtu > RL_MTU);
3031 if (re_rx_list_init(sc) != 0) {
3032 device_printf(sc->rl_dev, "no memory for RX buffers\n");
3036 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 &&
3037 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) {
3038 if (ifp->if_mtu > RL_MTU)
3039 pci_set_max_read_req(sc->rl_dev, 512);
3041 pci_set_max_read_req(sc->rl_dev, 4096);
3044 re_tx_list_init(sc);
3047 * Enable C+ RX and TX mode, as well as VLAN stripping and
3048 * RX checksum offload. We must configure the C+ register
3049 * before all others.
3051 cfg = RL_CPLUSCMD_PCI_MRW;
3052 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
3053 cfg |= RL_CPLUSCMD_RXCSUM_ENB;
3054 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3055 cfg |= RL_CPLUSCMD_VLANSTRIP;
3056 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) {
3057 cfg |= RL_CPLUSCMD_MACSTAT_DIS;
3061 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB;
3062 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg);
3063 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC ||
3064 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) {
3066 if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_PCI66MHZ) != 0)
3068 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE)
3070 CSR_WRITE_4(sc, 0x7c, reg);
3071 /* Disable interrupt mitigation. */
3072 CSR_WRITE_2(sc, 0xe2, 0);
3075 * Disable TSO if interface MTU size is greater than MSS
3076 * allowed in controller.
3078 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) {
3079 ifp->if_capenable &= ~IFCAP_TSO4;
3080 ifp->if_hwassist &= ~CSUM_TSO;
3084 * Init our MAC address. Even though the chipset
3085 * documentation doesn't mention it, we need to enter "Config
3086 * register write enable" mode to modify the ID registers.
3088 /* Copy MAC address on stack to align. */
3089 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN);
3090 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
3091 CSR_WRITE_4(sc, RL_IDR0,
3092 htole32(*(u_int32_t *)(&eaddr.eaddr[0])));
3093 CSR_WRITE_4(sc, RL_IDR4,
3094 htole32(*(u_int32_t *)(&eaddr.eaddr[4])));
3095 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3098 * Load the addresses of the RX and TX lists into the chip.
3101 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,
3102 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr));
3103 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,
3104 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr));
3106 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
3107 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr));
3108 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
3109 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
3112 * Set the initial TX configuration.
3114 if (sc->rl_testmode) {
3115 if (sc->rl_type == RL_8169)
3116 CSR_WRITE_4(sc, RL_TXCFG,
3117 RL_TXCFG_CONFIG|RL_LOOPTEST_ON);
3119 CSR_WRITE_4(sc, RL_TXCFG,
3120 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS);
3122 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
3124 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
3127 * Set the initial RX configuration.
3131 /* Configure interrupt moderation. */
3132 if (sc->rl_type == RL_8169) {
3133 /* Magic from vendor. */
3134 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100);
3138 * Enable transmit and receive.
3140 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB | RL_CMD_RX_ENB);
3142 #ifdef DEVICE_POLLING
3144 * Disable interrupts if we are polling.
3146 if (ifp->if_capenable & IFCAP_POLLING)
3147 CSR_WRITE_2(sc, RL_IMR, 0);
3148 else /* otherwise ... */
3152 * Enable interrupts.
3154 if (sc->rl_testmode)
3155 CSR_WRITE_2(sc, RL_IMR, 0);
3157 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
3158 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS);
3160 /* Set initial TX threshold */
3161 sc->rl_txthresh = RL_TX_THRESH_INIT;
3163 /* Start RX/TX process. */
3164 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
3167 * Initialize the timer interrupt register so that
3168 * a timer interrupt will be generated once the timer
3169 * reaches a certain number of ticks. The timer is
3170 * reloaded on each transmit.
3172 #ifdef RE_TX_MODERATION
3174 * Use timer interrupt register to moderate TX interrupt
3175 * moderation, which dramatically improves TX frame rate.
3177 if (sc->rl_type == RL_8169)
3178 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800);
3180 CSR_WRITE_4(sc, RL_TIMERINT, 0x400);
3183 * Use timer interrupt register to moderate RX interrupt
3186 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 &&
3188 if (sc->rl_type == RL_8169)
3189 CSR_WRITE_4(sc, RL_TIMERINT_8169,
3190 RL_USECS(sc->rl_int_rx_mod));
3192 if (sc->rl_type == RL_8169)
3193 CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0));
3198 * For 8169 gigE NICs, set the max allowed RX packet
3199 * size so we can receive jumbo frames.
3201 if (sc->rl_type == RL_8169) {
3202 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
3204 * For controllers that use new jumbo frame scheme,
3205 * set maximum size of jumbo frame depedning on
3206 * controller revisions.
3208 if (ifp->if_mtu > RL_MTU)
3209 CSR_WRITE_2(sc, RL_MAXRXPKTLEN,
3210 sc->rl_hwrev->rl_max_mtu +
3211 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN +
3214 CSR_WRITE_2(sc, RL_MAXRXPKTLEN,
3216 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 &&
3217 sc->rl_hwrev->rl_max_mtu == RL_MTU) {
3218 /* RTL810x has no jumbo frame support. */
3219 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN);
3221 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);
3224 if (sc->rl_testmode)
3227 CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) |
3230 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3231 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3233 sc->rl_flags &= ~RL_FLAG_LINK;
3236 sc->rl_watchdog_timer = 0;
3237 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
3241 * Set media options.
3244 re_ifmedia_upd(struct ifnet *ifp)
3246 struct rl_softc *sc;
3247 struct mii_data *mii;
3251 mii = device_get_softc(sc->rl_miibus);
3253 error = mii_mediachg(mii);
3260 * Report current media status.
3263 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3265 struct rl_softc *sc;
3266 struct mii_data *mii;
3269 mii = device_get_softc(sc->rl_miibus);
3273 ifmr->ifm_active = mii->mii_media_active;
3274 ifmr->ifm_status = mii->mii_media_status;
3279 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3281 struct rl_softc *sc = ifp->if_softc;
3282 struct ifreq *ifr = (struct ifreq *) data;
3283 struct mii_data *mii;
3289 if (ifr->ifr_mtu < ETHERMIN ||
3290 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu) {
3295 if (ifp->if_mtu != ifr->ifr_mtu) {
3296 ifp->if_mtu = ifr->ifr_mtu;
3297 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
3298 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
3299 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3302 if (ifp->if_mtu > RL_TSO_MTU &&
3303 (ifp->if_capenable & IFCAP_TSO4) != 0) {
3304 ifp->if_capenable &= ~(IFCAP_TSO4 |
3306 ifp->if_hwassist &= ~CSUM_TSO;
3308 VLAN_CAPABILITIES(ifp);
3314 if ((ifp->if_flags & IFF_UP) != 0) {
3315 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
3316 if (((ifp->if_flags ^ sc->rl_if_flags)
3317 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
3322 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3325 sc->rl_if_flags = ifp->if_flags;
3331 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3337 mii = device_get_softc(sc->rl_miibus);
3338 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3344 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3346 #ifdef DEVICE_POLLING
3347 if (mask & IFCAP_POLLING) {
3348 if (ifr->ifr_reqcap & IFCAP_POLLING) {
3349 error = ether_poll_register(re_poll, ifp);
3353 /* Disable interrupts */
3354 CSR_WRITE_2(sc, RL_IMR, 0x0000);
3355 ifp->if_capenable |= IFCAP_POLLING;
3358 error = ether_poll_deregister(ifp);
3359 /* Enable interrupts. */
3361 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
3362 ifp->if_capenable &= ~IFCAP_POLLING;
3366 #endif /* DEVICE_POLLING */
3368 if ((mask & IFCAP_TXCSUM) != 0 &&
3369 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
3370 ifp->if_capenable ^= IFCAP_TXCSUM;
3371 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) {
3372 rev = sc->rl_hwrev->rl_rev;
3373 if (rev == RL_HWREV_8168C ||
3374 rev == RL_HWREV_8168C_SPIN2 ||
3375 rev == RL_HWREV_8168CP)
3376 ifp->if_hwassist |= CSUM_TCP | CSUM_UDP;
3378 ifp->if_hwassist |= RE_CSUM_FEATURES;
3380 ifp->if_hwassist &= ~RE_CSUM_FEATURES;
3383 if ((mask & IFCAP_RXCSUM) != 0 &&
3384 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
3385 ifp->if_capenable ^= IFCAP_RXCSUM;
3388 if ((mask & IFCAP_TSO4) != 0 &&
3389 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
3390 ifp->if_capenable ^= IFCAP_TSO4;
3391 if ((IFCAP_TSO4 & ifp->if_capenable) != 0)
3392 ifp->if_hwassist |= CSUM_TSO;
3394 ifp->if_hwassist &= ~CSUM_TSO;
3395 if (ifp->if_mtu > RL_TSO_MTU &&
3396 (ifp->if_capenable & IFCAP_TSO4) != 0) {
3397 ifp->if_capenable &= ~IFCAP_TSO4;
3398 ifp->if_hwassist &= ~CSUM_TSO;
3401 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
3402 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
3403 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
3404 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
3405 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
3406 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3407 /* TSO over VLAN requires VLAN hardware tagging. */
3408 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
3409 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
3412 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
3413 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 |
3414 IFCAP_VLAN_HWTSO)) != 0)
3416 if ((mask & IFCAP_WOL) != 0 &&
3417 (ifp->if_capabilities & IFCAP_WOL) != 0) {
3418 if ((mask & IFCAP_WOL_UCAST) != 0)
3419 ifp->if_capenable ^= IFCAP_WOL_UCAST;
3420 if ((mask & IFCAP_WOL_MCAST) != 0)
3421 ifp->if_capenable ^= IFCAP_WOL_MCAST;
3422 if ((mask & IFCAP_WOL_MAGIC) != 0)
3423 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3425 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) {
3426 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3430 VLAN_CAPABILITIES(ifp);
3434 error = ether_ioctl(ifp, command, data);
3442 re_watchdog(struct rl_softc *sc)
3448 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0)
3453 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) {
3454 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
3456 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3457 re_start_locked(ifp);
3461 if_printf(ifp, "watchdog timeout\n");
3465 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3467 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3468 re_start_locked(ifp);
3472 * Stop the adapter and free any mbufs allocated to the
3476 re_stop(struct rl_softc *sc)
3480 struct rl_txdesc *txd;
3481 struct rl_rxdesc *rxd;
3487 sc->rl_watchdog_timer = 0;
3488 callout_stop(&sc->rl_stat_callout);
3489 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3492 * Disable accepting frames to put RX MAC into idle state.
3493 * Otherwise it's possible to get frames while stop command
3494 * execution is in progress and controller can DMA the frame
3495 * to already freed RX buffer during that period.
3497 CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) &
3498 ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI |
3499 RL_RXCFG_RX_BROAD));
3501 if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) {
3502 for (i = RL_TIMEOUT; i > 0; i--) {
3503 if ((CSR_READ_1(sc, sc->rl_txstart) &
3504 RL_TXSTART_START) == 0)
3509 device_printf(sc->rl_dev,
3510 "stopping TX poll timed out!\n");
3511 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
3512 } else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) {
3513 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB |
3515 if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) {
3516 for (i = RL_TIMEOUT; i > 0; i--) {
3517 if ((CSR_READ_4(sc, RL_TXCFG) &
3518 RL_TXCFG_QUEUE_EMPTY) != 0)
3523 device_printf(sc->rl_dev,
3524 "stopping TXQ timed out!\n");
3527 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
3529 CSR_WRITE_2(sc, RL_IMR, 0x0000);
3530 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
3532 if (sc->rl_head != NULL) {
3533 m_freem(sc->rl_head);
3534 sc->rl_head = sc->rl_tail = NULL;
3537 /* Free the TX list buffers. */
3538 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
3539 txd = &sc->rl_ldata.rl_tx_desc[i];
3540 if (txd->tx_m != NULL) {
3541 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
3542 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3543 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag,
3550 /* Free the RX list buffers. */
3551 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
3552 rxd = &sc->rl_ldata.rl_rx_desc[i];
3553 if (rxd->rx_m != NULL) {
3554 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag,
3555 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3556 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
3563 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
3564 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
3565 rxd = &sc->rl_ldata.rl_jrx_desc[i];
3566 if (rxd->rx_m != NULL) {
3567 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag,
3568 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3569 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag,
3579 * Device suspend routine. Stop the interface and save some PCI
3580 * settings in case the BIOS doesn't restore them properly on
3584 re_suspend(device_t dev)
3586 struct rl_softc *sc;
3588 sc = device_get_softc(dev);
3600 * Device resume routine. Restore some PCI settings in case the BIOS
3601 * doesn't, re-enable busmastering, and restart the interface if
3605 re_resume(device_t dev)
3607 struct rl_softc *sc;
3610 sc = device_get_softc(dev);
3615 /* Take controller out of sleep mode. */
3616 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
3617 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
3618 CSR_WRITE_1(sc, RL_GPIO,
3619 CSR_READ_1(sc, RL_GPIO) | 0x01);
3623 * Clear WOL matching such that normal Rx filtering
3624 * wouldn't interfere with WOL patterns.
3628 /* reinitialize interface if necessary */
3629 if (ifp->if_flags & IFF_UP)
3639 * Stop all chip I/O so that the kernel's probe routines don't
3640 * get confused by errant DMAs when rebooting.
3643 re_shutdown(device_t dev)
3645 struct rl_softc *sc;
3647 sc = device_get_softc(dev);
3652 * Mark interface as down since otherwise we will panic if
3653 * interrupt comes in later on, which can happen in some
3656 sc->rl_ifp->if_flags &= ~IFF_UP;
3664 re_set_linkspeed(struct rl_softc *sc)
3666 struct mii_softc *miisc;
3667 struct mii_data *mii;
3672 mii = device_get_softc(sc->rl_miibus);
3675 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
3676 (IFM_ACTIVE | IFM_AVALID)) {
3677 switch IFM_SUBTYPE(mii->mii_media_active) {
3688 miisc = LIST_FIRST(&mii->mii_phys);
3689 phyno = miisc->mii_phy;
3690 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3691 mii_phy_reset(miisc);
3692 re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0);
3693 re_miibus_writereg(sc->rl_dev, phyno,
3694 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
3695 re_miibus_writereg(sc->rl_dev, phyno,
3696 MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
3700 * Poll link state until re(4) get a 10/100Mbps link.
3702 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
3704 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
3705 == (IFM_ACTIVE | IFM_AVALID)) {
3706 switch (IFM_SUBTYPE(mii->mii_media_active)) {
3718 if (i == MII_ANEGTICKS_GIGE)
3719 device_printf(sc->rl_dev,
3720 "establishing a link failed, WOL may not work!");
3723 * No link, force MAC to have 100Mbps, full-duplex link.
3724 * MAC does not require reprogramming on resolved speed/duplex,
3725 * so this is just for completeness.
3727 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
3728 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
3732 re_setwol(struct rl_softc *sc)
3741 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
3745 /* Put controller into sleep mode. */
3746 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
3747 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
3748 CSR_WRITE_1(sc, RL_GPIO,
3749 CSR_READ_1(sc, RL_GPIO) & ~0x01);
3751 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
3753 if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0)
3754 re_set_linkspeed(sc);
3755 if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0)
3756 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB);
3758 /* Enable config register write. */
3759 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
3762 v = CSR_READ_1(sc, sc->rl_cfg1);
3764 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3766 CSR_WRITE_1(sc, sc->rl_cfg1, v);
3768 v = CSR_READ_1(sc, sc->rl_cfg3);
3769 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
3770 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3771 v |= RL_CFG3_WOL_MAGIC;
3772 CSR_WRITE_1(sc, sc->rl_cfg3, v);
3774 v = CSR_READ_1(sc, sc->rl_cfg5);
3775 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST |
3776 RL_CFG5_WOL_LANWAKE);
3777 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
3778 v |= RL_CFG5_WOL_UCAST;
3779 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
3780 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST;
3781 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3782 v |= RL_CFG5_WOL_LANWAKE;
3783 CSR_WRITE_1(sc, sc->rl_cfg5, v);
3785 /* Config register write done. */
3786 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3788 if ((ifp->if_capenable & IFCAP_WOL) == 0 &&
3789 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0)
3790 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80);
3792 * It seems that hardware resets its link speed to 100Mbps in
3793 * power down mode so switching to 100Mbps in driver is not
3797 /* Request PME if WOL is requested. */
3798 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2);
3799 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3800 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3801 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3802 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
3806 re_clrwol(struct rl_softc *sc)
3813 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
3816 /* Enable config register write. */
3817 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
3819 v = CSR_READ_1(sc, sc->rl_cfg3);
3820 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
3821 CSR_WRITE_1(sc, sc->rl_cfg3, v);
3823 /* Config register write done. */
3824 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3826 v = CSR_READ_1(sc, sc->rl_cfg5);
3827 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
3828 v &= ~RL_CFG5_WOL_LANWAKE;
3829 CSR_WRITE_1(sc, sc->rl_cfg5, v);
3833 re_add_sysctls(struct rl_softc *sc)
3835 struct sysctl_ctx_list *ctx;
3836 struct sysctl_oid_list *children;
3839 ctx = device_get_sysctl_ctx(sc->rl_dev);
3840 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev));
3842 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats",
3843 CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I",
3844 "Statistics Information");
3845 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0)
3848 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod",
3849 CTLTYPE_INT | CTLFLAG_RW, &sc->rl_int_rx_mod, 0,
3850 sysctl_hw_re_int_mod, "I", "re RX interrupt moderation");
3851 /* Pull in device tunables. */
3852 sc->rl_int_rx_mod = RL_TIMER_DEFAULT;
3853 error = resource_int_value(device_get_name(sc->rl_dev),
3854 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod);
3856 if (sc->rl_int_rx_mod < RL_TIMER_MIN ||
3857 sc->rl_int_rx_mod > RL_TIMER_MAX) {
3858 device_printf(sc->rl_dev, "int_rx_mod value out of "
3859 "range; using default: %d\n",
3861 sc->rl_int_rx_mod = RL_TIMER_DEFAULT;
3868 re_sysctl_stats(SYSCTL_HANDLER_ARGS)
3870 struct rl_softc *sc;
3871 struct rl_stats *stats;
3872 int error, i, result;
3875 error = sysctl_handle_int(oidp, &result, 0, req);
3876 if (error || req->newptr == NULL)
3880 sc = (struct rl_softc *)arg1;
3882 if ((sc->rl_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
3886 bus_dmamap_sync(sc->rl_ldata.rl_stag,
3887 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD);
3888 CSR_WRITE_4(sc, RL_DUMPSTATS_HI,
3889 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr));
3890 CSR_WRITE_4(sc, RL_DUMPSTATS_LO,
3891 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr));
3892 CSR_WRITE_4(sc, RL_DUMPSTATS_LO,
3893 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr |
3894 RL_DUMPSTATS_START));
3895 for (i = RL_TIMEOUT; i > 0; i--) {
3896 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) &
3897 RL_DUMPSTATS_START) == 0)
3901 bus_dmamap_sync(sc->rl_ldata.rl_stag,
3902 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD);
3905 device_printf(sc->rl_dev,
3906 "DUMP statistics request timedout\n");
3910 stats = sc->rl_ldata.rl_stats;
3911 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev));
3912 printf("Tx frames : %ju\n",
3913 (uintmax_t)le64toh(stats->rl_tx_pkts));
3914 printf("Rx frames : %ju\n",
3915 (uintmax_t)le64toh(stats->rl_rx_pkts));
3916 printf("Tx errors : %ju\n",
3917 (uintmax_t)le64toh(stats->rl_tx_errs));
3918 printf("Rx errors : %u\n",
3919 le32toh(stats->rl_rx_errs));
3920 printf("Rx missed frames : %u\n",
3921 (uint32_t)le16toh(stats->rl_missed_pkts));
3922 printf("Rx frame alignment errs : %u\n",
3923 (uint32_t)le16toh(stats->rl_rx_framealign_errs));
3924 printf("Tx single collisions : %u\n",
3925 le32toh(stats->rl_tx_onecoll));
3926 printf("Tx multiple collisions : %u\n",
3927 le32toh(stats->rl_tx_multicolls));
3928 printf("Rx unicast frames : %ju\n",
3929 (uintmax_t)le64toh(stats->rl_rx_ucasts));
3930 printf("Rx broadcast frames : %ju\n",
3931 (uintmax_t)le64toh(stats->rl_rx_bcasts));
3932 printf("Rx multicast frames : %u\n",
3933 le32toh(stats->rl_rx_mcasts));
3934 printf("Tx aborts : %u\n",
3935 (uint32_t)le16toh(stats->rl_tx_aborts));
3936 printf("Tx underruns : %u\n",
3937 (uint32_t)le16toh(stats->rl_rx_underruns));
3944 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3950 value = *(int *)arg1;
3951 error = sysctl_handle_int(oidp, &value, 0, req);
3952 if (error || req->newptr == NULL)
3954 if (value < low || value > high)
3956 *(int *)arg1 = value;
3962 sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS)
3965 return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN,