2 * Copyright (c) 1999 Seigo Tanimura
5 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in
6 * cwcealdr1.zip, the sample sources by Crystal Semiconductor.
7 * Copyright (c) 1996-1998 Crystal Semiconductor Corp.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
37 #include <machine/resource.h>
38 #include <machine/bus.h>
41 #ifdef HAVE_KERNEL_OPTION_HEADERS
45 #include <dev/sound/pcm/sound.h>
46 #include <dev/sound/chip.h>
47 #include <dev/sound/pci/csareg.h>
48 #include <dev/sound/pci/csavar.h>
50 #include <dev/pci/pcireg.h>
51 #include <dev/pci/pcivar.h>
53 #include <dev/sound/pci/cs461x_dsp.h>
55 SND_DECLARE_FILE("$FreeBSD$");
57 /* This is the pci device id. */
58 #define CS4610_PCI_ID 0x60011013
59 #define CS4614_PCI_ID 0x60031013
60 #define CS4615_PCI_ID 0x60041013
62 /* Here is the parameter structure per a device. */
64 device_t dev; /* device */
65 csa_res res; /* resources */
67 device_t pcm; /* pcm device */
68 driver_intr_t* pcmintr; /* pcm intr */
69 void *pcmintr_arg; /* pcm intr arg */
70 device_t midi; /* midi device */
71 driver_intr_t* midiintr; /* midi intr */
72 void *midiintr_arg; /* midi intr arg */
73 void *ih; /* cookie */
75 struct csa_card *card;
76 struct csa_bridgeinfo binfo; /* The state of this bridge. */
79 typedef struct csa_softc *sc_p;
81 static int csa_probe(device_t dev);
82 static int csa_attach(device_t dev);
83 static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid,
84 u_long start, u_long end, u_long count, u_int flags);
85 static int csa_release_resource(device_t bus, device_t child, int type, int rid,
87 static int csa_setup_intr(device_t bus, device_t child,
88 struct resource *irq, int flags,
89 #if __FreeBSD_version >= 700031
90 driver_filter_t *filter,
92 driver_intr_t *intr, void *arg, void **cookiep);
93 static int csa_teardown_intr(device_t bus, device_t child,
94 struct resource *irq, void *cookie);
95 static driver_intr_t csa_intr;
96 static int csa_initialize(sc_p scp);
97 static int csa_downloadimage(csa_res *resp);
98 static int csa_transferimage(csa_res *resp, u_int32_t *src, u_long dest, u_long len);
100 static devclass_t csa_devclass;
116 devclass_t pci_devclass;
117 device_t *pci_devices, *pci_children, *busp, *childp;
118 int pci_count = 0, pci_childcount = 0;
121 bus_space_tag_t btag;
123 if ((pci_devclass = devclass_find("pci")) == NULL) {
127 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
129 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
131 if (device_get_children(*busp, &pci_children, &pci_childcount))
133 for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) {
134 if (pci_get_vendor(*childp) == 0x8086 && pci_get_device(*childp) == 0x7113) {
135 port = (pci_read_config(*childp, 0x41, 1) << 8) + 0x10;
137 btag = I386_BUS_SPACE_IO;
139 control = bus_space_read_2(btag, 0x0, port);
141 control |= run? 0 : 0x2000;
142 bus_space_write_2(btag, 0x0, port, control);
143 free(pci_devices, M_TEMP);
144 free(pci_children, M_TEMP);
148 free(pci_children, M_TEMP);
151 free(pci_devices, M_TEMP);
158 static struct csa_card cards_4610[] = {
159 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0},
162 static struct csa_card cards_4614[] = {
163 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0},
164 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1},
165 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0},
166 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0},
167 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0},
168 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, NULL, 0},
169 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0},
170 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0},
171 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0},
174 static struct csa_card cards_4615[] = {
175 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0},
178 static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0};
183 struct csa_card *cards;
186 static struct card_type cards[] = {
187 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610},
188 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614},
189 {CS4615_PCI_ID, "CS4615", cards_4615},
193 static struct card_type *
194 csa_findcard(device_t dev)
199 while (cards[i].devid != 0) {
200 if (pci_get_devid(dev) == cards[i].devid)
208 csa_findsubcard(device_t dev)
211 struct card_type *card;
212 struct csa_card *subcard;
214 card = csa_findcard(dev);
217 subcard = card->cards;
219 while (subcard[i].subvendor != 0) {
220 if (pci_get_subvendor(dev) == subcard[i].subvendor
221 && pci_get_subdevice(dev) == subcard[i].subdevice) {
230 csa_probe(device_t dev)
232 struct card_type *card;
234 card = csa_findcard(dev);
236 device_set_desc(dev, card->name);
237 return BUS_PROBE_DEFAULT;
243 csa_attach(device_t dev)
248 struct sndcard_func *func;
251 scp = device_get_softc(dev);
253 /* Fill in the softc. */
254 bzero(scp, sizeof(*scp));
257 /* Wake up the device. */
258 stcmd = pci_read_config(dev, PCIR_COMMAND, 2);
259 if ((stcmd & PCIM_CMD_MEMEN) == 0 || (stcmd & PCIM_CMD_BUSMASTEREN) == 0) {
260 stcmd |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
261 pci_write_config(dev, PCIR_COMMAND, stcmd, 2);
264 /* Allocate the resources. */
266 scp->card = csa_findsubcard(dev);
267 scp->binfo.card = scp->card;
268 printf("csa: card is %s\n", scp->card->name);
269 resp->io_rid = PCIR_BAR(0);
270 resp->io = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
271 &resp->io_rid, RF_ACTIVE);
272 if (resp->io == NULL)
274 resp->mem_rid = PCIR_BAR(1);
275 resp->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
276 &resp->mem_rid, RF_ACTIVE);
277 if (resp->mem == NULL)
280 resp->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
281 &resp->irq_rid, RF_ACTIVE | RF_SHAREABLE);
282 if (resp->irq == NULL)
285 /* Enable interrupt. */
286 if (snd_setup_intr(dev, resp->irq, 0, csa_intr, scp, &scp->ih))
289 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0)
290 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
293 /* Initialize the chip. */
294 if (csa_initialize(scp))
297 /* Reset the Processor. */
300 /* Download the Processor Image to the processor. */
301 if (csa_downloadimage(resp))
304 /* Attach the children. */
307 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO);
312 func->varinfo = &scp->binfo;
313 func->func = SCF_PCM;
314 scp->pcm = device_add_child(dev, "pcm", -1);
315 device_set_ivars(scp->pcm, func);
318 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO);
323 func->varinfo = &scp->binfo;
324 func->func = SCF_MIDI;
325 scp->midi = device_add_child(dev, "midi", -1);
326 device_set_ivars(scp->midi, func);
328 bus_generic_attach(dev);
333 bus_teardown_intr(dev, resp->irq, scp->ih);
335 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq);
337 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
339 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
344 csa_detach(device_t dev)
348 struct sndcard_func *func;
351 scp = device_get_softc(dev);
354 if (scp->midi != NULL) {
355 func = device_get_ivars(scp->midi);
356 err = device_delete_child(dev, scp->midi);
360 free(func, M_DEVBUF);
364 if (scp->pcm != NULL) {
365 func = device_get_ivars(scp->pcm);
366 err = device_delete_child(dev, scp->pcm);
370 free(func, M_DEVBUF);
374 bus_teardown_intr(dev, resp->irq, scp->ih);
375 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq);
376 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
377 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
379 return bus_generic_detach(dev);
383 csa_resume(device_t dev)
388 scp = device_get_softc(dev);
391 /* Initialize the chip. */
392 if (csa_initialize(scp))
395 /* Reset the Processor. */
398 /* Download the Processor Image to the processor. */
399 if (csa_downloadimage(resp))
402 return (bus_generic_resume(dev));
405 static struct resource *
406 csa_alloc_resource(device_t bus, device_t child, int type, int *rid,
407 u_long start, u_long end, u_long count, u_int flags)
411 struct resource *res;
413 scp = device_get_softc(bus);
441 csa_release_resource(device_t bus, device_t child, int type, int rid,
448 * The following three functions deal with interrupt handling.
449 * An interrupt is primarily handled by the bridge driver.
450 * The bridge driver then determines the child devices to pass
451 * the interrupt. Certain information of the device can be read
452 * only once(eg the value of HISR). The bridge driver is responsible
453 * to pass such the information to the children.
457 csa_setup_intr(device_t bus, device_t child,
458 struct resource *irq, int flags,
459 #if __FreeBSD_version >= 700031
460 driver_filter_t *filter,
462 driver_intr_t *intr, void *arg, void **cookiep)
466 struct sndcard_func *func;
468 #if __FreeBSD_version >= 700031
469 if (filter != NULL) {
470 printf("ata-csa.c: we cannot use a filter here\n");
474 scp = device_get_softc(bus);
478 * Look at the function code of the child to determine
479 * the appropriate hander for it.
481 func = device_get_ivars(child);
482 if (func == NULL || irq != resp->irq)
485 switch (func->func) {
488 scp->pcmintr_arg = arg;
492 scp->midiintr = intr;
493 scp->midiintr_arg = arg;
500 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0)
501 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
507 csa_teardown_intr(device_t bus, device_t child,
508 struct resource *irq, void *cookie)
512 struct sndcard_func *func;
514 scp = device_get_softc(bus);
518 * Look at the function code of the child to determine
519 * the appropriate hander for it.
521 func = device_get_ivars(child);
522 if (func == NULL || irq != resp->irq || cookie != scp)
525 switch (func->func) {
528 scp->pcmintr_arg = NULL;
532 scp->midiintr = NULL;
533 scp->midiintr_arg = NULL;
543 /* The interrupt handler */
553 /* Is this interrupt for us? */
554 hisr = csa_readio(resp, BA0_HISR);
555 if ((hisr & 0x7fffffff) == 0) {
557 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
562 * Pass the value of HISR via struct csa_bridgeinfo.
563 * The children get access through their ivars.
565 scp->binfo.hisr = hisr;
567 /* Invoke the handlers of the children. */
568 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) {
569 scp->pcmintr(scp->pcmintr_arg);
570 hisr &= ~(HISR_VC0 | HISR_VC1);
572 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) {
573 scp->midiintr(scp->midiintr_arg);
578 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
582 csa_initialize(sc_p scp)
585 u_int32_t acsts, acisv;
591 * First, blast the clock control register to zero so that the PLL starts
592 * out in a known state, and blast the master serial port control register
593 * to zero so that the serial ports also start out in a known state.
595 csa_writeio(resp, BA0_CLKCR1, 0);
596 csa_writeio(resp, BA0_SERMC1, 0);
599 * If we are in AC97 mode, then we must set the part to a host controlled
600 * AC-link. Otherwise, we won't be able to bring up the link.
603 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */
605 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */
609 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
610 * spec) and then drive it high. This is done for non AC97 modes since
611 * there might be logic external to the CS461x that uses the ARST# line
614 csa_writeio(resp, BA0_ACCTL, 1);
616 csa_writeio(resp, BA0_ACCTL, 0);
618 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN);
621 * The first thing we do here is to enable sync generation. As soon
622 * as we start receiving bit clock, we'll start producing the SYNC
625 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
628 * Now wait for a short while to allow the AC97 part to start
629 * generating bit clock (so we don't try to start the PLL without an
635 * Set the serial port timing configuration, so that
636 * the clock control circuit gets its clock from the correct place.
638 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97);
642 * Write the selected clock control setup to the hardware. Do not turn on
643 * SWCE yet (if requested), so that the devices clocked by the output of
644 * PLL are not clocked until the PLL is stable.
646 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
647 csa_writeio(resp, BA0_PLLM, 0x3a);
648 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8);
653 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP);
656 * Wait until the PLL has stabilized.
661 * Turn on clocking of the core so that we can setup the serial ports.
663 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE);
666 * Fill the serial port FIFOs with silence.
668 csa_clearserialfifos(resp);
671 * Set the serial port FIFO pointer to the first sample in the FIFO.
674 csa_writeio(resp, BA0_SERBSP, 0);
678 * Write the serial port configuration to the part. The master
679 * enable bit is not set until all other values have been written.
681 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
682 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
683 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
686 * Wait for the codec ready signal from the AC97 codec.
689 for (i = 0 ; i < 1000 ; i++) {
691 * First, lets wait a short while to let things settle out a bit,
692 * and to prevent retrying the read too quickly.
697 * Read the AC97 status register to see if we've seen a CODEC READY
698 * signal from the AC97 codec.
700 acsts = csa_readio(resp, BA0_ACSTS);
701 if ((acsts & ACSTS_CRDY) != 0)
706 * Make sure we sampled CODEC READY.
708 if ((acsts & ACSTS_CRDY) == 0)
712 * Assert the vaid frame signal so that we can start sending commands
715 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
718 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
719 * the codec is pumping ADC data across the AC-link.
722 for (i = 0 ; i < 2000 ; i++) {
724 * First, lets wait a short while to let things settle out a bit,
725 * and to prevent retrying the read too quickly.
728 DELAY(10000000L); /* clw */
733 * Read the input slot valid register and see if input slots 3 and
736 acisv = csa_readio(resp, BA0_ACISV);
737 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
741 * Make sure we sampled valid input slots 3 and 4. If not, then return
744 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4))
748 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
749 * commense the transfer of digital audio data to the AC97 codec.
751 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
754 * Power down the DAC and ADC. We will power them up (if) when we need
758 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300);
762 * Turn off the Processor by turning off the software clock enable flag in
763 * the clock control register.
766 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE;
767 csa_writeio(resp, BA0_CLKCR1, clkcr1);
771 * Enable interrupts on the part.
774 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
781 csa_clearserialfifos(csa_res *resp)
784 u_int8_t clkcr1, serbst;
787 * See if the devices are powered down. If so, we must power them up first
788 * or they will not respond.
791 clkcr1 = csa_readio(resp, BA0_CLKCR1);
792 if ((clkcr1 & CLKCR1_SWCE) == 0) {
793 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE);
798 * We want to clear out the serial port FIFOs so we don't end up playing
799 * whatever random garbage happens to be in them. We fill the sample FIFOs
800 * with zero (silence).
802 csa_writeio(resp, BA0_SERBWP, 0);
804 /* Fill all 256 sample FIFO locations. */
806 for (i = 0 ; i < 256 ; i++) {
807 /* Make sure the previous FIFO write operation has completed. */
808 for (j = 0 ; j < 5 ; j++) {
810 serbst = csa_readio(resp, BA0_SERBST);
811 if ((serbst & SERBST_WBSY) == 0)
814 if ((serbst & SERBST_WBSY) != 0) {
816 csa_writeio(resp, BA0_CLKCR1, clkcr1);
818 /* Write the serial port FIFO index. */
819 csa_writeio(resp, BA0_SERBAD, i);
820 /* Tell the serial port to load the new value into the FIFO location. */
821 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC);
824 * Now, if we powered up the devices, then power them back down again.
825 * This is kinda ugly, but should never happen.
828 csa_writeio(resp, BA0_CLKCR1, clkcr1);
832 csa_resetdsp(csa_res *resp)
837 * Write the reset bit of the SP control register.
839 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP);
842 * Write the control register.
844 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN);
847 * Clear the trap registers.
849 for (i = 0 ; i < 8 ; i++) {
850 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i);
851 csa_writemem(resp, BA1_TWPR, 0xffff);
853 csa_writemem(resp, BA1_DREG, 0);
856 * Set the frame timer to reflect the number of cycles per frame.
858 csa_writemem(resp, BA1_FRMT, 0xadf);
862 csa_downloadimage(csa_res *resp)
867 for (ul = 0, offset = 0 ; ul < INKY_MEMORY_COUNT ; ul++) {
869 * DMA this block from host memory to the appropriate
870 * memory on the CSDevice.
872 ret = csa_transferimage(resp,
873 cs461x_firmware.BA1Array + offset,
874 cs461x_firmware.MemoryStat[ul].ulDestAddr,
875 cs461x_firmware.MemoryStat[ul].ulSourceSize);
878 offset += cs461x_firmware.MemoryStat[ul].ulSourceSize >> 2;
884 csa_transferimage(csa_res *resp, u_int32_t *src, u_long dest, u_long len)
889 * We do not allow DMAs from host memory to host memory (although the DMA
890 * can do it) and we do not allow DMAs which are not a multiple of 4 bytes
891 * in size (because that DMA can not do that). Return an error if either
892 * of these conditions exist.
894 if ((len & 0x3) != 0)
897 /* Check the destination address that it is a multiple of 4 */
898 if ((dest & 0x3) != 0)
901 /* Write the buffer out. */
902 for (ul = 0 ; ul < len ; ul += 4)
903 csa_writemem(resp, dest + ul, src[ul >> 2]);
908 csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data)
911 u_int32_t acctl, acsts;
914 * Make sure that there is not data sitting around from a previous
915 * uncompleted access. ACSDA = Status Data Register = 47Ch
917 csa_readio(resp, BA0_ACSDA);
920 * Setup the AC97 control registers on the CS461x to send the
921 * appropriate command to the AC97 to perform the read.
922 * ACCAD = Command Address Register = 46Ch
923 * ACCDA = Command Data Register = 470h
924 * ACCTL = Control Register = 460h
925 * set DCV - will clear when process completed
926 * set CRW - Read command
927 * set VFRM - valid frame enabled
928 * set ESYN - ASYNC generation enabled
929 * set RSTN - ARST# inactive, AC97 codec not reset
933 * Get the actual AC97 register from the offset
935 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET);
936 csa_writeio(resp, BA0_ACCDA, 0);
937 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
940 * Wait for the read to occur.
943 for (i = 0 ; i < 10 ; i++) {
945 * First, we want to wait for a short time.
950 * Now, check to see if the read has completed.
951 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
953 acctl = csa_readio(resp, BA0_ACCTL);
954 if ((acctl & ACCTL_DCV) == 0)
959 * Make sure the read completed.
961 if ((acctl & ACCTL_DCV) != 0)
965 * Wait for the valid status bit to go active.
968 for (i = 0 ; i < 10 ; i++) {
970 * Read the AC97 status register.
971 * ACSTS = Status Register = 464h
973 acsts = csa_readio(resp, BA0_ACSTS);
975 * See if we have valid status.
976 * VSTS - Valid Status
978 if ((acsts & ACSTS_VSTS) != 0)
981 * Wait for a short while.
987 * Make sure we got valid status.
989 if ((acsts & ACSTS_VSTS) == 0)
993 * Read the data returned from the AC97 register.
994 * ACSDA = Status Data Register = 474h
996 *data = csa_readio(resp, BA0_ACSDA);
1002 csa_writecodec(csa_res *resp, u_long offset, u_int32_t data)
1008 * Setup the AC97 control registers on the CS461x to send the
1009 * appropriate command to the AC97 to perform the write.
1010 * ACCAD = Command Address Register = 46Ch
1011 * ACCDA = Command Data Register = 470h
1012 * ACCTL = Control Register = 460h
1013 * set DCV - will clear when process completed
1014 * set VFRM - valid frame enabled
1015 * set ESYN - ASYNC generation enabled
1016 * set RSTN - ARST# inactive, AC97 codec not reset
1020 * Get the actual AC97 register from the offset
1022 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET);
1023 csa_writeio(resp, BA0_ACCDA, data);
1024 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
1027 * Wait for the write to occur.
1030 for (i = 0 ; i < 10 ; i++) {
1032 * First, we want to wait for a short time.
1037 * Now, check to see if the read has completed.
1038 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
1040 acctl = csa_readio(resp, BA0_ACCTL);
1041 if ((acctl & ACCTL_DCV) == 0)
1046 * Make sure the write completed.
1048 if ((acctl & ACCTL_DCV) != 0)
1055 csa_readio(csa_res *resp, u_long offset)
1059 if (offset < BA0_AC97_RESET)
1060 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff;
1062 if (csa_readcodec(resp, offset, &ul))
1069 csa_writeio(csa_res *resp, u_long offset, u_int32_t data)
1071 if (offset < BA0_AC97_RESET)
1072 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data);
1074 csa_writecodec(resp, offset, data);
1078 csa_readmem(csa_res *resp, u_long offset)
1080 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset);
1084 csa_writemem(csa_res *resp, u_long offset, u_int32_t data)
1086 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data);
1089 static device_method_t csa_methods[] = {
1090 /* Device interface */
1091 DEVMETHOD(device_probe, csa_probe),
1092 DEVMETHOD(device_attach, csa_attach),
1093 DEVMETHOD(device_detach, csa_detach),
1094 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1095 DEVMETHOD(device_suspend, bus_generic_suspend),
1096 DEVMETHOD(device_resume, csa_resume),
1099 DEVMETHOD(bus_alloc_resource, csa_alloc_resource),
1100 DEVMETHOD(bus_release_resource, csa_release_resource),
1101 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1102 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1103 DEVMETHOD(bus_setup_intr, csa_setup_intr),
1104 DEVMETHOD(bus_teardown_intr, csa_teardown_intr),
1109 static driver_t csa_driver = {
1112 sizeof(struct csa_softc),
1116 * csa can be attached to a pci bus.
1118 DRIVER_MODULE(snd_csa, pci, csa_driver, csa_devclass, 0, 0);
1119 MODULE_DEPEND(snd_csa, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1120 MODULE_VERSION(snd_csa, 1);