2 * Copyright (c) 1999 Cameron Grant <cg@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
27 #ifdef HAVE_KERNEL_OPTION_HEADERS
31 #include <dev/sound/pcm/sound.h>
32 #include <dev/sound/pcm/ac97.h>
33 #include <dev/sound/pci/t4dwave.h>
35 #include <dev/pci/pcireg.h>
36 #include <dev/pci/pcivar.h>
38 SND_DECLARE_FILE("$FreeBSD$");
40 /* -------------------------------------------------------------------- */
42 #define TDX_PCI_ID 0x20001023
43 #define TNX_PCI_ID 0x20011023
44 #define ALI_PCI_ID 0x545110b9
45 #define SPA_PCI_ID 0x70181039
47 #define TR_DEFAULT_BUFSZ 0x1000
48 #define TR_TIMEOUT_CDC 0xffff
49 #define TR_MAXPLAYCH 4
51 * Though, it's not clearly documented in trident datasheet, trident
52 * audio cards can't handle DMA addresses located above 1GB. The LBA
53 * (loop begin address) register which holds DMA base address is 32bits
55 * But the MSB 2bits are used for other purposes(I guess it is really
56 * bad idea). This effectivly limits the DMA address space up to 1GB.
58 #define TR_MAXADDR ((1 << 30) - 1)
63 /* channel registers */
65 u_int32_t cso, alpha, fms, fmc, ec;
69 u_int32_t gvsel, pan, vol, ctrl;
70 u_int32_t active:1, was_active:1;
72 struct snd_dbuf *buffer;
73 struct pcm_channel *channel;
74 struct tr_info *parent;
79 u_int32_t active:1, was_active:1;
80 struct snd_dbuf *buffer;
81 struct pcm_channel *channel;
82 struct tr_info *parent;
85 /* device private data */
91 bus_space_handle_t sh;
92 bus_dma_tag_t parent_dmat;
94 struct resource *reg, *irq;
95 int regtype, regid, irqid;
103 struct tr_chinfo chinfo[TR_MAXPLAYCH];
104 struct tr_rchinfo recchinfo;
107 /* -------------------------------------------------------------------- */
109 static u_int32_t tr_recfmt[] = {
110 SND_FORMAT(AFMT_U8, 1, 0),
111 SND_FORMAT(AFMT_U8, 2, 0),
112 SND_FORMAT(AFMT_S8, 1, 0),
113 SND_FORMAT(AFMT_S8, 2, 0),
114 SND_FORMAT(AFMT_S16_LE, 1, 0),
115 SND_FORMAT(AFMT_S16_LE, 2, 0),
116 SND_FORMAT(AFMT_U16_LE, 1, 0),
117 SND_FORMAT(AFMT_U16_LE, 2, 0),
120 static struct pcmchan_caps tr_reccaps = {4000, 48000, tr_recfmt, 0};
122 static u_int32_t tr_playfmt[] = {
123 SND_FORMAT(AFMT_U8, 1, 0),
124 SND_FORMAT(AFMT_U8, 2, 0),
125 SND_FORMAT(AFMT_S8, 1, 0),
126 SND_FORMAT(AFMT_S8, 2, 0),
127 SND_FORMAT(AFMT_S16_LE, 1, 0),
128 SND_FORMAT(AFMT_S16_LE, 2, 0),
129 SND_FORMAT(AFMT_U16_LE, 1, 0),
130 SND_FORMAT(AFMT_U16_LE, 2, 0),
133 static struct pcmchan_caps tr_playcaps = {4000, 48000, tr_playfmt, 0};
135 /* -------------------------------------------------------------------- */
140 tr_rd(struct tr_info *tr, int regno, int size)
144 return bus_space_read_1(tr->st, tr->sh, regno);
146 return bus_space_read_2(tr->st, tr->sh, regno);
148 return bus_space_read_4(tr->st, tr->sh, regno);
155 tr_wr(struct tr_info *tr, int regno, u_int32_t data, int size)
159 bus_space_write_1(tr->st, tr->sh, regno, data);
162 bus_space_write_2(tr->st, tr->sh, regno, data);
165 bus_space_write_4(tr->st, tr->sh, regno, data);
170 /* -------------------------------------------------------------------- */
174 tr_rdcd(kobj_t obj, void *devinfo, int regno)
176 struct tr_info *tr = (struct tr_info *)devinfo;
181 treg=SPA_REG_CODECRD;
186 treg=TDX_REG_CODECWR;
188 treg=TDX_REG_CODECRD;
192 treg=TDX_REG_CODECRD;
196 treg=(regno & 0x100)? TNX_REG_CODEC2RD : TNX_REG_CODEC1RD;
200 printf("!!! tr_rdcd defaulted !!!\n");
207 snd_mtxlock(tr->lock);
208 if (tr->type == ALI_PCI_ID) {
209 u_int32_t chk1, chk2;
211 for (i = TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--)
212 j = tr_rd(tr, treg, 4);
214 chk1 = tr_rd(tr, 0xc8, 4);
215 chk2 = tr_rd(tr, 0xc8, 4);
216 for (i = TR_TIMEOUT_CDC; (i > 0) && (chk1 == chk2);
218 chk2 = tr_rd(tr, 0xc8, 4);
221 if (tr->type != ALI_PCI_ID || i > 0) {
222 tr_wr(tr, treg, regno | trw, 4);
224 for (i=TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--)
225 j=tr_rd(tr, treg, 4);
227 snd_mtxunlock(tr->lock);
228 if (i == 0) printf("codec timeout during read of register %x\n", regno);
229 return (j >> TR_CDC_DATA) & 0xffff;
233 tr_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data)
235 struct tr_info *tr = (struct tr_info *)devinfo;
240 treg=SPA_REG_CODECWR;
245 treg=TDX_REG_CODECWR;
249 treg=TNX_REG_CODECWR;
250 trw=TNX_CDC_RWSTAT | ((regno & 0x100)? TNX_CDC_SEC : 0);
253 printf("!!! tr_wrcd defaulted !!!");
261 printf("tr_wrcd: reg %x was %x", regno, tr_rdcd(devinfo, regno));
264 snd_mtxlock(tr->lock);
265 if (tr->type == ALI_PCI_ID) {
267 for (i = TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--)
268 j = tr_rd(tr, treg, 4);
270 u_int32_t chk1, chk2;
271 chk1 = tr_rd(tr, 0xc8, 4);
272 chk2 = tr_rd(tr, 0xc8, 4);
273 for (i = TR_TIMEOUT_CDC; (i > 0) && (chk1 == chk2);
275 chk2 = tr_rd(tr, 0xc8, 4);
278 if (tr->type != ALI_PCI_ID || i > 0) {
279 for (i=TR_TIMEOUT_CDC; (i>0) && (j & trw); i--)
280 j=tr_rd(tr, treg, 4);
281 if (tr->type == ALI_PCI_ID && tr->rev > 0x01)
283 tr_wr(tr, treg, (data << TR_CDC_DATA) | regno | trw, 4);
286 printf(" - wrote %x, now %x\n", data, tr_rdcd(devinfo, regno));
288 snd_mtxunlock(tr->lock);
289 if (i==0) printf("codec timeout writing %x, data %x\n", regno, data);
290 return (i > 0)? 0 : -1;
293 static kobj_method_t tr_ac97_methods[] = {
294 KOBJMETHOD(ac97_read, tr_rdcd),
295 KOBJMETHOD(ac97_write, tr_wrcd),
298 AC97_DECLARE(tr_ac97);
300 /* -------------------------------------------------------------------- */
301 /* playback channel interrupts */
305 tr_testint(struct tr_chinfo *ch)
307 struct tr_info *tr = ch->parent;
310 bank = (ch->index & 0x20) ? 1 : 0;
311 chan = ch->index & 0x1f;
312 return tr_rd(tr, bank? TR_REG_ADDRINTB : TR_REG_ADDRINTA, 4) & (1 << chan);
317 tr_clrint(struct tr_chinfo *ch)
319 struct tr_info *tr = ch->parent;
322 bank = (ch->index & 0x20) ? 1 : 0;
323 chan = ch->index & 0x1f;
324 tr_wr(tr, bank? TR_REG_ADDRINTB : TR_REG_ADDRINTA, 1 << chan, 4);
328 tr_enaint(struct tr_chinfo *ch, int enable)
330 struct tr_info *tr = ch->parent;
334 snd_mtxlock(tr->lock);
335 bank = (ch->index & 0x20) ? 1 : 0;
336 chan = ch->index & 0x1f;
337 reg = bank? TR_REG_INTENB : TR_REG_INTENA;
339 i = tr_rd(tr, reg, 4);
341 i |= (enable? 1 : 0) << chan;
344 tr_wr(tr, reg, i, 4);
345 snd_mtxunlock(tr->lock);
348 /* playback channels */
351 tr_selch(struct tr_chinfo *ch)
353 struct tr_info *tr = ch->parent;
356 i = tr_rd(tr, TR_REG_CIR, 4);
358 i |= ch->index & 0x3f;
359 tr_wr(tr, TR_REG_CIR, i, 4);
363 tr_startch(struct tr_chinfo *ch)
365 struct tr_info *tr = ch->parent;
368 bank = (ch->index & 0x20) ? 1 : 0;
369 chan = ch->index & 0x1f;
370 tr_wr(tr, bank? TR_REG_STARTB : TR_REG_STARTA, 1 << chan, 4);
374 tr_stopch(struct tr_chinfo *ch)
376 struct tr_info *tr = ch->parent;
379 bank = (ch->index & 0x20) ? 1 : 0;
380 chan = ch->index & 0x1f;
381 tr_wr(tr, bank? TR_REG_STOPB : TR_REG_STOPA, 1 << chan, 4);
385 tr_wrch(struct tr_chinfo *ch)
387 struct tr_info *tr = ch->parent;
388 u_int32_t cr[TR_CHN_REGS], i;
390 ch->gvsel &= 0x00000001;
391 ch->fmc &= 0x00000003;
392 ch->fms &= 0x0000000f;
393 ch->ctrl &= 0x0000000f;
394 ch->pan &= 0x0000007f;
395 ch->rvol &= 0x0000007f;
396 ch->cvol &= 0x0000007f;
397 ch->vol &= 0x000000ff;
398 ch->ec &= 0x00000fff;
399 ch->alpha &= 0x00000fff;
400 ch->delta &= 0x0000ffff;
401 ch->lba &= 0x3fffffff;
404 cr[3]=(ch->fmc<<14) | (ch->rvol<<7) | (ch->cvol);
405 cr[4]=(ch->gvsel<<31) | (ch->pan<<24) | (ch->vol<<16) | (ch->ctrl<<12) | (ch->ec);
411 ch->cso &= 0x0000ffff;
412 ch->eso &= 0x0000ffff;
413 cr[0]=(ch->cso<<16) | (ch->alpha<<4) | (ch->fms);
414 cr[2]=(ch->eso<<16) | (ch->delta);
417 ch->cso &= 0x00ffffff;
418 ch->eso &= 0x00ffffff;
419 cr[0]=((ch->delta & 0xff)<<24) | (ch->cso);
420 cr[2]=((ch->delta>>8)<<24) | (ch->eso);
421 cr[3]|=(ch->alpha<<20) | (ch->fms<<16) | (ch->fmc<<14);
424 snd_mtxlock(tr->lock);
426 for (i=0; i<TR_CHN_REGS; i++)
427 tr_wr(tr, TR_REG_CHNBASE+(i<<2), cr[i], 4);
428 snd_mtxunlock(tr->lock);
432 tr_rdch(struct tr_chinfo *ch)
434 struct tr_info *tr = ch->parent;
437 snd_mtxlock(tr->lock);
440 cr[i]=tr_rd(tr, TR_REG_CHNBASE+(i<<2), 4);
441 snd_mtxunlock(tr->lock);
444 ch->lba= (cr[1] & 0x3fffffff);
445 ch->fmc= (cr[3] & 0x0000c000) >> 14;
446 ch->rvol= (cr[3] & 0x00003f80) >> 7;
447 ch->cvol= (cr[3] & 0x0000007f);
448 ch->gvsel= (cr[4] & 0x80000000) >> 31;
449 ch->pan= (cr[4] & 0x7f000000) >> 24;
450 ch->vol= (cr[4] & 0x00ff0000) >> 16;
451 ch->ctrl= (cr[4] & 0x0000f000) >> 12;
452 ch->ec= (cr[4] & 0x00000fff);
457 ch->cso= (cr[0] & 0xffff0000) >> 16;
458 ch->alpha= (cr[0] & 0x0000fff0) >> 4;
459 ch->fms= (cr[0] & 0x0000000f);
460 ch->eso= (cr[2] & 0xffff0000) >> 16;
461 ch->delta= (cr[2] & 0x0000ffff);
464 ch->cso= (cr[0] & 0x00ffffff);
465 ch->eso= (cr[2] & 0x00ffffff);
466 ch->delta= ((cr[2] & 0xff000000) >> 16) | ((cr[0] & 0xff000000) >> 24);
467 ch->alpha= (cr[3] & 0xfff00000) >> 20;
468 ch->fms= (cr[3] & 0x000f0000) >> 16;
474 tr_fmttobits(u_int32_t fmt)
479 bits |= (fmt & AFMT_SIGNED)? 0x2 : 0;
480 bits |= (AFMT_CHANNEL(fmt) > 1)? 0x4 : 0;
481 bits |= (fmt & AFMT_16BIT)? 0x8 : 0;
486 /* -------------------------------------------------------------------- */
487 /* channel interface */
490 trpchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
492 struct tr_info *tr = devinfo;
493 struct tr_chinfo *ch;
495 KASSERT(dir == PCMDIR_PLAY, ("trpchan_init: bad direction"));
496 ch = &tr->chinfo[tr->playchns];
497 ch->index = tr->playchns++;
501 if (sndbuf_alloc(ch->buffer, tr->parent_dmat, 0, tr->bufsz) != 0)
508 trpchan_setformat(kobj_t obj, void *data, u_int32_t format)
510 struct tr_chinfo *ch = data;
512 ch->ctrl = tr_fmttobits(format) | 0x01;
518 trpchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
520 struct tr_chinfo *ch = data;
522 ch->delta = (speed << 12) / 48000;
523 return (ch->delta * 48000) >> 12;
527 trpchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
529 struct tr_chinfo *ch = data;
531 sndbuf_resize(ch->buffer, 2, blocksize);
536 trpchan_trigger(kobj_t obj, void *data, int go)
538 struct tr_chinfo *ch = data;
540 if (!PCMTRIG_COMMON(go))
543 if (go == PCMTRIG_START) {
548 ch->lba = sndbuf_getbufaddr(ch->buffer);
550 ch->eso = (sndbuf_getsize(ch->buffer) / sndbuf_getalign(ch->buffer)) - 1;
551 ch->rvol = ch->cvol = 0x7f;
569 trpchan_getptr(kobj_t obj, void *data)
571 struct tr_chinfo *ch = data;
574 return ch->cso * sndbuf_getalign(ch->buffer);
577 static struct pcmchan_caps *
578 trpchan_getcaps(kobj_t obj, void *data)
583 static kobj_method_t trpchan_methods[] = {
584 KOBJMETHOD(channel_init, trpchan_init),
585 KOBJMETHOD(channel_setformat, trpchan_setformat),
586 KOBJMETHOD(channel_setspeed, trpchan_setspeed),
587 KOBJMETHOD(channel_setblocksize, trpchan_setblocksize),
588 KOBJMETHOD(channel_trigger, trpchan_trigger),
589 KOBJMETHOD(channel_getptr, trpchan_getptr),
590 KOBJMETHOD(channel_getcaps, trpchan_getcaps),
593 CHANNEL_DECLARE(trpchan);
595 /* -------------------------------------------------------------------- */
596 /* rec channel interface */
599 trrchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
601 struct tr_info *tr = devinfo;
602 struct tr_rchinfo *ch;
604 KASSERT(dir == PCMDIR_REC, ("trrchan_init: bad direction"));
609 if (sndbuf_alloc(ch->buffer, tr->parent_dmat, 0, tr->bufsz) != 0)
616 trrchan_setformat(kobj_t obj, void *data, u_int32_t format)
618 struct tr_rchinfo *ch = data;
619 struct tr_info *tr = ch->parent;
622 bits = tr_fmttobits(format);
623 /* set # of samples between interrupts */
624 i = (sndbuf_runsz(ch->buffer) >> ((bits & 0x08)? 1 : 0)) - 1;
625 tr_wr(tr, TR_REG_SBBL, i | (i << 16), 4);
626 /* set sample format */
627 i = 0x18 | (bits << 4);
628 tr_wr(tr, TR_REG_SBCTRL, i, 1);
635 trrchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
637 struct tr_rchinfo *ch = data;
638 struct tr_info *tr = ch->parent;
641 ch->delta = (48000 << 12) / speed;
642 tr_wr(tr, TR_REG_SBDELTA, ch->delta, 2);
644 /* return closest possible speed */
645 return (48000 << 12) / ch->delta;
649 trrchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
651 struct tr_rchinfo *ch = data;
653 sndbuf_resize(ch->buffer, 2, blocksize);
659 trrchan_trigger(kobj_t obj, void *data, int go)
661 struct tr_rchinfo *ch = data;
662 struct tr_info *tr = ch->parent;
665 if (!PCMTRIG_COMMON(go))
668 if (go == PCMTRIG_START) {
669 /* set up dma mode regs */
670 tr_wr(tr, TR_REG_DMAR15, 0, 1);
671 i = tr_rd(tr, TR_REG_DMAR11, 1) & 0x03;
672 tr_wr(tr, TR_REG_DMAR11, i | 0x54, 1);
673 /* set up base address */
674 tr_wr(tr, TR_REG_DMAR0, sndbuf_getbufaddr(ch->buffer), 4);
675 /* set up buffer size */
676 i = tr_rd(tr, TR_REG_DMAR4, 4) & ~0x00ffffff;
677 tr_wr(tr, TR_REG_DMAR4, i | (sndbuf_runsz(ch->buffer) - 1), 4);
679 tr_wr(tr, TR_REG_SBCTRL, tr_rd(tr, TR_REG_SBCTRL, 1) | 1, 1);
682 tr_wr(tr, TR_REG_SBCTRL, tr_rd(tr, TR_REG_SBCTRL, 1) & ~7, 1);
691 trrchan_getptr(kobj_t obj, void *data)
693 struct tr_rchinfo *ch = data;
694 struct tr_info *tr = ch->parent;
696 /* return current byte offset of channel */
697 return tr_rd(tr, TR_REG_DMAR0, 4) - sndbuf_getbufaddr(ch->buffer);
700 static struct pcmchan_caps *
701 trrchan_getcaps(kobj_t obj, void *data)
706 static kobj_method_t trrchan_methods[] = {
707 KOBJMETHOD(channel_init, trrchan_init),
708 KOBJMETHOD(channel_setformat, trrchan_setformat),
709 KOBJMETHOD(channel_setspeed, trrchan_setspeed),
710 KOBJMETHOD(channel_setblocksize, trrchan_setblocksize),
711 KOBJMETHOD(channel_trigger, trrchan_trigger),
712 KOBJMETHOD(channel_getptr, trrchan_getptr),
713 KOBJMETHOD(channel_getcaps, trrchan_getcaps),
716 CHANNEL_DECLARE(trrchan);
718 /* -------------------------------------------------------------------- */
719 /* The interrupt handler */
724 struct tr_info *tr = (struct tr_info *)p;
725 struct tr_chinfo *ch;
726 u_int32_t active, mask, bufhalf, chnum, intsrc;
729 intsrc = tr_rd(tr, TR_REG_MISCINT, 4);
730 if (intsrc & TR_INT_ADDR) {
734 active = tr_rd(tr, (chnum < 32)? TR_REG_ADDRINTA : TR_REG_ADDRINTB, 4);
735 bufhalf = tr_rd(tr, (chnum < 32)? TR_REG_CSPF_A : TR_REG_CSPF_B, 4);
739 tmp = (bufhalf & mask)? 1 : 0;
740 if (chnum < tr->playchns) {
741 ch = &tr->chinfo[chnum];
742 /* printf("%d @ %d, ", chnum, trpchan_getptr(NULL, ch)); */
743 if (ch->bufhalf != tmp) {
744 chn_intr(ch->channel);
751 } while (chnum & 31);
755 tr_wr(tr, (chnum <= 32)? TR_REG_ADDRINTA : TR_REG_ADDRINTB, active, 4);
758 if (intsrc & TR_INT_SB) {
759 chn_intr(tr->recchinfo.channel);
760 tr_rd(tr, TR_REG_SBR9, 1);
761 tr_rd(tr, TR_REG_SBR10, 1);
765 /* -------------------------------------------------------------------- */
768 * Probe and attach the card
772 tr_init(struct tr_info *tr)
776 tr_wr(tr, SPA_REG_GPIO, 0, 4);
777 tr_wr(tr, SPA_REG_CODECST, SPA_RST_OFF, 4);
780 tr_wr(tr, TDX_REG_CODECST, TDX_CDC_ON, 4);
783 tr_wr(tr, TNX_REG_CODECST, TNX_CDC_ON, 4);
787 tr_wr(tr, TR_REG_CIR, TR_CIR_MIDENA | TR_CIR_ADDRENA, 4);
792 tr_pci_probe(device_t dev)
794 switch (pci_get_devid(dev)) {
796 device_set_desc(dev, "SiS 7018");
797 return BUS_PROBE_DEFAULT;
799 device_set_desc(dev, "Acer Labs M5451");
800 return BUS_PROBE_DEFAULT;
802 device_set_desc(dev, "Trident 4DWave DX");
803 return BUS_PROBE_DEFAULT;
805 device_set_desc(dev, "Trident 4DWave NX");
806 return BUS_PROBE_DEFAULT;
813 tr_pci_attach(device_t dev)
817 struct ac97_info *codec = 0;
819 char status[SND_STATUSLEN];
821 tr = malloc(sizeof(*tr), M_DEVBUF, M_WAITOK | M_ZERO);
822 tr->type = pci_get_devid(dev);
823 tr->rev = pci_get_revid(dev);
824 tr->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_t4dwave softc");
826 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
830 else if (i > TR_MAXPLAYCH)
845 data = pci_read_config(dev, PCIR_COMMAND, 2);
846 data |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
847 pci_write_config(dev, PCIR_COMMAND, data, 2);
848 data = pci_read_config(dev, PCIR_COMMAND, 2);
850 tr->regid = PCIR_BAR(0);
851 tr->regtype = SYS_RES_IOPORT;
852 tr->reg = bus_alloc_resource_any(dev, tr->regtype, &tr->regid,
855 tr->st = rman_get_bustag(tr->reg);
856 tr->sh = rman_get_bushandle(tr->reg);
858 device_printf(dev, "unable to map register space\n");
862 tr->bufsz = pcm_getbuffersize(dev, 4096, TR_DEFAULT_BUFSZ, 65536);
864 if (tr_init(tr) == -1) {
865 device_printf(dev, "unable to initialize the card\n");
870 codec = AC97_CREATE(dev, tr, tr_ac97);
871 if (codec == NULL) goto bad;
872 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) goto bad;
875 tr->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &tr->irqid,
876 RF_ACTIVE | RF_SHAREABLE);
877 if (!tr->irq || snd_setup_intr(dev, tr->irq, 0, tr_intr, tr, &tr->ih)) {
878 device_printf(dev, "unable to map interrupt\n");
882 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2,
884 /*lowaddr*/TR_MAXADDR,
885 /*highaddr*/BUS_SPACE_MAXADDR,
886 /*filter*/NULL, /*filterarg*/NULL,
887 /*maxsize*/tr->bufsz, /*nsegments*/1, /*maxsegz*/0x3ffff,
888 /*flags*/0, /*lockfunc*/busdma_lock_mutex,
889 /*lockarg*/&Giant, &tr->parent_dmat) != 0) {
890 device_printf(dev, "unable to create dma tag\n");
894 snprintf(status, 64, "at io 0x%lx irq %ld %s",
895 rman_get_start(tr->reg), rman_get_start(tr->irq),PCM_KLDSTRING(snd_t4dwave));
897 if (pcm_register(dev, tr, dacn, 1))
899 pcm_addchan(dev, PCMDIR_REC, &trrchan_class, tr);
900 for (i = 0; i < dacn; i++)
901 pcm_addchan(dev, PCMDIR_PLAY, &trpchan_class, tr);
902 pcm_setstatus(dev, status);
907 if (codec) ac97_destroy(codec);
908 if (tr->reg) bus_release_resource(dev, tr->regtype, tr->regid, tr->reg);
909 if (tr->ih) bus_teardown_intr(dev, tr->irq, tr->ih);
910 if (tr->irq) bus_release_resource(dev, SYS_RES_IRQ, tr->irqid, tr->irq);
911 if (tr->parent_dmat) bus_dma_tag_destroy(tr->parent_dmat);
912 if (tr->lock) snd_mtxfree(tr->lock);
918 tr_pci_detach(device_t dev)
923 r = pcm_unregister(dev);
927 tr = pcm_getdevinfo(dev);
928 bus_release_resource(dev, tr->regtype, tr->regid, tr->reg);
929 bus_teardown_intr(dev, tr->irq, tr->ih);
930 bus_release_resource(dev, SYS_RES_IRQ, tr->irqid, tr->irq);
931 bus_dma_tag_destroy(tr->parent_dmat);
932 snd_mtxfree(tr->lock);
939 tr_pci_suspend(device_t dev)
944 tr = pcm_getdevinfo(dev);
946 for (i = 0; i < tr->playchns; i++) {
947 tr->chinfo[i].was_active = tr->chinfo[i].active;
948 if (tr->chinfo[i].active) {
949 trpchan_trigger(NULL, &tr->chinfo[i], PCMTRIG_STOP);
953 tr->recchinfo.was_active = tr->recchinfo.active;
954 if (tr->recchinfo.active) {
955 trrchan_trigger(NULL, &tr->recchinfo, PCMTRIG_STOP);
962 tr_pci_resume(device_t dev)
967 tr = pcm_getdevinfo(dev);
969 if (tr_init(tr) == -1) {
970 device_printf(dev, "unable to initialize the card\n");
974 if (mixer_reinit(dev) == -1) {
975 device_printf(dev, "unable to initialize the mixer\n");
979 for (i = 0; i < tr->playchns; i++) {
980 if (tr->chinfo[i].was_active) {
981 trpchan_trigger(NULL, &tr->chinfo[i], PCMTRIG_START);
985 if (tr->recchinfo.was_active) {
986 trrchan_trigger(NULL, &tr->recchinfo, PCMTRIG_START);
992 static device_method_t tr_methods[] = {
993 /* Device interface */
994 DEVMETHOD(device_probe, tr_pci_probe),
995 DEVMETHOD(device_attach, tr_pci_attach),
996 DEVMETHOD(device_detach, tr_pci_detach),
997 DEVMETHOD(device_suspend, tr_pci_suspend),
998 DEVMETHOD(device_resume, tr_pci_resume),
1002 static driver_t tr_driver = {
1008 DRIVER_MODULE(snd_t4dwave, pci, tr_driver, pcm_devclass, 0, 0);
1009 MODULE_DEPEND(snd_t4dwave, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1010 MODULE_VERSION(snd_t4dwave, 1);