2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
35 * Manuals, sample driver and firmware source kits are available
36 * from http://www.alteon.com/support/openkits.
38 * Written by Bill Paul <wpaul@ctr.columbia.edu>
39 * Electrical Engineering Department
40 * Columbia University, New York City
44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast
48 * filtering and jumbo (9014 byte) frames. The hardware is largely
49 * controlled by firmware, which must be loaded into the NIC during
52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
53 * revision, which supports new features such as extended commands,
54 * extended jumbo receive ring desciptors and a mini receive ring.
56 * Alteon Networks is to be commended for releasing such a vast amount
57 * of development material for the Tigon NIC without requiring an NDA
58 * (although they really should have done it a long time ago). With
59 * any luck, the other vendors will finally wise up and follow Alteon's
62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into
63 * this driver by #including it as a C header file. This bloats the
64 * driver somewhat, but it's the easiest method considering that the
65 * driver code and firmware code need to be kept in sync. The source
66 * for the firmware is not provided with the FreeBSD distribution since
67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
69 * The following people deserve special thanks:
70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
72 * - Raymond Lee of Netgear, for providing a pair of Netgear
73 * GA620 Tigon 2 boards for testing
74 * - Ulf Zimmermann, for bringing the GA260 to my attention and
75 * convincing me to write this driver.
76 * - Andrew Gallatin for providing FreeBSD/Alpha support.
79 #include <sys/cdefs.h>
80 __FBSDID("$FreeBSD$");
84 #include <sys/param.h>
85 #include <sys/systm.h>
86 #include <sys/sockio.h>
88 #include <sys/malloc.h>
89 #include <sys/kernel.h>
90 #include <sys/module.h>
91 #include <sys/socket.h>
92 #include <sys/queue.h>
94 #include <sys/sf_buf.h>
97 #include <net/if_arp.h>
98 #include <net/ethernet.h>
99 #include <net/if_dl.h>
100 #include <net/if_media.h>
101 #include <net/if_types.h>
102 #include <net/if_vlan_var.h>
106 #include <netinet/in_systm.h>
107 #include <netinet/in.h>
108 #include <netinet/ip.h>
110 #include <machine/bus.h>
111 #include <machine/resource.h>
113 #include <sys/rman.h>
115 #ifdef TI_SF_BUF_JUMBO
117 #include <vm/vm_page.h>
120 #include <dev/pci/pcireg.h>
121 #include <dev/pci/pcivar.h>
123 #include <sys/tiio.h>
124 #include <dev/ti/if_tireg.h>
125 #include <dev/ti/ti_fw.h>
126 #include <dev/ti/ti_fw2.h>
128 #include <sys/sysctl.h>
130 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
132 * We can only turn on header splitting if we're using extended receive
135 #if defined(TI_JUMBO_HDRSPLIT) && !defined(TI_SF_BUF_JUMBO)
136 #error "options TI_JUMBO_HDRSPLIT requires TI_SF_BUF_JUMBO"
137 #endif /* TI_JUMBO_HDRSPLIT && !TI_SF_BUF_JUMBO */
145 * Various supported device vendors/types and their names.
148 static const struct ti_type ti_devs[] = {
149 { ALT_VENDORID, ALT_DEVICEID_ACENIC,
150 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
151 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
152 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
153 { TC_VENDORID, TC_DEVICEID_3C985,
154 "3Com 3c985-SX Gigabit Ethernet" },
155 { NG_VENDORID, NG_DEVICEID_GA620,
156 "Netgear GA620 1000baseSX Gigabit Ethernet" },
157 { NG_VENDORID, NG_DEVICEID_GA620T,
158 "Netgear GA620 1000baseT Gigabit Ethernet" },
159 { SGI_VENDORID, SGI_DEVICEID_TIGON,
160 "Silicon Graphics Gigabit Ethernet" },
161 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
162 "Farallon PN9000SX Gigabit Ethernet" },
167 static d_open_t ti_open;
168 static d_close_t ti_close;
169 static d_ioctl_t ti_ioctl2;
171 static struct cdevsw ti_cdevsw = {
172 .d_version = D_VERSION,
176 .d_ioctl = ti_ioctl2,
180 static int ti_probe(device_t);
181 static int ti_attach(device_t);
182 static int ti_detach(device_t);
183 static void ti_txeof(struct ti_softc *);
184 static void ti_rxeof(struct ti_softc *);
186 static void ti_stats_update(struct ti_softc *);
187 static int ti_encap(struct ti_softc *, struct mbuf **);
189 static void ti_intr(void *);
190 static void ti_start(struct ifnet *);
191 static void ti_start_locked(struct ifnet *);
192 static int ti_ioctl(struct ifnet *, u_long, caddr_t);
193 static void ti_init(void *);
194 static void ti_init_locked(void *);
195 static void ti_init2(struct ti_softc *);
196 static void ti_stop(struct ti_softc *);
197 static void ti_watchdog(void *);
198 static int ti_shutdown(device_t);
199 static int ti_ifmedia_upd(struct ifnet *);
200 static int ti_ifmedia_upd_locked(struct ti_softc *);
201 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *);
203 static uint32_t ti_eeprom_putbyte(struct ti_softc *, int);
204 static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *);
205 static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int);
207 static void ti_add_mcast(struct ti_softc *, struct ether_addr *);
208 static void ti_del_mcast(struct ti_softc *, struct ether_addr *);
209 static void ti_setmulti(struct ti_softc *);
211 static void ti_mem_read(struct ti_softc *, uint32_t, uint32_t, void *);
212 static void ti_mem_write(struct ti_softc *, uint32_t, uint32_t, void *);
213 static void ti_mem_zero(struct ti_softc *, uint32_t, uint32_t);
214 static int ti_copy_mem(struct ti_softc *, uint32_t, uint32_t, caddr_t, int,
216 static int ti_copy_scratch(struct ti_softc *, uint32_t, uint32_t, caddr_t,
218 static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type);
219 static void ti_loadfw(struct ti_softc *);
220 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *);
221 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int);
222 static void ti_handle_events(struct ti_softc *);
223 static void ti_dma_map_addr(void *, bus_dma_segment_t *, int, int);
224 static int ti_dma_alloc(struct ti_softc *);
225 static void ti_dma_free(struct ti_softc *);
226 static int ti_dma_ring_alloc(struct ti_softc *, bus_size_t, bus_size_t,
227 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
228 static void ti_dma_ring_free(struct ti_softc *, bus_dma_tag_t *, uint8_t **,
230 static int ti_newbuf_std(struct ti_softc *, int);
231 static int ti_newbuf_mini(struct ti_softc *, int);
232 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *);
233 static int ti_init_rx_ring_std(struct ti_softc *);
234 static void ti_free_rx_ring_std(struct ti_softc *);
235 static int ti_init_rx_ring_jumbo(struct ti_softc *);
236 static void ti_free_rx_ring_jumbo(struct ti_softc *);
237 static int ti_init_rx_ring_mini(struct ti_softc *);
238 static void ti_free_rx_ring_mini(struct ti_softc *);
239 static void ti_free_tx_ring(struct ti_softc *);
240 static int ti_init_tx_ring(struct ti_softc *);
241 static void ti_discard_std(struct ti_softc *, int);
242 #ifndef TI_SF_BUF_JUMBO
243 static void ti_discard_jumbo(struct ti_softc *, int);
245 static void ti_discard_mini(struct ti_softc *, int);
247 static int ti_64bitslot_war(struct ti_softc *);
248 static int ti_chipinit(struct ti_softc *);
249 static int ti_gibinit(struct ti_softc *);
251 #ifdef TI_JUMBO_HDRSPLIT
252 static __inline void ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len,
254 #endif /* TI_JUMBO_HDRSPLIT */
256 static void ti_sysctl_node(struct ti_softc *);
258 static device_method_t ti_methods[] = {
259 /* Device interface */
260 DEVMETHOD(device_probe, ti_probe),
261 DEVMETHOD(device_attach, ti_attach),
262 DEVMETHOD(device_detach, ti_detach),
263 DEVMETHOD(device_shutdown, ti_shutdown),
267 static driver_t ti_driver = {
270 sizeof(struct ti_softc)
273 static devclass_t ti_devclass;
275 DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0);
276 MODULE_DEPEND(ti, pci, 1, 1, 1);
277 MODULE_DEPEND(ti, ether, 1, 1, 1);
280 * Send an instruction or address to the EEPROM, check for ACK.
283 ti_eeprom_putbyte(struct ti_softc *sc, int byte)
288 * Make sure we're in TX mode.
290 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
293 * Feed in each bit and stobe the clock.
295 for (i = 0x80; i; i >>= 1) {
297 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
299 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
302 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
304 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
310 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
315 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
316 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
317 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
323 * Read a byte of data stored in the EEPROM at address 'addr.'
324 * We have to send two address bytes since the EEPROM can hold
325 * more than 256 bytes of data.
328 ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest)
336 * Send write control code to EEPROM.
338 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
339 device_printf(sc->ti_dev,
340 "failed to send write command, status: %x\n",
341 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
346 * Send first byte of address of byte we want to read.
348 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
349 device_printf(sc->ti_dev, "failed to send address, status: %x\n",
350 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
354 * Send second byte address of byte we want to read.
356 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
357 device_printf(sc->ti_dev, "failed to send address, status: %x\n",
358 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
365 * Send read control code to EEPROM.
367 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
368 device_printf(sc->ti_dev,
369 "failed to send read command, status: %x\n",
370 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
375 * Start reading bits from EEPROM.
377 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
378 for (i = 0x80; i; i >>= 1) {
379 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
381 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
383 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
390 * No ACK generated for read, so just return byte.
399 * Read a sequence of bytes from the EEPROM.
402 ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt)
407 for (i = 0; i < cnt; i++) {
408 err = ti_eeprom_getbyte(sc, off + i, &byte);
414 return (err ? 1 : 0);
418 * NIC memory read function.
419 * Can be used to copy data from NIC local memory.
422 ti_mem_read(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf)
424 int segptr, segsize, cnt;
435 segsize = TI_WINLEN - (segptr % TI_WINLEN);
436 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
437 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
438 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr,
448 * NIC memory write function.
449 * Can be used to copy data into NIC local memory.
452 ti_mem_write(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf)
454 int segptr, segsize, cnt;
465 segsize = TI_WINLEN - (segptr % TI_WINLEN);
466 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
467 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
468 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr,
477 * NIC memory read function.
478 * Can be used to clear a section of NIC local memory.
481 ti_mem_zero(struct ti_softc *sc, uint32_t addr, uint32_t len)
483 int segptr, segsize, cnt;
492 segsize = TI_WINLEN - (segptr % TI_WINLEN);
493 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
494 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle,
495 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4);
502 ti_copy_mem(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len,
503 caddr_t buf, int useraddr, int readdata)
505 int segptr, segsize, cnt;
514 * At the moment, we don't handle non-aligned cases, we just bail.
515 * If this proves to be a problem, it will be fixed.
517 if (readdata == 0 && (tigon_addr & 0x3) != 0) {
518 device_printf(sc->ti_dev, "%s: tigon address %#x isn't "
519 "word-aligned\n", __func__, tigon_addr);
520 device_printf(sc->ti_dev, "%s: unaligned writes aren't "
521 "yet supported\n", __func__);
525 segptr = tigon_addr & ~0x3;
526 segresid = tigon_addr - segptr;
529 * This is the non-aligned amount left over that we'll need to
534 /* Add in the left over amount at the front of the buffer */
539 * If resid + segresid is >= 4, add multiples of 4 to the count and
540 * decrease the residual by that much.
543 resid -= resid & ~0x3;
550 * Save the old window base value.
552 origwin = CSR_READ_4(sc, TI_WINBASE);
555 bus_size_t ti_offset;
560 segsize = TI_WINLEN - (segptr % TI_WINLEN);
561 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
563 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1));
566 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
567 ti_offset, (uint32_t *)sc->ti_membuf, segsize >> 2);
570 * Yeah, this is a little on the kludgy
571 * side, but at least this code is only
572 * used for debugging.
574 ti_bcopy_swap(sc->ti_membuf, sc->ti_membuf2,
575 segsize, TI_SWAP_NTOH);
579 copyout(&sc->ti_membuf2[segresid], ptr,
583 copyout(sc->ti_membuf2, ptr, segsize);
588 ti_bcopy_swap(sc->ti_membuf,
589 sc->ti_membuf2, segsize,
592 bcopy(&sc->ti_membuf2[segresid], ptr,
597 ti_bcopy_swap(sc->ti_membuf, ptr,
598 segsize, TI_SWAP_NTOH);
604 copyin(ptr, sc->ti_membuf2, segsize);
606 ti_bcopy_swap(sc->ti_membuf2, sc->ti_membuf,
607 segsize, TI_SWAP_HTON);
609 ti_bcopy_swap(ptr, sc->ti_membuf, segsize,
612 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
613 ti_offset, (uint32_t *)sc->ti_membuf, segsize >> 2);
621 * Handle leftover, non-word-aligned bytes.
624 uint32_t tmpval, tmpval2;
625 bus_size_t ti_offset;
628 * Set the segment pointer.
630 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
632 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1));
635 * First, grab whatever is in our source/destination.
636 * We'll obviously need this for reads, but also for
637 * writes, since we'll be doing read/modify/write.
639 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
640 ti_offset, &tmpval, 1);
643 * Next, translate this from little-endian to big-endian
644 * (at least on i386 boxes).
646 tmpval2 = ntohl(tmpval);
650 * If we're reading, just copy the leftover number
651 * of bytes from the host byte order buffer to
656 copyout(&tmpval2, ptr, resid);
659 bcopy(&tmpval2, ptr, resid);
662 * If we're writing, first copy the bytes to be
663 * written into the network byte order buffer,
664 * leaving the rest of the buffer with whatever was
665 * originally in there. Then, swap the bytes
666 * around into host order and write them out.
668 * XXX KDM the read side of this has been verified
669 * to work, but the write side of it has not been
670 * verified. So user beware.
674 copyin(ptr, &tmpval2, resid);
677 bcopy(ptr, &tmpval2, resid);
679 tmpval = htonl(tmpval2);
681 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
682 ti_offset, &tmpval, 1);
686 CSR_WRITE_4(sc, TI_WINBASE, origwin);
692 ti_copy_scratch(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len,
693 caddr_t buf, int useraddr, int readdata, int cpu)
697 uint32_t tmpval, tmpval2;
703 * At the moment, we don't handle non-aligned cases, we just bail.
704 * If this proves to be a problem, it will be fixed.
706 if (tigon_addr & 0x3) {
707 device_printf(sc->ti_dev, "%s: tigon address %#x "
708 "isn't word-aligned\n", __func__, tigon_addr);
713 device_printf(sc->ti_dev, "%s: transfer length %d "
714 "isn't word-aligned\n", __func__, len);
723 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr);
726 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu));
728 tmpval = ntohl(tmpval2);
731 * Note: I've used this debugging interface
732 * extensively with Alteon's 12.3.15 firmware,
733 * compiled with GCC 2.7.2.1 and binutils 2.9.1.
735 * When you compile the firmware without
736 * optimization, which is necessary sometimes in
737 * order to properly step through it, you sometimes
738 * read out a bogus value of 0xc0017c instead of
739 * whatever was supposed to be in that scratchpad
740 * location. That value is on the stack somewhere,
741 * but I've never been able to figure out what was
742 * causing the problem.
744 * The address seems to pop up in random places,
745 * often not in the same place on two subsequent
748 * In any case, the underlying data doesn't seem
749 * to be affected, just the value read out.
754 if (tmpval2 == 0xc0017c)
755 device_printf(sc->ti_dev, "found 0xc0017c at "
756 "%#x (tmpval2)\n", segptr);
758 if (tmpval == 0xc0017c)
759 device_printf(sc->ti_dev, "found 0xc0017c at "
760 "%#x (tmpval)\n", segptr);
763 copyout(&tmpval, ptr, 4);
765 bcopy(&tmpval, ptr, 4);
768 copyin(ptr, &tmpval2, 4);
770 bcopy(ptr, &tmpval2, 4);
772 tmpval = htonl(tmpval2);
774 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval);
786 ti_bcopy_swap(const void *src, void *dst, size_t len, ti_swap_type swap_type)
788 const uint8_t *tmpsrc;
793 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", len);
802 if (swap_type == TI_SWAP_NTOH)
803 *(uint32_t *)tmpdst = ntohl(*(const uint32_t *)tmpsrc);
805 *(uint32_t *)tmpdst = htonl(*(const uint32_t *)tmpsrc);
815 * Load firmware image into the NIC. Check that the firmware revision
816 * is acceptable and see if we want the firmware for the Tigon 1 or
820 ti_loadfw(struct ti_softc *sc)
825 switch (sc->ti_hwrev) {
827 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
828 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
829 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
830 device_printf(sc->ti_dev, "firmware revision mismatch; "
831 "want %d.%d.%d, got %d.%d.%d\n",
832 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
833 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
834 tigonFwReleaseMinor, tigonFwReleaseFix);
837 ti_mem_write(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText);
838 ti_mem_write(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData);
839 ti_mem_write(sc, tigonFwRodataAddr, tigonFwRodataLen,
841 ti_mem_zero(sc, tigonFwBssAddr, tigonFwBssLen);
842 ti_mem_zero(sc, tigonFwSbssAddr, tigonFwSbssLen);
843 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
845 case TI_HWREV_TIGON_II:
846 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
847 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
848 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
849 device_printf(sc->ti_dev, "firmware revision mismatch; "
850 "want %d.%d.%d, got %d.%d.%d\n",
851 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
852 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
853 tigon2FwReleaseMinor, tigon2FwReleaseFix);
856 ti_mem_write(sc, tigon2FwTextAddr, tigon2FwTextLen,
858 ti_mem_write(sc, tigon2FwDataAddr, tigon2FwDataLen,
860 ti_mem_write(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
862 ti_mem_zero(sc, tigon2FwBssAddr, tigon2FwBssLen);
863 ti_mem_zero(sc, tigon2FwSbssAddr, tigon2FwSbssLen);
864 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
867 device_printf(sc->ti_dev,
868 "can't load firmware: unknown hardware rev\n");
874 * Send the NIC a command via the command ring.
877 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd)
881 index = sc->ti_cmd_saved_prodidx;
882 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
883 TI_INC(index, TI_CMD_RING_CNT);
884 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
885 sc->ti_cmd_saved_prodidx = index;
889 * Send the NIC an extended command. The 'len' parameter specifies the
890 * number of command slots to include after the initial command.
893 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg, int len)
898 index = sc->ti_cmd_saved_prodidx;
899 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
900 TI_INC(index, TI_CMD_RING_CNT);
901 for (i = 0; i < len; i++) {
902 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
903 *(uint32_t *)(&arg[i * 4]));
904 TI_INC(index, TI_CMD_RING_CNT);
906 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
907 sc->ti_cmd_saved_prodidx = index;
911 * Handle events that have triggered interrupts.
914 ti_handle_events(struct ti_softc *sc)
916 struct ti_event_desc *e;
918 if (sc->ti_rdata.ti_event_ring == NULL)
921 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag,
922 sc->ti_cdata.ti_event_ring_map, BUS_DMASYNC_POSTREAD);
923 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
924 e = &sc->ti_rdata.ti_event_ring[sc->ti_ev_saved_considx];
925 switch (TI_EVENT_EVENT(e)) {
926 case TI_EV_LINKSTAT_CHANGED:
927 sc->ti_linkstat = TI_EVENT_CODE(e);
928 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
929 if_link_state_change(sc->ti_ifp, LINK_STATE_UP);
930 sc->ti_ifp->if_baudrate = IF_Mbps(100);
932 device_printf(sc->ti_dev,
934 } else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
935 if_link_state_change(sc->ti_ifp, LINK_STATE_UP);
936 sc->ti_ifp->if_baudrate = IF_Gbps(1UL);
938 device_printf(sc->ti_dev,
939 "gigabit link up\n");
940 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) {
941 if_link_state_change(sc->ti_ifp,
943 sc->ti_ifp->if_baudrate = 0;
945 device_printf(sc->ti_dev,
950 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD)
951 device_printf(sc->ti_dev, "invalid command\n");
952 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD)
953 device_printf(sc->ti_dev, "unknown command\n");
954 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG)
955 device_printf(sc->ti_dev, "bad config data\n");
957 case TI_EV_FIRMWARE_UP:
960 case TI_EV_STATS_UPDATED:
963 case TI_EV_RESET_JUMBO_RING:
964 case TI_EV_MCAST_UPDATED:
968 device_printf(sc->ti_dev, "unknown event: %d\n",
972 /* Advance the consumer index. */
973 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
974 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
976 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag,
977 sc->ti_cdata.ti_event_ring_map, BUS_DMASYNC_PREREAD);
980 struct ti_dmamap_arg {
981 bus_addr_t ti_busaddr;
985 ti_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
987 struct ti_dmamap_arg *ctx;
992 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg));
995 ctx->ti_busaddr = segs->ds_addr;
999 ti_dma_ring_alloc(struct ti_softc *sc, bus_size_t alignment, bus_size_t maxsize,
1000 bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, bus_addr_t *paddr,
1003 struct ti_dmamap_arg ctx;
1006 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag,
1007 alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
1008 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag);
1010 device_printf(sc->ti_dev,
1011 "could not create %s dma tag\n", msg);
1014 /* Allocate DMA'able memory for ring. */
1015 error = bus_dmamem_alloc(*tag, (void **)ring,
1016 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
1018 device_printf(sc->ti_dev,
1019 "could not allocate DMA'able memory for %s\n", msg);
1022 /* Load the address of the ring. */
1024 error = bus_dmamap_load(*tag, *map, *ring, maxsize, ti_dma_map_addr,
1025 &ctx, BUS_DMA_NOWAIT);
1027 device_printf(sc->ti_dev,
1028 "could not load DMA'able memory for %s\n", msg);
1031 *paddr = ctx.ti_busaddr;
1036 ti_dma_ring_free(struct ti_softc *sc, bus_dma_tag_t *tag, uint8_t **ring,
1041 bus_dmamap_unload(*tag, *map);
1042 if (*map != NULL && *ring != NULL) {
1043 bus_dmamem_free(*tag, *ring, *map);
1048 bus_dma_tag_destroy(*tag);
1054 ti_dma_alloc(struct ti_softc *sc)
1059 lowaddr = BUS_SPACE_MAXADDR;
1060 if (sc->ti_dac == 0)
1061 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1063 error = bus_dma_tag_create(bus_get_dma_tag(sc->ti_dev), 1, 0, lowaddr,
1064 BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0,
1065 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
1066 &sc->ti_cdata.ti_parent_tag);
1068 device_printf(sc->ti_dev,
1069 "could not allocate parent dma tag\n");
1073 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, sizeof(struct ti_gib),
1074 &sc->ti_cdata.ti_gib_tag, (uint8_t **)&sc->ti_rdata.ti_info,
1075 &sc->ti_cdata.ti_gib_map, &sc->ti_rdata.ti_info_paddr, "GIB");
1079 /* Producer/consumer status */
1080 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, sizeof(struct ti_status),
1081 &sc->ti_cdata.ti_status_tag, (uint8_t **)&sc->ti_rdata.ti_status,
1082 &sc->ti_cdata.ti_status_map, &sc->ti_rdata.ti_status_paddr,
1088 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_EVENT_RING_SZ,
1089 &sc->ti_cdata.ti_event_ring_tag,
1090 (uint8_t **)&sc->ti_rdata.ti_event_ring,
1091 &sc->ti_cdata.ti_event_ring_map, &sc->ti_rdata.ti_event_ring_paddr,
1096 /* Command ring lives in shared memory so no need to create DMA area. */
1098 /* Standard RX ring */
1099 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_STD_RX_RING_SZ,
1100 &sc->ti_cdata.ti_rx_std_ring_tag,
1101 (uint8_t **)&sc->ti_rdata.ti_rx_std_ring,
1102 &sc->ti_cdata.ti_rx_std_ring_map,
1103 &sc->ti_rdata.ti_rx_std_ring_paddr, "RX ring");
1108 error = ti_dma_ring_alloc(sc, TI_JUMBO_RING_ALIGN, TI_JUMBO_RX_RING_SZ,
1109 &sc->ti_cdata.ti_rx_jumbo_ring_tag,
1110 (uint8_t **)&sc->ti_rdata.ti_rx_jumbo_ring,
1111 &sc->ti_cdata.ti_rx_jumbo_ring_map,
1112 &sc->ti_rdata.ti_rx_jumbo_ring_paddr, "jumbo RX ring");
1116 /* RX return ring */
1117 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_RX_RETURN_RING_SZ,
1118 &sc->ti_cdata.ti_rx_return_ring_tag,
1119 (uint8_t **)&sc->ti_rdata.ti_rx_return_ring,
1120 &sc->ti_cdata.ti_rx_return_ring_map,
1121 &sc->ti_rdata.ti_rx_return_ring_paddr, "RX return ring");
1125 /* Create DMA tag for standard RX mbufs. */
1126 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0,
1127 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
1128 MCLBYTES, 0, NULL, NULL, &sc->ti_cdata.ti_rx_std_tag);
1130 device_printf(sc->ti_dev, "could not allocate RX dma tag\n");
1134 /* Create DMA tag for jumbo RX mbufs. */
1135 #ifdef TI_SF_BUF_JUMBO
1137 * The VM system will take care of providing aligned pages. Alignment
1138 * is set to 1 here so that busdma resources won't be wasted.
1140 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0,
1141 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, PAGE_SIZE * 4, 4,
1142 PAGE_SIZE, 0, NULL, NULL, &sc->ti_cdata.ti_rx_jumbo_tag);
1144 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0,
1145 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MJUM9BYTES, 1,
1146 MJUM9BYTES, 0, NULL, NULL, &sc->ti_cdata.ti_rx_jumbo_tag);
1149 device_printf(sc->ti_dev,
1150 "could not allocate jumbo RX dma tag\n");
1154 /* Create DMA tag for TX mbufs. */
1155 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1,
1156 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1157 MCLBYTES * TI_MAXTXSEGS, TI_MAXTXSEGS, MCLBYTES, 0, NULL, NULL,
1158 &sc->ti_cdata.ti_tx_tag);
1160 device_printf(sc->ti_dev, "could not allocate TX dma tag\n");
1164 /* Create DMA maps for RX buffers. */
1165 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1166 error = bus_dmamap_create(sc->ti_cdata.ti_rx_std_tag, 0,
1167 &sc->ti_cdata.ti_rx_std_maps[i]);
1169 device_printf(sc->ti_dev,
1170 "could not create DMA map for RX\n");
1174 error = bus_dmamap_create(sc->ti_cdata.ti_rx_std_tag, 0,
1175 &sc->ti_cdata.ti_rx_std_sparemap);
1177 device_printf(sc->ti_dev,
1178 "could not create spare DMA map for RX\n");
1182 /* Create DMA maps for jumbo RX buffers. */
1183 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1184 error = bus_dmamap_create(sc->ti_cdata.ti_rx_jumbo_tag, 0,
1185 &sc->ti_cdata.ti_rx_jumbo_maps[i]);
1187 device_printf(sc->ti_dev,
1188 "could not create DMA map for jumbo RX\n");
1192 error = bus_dmamap_create(sc->ti_cdata.ti_rx_jumbo_tag, 0,
1193 &sc->ti_cdata.ti_rx_jumbo_sparemap);
1195 device_printf(sc->ti_dev,
1196 "could not create spare DMA map for jumbo RX\n");
1200 /* Create DMA maps for TX buffers. */
1201 for (i = 0; i < TI_TX_RING_CNT; i++) {
1202 error = bus_dmamap_create(sc->ti_cdata.ti_tx_tag, 0,
1203 &sc->ti_cdata.ti_txdesc[i].tx_dmamap);
1205 device_printf(sc->ti_dev,
1206 "could not create DMA map for TX\n");
1211 /* Mini ring and TX ring is not available on Tigon 1. */
1212 if (sc->ti_hwrev == TI_HWREV_TIGON)
1216 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_TX_RING_SZ,
1217 &sc->ti_cdata.ti_tx_ring_tag, (uint8_t **)&sc->ti_rdata.ti_tx_ring,
1218 &sc->ti_cdata.ti_tx_ring_map, &sc->ti_rdata.ti_tx_ring_paddr,
1224 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_MINI_RX_RING_SZ,
1225 &sc->ti_cdata.ti_rx_mini_ring_tag,
1226 (uint8_t **)&sc->ti_rdata.ti_rx_mini_ring,
1227 &sc->ti_cdata.ti_rx_mini_ring_map,
1228 &sc->ti_rdata.ti_rx_mini_ring_paddr, "mini RX ring");
1232 /* Create DMA tag for mini RX mbufs. */
1233 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0,
1234 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MHLEN, 1,
1235 MHLEN, 0, NULL, NULL, &sc->ti_cdata.ti_rx_mini_tag);
1237 device_printf(sc->ti_dev,
1238 "could not allocate mini RX dma tag\n");
1242 /* Create DMA maps for mini RX buffers. */
1243 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1244 error = bus_dmamap_create(sc->ti_cdata.ti_rx_mini_tag, 0,
1245 &sc->ti_cdata.ti_rx_mini_maps[i]);
1247 device_printf(sc->ti_dev,
1248 "could not create DMA map for mini RX\n");
1252 error = bus_dmamap_create(sc->ti_cdata.ti_rx_mini_tag, 0,
1253 &sc->ti_cdata.ti_rx_mini_sparemap);
1255 device_printf(sc->ti_dev,
1256 "could not create spare DMA map for mini RX\n");
1264 ti_dma_free(struct ti_softc *sc)
1268 /* Destroy DMA maps for RX buffers. */
1269 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1270 if (sc->ti_cdata.ti_rx_std_maps[i]) {
1271 bus_dmamap_destroy(sc->ti_cdata.ti_rx_std_tag,
1272 sc->ti_cdata.ti_rx_std_maps[i]);
1273 sc->ti_cdata.ti_rx_std_maps[i] = NULL;
1276 if (sc->ti_cdata.ti_rx_std_sparemap) {
1277 bus_dmamap_destroy(sc->ti_cdata.ti_rx_std_tag,
1278 sc->ti_cdata.ti_rx_std_sparemap);
1279 sc->ti_cdata.ti_rx_std_sparemap = NULL;
1281 if (sc->ti_cdata.ti_rx_std_tag) {
1282 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_std_tag);
1283 sc->ti_cdata.ti_rx_std_tag = NULL;
1286 /* Destroy DMA maps for jumbo RX buffers. */
1287 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1288 if (sc->ti_cdata.ti_rx_jumbo_maps[i]) {
1289 bus_dmamap_destroy(sc->ti_cdata.ti_rx_jumbo_tag,
1290 sc->ti_cdata.ti_rx_jumbo_maps[i]);
1291 sc->ti_cdata.ti_rx_jumbo_maps[i] = NULL;
1294 if (sc->ti_cdata.ti_rx_jumbo_sparemap) {
1295 bus_dmamap_destroy(sc->ti_cdata.ti_rx_jumbo_tag,
1296 sc->ti_cdata.ti_rx_jumbo_sparemap);
1297 sc->ti_cdata.ti_rx_jumbo_sparemap = NULL;
1299 if (sc->ti_cdata.ti_rx_jumbo_tag) {
1300 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_jumbo_tag);
1301 sc->ti_cdata.ti_rx_jumbo_tag = NULL;
1304 /* Destroy DMA maps for mini RX buffers. */
1305 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1306 if (sc->ti_cdata.ti_rx_mini_maps[i]) {
1307 bus_dmamap_destroy(sc->ti_cdata.ti_rx_mini_tag,
1308 sc->ti_cdata.ti_rx_mini_maps[i]);
1309 sc->ti_cdata.ti_rx_mini_maps[i] = NULL;
1312 if (sc->ti_cdata.ti_rx_mini_sparemap) {
1313 bus_dmamap_destroy(sc->ti_cdata.ti_rx_mini_tag,
1314 sc->ti_cdata.ti_rx_mini_sparemap);
1315 sc->ti_cdata.ti_rx_mini_sparemap = NULL;
1317 if (sc->ti_cdata.ti_rx_mini_tag) {
1318 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_mini_tag);
1319 sc->ti_cdata.ti_rx_mini_tag = NULL;
1322 /* Destroy DMA maps for TX buffers. */
1323 for (i = 0; i < TI_TX_RING_CNT; i++) {
1324 if (sc->ti_cdata.ti_txdesc[i].tx_dmamap) {
1325 bus_dmamap_destroy(sc->ti_cdata.ti_tx_tag,
1326 sc->ti_cdata.ti_txdesc[i].tx_dmamap);
1327 sc->ti_cdata.ti_txdesc[i].tx_dmamap = NULL;
1330 if (sc->ti_cdata.ti_tx_tag) {
1331 bus_dma_tag_destroy(sc->ti_cdata.ti_tx_tag);
1332 sc->ti_cdata.ti_tx_tag = NULL;
1335 /* Destroy standard RX ring. */
1336 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_std_ring_tag,
1337 (void *)&sc->ti_rdata.ti_rx_std_ring,
1338 &sc->ti_cdata.ti_rx_std_ring_map);
1339 /* Destroy jumbo RX ring. */
1340 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_jumbo_ring_tag,
1341 (void *)&sc->ti_rdata.ti_rx_jumbo_ring,
1342 &sc->ti_cdata.ti_rx_jumbo_ring_map);
1343 /* Destroy mini RX ring. */
1344 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_mini_ring_tag,
1345 (void *)&sc->ti_rdata.ti_rx_mini_ring,
1346 &sc->ti_cdata.ti_rx_mini_ring_map);
1347 /* Destroy RX return ring. */
1348 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_return_ring_tag,
1349 (void *)&sc->ti_rdata.ti_rx_return_ring,
1350 &sc->ti_cdata.ti_rx_return_ring_map);
1351 /* Destroy TX ring. */
1352 ti_dma_ring_free(sc, &sc->ti_cdata.ti_tx_ring_tag,
1353 (void *)&sc->ti_rdata.ti_tx_ring, &sc->ti_cdata.ti_tx_ring_map);
1354 /* Destroy status block. */
1355 ti_dma_ring_free(sc, &sc->ti_cdata.ti_status_tag,
1356 (void *)&sc->ti_rdata.ti_status, &sc->ti_cdata.ti_status_map);
1357 /* Destroy event ring. */
1358 ti_dma_ring_free(sc, &sc->ti_cdata.ti_event_ring_tag,
1359 (void *)&sc->ti_rdata.ti_event_ring,
1360 &sc->ti_cdata.ti_event_ring_map);
1362 ti_dma_ring_free(sc, &sc->ti_cdata.ti_gib_tag,
1363 (void *)&sc->ti_rdata.ti_info, &sc->ti_cdata.ti_gib_map);
1365 /* Destroy the parent tag. */
1366 if (sc->ti_cdata.ti_parent_tag) {
1367 bus_dma_tag_destroy(sc->ti_cdata.ti_parent_tag);
1368 sc->ti_cdata.ti_parent_tag = NULL;
1373 * Intialize a standard receive ring descriptor.
1376 ti_newbuf_std(struct ti_softc *sc, int i)
1379 bus_dma_segment_t segs[1];
1381 struct ti_rx_desc *r;
1384 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1387 m->m_len = m->m_pkthdr.len = MCLBYTES;
1388 m_adj(m, ETHER_ALIGN);
1390 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_std_tag,
1391 sc->ti_cdata.ti_rx_std_sparemap, m, segs, &nsegs, 0);
1396 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1398 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
1399 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag,
1400 sc->ti_cdata.ti_rx_std_maps[i], BUS_DMASYNC_POSTREAD);
1401 bus_dmamap_unload(sc->ti_cdata.ti_rx_std_tag,
1402 sc->ti_cdata.ti_rx_std_maps[i]);
1405 map = sc->ti_cdata.ti_rx_std_maps[i];
1406 sc->ti_cdata.ti_rx_std_maps[i] = sc->ti_cdata.ti_rx_std_sparemap;
1407 sc->ti_cdata.ti_rx_std_sparemap = map;
1408 sc->ti_cdata.ti_rx_std_chain[i] = m;
1410 r = &sc->ti_rdata.ti_rx_std_ring[i];
1411 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr);
1412 r->ti_len = segs[0].ds_len;
1413 r->ti_type = TI_BDTYPE_RECV_BD;
1416 r->ti_tcp_udp_cksum = 0;
1417 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
1418 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1421 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag,
1422 sc->ti_cdata.ti_rx_std_maps[i], BUS_DMASYNC_PREREAD);
1427 * Intialize a mini receive ring descriptor. This only applies to
1431 ti_newbuf_mini(struct ti_softc *sc, int i)
1434 bus_dma_segment_t segs[1];
1436 struct ti_rx_desc *r;
1439 MGETHDR(m, M_DONTWAIT, MT_DATA);
1442 m->m_len = m->m_pkthdr.len = MHLEN;
1443 m_adj(m, ETHER_ALIGN);
1445 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_mini_tag,
1446 sc->ti_cdata.ti_rx_mini_sparemap, m, segs, &nsegs, 0);
1451 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1453 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1454 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag,
1455 sc->ti_cdata.ti_rx_mini_maps[i], BUS_DMASYNC_POSTREAD);
1456 bus_dmamap_unload(sc->ti_cdata.ti_rx_mini_tag,
1457 sc->ti_cdata.ti_rx_mini_maps[i]);
1460 map = sc->ti_cdata.ti_rx_mini_maps[i];
1461 sc->ti_cdata.ti_rx_mini_maps[i] = sc->ti_cdata.ti_rx_mini_sparemap;
1462 sc->ti_cdata.ti_rx_mini_sparemap = map;
1463 sc->ti_cdata.ti_rx_mini_chain[i] = m;
1465 r = &sc->ti_rdata.ti_rx_mini_ring[i];
1466 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr);
1467 r->ti_len = segs[0].ds_len;
1468 r->ti_type = TI_BDTYPE_RECV_BD;
1469 r->ti_flags = TI_BDFLAG_MINI_RING;
1471 r->ti_tcp_udp_cksum = 0;
1472 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
1473 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1476 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag,
1477 sc->ti_cdata.ti_rx_mini_maps[i], BUS_DMASYNC_PREREAD);
1481 #ifndef TI_SF_BUF_JUMBO
1484 * Initialize a jumbo receive ring descriptor. This allocates
1485 * a jumbo buffer from the pool managed internally by the driver.
1488 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *dummy)
1491 bus_dma_segment_t segs[1];
1493 struct ti_rx_desc *r;
1498 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1501 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1502 m_adj(m, ETHER_ALIGN);
1504 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_jumbo_tag,
1505 sc->ti_cdata.ti_rx_jumbo_sparemap, m, segs, &nsegs, 0);
1510 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1512 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
1513 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag,
1514 sc->ti_cdata.ti_rx_jumbo_maps[i], BUS_DMASYNC_POSTREAD);
1515 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag,
1516 sc->ti_cdata.ti_rx_jumbo_maps[i]);
1519 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1520 sc->ti_cdata.ti_rx_jumbo_maps[i] = sc->ti_cdata.ti_rx_jumbo_sparemap;
1521 sc->ti_cdata.ti_rx_jumbo_sparemap = map;
1522 sc->ti_cdata.ti_rx_jumbo_chain[i] = m;
1524 r = &sc->ti_rdata.ti_rx_jumbo_ring[i];
1525 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr);
1526 r->ti_len = segs[0].ds_len;
1527 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1528 r->ti_flags = TI_BDFLAG_JUMBO_RING;
1530 r->ti_tcp_udp_cksum = 0;
1531 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
1532 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1535 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag,
1536 sc->ti_cdata.ti_rx_jumbo_maps[i], BUS_DMASYNC_PREREAD);
1542 #if (PAGE_SIZE == 4096)
1548 #define TCP_HDR_LEN (52 + sizeof(struct ether_header))
1549 #define UDP_HDR_LEN (28 + sizeof(struct ether_header))
1550 #define NFS_HDR_LEN (UDP_HDR_LEN)
1551 static int HDR_LEN = TCP_HDR_LEN;
1554 * Initialize a jumbo receive ring descriptor. This allocates
1555 * a jumbo buffer from the pool managed internally by the driver.
1558 ti_newbuf_jumbo(struct ti_softc *sc, int idx, struct mbuf *m_old)
1561 struct mbuf *cur, *m_new = NULL;
1562 struct mbuf *m[3] = {NULL, NULL, NULL};
1563 struct ti_rx_desc_ext *r;
1566 /* 1 extra buf to make nobufs easy*/
1567 struct sf_buf *sf[3] = {NULL, NULL, NULL};
1569 bus_dma_segment_t segs[4];
1572 if (m_old != NULL) {
1574 cur = m_old->m_next;
1575 for (i = 0; i <= NPAYLOAD; i++){
1580 /* Allocate the mbufs. */
1581 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1582 if (m_new == NULL) {
1583 device_printf(sc->ti_dev, "mbuf allocation failed "
1584 "-- packet dropped!\n");
1587 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA);
1588 if (m[NPAYLOAD] == NULL) {
1589 device_printf(sc->ti_dev, "cluster mbuf allocation "
1590 "failed -- packet dropped!\n");
1593 MCLGET(m[NPAYLOAD], M_DONTWAIT);
1594 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) {
1595 device_printf(sc->ti_dev, "mbuf allocation failed "
1596 "-- packet dropped!\n");
1599 m[NPAYLOAD]->m_len = MCLBYTES;
1601 for (i = 0; i < NPAYLOAD; i++){
1602 MGET(m[i], M_DONTWAIT, MT_DATA);
1604 device_printf(sc->ti_dev, "mbuf allocation "
1605 "failed -- packet dropped!\n");
1608 frame = vm_page_alloc(NULL, color++,
1609 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1611 if (frame == NULL) {
1612 device_printf(sc->ti_dev, "buffer allocation "
1613 "failed -- packet dropped!\n");
1614 printf(" index %d page %d\n", idx, i);
1617 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT);
1618 if (sf[i] == NULL) {
1619 vm_page_lock_queues();
1620 vm_page_unwire(frame, 0);
1621 vm_page_free(frame);
1622 vm_page_unlock_queues();
1623 device_printf(sc->ti_dev, "buffer allocation "
1624 "failed -- packet dropped!\n");
1625 printf(" index %d page %d\n", idx, i);
1629 for (i = 0; i < NPAYLOAD; i++){
1630 /* Attach the buffer to the mbuf. */
1631 m[i]->m_data = (void *)sf_buf_kva(sf[i]);
1632 m[i]->m_len = PAGE_SIZE;
1633 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE,
1634 sf_buf_mext, (void*)sf_buf_kva(sf[i]), sf[i],
1636 m[i]->m_next = m[i+1];
1638 /* link the buffers to the header */
1639 m_new->m_next = m[0];
1640 m_new->m_data += ETHER_ALIGN;
1641 if (sc->ti_hdrsplit)
1642 m_new->m_len = MHLEN - ETHER_ALIGN;
1644 m_new->m_len = HDR_LEN;
1645 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len;
1648 /* Set up the descriptor. */
1649 r = &sc->ti_rdata.ti_rx_jumbo_ring[idx];
1650 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new;
1651 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1652 if (bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_jumbo_tag, map, m_new,
1655 if ((nsegs < 1) || (nsegs > 4))
1657 ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr);
1658 r->ti_len0 = m_new->m_len;
1660 ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr);
1661 r->ti_len1 = PAGE_SIZE;
1663 ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr);
1664 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */
1666 if (PAGE_SIZE == 4096) {
1667 ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr);
1668 r->ti_len3 = MCLBYTES;
1672 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1674 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD;
1676 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
1677 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM;
1681 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map, BUS_DMASYNC_PREREAD);
1688 * This can only be called before the mbufs are strung together.
1689 * If the mbufs are strung together, m_freem() will free the chain,
1690 * so that the later mbufs will be freed multiple times.
1695 for (i = 0; i < 3; i++) {
1699 sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]);
1706 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1707 * that's 1MB or memory, which is a lot. For now, we fill only the first
1708 * 256 ring entries and hope that our CPU is fast enough to keep up with
1712 ti_init_rx_ring_std(struct ti_softc *sc)
1715 struct ti_cmd_desc cmd;
1717 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1718 if (ti_newbuf_std(sc, i) != 0)
1722 sc->ti_std = TI_STD_RX_RING_CNT - 1;
1723 TI_UPDATE_STDPROD(sc, TI_STD_RX_RING_CNT - 1);
1729 ti_free_rx_ring_std(struct ti_softc *sc)
1734 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1735 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
1736 map = sc->ti_cdata.ti_rx_std_maps[i];
1737 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag, map,
1738 BUS_DMASYNC_POSTREAD);
1739 bus_dmamap_unload(sc->ti_cdata.ti_rx_std_tag, map);
1740 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
1741 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
1744 bzero(sc->ti_rdata.ti_rx_std_ring, TI_STD_RX_RING_SZ);
1745 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag,
1746 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1750 ti_init_rx_ring_jumbo(struct ti_softc *sc)
1752 struct ti_cmd_desc cmd;
1755 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1756 if (ti_newbuf_jumbo(sc, i, NULL) != 0)
1760 sc->ti_jumbo = TI_JUMBO_RX_RING_CNT - 1;
1761 TI_UPDATE_JUMBOPROD(sc, TI_JUMBO_RX_RING_CNT - 1);
1767 ti_free_rx_ring_jumbo(struct ti_softc *sc)
1772 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1773 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
1774 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1775 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map,
1776 BUS_DMASYNC_POSTREAD);
1777 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, map);
1778 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
1779 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
1782 bzero(sc->ti_rdata.ti_rx_jumbo_ring, TI_JUMBO_RX_RING_SZ);
1783 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag,
1784 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1788 ti_init_rx_ring_mini(struct ti_softc *sc)
1792 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1793 if (ti_newbuf_mini(sc, i) != 0)
1797 sc->ti_mini = TI_MINI_RX_RING_CNT - 1;
1798 TI_UPDATE_MINIPROD(sc, TI_MINI_RX_RING_CNT - 1);
1804 ti_free_rx_ring_mini(struct ti_softc *sc)
1809 if (sc->ti_rdata.ti_rx_mini_ring == NULL)
1812 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1813 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1814 map = sc->ti_cdata.ti_rx_mini_maps[i];
1815 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag, map,
1816 BUS_DMASYNC_POSTREAD);
1817 bus_dmamap_unload(sc->ti_cdata.ti_rx_mini_tag, map);
1818 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
1819 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
1822 bzero(sc->ti_rdata.ti_rx_mini_ring, TI_MINI_RX_RING_SZ);
1823 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag,
1824 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_PREWRITE);
1828 ti_free_tx_ring(struct ti_softc *sc)
1830 struct ti_txdesc *txd;
1833 if (sc->ti_rdata.ti_tx_ring == NULL)
1836 for (i = 0; i < TI_TX_RING_CNT; i++) {
1837 txd = &sc->ti_cdata.ti_txdesc[i];
1838 if (txd->tx_m != NULL) {
1839 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap,
1840 BUS_DMASYNC_POSTWRITE);
1841 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag,
1847 bzero(sc->ti_rdata.ti_tx_ring, TI_TX_RING_SZ);
1848 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag,
1849 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE);
1853 ti_init_tx_ring(struct ti_softc *sc)
1855 struct ti_txdesc *txd;
1858 STAILQ_INIT(&sc->ti_cdata.ti_txfreeq);
1859 STAILQ_INIT(&sc->ti_cdata.ti_txbusyq);
1860 for (i = 0; i < TI_TX_RING_CNT; i++) {
1861 txd = &sc->ti_cdata.ti_txdesc[i];
1862 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q);
1865 sc->ti_tx_saved_considx = 0;
1866 sc->ti_tx_saved_prodidx = 0;
1867 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
1872 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
1873 * but we have to support the old way too so that Tigon 1 cards will
1877 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr)
1879 struct ti_cmd_desc cmd;
1881 uint32_t ext[2] = {0, 0};
1883 m = (uint16_t *)&addr->octet[0];
1885 switch (sc->ti_hwrev) {
1886 case TI_HWREV_TIGON:
1887 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1888 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1889 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
1891 case TI_HWREV_TIGON_II:
1892 ext[0] = htons(m[0]);
1893 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1894 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
1897 device_printf(sc->ti_dev, "unknown hwrev\n");
1903 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr)
1905 struct ti_cmd_desc cmd;
1907 uint32_t ext[2] = {0, 0};
1909 m = (uint16_t *)&addr->octet[0];
1911 switch (sc->ti_hwrev) {
1912 case TI_HWREV_TIGON:
1913 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1914 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1915 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
1917 case TI_HWREV_TIGON_II:
1918 ext[0] = htons(m[0]);
1919 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1920 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
1923 device_printf(sc->ti_dev, "unknown hwrev\n");
1929 * Configure the Tigon's multicast address filter.
1931 * The actual multicast table management is a bit of a pain, thanks to
1932 * slight brain damage on the part of both Alteon and us. With our
1933 * multicast code, we are only alerted when the multicast address table
1934 * changes and at that point we only have the current list of addresses:
1935 * we only know the current state, not the previous state, so we don't
1936 * actually know what addresses were removed or added. The firmware has
1937 * state, but we can't get our grubby mits on it, and there is no 'delete
1938 * all multicast addresses' command. Hence, we have to maintain our own
1939 * state so we know what addresses have been programmed into the NIC at
1943 ti_setmulti(struct ti_softc *sc)
1946 struct ifmultiaddr *ifma;
1947 struct ti_cmd_desc cmd;
1948 struct ti_mc_entry *mc;
1955 if (ifp->if_flags & IFF_ALLMULTI) {
1956 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1959 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1962 /* Disable interrupts. */
1963 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1964 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1966 /* First, zot all the existing filters. */
1967 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) {
1968 mc = SLIST_FIRST(&sc->ti_mc_listhead);
1969 ti_del_mcast(sc, &mc->mc_addr);
1970 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1974 /* Now program new ones. */
1975 if_maddr_rlock(ifp);
1976 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1977 if (ifma->ifma_addr->sa_family != AF_LINK)
1979 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT);
1981 device_printf(sc->ti_dev,
1982 "no memory for mcast filter entry\n");
1985 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1986 (char *)&mc->mc_addr, ETHER_ADDR_LEN);
1987 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1988 ti_add_mcast(sc, &mc->mc_addr);
1990 if_maddr_runlock(ifp);
1992 /* Re-enable interrupts. */
1993 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1997 * Check to see if the BIOS has configured us for a 64 bit slot when
1998 * we aren't actually in one. If we detect this condition, we can work
1999 * around it on the Tigon 2 by setting a bit in the PCI state register,
2000 * but for the Tigon 1 we must give up and abort the interface attach.
2003 ti_64bitslot_war(struct ti_softc *sc)
2006 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
2007 CSR_WRITE_4(sc, 0x600, 0);
2008 CSR_WRITE_4(sc, 0x604, 0);
2009 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
2010 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
2011 if (sc->ti_hwrev == TI_HWREV_TIGON)
2014 TI_SETBIT(sc, TI_PCI_STATE,
2015 TI_PCISTATE_32BIT_BUS);
2025 * Do endian, PCI and DMA initialization. Also check the on-board ROM
2026 * self-test results.
2029 ti_chipinit(struct ti_softc *sc)
2032 uint32_t pci_writemax = 0;
2035 /* Initialize link to down state. */
2036 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
2038 /* Set endianness before we access any non-PCI registers. */
2039 #if 0 && BYTE_ORDER == BIG_ENDIAN
2040 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
2041 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
2043 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
2044 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
2047 /* Check the ROM failed bit to see if self-tests passed. */
2048 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
2049 device_printf(sc->ti_dev, "board self-diagnostics failed!\n");
2054 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
2056 /* Figure out the hardware revision. */
2057 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
2058 case TI_REV_TIGON_I:
2059 sc->ti_hwrev = TI_HWREV_TIGON;
2061 case TI_REV_TIGON_II:
2062 sc->ti_hwrev = TI_HWREV_TIGON_II;
2065 device_printf(sc->ti_dev, "unsupported chip revision\n");
2069 /* Do special setup for Tigon 2. */
2070 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
2071 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
2072 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
2073 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
2077 * We don't have firmware source for the Tigon 1, so Tigon 1 boards
2078 * can't do header splitting.
2080 #ifdef TI_JUMBO_HDRSPLIT
2081 if (sc->ti_hwrev != TI_HWREV_TIGON)
2082 sc->ti_hdrsplit = 1;
2084 device_printf(sc->ti_dev,
2085 "can't do header splitting on a Tigon I board\n");
2086 #endif /* TI_JUMBO_HDRSPLIT */
2088 /* Set up the PCI state register. */
2089 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
2090 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
2091 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
2094 /* Clear the read/write max DMA parameters. */
2095 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
2096 TI_PCISTATE_READ_MAXDMA));
2098 /* Get cache line size. */
2099 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
2102 * If the system has set enabled the PCI memory write
2103 * and invalidate command in the command register, set
2104 * the write max parameter accordingly. This is necessary
2105 * to use MWI with the Tigon 2.
2107 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
2108 switch (cacheline) {
2117 /* Disable PCI memory write and invalidate. */
2119 device_printf(sc->ti_dev, "cache line size %d"
2120 " not supported; disabling PCI MWI\n",
2122 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
2123 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
2128 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
2130 /* This sets the min dma param all the way up (0xff). */
2131 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
2133 if (sc->ti_hdrsplit)
2134 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT;
2138 /* Configure DMA variables. */
2139 #if BYTE_ORDER == BIG_ENDIAN
2140 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
2141 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
2142 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
2143 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit);
2144 #else /* BYTE_ORDER */
2145 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
2146 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
2147 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit);
2148 #endif /* BYTE_ORDER */
2151 * Only allow 1 DMA channel to be active at a time.
2152 * I don't think this is a good idea, but without it
2153 * the firmware racks up lots of nicDmaReadRingFull
2154 * errors. This is not compatible with hardware checksums.
2156 if ((sc->ti_ifp->if_capenable & (IFCAP_TXCSUM | IFCAP_RXCSUM)) == 0)
2157 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
2159 /* Recommended settings from Tigon manual. */
2160 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
2161 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
2163 if (ti_64bitslot_war(sc)) {
2164 device_printf(sc->ti_dev, "bios thinks we're in a 64 bit slot, "
2173 * Initialize the general information block and firmware, and
2174 * start the CPU(s) running.
2177 ti_gibinit(struct ti_softc *sc)
2187 /* Disable interrupts for now. */
2188 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2190 /* Tell the chip where to find the general information block. */
2191 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI,
2192 (uint64_t)sc->ti_rdata.ti_info_paddr >> 32);
2193 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO,
2194 sc->ti_rdata.ti_info_paddr & 0xFFFFFFFF);
2196 /* Load the firmware into SRAM. */
2199 /* Set up the contents of the general info and ring control blocks. */
2201 /* Set up the event ring and producer pointer. */
2202 bzero(sc->ti_rdata.ti_event_ring, TI_EVENT_RING_SZ);
2203 rcb = &sc->ti_rdata.ti_info->ti_ev_rcb;
2204 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_event_ring_paddr);
2206 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_ev_prodidx_ptr,
2207 sc->ti_rdata.ti_status_paddr +
2208 offsetof(struct ti_status, ti_ev_prodidx_r));
2209 sc->ti_ev_prodidx.ti_idx = 0;
2210 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
2211 sc->ti_ev_saved_considx = 0;
2213 /* Set up the command ring and producer mailbox. */
2214 rcb = &sc->ti_rdata.ti_info->ti_cmd_rcb;
2215 ti_hostaddr64(&rcb->ti_hostaddr, TI_GCR_NIC_ADDR(TI_GCR_CMDRING));
2217 rcb->ti_max_len = 0;
2218 for (i = 0; i < TI_CMD_RING_CNT; i++) {
2219 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
2221 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
2222 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
2223 sc->ti_cmd_saved_prodidx = 0;
2226 * Assign the address of the stats refresh buffer.
2227 * We re-use the current stats buffer for this to
2230 bzero(&sc->ti_rdata.ti_info->ti_stats, sizeof(struct ti_stats));
2231 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_refresh_stats_ptr,
2232 sc->ti_rdata.ti_info_paddr + offsetof(struct ti_gib, ti_stats));
2234 /* Set up the standard receive ring. */
2235 rcb = &sc->ti_rdata.ti_info->ti_std_rx_rcb;
2236 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_std_ring_paddr);
2237 rcb->ti_max_len = TI_FRAMELEN;
2239 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2240 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2241 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2242 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2243 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2245 /* Set up the jumbo receive ring. */
2246 rcb = &sc->ti_rdata.ti_info->ti_jumbo_rx_rcb;
2247 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_jumbo_ring_paddr);
2249 #ifndef TI_SF_BUF_JUMBO
2250 rcb->ti_max_len = MJUM9BYTES - ETHER_ALIGN;
2253 rcb->ti_max_len = PAGE_SIZE;
2254 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD;
2256 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2257 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2258 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2259 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2260 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2263 * Set up the mini ring. Only activated on the
2264 * Tigon 2 but the slot in the config block is
2265 * still there on the Tigon 1.
2267 rcb = &sc->ti_rdata.ti_info->ti_mini_rx_rcb;
2268 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_mini_ring_paddr);
2269 rcb->ti_max_len = MHLEN - ETHER_ALIGN;
2270 if (sc->ti_hwrev == TI_HWREV_TIGON)
2271 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
2274 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2275 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2276 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2277 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2278 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2281 * Set up the receive return ring.
2283 rcb = &sc->ti_rdata.ti_info->ti_return_rcb;
2284 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_return_ring_paddr);
2286 rcb->ti_max_len = TI_RETURN_RING_CNT;
2287 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_return_prodidx_ptr,
2288 sc->ti_rdata.ti_status_paddr +
2289 offsetof(struct ti_status, ti_return_prodidx_r));
2292 * Set up the tx ring. Note: for the Tigon 2, we have the option
2293 * of putting the transmit ring in the host's address space and
2294 * letting the chip DMA it instead of leaving the ring in the NIC's
2295 * memory and accessing it through the shared memory region. We
2296 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
2297 * so we have to revert to the shared memory scheme if we detect
2300 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
2301 if (sc->ti_rdata.ti_tx_ring != NULL)
2302 bzero(sc->ti_rdata.ti_tx_ring, TI_TX_RING_SZ);
2303 rcb = &sc->ti_rdata.ti_info->ti_tx_rcb;
2304 if (sc->ti_hwrev == TI_HWREV_TIGON)
2307 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
2308 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2309 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2310 if (sc->ti_ifp->if_capenable & IFCAP_TXCSUM)
2311 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2312 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2313 rcb->ti_max_len = TI_TX_RING_CNT;
2314 if (sc->ti_hwrev == TI_HWREV_TIGON)
2315 ti_hostaddr64(&rcb->ti_hostaddr, TI_TX_RING_BASE);
2317 ti_hostaddr64(&rcb->ti_hostaddr,
2318 sc->ti_rdata.ti_tx_ring_paddr);
2319 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_tx_considx_ptr,
2320 sc->ti_rdata.ti_status_paddr +
2321 offsetof(struct ti_status, ti_tx_considx_r));
2323 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, sc->ti_cdata.ti_gib_map,
2324 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2325 bus_dmamap_sync(sc->ti_cdata.ti_status_tag, sc->ti_cdata.ti_status_map,
2326 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2327 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag,
2328 sc->ti_cdata.ti_event_ring_map,
2329 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2330 if (sc->ti_rdata.ti_tx_ring != NULL)
2331 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag,
2332 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE);
2334 /* Set up tunables */
2336 if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN)
2337 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
2338 (sc->ti_rx_coal_ticks / 10));
2341 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
2342 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
2343 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
2344 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
2345 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
2346 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
2348 /* Turn interrupts on. */
2349 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
2350 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2353 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
2359 * Probe for a Tigon chip. Check the PCI vendor and device IDs
2360 * against our list and return its name if we find a match.
2363 ti_probe(device_t dev)
2365 const struct ti_type *t;
2369 while (t->ti_name != NULL) {
2370 if ((pci_get_vendor(dev) == t->ti_vid) &&
2371 (pci_get_device(dev) == t->ti_did)) {
2372 device_set_desc(dev, t->ti_name);
2373 return (BUS_PROBE_DEFAULT);
2382 ti_attach(device_t dev)
2385 struct ti_softc *sc;
2389 sc = device_get_softc(dev);
2392 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
2394 callout_init_mtx(&sc->ti_watchdog, &sc->ti_mtx, 0);
2395 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
2396 ifp = sc->ti_ifp = if_alloc(IFT_ETHER);
2398 device_printf(dev, "can not if_alloc()\n");
2402 sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES;
2403 sc->ti_ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM;
2404 sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities;
2407 * Map control/status registers.
2409 pci_enable_busmaster(dev);
2412 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2415 if (sc->ti_res == NULL) {
2416 device_printf(dev, "couldn't map memory\n");
2421 sc->ti_btag = rman_get_bustag(sc->ti_res);
2422 sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
2424 /* Allocate interrupt */
2427 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2428 RF_SHAREABLE | RF_ACTIVE);
2430 if (sc->ti_irq == NULL) {
2431 device_printf(dev, "couldn't map interrupt\n");
2436 if (ti_chipinit(sc)) {
2437 device_printf(dev, "chip initialization failed\n");
2442 /* Zero out the NIC's on-board SRAM. */
2443 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000);
2445 /* Init again -- zeroing memory may have clobbered some registers. */
2446 if (ti_chipinit(sc)) {
2447 device_printf(dev, "chip initialization failed\n");
2453 * Get station address from the EEPROM. Note: the manual states
2454 * that the MAC address is at offset 0x8c, however the data is
2455 * stored as two longwords (since that's how it's loaded into
2456 * the NIC). This means the MAC address is actually preceded
2457 * by two zero bytes. We need to skip over those.
2459 if (ti_read_eeprom(sc, eaddr, TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
2460 device_printf(dev, "failed to read station address\n");
2465 /* Allocate working area for memory dump. */
2466 sc->ti_membuf = malloc(sizeof(uint8_t) * TI_WINLEN, M_DEVBUF, M_NOWAIT);
2467 sc->ti_membuf2 = malloc(sizeof(uint8_t) * TI_WINLEN, M_DEVBUF,
2469 if (sc->ti_membuf == NULL || sc->ti_membuf2 == NULL) {
2470 device_printf(dev, "cannot allocate memory buffer\n");
2474 if ((error = ti_dma_alloc(sc)) != 0)
2478 * We really need a better way to tell a 1000baseTX card
2479 * from a 1000baseSX one, since in theory there could be
2480 * OEMed 1000baseTX cards from lame vendors who aren't
2481 * clever enough to change the PCI ID. For the moment
2482 * though, the AceNIC is the only copper card available.
2484 if (pci_get_vendor(dev) == ALT_VENDORID &&
2485 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER)
2487 /* Ok, it's not the only copper card available. */
2488 if (pci_get_vendor(dev) == NG_VENDORID &&
2489 pci_get_device(dev) == NG_DEVICEID_GA620T)
2492 /* Set default tunable values. */
2495 /* Set up ifnet structure */
2497 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2498 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2499 ifp->if_ioctl = ti_ioctl;
2500 ifp->if_start = ti_start;
2501 ifp->if_init = ti_init;
2502 ifp->if_baudrate = IF_Gbps(1UL);
2503 ifp->if_snd.ifq_drv_maxlen = TI_TX_RING_CNT - 1;
2504 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
2505 IFQ_SET_READY(&ifp->if_snd);
2507 /* Set up ifmedia support. */
2508 if (sc->ti_copper) {
2510 * Copper cards allow manual 10/100 mode selection,
2511 * but not manual 1000baseTX mode selection. Why?
2512 * Becuase currently there's no way to specify the
2513 * master/slave setting through the firmware interface,
2514 * so Alteon decided to just bag it and handle it
2515 * via autonegotiation.
2517 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
2518 ifmedia_add(&sc->ifmedia,
2519 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
2520 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
2521 ifmedia_add(&sc->ifmedia,
2522 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
2523 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL);
2524 ifmedia_add(&sc->ifmedia,
2525 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL);
2527 /* Fiber cards don't support 10/100 modes. */
2528 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2529 ifmedia_add(&sc->ifmedia,
2530 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2532 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2533 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
2536 * We're assuming here that card initialization is a sequential
2537 * thing. If it isn't, multiple cards probing at the same time
2538 * could stomp on the list of softcs here.
2541 /* Register the device */
2542 sc->dev = make_dev(&ti_cdevsw, device_get_unit(dev), UID_ROOT,
2543 GID_OPERATOR, 0600, "ti%d", device_get_unit(dev));
2544 sc->dev->si_drv1 = sc;
2547 * Call MI attach routine.
2549 ether_ifattach(ifp, eaddr);
2551 /* VLAN capability setup. */
2552 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM |
2553 IFCAP_VLAN_HWTAGGING;
2554 ifp->if_capenable = ifp->if_capabilities;
2555 /* Tell the upper layer we support VLAN over-sized frames. */
2556 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
2558 /* Driver supports link state tracking. */
2559 ifp->if_capabilities |= IFCAP_LINKSTATE;
2560 ifp->if_capenable |= IFCAP_LINKSTATE;
2562 /* Hook interrupt last to avoid having to lock softc */
2563 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE,
2564 NULL, ti_intr, sc, &sc->ti_intrhand);
2567 device_printf(dev, "couldn't set up irq\n");
2579 * Shutdown hardware and free up resources. This can be called any
2580 * time after the mutex has been initialized. It is called in both
2581 * the error case in attach and the normal detach case so it needs
2582 * to be careful about only freeing resources that have actually been
2586 ti_detach(device_t dev)
2588 struct ti_softc *sc;
2591 sc = device_get_softc(dev);
2593 destroy_dev(sc->dev);
2594 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized"));
2596 if (device_is_attached(dev)) {
2597 ether_ifdetach(ifp);
2603 /* These should only be active if attach succeeded */
2604 callout_drain(&sc->ti_watchdog);
2605 bus_generic_detach(dev);
2607 ifmedia_removeall(&sc->ifmedia);
2609 if (sc->ti_intrhand)
2610 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
2612 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
2614 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
2620 free(sc->ti_membuf, M_DEVBUF);
2622 free(sc->ti_membuf2, M_DEVBUF);
2624 mtx_destroy(&sc->ti_mtx);
2629 #ifdef TI_JUMBO_HDRSPLIT
2631 * If hdr_len is 0, that means that header splitting wasn't done on
2632 * this packet for some reason. The two most likely reasons are that
2633 * the protocol isn't a supported protocol for splitting, or this
2634 * packet had a fragment offset that wasn't 0.
2636 * The header length, if it is non-zero, will always be the length of
2637 * the headers on the packet, but that length could be longer than the
2638 * first mbuf. So we take the minimum of the two as the actual
2641 static __inline void
2642 ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx)
2645 int lengths[4] = {0, 0, 0, 0};
2646 struct mbuf *m, *mp;
2649 top->m_len = min(hdr_len, top->m_len);
2650 pkt_len -= top->m_len;
2651 lengths[i++] = top->m_len;
2654 for (m = top->m_next; m && pkt_len; m = m->m_next) {
2655 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len);
2656 pkt_len -= m->m_len;
2657 lengths[i++] = m->m_len;
2663 printf("got split packet: ");
2665 printf("got non-split packet: ");
2667 printf("%d,%d,%d,%d = %d\n", lengths[0],
2668 lengths[1], lengths[2], lengths[3],
2669 lengths[0] + lengths[1] + lengths[2] +
2674 panic("header splitting didn't");
2681 if (mp->m_next != NULL)
2682 panic("ti_hdr_split: last mbuf in chain should be null");
2684 #endif /* TI_JUMBO_HDRSPLIT */
2687 ti_discard_std(struct ti_softc *sc, int i)
2690 struct ti_rx_desc *r;
2692 r = &sc->ti_rdata.ti_rx_std_ring[i];
2693 r->ti_len = MCLBYTES - ETHER_ALIGN;
2694 r->ti_type = TI_BDTYPE_RECV_BD;
2697 r->ti_tcp_udp_cksum = 0;
2698 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2699 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
2704 ti_discard_mini(struct ti_softc *sc, int i)
2707 struct ti_rx_desc *r;
2709 r = &sc->ti_rdata.ti_rx_mini_ring[i];
2710 r->ti_len = MHLEN - ETHER_ALIGN;
2711 r->ti_type = TI_BDTYPE_RECV_BD;
2712 r->ti_flags = TI_BDFLAG_MINI_RING;
2714 r->ti_tcp_udp_cksum = 0;
2715 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2716 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
2720 #ifndef TI_SF_BUF_JUMBO
2722 ti_discard_jumbo(struct ti_softc *sc, int i)
2725 struct ti_rx_desc *r;
2727 r = &sc->ti_rdata.ti_rx_jumbo_ring[i];
2728 r->ti_len = MJUM9BYTES - ETHER_ALIGN;
2729 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
2730 r->ti_flags = TI_BDFLAG_JUMBO_RING;
2732 r->ti_tcp_udp_cksum = 0;
2733 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2734 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
2740 * Frame reception handling. This is called if there's a frame
2741 * on the receive return list.
2743 * Note: we have to be able to handle three possibilities here:
2744 * 1) the frame is from the mini receive ring (can only happen)
2745 * on Tigon 2 boards)
2746 * 2) the frame is from the jumbo recieve ring
2747 * 3) the frame is from the standard receive ring
2751 ti_rxeof(struct ti_softc *sc)
2754 #ifdef TI_SF_BUF_JUMBO
2757 struct ti_cmd_desc cmd;
2758 int jumbocnt, minicnt, stdcnt, ti_len;
2764 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag,
2765 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
2766 if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN)
2767 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag,
2768 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
2769 if (sc->ti_rdata.ti_rx_mini_ring != NULL)
2770 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag,
2771 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_POSTWRITE);
2772 bus_dmamap_sync(sc->ti_cdata.ti_rx_return_ring_tag,
2773 sc->ti_cdata.ti_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
2775 jumbocnt = minicnt = stdcnt = 0;
2776 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
2777 struct ti_rx_desc *cur_rx;
2779 struct mbuf *m = NULL;
2780 uint16_t vlan_tag = 0;
2784 &sc->ti_rdata.ti_rx_return_ring[sc->ti_rx_saved_considx];
2785 rxidx = cur_rx->ti_idx;
2786 ti_len = cur_rx->ti_len;
2787 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
2789 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
2791 vlan_tag = cur_rx->ti_vlan_tag;
2794 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
2796 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
2797 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
2798 #ifndef TI_SF_BUF_JUMBO
2799 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2801 ti_discard_jumbo(sc, rxidx);
2804 if (ti_newbuf_jumbo(sc, rxidx, NULL) != 0) {
2806 ti_discard_jumbo(sc, rxidx);
2810 #else /* !TI_SF_BUF_JUMBO */
2811 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
2812 map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx];
2813 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map,
2814 BUS_DMASYNC_POSTREAD);
2815 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, map);
2816 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2818 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2821 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
2823 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2826 #ifdef TI_JUMBO_HDRSPLIT
2827 if (sc->ti_hdrsplit)
2828 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr),
2831 #endif /* TI_JUMBO_HDRSPLIT */
2832 m_adj(m, ti_len - m->m_pkthdr.len);
2833 #endif /* TI_SF_BUF_JUMBO */
2834 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
2836 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
2837 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
2838 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2840 ti_discard_mini(sc, rxidx);
2843 if (ti_newbuf_mini(sc, rxidx) != 0) {
2845 ti_discard_mini(sc, rxidx);
2851 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
2852 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
2853 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2855 ti_discard_std(sc, rxidx);
2858 if (ti_newbuf_std(sc, rxidx) != 0) {
2860 ti_discard_std(sc, rxidx);
2866 m->m_pkthdr.len = ti_len;
2868 m->m_pkthdr.rcvif = ifp;
2870 if (ifp->if_capenable & IFCAP_RXCSUM) {
2871 if (cur_rx->ti_flags & TI_BDFLAG_IP_CKSUM) {
2872 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2873 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
2874 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2876 if (cur_rx->ti_flags & TI_BDFLAG_TCP_UDP_CKSUM) {
2877 m->m_pkthdr.csum_data =
2878 cur_rx->ti_tcp_udp_cksum;
2879 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
2884 * If we received a packet with a vlan tag,
2885 * tag it before passing the packet upward.
2888 m->m_pkthdr.ether_vtag = vlan_tag;
2889 m->m_flags |= M_VLANTAG;
2892 (*ifp->if_input)(ifp, m);
2896 bus_dmamap_sync(sc->ti_cdata.ti_rx_return_ring_tag,
2897 sc->ti_cdata.ti_rx_return_ring_map, BUS_DMASYNC_PREREAD);
2898 /* Only necessary on the Tigon 1. */
2899 if (sc->ti_hwrev == TI_HWREV_TIGON)
2900 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
2901 sc->ti_rx_saved_considx);
2904 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag,
2905 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
2906 TI_UPDATE_STDPROD(sc, sc->ti_std);
2909 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag,
2910 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_PREWRITE);
2911 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
2914 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag,
2915 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
2916 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
2921 ti_txeof(struct ti_softc *sc)
2923 struct ti_txdesc *txd;
2924 struct ti_tx_desc txdesc;
2925 struct ti_tx_desc *cur_tx = NULL;
2931 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq);
2935 if (sc->ti_rdata.ti_tx_ring != NULL)
2936 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag,
2937 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_POSTWRITE);
2939 * Go through our tx ring and free mbufs for those
2940 * frames that have been sent.
2942 for (idx = sc->ti_tx_saved_considx; idx != sc->ti_tx_considx.ti_idx;
2943 TI_INC(idx, TI_TX_RING_CNT)) {
2944 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2945 ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc),
2946 sizeof(txdesc), &txdesc);
2949 cur_tx = &sc->ti_rdata.ti_tx_ring[idx];
2951 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2952 if ((cur_tx->ti_flags & TI_BDFLAG_END) == 0)
2954 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap,
2955 BUS_DMASYNC_POSTWRITE);
2956 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap);
2961 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txbusyq, tx_q);
2962 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q);
2963 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq);
2965 sc->ti_tx_saved_considx = idx;
2966 if (sc->ti_txcnt == 0)
2973 struct ti_softc *sc;
2980 /* Make sure this is really our interrupt. */
2981 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) {
2986 /* Ack interrupt and stop others from occuring. */
2987 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2989 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2990 bus_dmamap_sync(sc->ti_cdata.ti_status_tag,
2991 sc->ti_cdata.ti_status_map, BUS_DMASYNC_POSTREAD);
2992 /* Check RX return ring producer/consumer */
2995 /* Check TX ring producer/consumer */
2997 bus_dmamap_sync(sc->ti_cdata.ti_status_tag,
2998 sc->ti_cdata.ti_status_map, BUS_DMASYNC_PREREAD);
3001 ti_handle_events(sc);
3003 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3004 /* Re-enable interrupts. */
3005 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
3006 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3007 ti_start_locked(ifp);
3014 ti_stats_update(struct ti_softc *sc)
3021 if (sc->ti_stat_ticks == 0)
3023 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, sc->ti_cdata.ti_gib_map,
3024 BUS_DMASYNC_POSTREAD);
3026 s = &sc->ti_rdata.ti_info->ti_stats;
3027 ifp->if_collisions += (s->dot3StatsSingleCollisionFrames +
3028 s->dot3StatsMultipleCollisionFrames +
3029 s->dot3StatsExcessiveCollisions + s->dot3StatsLateCollisions) -
3032 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, sc->ti_cdata.ti_gib_map,
3033 BUS_DMASYNC_PREREAD);
3037 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
3038 * pointers to descriptors.
3041 ti_encap(struct ti_softc *sc, struct mbuf **m_head)
3043 struct ti_txdesc *txd;
3044 struct ti_tx_desc *f;
3045 struct ti_tx_desc txdesc;
3047 bus_dma_segment_t txsegs[TI_MAXTXSEGS];
3048 uint16_t csum_flags;
3049 int error, frag, i, nseg;
3051 if ((txd = STAILQ_FIRST(&sc->ti_cdata.ti_txfreeq)) == NULL)
3054 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap,
3055 *m_head, txsegs, &nseg, 0);
3056 if (error == EFBIG) {
3057 m = m_defrag(*m_head, M_DONTWAIT);
3064 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_tx_tag,
3065 txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
3071 } else if (error != 0)
3079 if (sc->ti_txcnt + nseg >= TI_TX_RING_CNT) {
3080 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap);
3083 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap,
3084 BUS_DMASYNC_PREWRITE);
3088 if (m->m_pkthdr.csum_flags & CSUM_IP)
3089 csum_flags |= TI_BDFLAG_IP_CKSUM;
3090 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
3091 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
3093 frag = sc->ti_tx_saved_prodidx;
3094 for (i = 0; i < nseg; i++) {
3095 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3096 bzero(&txdesc, sizeof(txdesc));
3099 f = &sc->ti_rdata.ti_tx_ring[frag];
3100 ti_hostaddr64(&f->ti_addr, txsegs[i].ds_addr);
3101 f->ti_len = txsegs[i].ds_len;
3102 f->ti_flags = csum_flags;
3103 if (m->m_flags & M_VLANTAG) {
3104 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
3105 f->ti_vlan_tag = m->m_pkthdr.ether_vtag;
3110 if (sc->ti_hwrev == TI_HWREV_TIGON)
3111 ti_mem_write(sc, TI_TX_RING_BASE + frag *
3112 sizeof(txdesc), sizeof(txdesc), &txdesc);
3113 TI_INC(frag, TI_TX_RING_CNT);
3116 sc->ti_tx_saved_prodidx = frag;
3117 /* set TI_BDFLAG_END on the last descriptor */
3118 frag = (frag + TI_TX_RING_CNT - 1) % TI_TX_RING_CNT;
3119 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3120 txdesc.ti_flags |= TI_BDFLAG_END;
3121 ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc),
3122 sizeof(txdesc), &txdesc);
3124 sc->ti_rdata.ti_tx_ring[frag].ti_flags |= TI_BDFLAG_END;
3126 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txfreeq, tx_q);
3127 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txbusyq, txd, tx_q);
3129 sc->ti_txcnt += nseg;
3135 ti_start(struct ifnet *ifp)
3137 struct ti_softc *sc;
3141 ti_start_locked(ifp);
3146 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3147 * to the mbuf data regions directly in the transmit descriptors.
3150 ti_start_locked(struct ifnet *ifp)
3152 struct ti_softc *sc;
3153 struct mbuf *m_head = NULL;
3158 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
3159 sc->ti_txcnt < (TI_TX_RING_CNT - 16);) {
3160 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
3166 * safety overkill. If this is a fragmented packet chain
3167 * with delayed TCP/UDP checksums, then only encapsulate
3168 * it if we have enough descriptors to handle the entire
3170 * (paranoia -- may not actually be needed)
3172 if (m_head->m_flags & M_FIRSTFRAG &&
3173 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
3174 if ((TI_TX_RING_CNT - sc->ti_txcnt) <
3175 m_head->m_pkthdr.csum_data + 16) {
3176 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3177 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3183 * Pack the data into the transmit ring. If we
3184 * don't have room, set the OACTIVE flag and wait
3185 * for the NIC to drain the ring.
3187 if (ti_encap(sc, &m_head)) {
3190 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3191 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3197 * If there's a BPF listener, bounce a copy of this frame
3200 ETHER_BPF_MTAP(ifp, m_head);
3204 if (sc->ti_rdata.ti_tx_ring != NULL)
3205 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag,
3206 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE);
3208 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, sc->ti_tx_saved_prodidx);
3211 * Set a timeout in case the chip goes out to lunch.
3220 struct ti_softc *sc;
3229 ti_init_locked(void *xsc)
3231 struct ti_softc *sc = xsc;
3233 if (sc->ti_ifp->if_drv_flags & IFF_DRV_RUNNING)
3236 /* Cancel pending I/O and flush buffers. */
3239 /* Init the gen info block, ring control blocks and firmware. */
3240 if (ti_gibinit(sc)) {
3241 device_printf(sc->ti_dev, "initialization failure\n");
3246 static void ti_init2(struct ti_softc *sc)
3248 struct ti_cmd_desc cmd;
3251 struct ifmedia *ifm;
3258 /* Specify MTU and interface index. */
3259 CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_get_unit(sc->ti_dev));
3260 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
3261 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
3262 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
3264 /* Load our MAC address. */
3265 ea = IF_LLADDR(sc->ti_ifp);
3266 CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]);
3267 CSR_WRITE_4(sc, TI_GCR_PAR1,
3268 (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]);
3269 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
3271 /* Enable or disable promiscuous mode as needed. */
3272 if (ifp->if_flags & IFF_PROMISC) {
3273 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
3275 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
3278 /* Program multicast filter. */
3282 * If this is a Tigon 1, we should tell the
3283 * firmware to use software packet filtering.
3285 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3286 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
3290 if (ti_init_rx_ring_std(sc) != 0) {
3292 device_printf(sc->ti_dev, "no memory for std Rx buffers.\n");
3296 /* Init jumbo RX ring. */
3297 if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) {
3298 if (ti_init_rx_ring_jumbo(sc) != 0) {
3300 device_printf(sc->ti_dev,
3301 "no memory for jumbo Rx buffers.\n");
3307 * If this is a Tigon 2, we can also configure the
3310 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
3311 if (ti_init_rx_ring_mini(sc) != 0) {
3313 device_printf(sc->ti_dev,
3314 "no memory for mini Rx buffers.\n");
3319 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
3320 sc->ti_rx_saved_considx = 0;
3323 ti_init_tx_ring(sc);
3325 /* Tell firmware we're alive. */
3326 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
3328 /* Enable host interrupts. */
3329 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
3331 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3332 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3333 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc);
3336 * Make sure to set media properly. We have to do this
3337 * here since we have to issue commands in order to set
3338 * the link negotiation and we can't issue commands until
3339 * the firmware is running.
3342 tmp = ifm->ifm_media;
3343 ifm->ifm_media = ifm->ifm_cur->ifm_media;
3344 ti_ifmedia_upd_locked(sc);
3345 ifm->ifm_media = tmp;
3349 * Set media options.
3352 ti_ifmedia_upd(struct ifnet *ifp)
3354 struct ti_softc *sc;
3359 error = ti_ifmedia_upd_locked(sc);
3366 ti_ifmedia_upd_locked(struct ti_softc *sc)
3368 struct ifmedia *ifm;
3369 struct ti_cmd_desc cmd;
3374 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3379 switch (IFM_SUBTYPE(ifm->ifm_media)) {
3382 * Transmit flow control doesn't work on the Tigon 1.
3384 flowctl = TI_GLNK_RX_FLOWCTL_Y;
3387 * Transmit flow control can also cause problems on the
3388 * Tigon 2, apparantly with both the copper and fiber
3389 * boards. The symptom is that the interface will just
3390 * hang. This was reproduced with Alteon 180 switches.
3393 if (sc->ti_hwrev != TI_HWREV_TIGON)
3394 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
3397 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
3398 TI_GLNK_FULL_DUPLEX| flowctl |
3399 TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
3401 flowctl = TI_LNK_RX_FLOWCTL_Y;
3403 if (sc->ti_hwrev != TI_HWREV_TIGON)
3404 flowctl |= TI_LNK_TX_FLOWCTL_Y;
3407 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
3408 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl |
3409 TI_LNK_AUTONEGENB|TI_LNK_ENB);
3410 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3411 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
3415 flowctl = TI_GLNK_RX_FLOWCTL_Y;
3417 if (sc->ti_hwrev != TI_HWREV_TIGON)
3418 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
3421 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
3422 flowctl |TI_GLNK_ENB);
3423 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
3424 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3425 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
3427 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3428 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
3434 flowctl = TI_LNK_RX_FLOWCTL_Y;
3436 if (sc->ti_hwrev != TI_HWREV_TIGON)
3437 flowctl |= TI_LNK_TX_FLOWCTL_Y;
3440 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
3441 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl);
3442 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
3443 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
3444 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
3446 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
3448 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3449 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
3451 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
3453 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3454 TI_CMD_CODE_NEGOTIATE_10_100, 0);
3462 * Report current media status.
3465 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3467 struct ti_softc *sc;
3474 ifmr->ifm_status = IFM_AVALID;
3475 ifmr->ifm_active = IFM_ETHER;
3477 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) {
3482 ifmr->ifm_status |= IFM_ACTIVE;
3484 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
3485 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
3487 ifmr->ifm_active |= IFM_1000_T;
3489 ifmr->ifm_active |= IFM_1000_SX;
3490 if (media & TI_GLNK_FULL_DUPLEX)
3491 ifmr->ifm_active |= IFM_FDX;
3493 ifmr->ifm_active |= IFM_HDX;
3494 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
3495 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
3496 if (sc->ti_copper) {
3497 if (media & TI_LNK_100MB)
3498 ifmr->ifm_active |= IFM_100_TX;
3499 if (media & TI_LNK_10MB)
3500 ifmr->ifm_active |= IFM_10_T;
3502 if (media & TI_LNK_100MB)
3503 ifmr->ifm_active |= IFM_100_FX;
3504 if (media & TI_LNK_10MB)
3505 ifmr->ifm_active |= IFM_10_FL;
3507 if (media & TI_LNK_FULL_DUPLEX)
3508 ifmr->ifm_active |= IFM_FDX;
3509 if (media & TI_LNK_HALF_DUPLEX)
3510 ifmr->ifm_active |= IFM_HDX;
3516 ti_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3518 struct ti_softc *sc = ifp->if_softc;
3519 struct ifreq *ifr = (struct ifreq *) data;
3520 struct ti_cmd_desc cmd;
3521 int mask, error = 0;
3526 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > TI_JUMBO_MTU)
3529 ifp->if_mtu = ifr->ifr_mtu;
3530 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3531 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3539 if (ifp->if_flags & IFF_UP) {
3541 * If only the state of the PROMISC flag changed,
3542 * then just use the 'set promisc mode' command
3543 * instead of reinitializing the entire NIC. Doing
3544 * a full re-init means reloading the firmware and
3545 * waiting for it to start up, which may take a
3548 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3549 ifp->if_flags & IFF_PROMISC &&
3550 !(sc->ti_if_flags & IFF_PROMISC)) {
3551 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3552 TI_CMD_CODE_PROMISC_ENB, 0);
3553 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3554 !(ifp->if_flags & IFF_PROMISC) &&
3555 sc->ti_if_flags & IFF_PROMISC) {
3556 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3557 TI_CMD_CODE_PROMISC_DIS, 0);
3561 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3565 sc->ti_if_flags = ifp->if_flags;
3571 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3577 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
3581 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3582 if ((mask & IFCAP_TXCSUM) != 0 &&
3583 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
3584 ifp->if_capenable ^= IFCAP_TXCSUM;
3585 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
3586 ifp->if_hwassist |= TI_CSUM_FEATURES;
3588 ifp->if_hwassist &= ~TI_CSUM_FEATURES;
3590 if ((mask & IFCAP_RXCSUM) != 0 &&
3591 (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
3592 ifp->if_capenable ^= IFCAP_RXCSUM;
3593 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
3594 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0)
3595 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3596 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
3597 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
3598 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
3599 if ((mask & (IFCAP_TXCSUM | IFCAP_RXCSUM |
3600 IFCAP_VLAN_HWTAGGING)) != 0) {
3601 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3602 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3607 VLAN_CAPABILITIES(ifp);
3610 error = ether_ioctl(ifp, command, data);
3618 ti_open(struct cdev *dev, int flags, int fmt, struct thread *td)
3620 struct ti_softc *sc;
3627 sc->ti_flags |= TI_FLAG_DEBUGING;
3634 ti_close(struct cdev *dev, int flag, int fmt, struct thread *td)
3636 struct ti_softc *sc;
3643 sc->ti_flags &= ~TI_FLAG_DEBUGING;
3650 * This ioctl routine goes along with the Tigon character device.
3653 ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag,
3656 struct ti_softc *sc;
3668 struct ti_stats *outstats;
3670 outstats = (struct ti_stats *)addr;
3673 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag,
3674 sc->ti_cdata.ti_gib_map, BUS_DMASYNC_POSTREAD);
3675 bcopy(&sc->ti_rdata.ti_info->ti_stats, outstats,
3676 sizeof(struct ti_stats));
3680 case TIIOCGETPARAMS:
3682 struct ti_params *params;
3684 params = (struct ti_params *)addr;
3687 params->ti_stat_ticks = sc->ti_stat_ticks;
3688 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks;
3689 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks;
3690 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds;
3691 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds;
3692 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio;
3693 params->param_mask = TI_PARAM_ALL;
3697 case TIIOCSETPARAMS:
3699 struct ti_params *params;
3701 params = (struct ti_params *)addr;
3704 if (params->param_mask & TI_PARAM_STAT_TICKS) {
3705 sc->ti_stat_ticks = params->ti_stat_ticks;
3706 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
3709 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) {
3710 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks;
3711 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
3712 sc->ti_rx_coal_ticks);
3715 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) {
3716 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks;
3717 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS,
3718 sc->ti_tx_coal_ticks);
3721 if (params->param_mask & TI_PARAM_RX_COAL_BDS) {
3722 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds;
3723 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD,
3724 sc->ti_rx_max_coal_bds);
3727 if (params->param_mask & TI_PARAM_TX_COAL_BDS) {
3728 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds;
3729 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD,
3730 sc->ti_tx_max_coal_bds);
3733 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) {
3734 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio;
3735 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO,
3736 sc->ti_tx_buf_ratio);
3741 case TIIOCSETTRACE: {
3742 ti_trace_type trace_type;
3744 trace_type = *(ti_trace_type *)addr;
3747 * Set tracing to whatever the user asked for. Setting
3748 * this register to 0 should have the effect of disabling
3752 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type);
3756 case TIIOCGETTRACE: {
3757 struct ti_trace_buf *trace_buf;
3758 uint32_t trace_start, cur_trace_ptr, trace_len;
3760 trace_buf = (struct ti_trace_buf *)addr;
3763 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START);
3764 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR);
3765 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN);
3767 if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, "
3768 "trace_len = %d\n", trace_start,
3769 cur_trace_ptr, trace_len);
3770 if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n",
3771 trace_buf->buf_len);
3773 error = ti_copy_mem(sc, trace_start, min(trace_len,
3774 trace_buf->buf_len), (caddr_t)trace_buf->buf, 1, 1);
3776 trace_buf->fill_len = min(trace_len,
3777 trace_buf->buf_len);
3778 if (cur_trace_ptr < trace_start)
3779 trace_buf->cur_trace_ptr =
3780 trace_start - cur_trace_ptr;
3782 trace_buf->cur_trace_ptr =
3783 cur_trace_ptr - trace_start;
3785 trace_buf->fill_len = 0;
3791 * For debugging, five ioctls are needed:
3800 * From what I can tell, Alteon's Solaris Tigon driver
3801 * only has one character device, so you have to attach
3802 * to the Tigon board you're interested in. This seems
3803 * like a not-so-good way to do things, since unless you
3804 * subsequently specify the unit number of the device
3805 * you're interested in every ioctl, you'll only be
3806 * able to debug one board at a time.
3809 case ALT_READ_TG_MEM:
3810 case ALT_WRITE_TG_MEM:
3812 struct tg_mem *mem_param;
3813 uint32_t sram_end, scratch_end;
3815 mem_param = (struct tg_mem *)addr;
3817 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3818 sram_end = TI_END_SRAM_I;
3819 scratch_end = TI_END_SCRATCH_I;
3821 sram_end = TI_END_SRAM_II;
3822 scratch_end = TI_END_SCRATCH_II;
3826 * For now, we'll only handle accessing regular SRAM,
3830 if (mem_param->tgAddr >= TI_BEG_SRAM &&
3831 mem_param->tgAddr + mem_param->len <= sram_end) {
3833 * In this instance, we always copy to/from user
3834 * space, so the user space argument is set to 1.
3836 error = ti_copy_mem(sc, mem_param->tgAddr,
3837 mem_param->len, mem_param->userAddr, 1,
3838 cmd == ALT_READ_TG_MEM ? 1 : 0);
3839 } else if (mem_param->tgAddr >= TI_BEG_SCRATCH &&
3840 mem_param->tgAddr <= scratch_end) {
3841 error = ti_copy_scratch(sc, mem_param->tgAddr,
3842 mem_param->len, mem_param->userAddr, 1,
3843 cmd == ALT_READ_TG_MEM ? 1 : 0, TI_PROCESSOR_A);
3844 } else if (mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG &&
3845 mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG) {
3846 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3847 if_printf(sc->ti_ifp,
3848 "invalid memory range for Tigon I\n");
3852 error = ti_copy_scratch(sc, mem_param->tgAddr -
3853 TI_SCRATCH_DEBUG_OFF, mem_param->len,
3854 mem_param->userAddr, 1,
3855 cmd == ALT_READ_TG_MEM ? 1 : 0, TI_PROCESSOR_B);
3857 if_printf(sc->ti_ifp, "memory address %#x len %d is "
3858 "out of supported range\n",
3859 mem_param->tgAddr, mem_param->len);
3865 case ALT_READ_TG_REG:
3866 case ALT_WRITE_TG_REG:
3868 struct tg_reg *regs;
3871 regs = (struct tg_reg *)addr;
3874 * Make sure the address in question isn't out of range.
3876 if (regs->addr > TI_REG_MAX) {
3881 if (cmd == ALT_READ_TG_REG) {
3882 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
3883 regs->addr, &tmpval, 1);
3884 regs->data = ntohl(tmpval);
3886 if ((regs->addr == TI_CPU_STATE)
3887 || (regs->addr == TI_CPU_CTL_B)) {
3888 if_printf(sc->ti_ifp, "register %#x = %#x\n",
3889 regs->addr, tmpval);
3893 tmpval = htonl(regs->data);
3894 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
3895 regs->addr, &tmpval, 1);
3908 ti_watchdog(void *arg)
3910 struct ti_softc *sc;
3915 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc);
3916 if (sc->ti_timer == 0 || --sc->ti_timer > 0)
3920 * When we're debugging, the chip is often stopped for long periods
3921 * of time, and that would normally cause the watchdog timer to fire.
3922 * Since that impedes debugging, we don't want to do that.
3924 if (sc->ti_flags & TI_FLAG_DEBUGING)
3928 if_printf(ifp, "watchdog timeout -- resetting\n");
3929 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3936 * Stop the adapter and free any mbufs allocated to the
3940 ti_stop(struct ti_softc *sc)
3943 struct ti_cmd_desc cmd;
3949 /* Disable host interrupts. */
3950 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
3952 * Tell firmware we're shutting down.
3954 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
3956 /* Halt and reinitialize. */
3957 if (ti_chipinit(sc) == 0) {
3958 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000);
3959 /* XXX ignore init errors. */
3963 /* Free the RX lists. */
3964 ti_free_rx_ring_std(sc);
3966 /* Free jumbo RX list. */
3967 ti_free_rx_ring_jumbo(sc);
3969 /* Free mini RX list. */
3970 ti_free_rx_ring_mini(sc);
3972 /* Free TX buffers. */
3973 ti_free_tx_ring(sc);
3975 sc->ti_ev_prodidx.ti_idx = 0;
3976 sc->ti_return_prodidx.ti_idx = 0;
3977 sc->ti_tx_considx.ti_idx = 0;
3978 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
3980 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3981 callout_stop(&sc->ti_watchdog);
3985 * Stop all chip I/O so that the kernel's probe routines don't
3986 * get confused by errant DMAs when rebooting.
3989 ti_shutdown(device_t dev)
3991 struct ti_softc *sc;
3993 sc = device_get_softc(dev);
4002 ti_sysctl_node(struct ti_softc *sc)
4004 struct sysctl_ctx_list *ctx;
4005 struct sysctl_oid_list *child;
4008 ctx = device_get_sysctl_ctx(sc->ti_dev);
4009 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ti_dev));
4013 snprintf(tname, sizeof(tname), "dev.ti.%d.dac",
4014 device_get_unit(sc->ti_dev));
4015 TUNABLE_INT_FETCH(tname, &sc->ti_dac);
4017 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_coal_ticks", CTLFLAG_RW,
4018 &sc->ti_rx_coal_ticks, 0, "Receive coalcesced ticks");
4019 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_max_coal_bds", CTLFLAG_RW,
4020 &sc->ti_rx_max_coal_bds, 0, "Receive max coalcesced BDs");
4022 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_coal_ticks", CTLFLAG_RW,
4023 &sc->ti_tx_coal_ticks, 0, "Send coalcesced ticks");
4024 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_max_coal_bds", CTLFLAG_RW,
4025 &sc->ti_tx_max_coal_bds, 0, "Send max coalcesced BDs");
4026 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_buf_ratio", CTLFLAG_RW,
4027 &sc->ti_tx_buf_ratio, 0,
4028 "Ratio of NIC memory devoted to TX buffer");
4030 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "stat_ticks", CTLFLAG_RW,
4031 &sc->ti_stat_ticks, 0,
4032 "Number of clock ticks for statistics update interval");
4034 /* Pull in device tunables. */
4035 sc->ti_rx_coal_ticks = 170;
4036 resource_int_value(device_get_name(sc->ti_dev),
4037 device_get_unit(sc->ti_dev), "rx_coal_ticks",
4038 &sc->ti_rx_coal_ticks);
4039 sc->ti_rx_max_coal_bds = 64;
4040 resource_int_value(device_get_name(sc->ti_dev),
4041 device_get_unit(sc->ti_dev), "rx_max_coal_bds",
4042 &sc->ti_rx_max_coal_bds);
4044 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
4045 resource_int_value(device_get_name(sc->ti_dev),
4046 device_get_unit(sc->ti_dev), "tx_coal_ticks",
4047 &sc->ti_tx_coal_ticks);
4048 sc->ti_tx_max_coal_bds = 32;
4049 resource_int_value(device_get_name(sc->ti_dev),
4050 device_get_unit(sc->ti_dev), "tx_max_coal_bds",
4051 &sc->ti_tx_max_coal_bds);
4052 sc->ti_tx_buf_ratio = 21;
4053 resource_int_value(device_get_name(sc->ti_dev),
4054 device_get_unit(sc->ti_dev), "tx_buf_ratio",
4055 &sc->ti_tx_buf_ratio);
4057 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
4058 resource_int_value(device_get_name(sc->ti_dev),
4059 device_get_unit(sc->ti_dev), "stat_ticks",
4060 &sc->ti_stat_ticks);