2 * Copyright (c) 2004-07 Applied Micro Circuits Corporation.
3 * Copyright (c) 2004-05 Vinod Kashyap.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * AMCC'S 3ware driver for 9000 series storage controllers.
33 * Author: Vinod Kashyap
34 * Modifications by: Adam Radford
35 * Modifications by: Manjunath Ranganathaiah
46 * OS Layer internal macros, structures and functions.
50 #define TW_OSLI_DEVICE_NAME "3ware 9000 series Storage Controller"
52 #define TW_OSLI_MALLOC_CLASS M_TWA
53 #define TW_OSLI_MAX_NUM_IOS TW_CL_MAX_SIMULTANEOUS_REQUESTS
54 #define TW_OSLI_MAX_NUM_AENS 0x100
56 /* Disabled, doesn't work yet.
57 #define TW_OSLI_DEFERRED_INTR_USED
61 #define TW_OSLI_DMA_BOUNDARY (1u << 31)
63 #define TW_OSLI_DMA_BOUNDARY ((bus_size_t)((uint64_t)1 << 32))
66 /* Possible values of req->state. */
67 #define TW_OSLI_REQ_STATE_INIT 0x0 /* being initialized */
68 #define TW_OSLI_REQ_STATE_BUSY 0x1 /* submitted to CL */
69 #define TW_OSLI_REQ_STATE_PENDING 0x2 /* in pending queue */
70 #define TW_OSLI_REQ_STATE_COMPLETE 0x3 /* completed by CL */
72 /* Possible values of req->flags. */
73 #define TW_OSLI_REQ_FLAGS_DATA_IN (1<<0) /* read request */
74 #define TW_OSLI_REQ_FLAGS_DATA_OUT (1<<1) /* write request */
75 #define TW_OSLI_REQ_FLAGS_DATA_COPY_NEEDED (1<<2)/* data in ccb is misaligned,
76 have to copy to/from private buffer */
77 #define TW_OSLI_REQ_FLAGS_MAPPED (1<<3) /* request has been mapped */
78 #define TW_OSLI_REQ_FLAGS_IN_PROGRESS (1<<4) /* bus_dmamap_load returned
80 #define TW_OSLI_REQ_FLAGS_PASSTHRU (1<<5) /* pass through request */
81 #define TW_OSLI_REQ_FLAGS_SLEEPING (1<<6) /* owner sleeping on this cmd */
83 /* Possible values of sc->state. */
84 #define TW_OSLI_CTLR_STATE_OPEN (1<<0) /* control device is open */
85 #define TW_OSLI_CTLR_STATE_SIMQ_FROZEN (1<<1) /* simq frozen */
89 struct tw_osli_q_stats {
90 TW_UINT32 cur_len; /* current # of items in q */
91 TW_UINT32 max_len; /* max value reached by q_length */
93 #endif /* TW_OSL_DEBUG */
96 /* Queues of OSL internal request context packets. */
97 #define TW_OSLI_FREE_Q 0 /* free q */
98 #define TW_OSLI_BUSY_Q 1 /* q of reqs submitted to CL */
99 #define TW_OSLI_Q_COUNT 2 /* total number of queues */
101 /* Driver's request packet. */
102 struct tw_osli_req_context {
103 struct tw_cl_req_handle req_handle;/* tag to track req b/w OSL & CL */
104 struct twa_softc *ctlr; /* ptr to OSL's controller context */
105 TW_VOID *data; /* ptr to data being passed to CL */
106 TW_UINT32 length; /* length of buf being passed to CL */
109 * ptr to, and length of data passed to us from above, in case a buffer
110 * copy was done due to non-compliance to alignment requirements
113 TW_UINT32 real_length;
115 TW_UINT32 state; /* request state */
116 TW_UINT32 flags; /* request flags */
118 /* error encountered before request submission to CL */
119 TW_UINT32 error_code;
121 /* ptr to orig req for use during callback */
124 struct tw_cl_link link; /* to link this request in a list */
125 bus_dmamap_t dma_map;/* DMA map for data */
126 struct tw_cl_req_packet req_pkt;/* req pkt understood by CL */
130 /* Per-controller structure. */
132 struct tw_cl_ctlr_handle ctlr_handle;
133 struct tw_osli_req_context *req_ctxt_buf;
135 /* Controller state. */
141 TW_UINT32 sg_size_factor;
143 TW_VOID *non_dma_mem;
145 TW_UINT64 dma_mem_phys;
147 /* Request queues and arrays. */
148 struct tw_cl_link req_q_head[TW_OSLI_Q_COUNT];
150 struct task deferred_intr_callback;/* taskqueue function */
151 struct mtx io_lock_handle;/* general purpose lock */
152 struct mtx *io_lock;/* ptr to general purpose lock */
153 struct mtx q_lock_handle; /* queue manipulation lock */
154 struct mtx *q_lock;/* ptr to queue manipulation lock */
155 struct mtx sim_lock_handle;/* sim lock shared with cam */
156 struct mtx *sim_lock;/* ptr to sim lock */
159 struct tw_osli_q_stats q_stats[TW_OSLI_Q_COUNT];/* queue statistics */
160 #endif /* TW_OSL_DEBUG */
162 device_t bus_dev; /* bus device */
163 struct cdev *ctrl_dev; /* control device */
164 struct resource *reg_res; /* register interface window */
165 TW_INT32 reg_res_id; /* register resource id */
166 bus_space_handle_t bus_handle; /* bus space handle */
167 bus_space_tag_t bus_tag; /* bus space tag */
168 bus_dma_tag_t parent_tag; /* parent DMA tag */
169 bus_dma_tag_t cmd_tag; /* DMA tag for CL's DMA'able mem */
170 bus_dma_tag_t dma_tag; /* data buffer DMA tag */
171 bus_dma_tag_t ioctl_tag; /* ioctl data buffer DMA tag */
172 bus_dmamap_t cmd_map; /* DMA map for CL's DMA'able mem */
173 bus_dmamap_t ioctl_map; /* DMA map for ioctl data buffers */
174 struct resource *irq_res; /* interrupt resource */
175 TW_INT32 irq_res_id; /* register resource id */
176 TW_VOID *intr_handle; /* interrupt handle */
178 struct sysctl_ctx_list sysctl_ctxt; /* sysctl context */
179 struct sysctl_oid *sysctl_tree; /* sysctl oid */
181 struct cam_sim *sim; /* sim for this controller */
182 struct cam_path *path; /* peripheral, path, tgt, lun
183 associated with this controller */
194 #define TW_OSLI_Q_INIT(sc, q_type) do { \
195 (sc)->q_stats[q_type].cur_len = 0; \
196 (sc)->q_stats[q_type].max_len = 0; \
200 #define TW_OSLI_Q_INSERT(sc, q_type) do { \
201 struct tw_osli_q_stats *q_stats = &((sc)->q_stats[q_type]); \
203 if (++(q_stats->cur_len) > q_stats->max_len) \
204 q_stats->max_len = q_stats->cur_len; \
208 #define TW_OSLI_Q_REMOVE(sc, q_type) \
209 (sc)->q_stats[q_type].cur_len--
212 #else /* TW_OSL_DEBUG */
214 #define TW_OSLI_Q_INIT(sc, q_index)
215 #define TW_OSLI_Q_INSERT(sc, q_index)
216 #define TW_OSLI_Q_REMOVE(sc, q_index)
218 #endif /* TW_OSL_DEBUG */
222 /* Initialize a queue of requests. */
223 static __inline TW_VOID
224 tw_osli_req_q_init(struct twa_softc *sc, TW_UINT8 q_type)
226 TW_CL_Q_INIT(&(sc->req_q_head[q_type]));
227 TW_OSLI_Q_INIT(sc, q_type);
232 /* Insert the given request at the head of the given queue (q_type). */
233 static __inline TW_VOID
234 tw_osli_req_q_insert_head(struct tw_osli_req_context *req, TW_UINT8 q_type)
236 mtx_lock_spin(req->ctlr->q_lock);
237 TW_CL_Q_INSERT_HEAD(&(req->ctlr->req_q_head[q_type]), &(req->link));
238 TW_OSLI_Q_INSERT(req->ctlr, q_type);
239 mtx_unlock_spin(req->ctlr->q_lock);
244 /* Insert the given request at the tail of the given queue (q_type). */
245 static __inline TW_VOID
246 tw_osli_req_q_insert_tail(struct tw_osli_req_context *req, TW_UINT8 q_type)
248 mtx_lock_spin(req->ctlr->q_lock);
249 TW_CL_Q_INSERT_TAIL(&(req->ctlr->req_q_head[q_type]), &(req->link));
250 TW_OSLI_Q_INSERT(req->ctlr, q_type);
251 mtx_unlock_spin(req->ctlr->q_lock);
256 /* Remove and return the request at the head of the given queue (q_type). */
257 static __inline struct tw_osli_req_context *
258 tw_osli_req_q_remove_head(struct twa_softc *sc, TW_UINT8 q_type)
260 struct tw_osli_req_context *req = NULL;
261 struct tw_cl_link *link;
263 mtx_lock_spin(sc->q_lock);
264 if ((link = TW_CL_Q_FIRST_ITEM(&(sc->req_q_head[q_type]))) !=
266 req = TW_CL_STRUCT_HEAD(link,
267 struct tw_osli_req_context, link);
268 TW_CL_Q_REMOVE_ITEM(&(sc->req_q_head[q_type]), &(req->link));
269 TW_OSLI_Q_REMOVE(sc, q_type);
271 mtx_unlock_spin(sc->q_lock);
277 /* Remove the given request from the given queue (q_type). */
278 static __inline TW_VOID
279 tw_osli_req_q_remove_item(struct tw_osli_req_context *req, TW_UINT8 q_type)
281 mtx_lock_spin(req->ctlr->q_lock);
282 TW_CL_Q_REMOVE_ITEM(&(req->ctlr->req_q_head[q_type]), &(req->link));
283 TW_OSLI_Q_REMOVE(req->ctlr, q_type);
284 mtx_unlock_spin(req->ctlr->q_lock);
291 extern TW_INT32 TW_DEBUG_LEVEL_FOR_OSL;
293 #define tw_osli_dbg_dprintf(dbg_level, sc, fmt, args...) \
294 if (dbg_level <= TW_DEBUG_LEVEL_FOR_OSL) \
295 device_printf(sc->bus_dev, "%s: " fmt "\n", \
299 #define tw_osli_dbg_printf(dbg_level, fmt, args...) \
300 if (dbg_level <= TW_DEBUG_LEVEL_FOR_OSL) \
301 printf("%s: " fmt "\n", __func__, ##args)
303 #else /* TW_OSL_DEBUG */
305 #define tw_osli_dbg_dprintf(dbg_level, sc, fmt, args...)
306 #define tw_osli_dbg_printf(dbg_level, fmt, args...)
308 #endif /* TW_OSL_DEBUG */
311 /* For regular printing. */
312 #define twa_printf(sc, fmt, args...) \
313 device_printf(((struct twa_softc *)(sc))->bus_dev, fmt, ##args)
315 /* For printing in the "consistent error reporting" format. */
316 #define tw_osli_printf(sc, err_specific_desc, args...) \
317 device_printf((sc)->bus_dev, \
318 "%s: (0x%02X: 0x%04X): %s: " err_specific_desc "\n", ##args)
322 #endif /* TW_OSL_H */