sys/dev/usb/controller/xhci.c

   1 /*-
   2  * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  */
  25
  26 /*
  27  * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
  28  *
  29  * The XHCI 1.0 spec can be found at
  30  * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
  31  * and the USB 3.0 spec at
  32  * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
  33  */
  34
  35 /*
  36  * A few words about the design implementation: This driver emulates
  37  * the concept about TDs which is found in EHCI specification. This
  38  * way we avoid too much diveration among USB drivers.
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include <sys/stdint.h>
  45 #include <sys/stddef.h>
  46 #include <sys/param.h>
  47 #include <sys/queue.h>
  48 #include <sys/types.h>
  49 #include <sys/systm.h>
  50 #include <sys/kernel.h>
  51 #include <sys/bus.h>
  52 #include <sys/module.h>
  53 #include <sys/lock.h>
  54 #include <sys/mutex.h>
  55 #include <sys/condvar.h>
  56 #include <sys/sysctl.h>
  57 #include <sys/sx.h>
  58 #include <sys/unistd.h>
  59 #include <sys/callout.h>
  60 #include <sys/malloc.h>
  61 #include <sys/priv.h>
  62
  63 #include <dev/usb/usb.h>
  64 #include <dev/usb/usbdi.h>
  65
  66 #define USB_DEBUG_VAR xhcidebug
  67
  68 #include <dev/usb/usb_core.h>
  69 #include <dev/usb/usb_debug.h>
  70 #include <dev/usb/usb_busdma.h>
  71 #include <dev/usb/usb_process.h>
  72 #include <dev/usb/usb_transfer.h>
  73 #include <dev/usb/usb_device.h>
  74 #include <dev/usb/usb_hub.h>
  75 #include <dev/usb/usb_util.h>
  76
  77 #include <dev/usb/usb_controller.h>
  78 #include <dev/usb/usb_bus.h>
  79 #include <dev/usb/controller/xhci.h>
  80 #include <dev/usb/controller/xhcireg.h>
  81
  82 #define XHCI_BUS2SC(bus) \
  83    ((struct xhci_softc *)(((uint8_t *)(bus)) - \
  84     ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
  85
  86 #ifdef USB_DEBUG
  87 static int xhcidebug;
  88 static int xhciroute;
  89 static int xhcipolling;
  90
  91 SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
  92 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
  93     &xhcidebug, 0, "Debug level");
  94 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
  95 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN,
  96     &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller");
  97 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
  98 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RW | CTLFLAG_TUN,
  99     &xhcipolling, 0, "Set to enable software interrupt polling for XHCI controller");
 100 TUNABLE_INT("hw.usb.xhci.use_polling", &xhcipolling);
 101 #else
 102 #define xhciroute 0
 103 #endif
 104
 105 #define XHCI_INTR_ENDPT 1
 106
 107 struct xhci_std_temp {
 108         struct xhci_softc       *sc;
 109         struct usb_page_cache   *pc;
 110         struct xhci_td          *td;
 111         struct xhci_td          *td_next;
 112         uint32_t                len;
 113         uint32_t                offset;
 114         uint32_t                max_packet_size;
 115         uint32_t                average;
 116         uint16_t                isoc_delta;
 117         uint16_t                isoc_frame;
 118         uint8_t                 shortpkt;
 119         uint8_t                 multishort;
 120         uint8_t                 last_frame;
 121         uint8_t                 trb_type;
 122         uint8_t                 direction;
 123         uint8_t                 tbc;
 124         uint8_t                 tlbpc;
 125         uint8_t                 step_td;
 126         uint8_t                 do_isoc_sync;
 127 };
 128
 129 static void     xhci_do_poll(struct usb_bus *);
 130 static void     xhci_device_done(struct usb_xfer *, usb_error_t);
 131 static void     xhci_root_intr(struct xhci_softc *);
 132 static void     xhci_free_device_ext(struct usb_device *);
 133 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
 134                     struct usb_endpoint_descriptor *);
 135 static usb_proc_callback_t xhci_configure_msg;
 136 static usb_error_t xhci_configure_device(struct usb_device *);
 137 static usb_error_t xhci_configure_endpoint(struct usb_device *,
 138     struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *,
 139     uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t);
 140 static usb_error_t xhci_configure_mask(struct usb_device *,
 141                     uint32_t, uint8_t);
 142 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
 143                     uint64_t, uint8_t);
 144 static void xhci_endpoint_doorbell(struct usb_xfer *);
 145 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
 146 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
 147 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
 148 #ifdef USB_DEBUG
 149 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
 150 #endif
 151
 152 extern struct usb_bus_methods xhci_bus_methods;
 153
 154 #ifdef USB_DEBUG
 155 static void
 156 xhci_dump_trb(struct xhci_trb *trb)
 157 {
 158         DPRINTFN(5, "trb = %p\n", trb);
 159         DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
 160         DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
 161         DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
 162 }
 163
 164 static void
 165 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
 166 {
 167         DPRINTFN(5, "pep = %p\n", pep);
 168         DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
 169         DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
 170         DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
 171         DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
 172         DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
 173         DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
 174         DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
 175 }
 176
 177 static void
 178 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
 179 {
 180         DPRINTFN(5, "psl = %p\n", psl);
 181         DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
 182         DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
 183         DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
 184         DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
 185 }
 186 #endif
 187
 188 uint8_t
 189 xhci_use_polling(void)
 190 {
 191 #ifdef USB_DEBUG
 192         return (xhcipolling != 0);
 193 #else
 194         return (0);
 195 #endif
 196 }
 197
 198 static void
 199 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
 200 {
 201         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 202         uint16_t i;
 203
 204         cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
 205            sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
 206
 207         cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
 208            sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
 209
 210         for (i = 0; i != sc->sc_noscratch; i++) {
 211                 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
 212                     XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
 213         }
 214 }
 215
 216 static void
 217 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
 218 {
 219         if (sc->sc_ctx_is_64_byte) {
 220                 uint32_t offset;
 221                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 222                 /* all contexts are initially 32-bytes */
 223                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 224                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 225         }
 226         *ptr = htole32(val);
 227 }
 228
 229 static uint32_t
 230 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
 231 {
 232         if (sc->sc_ctx_is_64_byte) {
 233                 uint32_t offset;
 234                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 235                 /* all contexts are initially 32-bytes */
 236                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 237                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 238         }
 239         return (le32toh(*ptr));
 240 }
 241
 242 static void
 243 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
 244 {
 245         if (sc->sc_ctx_is_64_byte) {
 246                 uint32_t offset;
 247                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 248                 /* all contexts are initially 32-bytes */
 249                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 250                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 251         }
 252         *ptr = htole64(val);
 253 }
 254
 255 #ifdef USB_DEBUG
 256 static uint64_t
 257 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
 258 {
 259         if (sc->sc_ctx_is_64_byte) {
 260                 uint32_t offset;
 261                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 262                 /* all contexts are initially 32-bytes */
 263                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 264                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 265         }
 266         return (le64toh(*ptr));
 267 }
 268 #endif
 269
 270 static int
 271 xhci_reset_command_queue_locked(struct xhci_softc *sc)
 272 {
 273         struct usb_page_search buf_res;
 274         struct xhci_hw_root *phwr;
 275         uint64_t addr;
 276         uint32_t temp;
 277
 278         DPRINTF("\n");
 279
 280         temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 281         if (temp & XHCI_CRCR_LO_CRR) {
 282                 DPRINTF("Command ring running\n");
 283                 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
 284
 285                 /*
 286                  * Try to abort the last command as per section
 287                  * 4.6.1.2 "Aborting a Command" of the XHCI
 288                  * specification:
 289                  */
 290
 291                 /* stop and cancel */
 292                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
 293                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 294
 295                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
 296                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 297
 298                 /* wait 250ms */
 299                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
 300
 301                 /* check if command ring is still running */
 302                 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 303                 if (temp & XHCI_CRCR_LO_CRR) {
 304                         DPRINTF("Comand ring still running\n");
 305                         return (USB_ERR_IOERROR);
 306                 }
 307         }
 308
 309         /* reset command ring */
 310         sc->sc_command_ccs = 1;
 311         sc->sc_command_idx = 0;
 312
 313         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 314
 315         /* setup command ring control base address */
 316         addr = buf_res.physaddr;
 317         phwr = buf_res.buffer;
 318         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 319
 320         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 321
 322         memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
 323         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 324
 325         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
 326
 327         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 328         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 329
 330         return (0);
 331 }
 332
 333 usb_error_t
 334 xhci_start_controller(struct xhci_softc *sc)
 335 {
 336         struct usb_page_search buf_res;
 337         struct xhci_hw_root *phwr;
 338         struct xhci_dev_ctx_addr *pdctxa;
 339         uint64_t addr;
 340         uint32_t temp;
 341         uint16_t i;
 342
 343         DPRINTF("\n");
 344
 345         sc->sc_capa_off = 0;
 346         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 347         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
 348         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 349
 350         DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
 351         DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
 352         DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
 353
 354         sc->sc_event_ccs = 1;
 355         sc->sc_event_idx = 0;
 356         sc->sc_command_ccs = 1;
 357         sc->sc_command_idx = 0;
 358
 359         DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
 360
 361         temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
 362
 363         DPRINTF("HCS0 = 0x%08x\n", temp);
 364
 365         if (XHCI_HCS0_CSZ(temp)) {
 366                 sc->sc_ctx_is_64_byte = 1;
 367                 device_printf(sc->sc_bus.parent, "64 byte context size.\n");
 368         } else {
 369                 sc->sc_ctx_is_64_byte = 0;
 370                 device_printf(sc->sc_bus.parent, "32 byte context size.\n");
 371         }
 372
 373         /* Reset controller */
 374         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
 375
 376         for (i = 0; i != 100; i++) {
 377                 usb_pause_mtx(NULL, hz / 100);
 378                 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
 379                     (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
 380                 if (!temp)
 381                         break;
 382         }
 383
 384         if (temp) {
 385                 device_printf(sc->sc_bus.parent, "Controller "
 386                     "reset timeout.\n");
 387                 return (USB_ERR_IOERROR);
 388         }
 389
 390         if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
 391                 device_printf(sc->sc_bus.parent, "Controller does "
 392                     "not support 4K page size.\n");
 393                 return (USB_ERR_IOERROR);
 394         }
 395
 396         temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
 397
 398         i = XHCI_HCS1_N_PORTS(temp);
 399
 400         if (i == 0) {
 401                 device_printf(sc->sc_bus.parent, "Invalid number "
 402                     "of ports: %u\n", i);
 403                 return (USB_ERR_IOERROR);
 404         }
 405
 406         sc->sc_noport = i;
 407         sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
 408
 409         if (sc->sc_noslot > XHCI_MAX_DEVICES)
 410                 sc->sc_noslot = XHCI_MAX_DEVICES;
 411
 412         /* setup number of device slots */
 413
 414         DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
 415             XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
 416
 417         XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
 418
 419         DPRINTF("Max slots: %u\n", sc->sc_noslot);
 420
 421         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 422
 423         sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
 424
 425         if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
 426                 device_printf(sc->sc_bus.parent, "XHCI request "
 427                     "too many scratchpads\n");
 428                 return (USB_ERR_NOMEM);
 429         }
 430
 431         DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
 432
 433         temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
 434
 435         sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
 436             XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
 437
 438         temp = XREAD4(sc, oper, XHCI_USBSTS);
 439
 440         /* clear interrupts */
 441         XWRITE4(sc, oper, XHCI_USBSTS, temp);
 442         /* disable all device notifications */
 443         XWRITE4(sc, oper, XHCI_DNCTRL, 0);
 444
 445         /* setup device context base address */
 446         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
 447         pdctxa = buf_res.buffer;
 448         memset(pdctxa, 0, sizeof(*pdctxa));
 449
 450         addr = buf_res.physaddr;
 451         addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
 452
 453         /* slot 0 points to the table of scratchpad pointers */
 454         pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
 455
 456         for (i = 0; i != sc->sc_noscratch; i++) {
 457                 struct usb_page_search buf_scp;
 458                 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
 459                 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
 460         }
 461
 462         addr = buf_res.physaddr;
 463
 464         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 465         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 466         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 467         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 468
 469         /* Setup event table size */
 470
 471         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 472
 473         DPRINTF("HCS2=0x%08x\n", temp);
 474
 475         temp = XHCI_HCS2_ERST_MAX(temp);
 476         temp = 1U << temp;
 477         if (temp > XHCI_MAX_RSEG)
 478                 temp = XHCI_MAX_RSEG;
 479
 480         sc->sc_erst_max = temp;
 481
 482         DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
 483             XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp);
 484
 485         XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp));
 486
 487         /* Check if we should use the default IMOD value */
 488         if (sc->sc_imod_default == 0)
 489                 sc->sc_imod_default = XHCI_IMOD_DEFAULT;
 490
 491         /* Setup interrupt rate */
 492         XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default);
 493
 494         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 495
 496         phwr = buf_res.buffer;
 497         addr = buf_res.physaddr;
 498         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
 499
 500         /* reset hardware root structure */
 501         memset(phwr, 0, sizeof(*phwr));
 502
 503         phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
 504         phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
 505
 506         DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
 507
 508         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
 509         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
 510
 511         addr = buf_res.physaddr;
 512
 513         DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
 514
 515         XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
 516         XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
 517
 518         /* Setup interrupter registers */
 519
 520         temp = XREAD4(sc, runt, XHCI_IMAN(0));
 521         temp |= XHCI_IMAN_INTR_ENA;
 522         XWRITE4(sc, runt, XHCI_IMAN(0), temp);
 523
 524         /* setup command ring control base address */
 525         addr = buf_res.physaddr;
 526         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 527
 528         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 529
 530         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 531         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 532
 533         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 534
 535         usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 536
 537         /* Go! */
 538         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
 539             XHCI_CMD_INTE | XHCI_CMD_HSEE);
 540
 541         for (i = 0; i != 100; i++) {
 542                 usb_pause_mtx(NULL, hz / 100);
 543                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 544                 if (!temp)
 545                         break;
 546         }
 547         if (temp) {
 548                 XWRITE4(sc, oper, XHCI_USBCMD, 0);
 549                 device_printf(sc->sc_bus.parent, "Run timeout.\n");
 550                 return (USB_ERR_IOERROR);
 551         }
 552
 553         /* catch any lost interrupts */
 554         xhci_do_poll(&sc->sc_bus);
 555
 556         if (sc->sc_port_route != NULL) {
 557                 /* Route all ports to the XHCI by default */
 558                 sc->sc_port_route(sc->sc_bus.parent,
 559                     ~xhciroute, xhciroute);
 560         }
 561         return (0);
 562 }
 563
 564 usb_error_t
 565 xhci_halt_controller(struct xhci_softc *sc)
 566 {
 567         uint32_t temp;
 568         uint16_t i;
 569
 570         DPRINTF("\n");
 571
 572         sc->sc_capa_off = 0;
 573         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 574         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
 575         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 576
 577         /* Halt controller */
 578         XWRITE4(sc, oper, XHCI_USBCMD, 0);
 579
 580         for (i = 0; i != 100; i++) {
 581                 usb_pause_mtx(NULL, hz / 100);
 582                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 583                 if (temp)
 584                         break;
 585         }
 586
 587         if (!temp) {
 588                 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
 589                 return (USB_ERR_IOERROR);
 590         }
 591         return (0);
 592 }
 593
 594 usb_error_t
 595 xhci_init(struct xhci_softc *sc, device_t self)
 596 {
 597         /* initialise some bus fields */
 598         sc->sc_bus.parent = self;
 599
 600         /* set the bus revision */
 601         sc->sc_bus.usbrev = USB_REV_3_0;
 602
 603         /* set up the bus struct */
 604         sc->sc_bus.methods = &xhci_bus_methods;
 605
 606         /* setup devices array */
 607         sc->sc_bus.devices = sc->sc_devices;
 608         sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
 609
 610         /* set default cycle state in case of early interrupts */
 611         sc->sc_event_ccs = 1;
 612         sc->sc_command_ccs = 1;
 613
 614         /* setup command queue mutex and condition varible */
 615         cv_init(&sc->sc_cmd_cv, "CMDQ");
 616         sx_init(&sc->sc_cmd_sx, "CMDQ lock");
 617
 618         /* get all DMA memory */
 619         if (usb_bus_mem_alloc_all(&sc->sc_bus,
 620             USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
 621                 return (ENOMEM);
 622         }
 623
 624         sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
 625         sc->sc_config_msg[0].bus = &sc->sc_bus;
 626         sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
 627         sc->sc_config_msg[1].bus = &sc->sc_bus;
 628
 629         if (usb_proc_create(&sc->sc_config_proc,
 630             &sc->sc_bus.bus_mtx, device_get_nameunit(self), USB_PRI_MED)) {
 631                 printf("WARNING: Creation of XHCI configure "
 632                     "callback process failed.\n");
 633         }
 634         return (0);
 635 }
 636
 637 void
 638 xhci_uninit(struct xhci_softc *sc)
 639 {
 640         usb_proc_free(&sc->sc_config_proc);
 641
 642         usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 643
 644         cv_destroy(&sc->sc_cmd_cv);
 645         sx_destroy(&sc->sc_cmd_sx);
 646 }
 647
 648 static void
 649 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
 650 {
 651         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 652
 653         switch (state) {
 654         case USB_HW_POWER_SUSPEND:
 655                 DPRINTF("Stopping the XHCI\n");
 656                 xhci_halt_controller(sc);
 657                 break;
 658         case USB_HW_POWER_SHUTDOWN:
 659                 DPRINTF("Stopping the XHCI\n");
 660                 xhci_halt_controller(sc);
 661                 break;
 662         case USB_HW_POWER_RESUME:
 663                 DPRINTF("Starting the XHCI\n");
 664                 xhci_start_controller(sc);
 665                 break;
 666         default:
 667                 break;
 668         }
 669 }
 670
 671 static usb_error_t
 672 xhci_generic_done_sub(struct usb_xfer *xfer)
 673 {
 674         struct xhci_td *td;
 675         struct xhci_td *td_alt_next;
 676         uint32_t len;
 677         uint8_t status;
 678
 679         td = xfer->td_transfer_cache;
 680         td_alt_next = td->alt_next;
 681
 682         if (xfer->aframes != xfer->nframes)
 683                 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
 684
 685         while (1) {
 686
 687                 usb_pc_cpu_invalidate(td->page_cache);
 688
 689                 status = td->status;
 690                 len = td->remainder;
 691
 692                 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
 693                     xfer, (unsigned int)xfer->aframes,
 694                     (unsigned int)xfer->nframes,
 695                     (unsigned int)len, (unsigned int)td->len,
 696                     (unsigned int)status);
 697
 698                 /*
 699                  * Verify the status length and
 700                  * add the length to "frlengths[]":
 701                  */
 702                 if (len > td->len) {
 703                         /* should not happen */
 704                         DPRINTF("Invalid status length, "
 705                             "0x%04x/0x%04x bytes\n", len, td->len);
 706                         status = XHCI_TRB_ERROR_LENGTH;
 707                 } else if (xfer->aframes != xfer->nframes) {
 708                         xfer->frlengths[xfer->aframes] += td->len - len;
 709                 }
 710                 /* Check for last transfer */
 711                 if (((void *)td) == xfer->td_transfer_last) {
 712                         td = NULL;
 713                         break;
 714                 }
 715                 /* Check for transfer error */
 716                 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
 717                     status != XHCI_TRB_ERROR_SUCCESS) {
 718                         /* the transfer is finished */
 719                         td = NULL;
 720                         break;
 721                 }
 722                 /* Check for short transfer */
 723                 if (len > 0) {
 724                         if (xfer->flags_int.short_frames_ok ||
 725                             xfer->flags_int.isochronous_xfr ||
 726                             xfer->flags_int.control_xfr) {
 727                                 /* follow alt next */
 728                                 td = td->alt_next;
 729                         } else {
 730                                 /* the transfer is finished */
 731                                 td = NULL;
 732                         }
 733                         break;
 734                 }
 735                 td = td->obj_next;
 736
 737                 if (td->alt_next != td_alt_next) {
 738                         /* this USB frame is complete */
 739                         break;
 740                 }
 741         }
 742
 743         /* update transfer cache */
 744
 745         xfer->td_transfer_cache = td;
 746
 747         return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
 748             (status != XHCI_TRB_ERROR_SHORT_PKT &&
 749             status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
 750             USB_ERR_NORMAL_COMPLETION);
 751 }
 752
 753 static void
 754 xhci_generic_done(struct usb_xfer *xfer)
 755 {
 756         usb_error_t err = 0;
 757
 758         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
 759             xfer, xfer->endpoint);
 760
 761         /* reset scanner */
 762
 763         xfer->td_transfer_cache = xfer->td_transfer_first;
 764
 765         if (xfer->flags_int.control_xfr) {
 766
 767                 if (xfer->flags_int.control_hdr)
 768                         err = xhci_generic_done_sub(xfer);
 769
 770                 xfer->aframes = 1;
 771
 772                 if (xfer->td_transfer_cache == NULL)
 773                         goto done;
 774         }
 775
 776         while (xfer->aframes != xfer->nframes) {
 777
 778                 err = xhci_generic_done_sub(xfer);
 779                 xfer->aframes++;
 780
 781                 if (xfer->td_transfer_cache == NULL)
 782                         goto done;
 783         }
 784
 785         if (xfer->flags_int.control_xfr &&
 786             !xfer->flags_int.control_act)
 787                 err = xhci_generic_done_sub(xfer);
 788 done:
 789         /* transfer is complete */
 790         xhci_device_done(xfer, err);
 791 }
 792
 793 static void
 794 xhci_activate_transfer(struct usb_xfer *xfer)
 795 {
 796         struct xhci_td *td;
 797
 798         td = xfer->td_transfer_cache;
 799
 800         usb_pc_cpu_invalidate(td->page_cache);
 801
 802         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 803
 804                 /* activate the transfer */
 805
 806                 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
 807                 usb_pc_cpu_flush(td->page_cache);
 808
 809                 xhci_endpoint_doorbell(xfer);
 810         }
 811 }
 812
 813 static void
 814 xhci_skip_transfer(struct usb_xfer *xfer)
 815 {
 816         struct xhci_td *td;
 817         struct xhci_td *td_last;
 818
 819         td = xfer->td_transfer_cache;
 820         td_last = xfer->td_transfer_last;
 821
 822         td = td->alt_next;
 823
 824         usb_pc_cpu_invalidate(td->page_cache);
 825
 826         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 827
 828                 usb_pc_cpu_invalidate(td_last->page_cache);
 829
 830                 /* copy LINK TRB to current waiting location */
 831
 832                 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
 833                 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
 834                 usb_pc_cpu_flush(td->page_cache);
 835
 836                 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
 837                 usb_pc_cpu_flush(td->page_cache);
 838
 839                 xhci_endpoint_doorbell(xfer);
 840         }
 841 }
 842
 843 /*------------------------------------------------------------------------*
 844  *      xhci_check_transfer
 845  *------------------------------------------------------------------------*/
 846 static void
 847 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
 848 {
 849         int64_t offset;
 850         uint64_t td_event;
 851         uint32_t temp;
 852         uint32_t remainder;
 853         uint8_t status;
 854         uint8_t halted;
 855         uint8_t epno;
 856         uint8_t index;
 857         uint8_t i;
 858
 859         /* decode TRB */
 860         td_event = le64toh(trb->qwTrb0);
 861         temp = le32toh(trb->dwTrb2);
 862
 863         remainder = XHCI_TRB_2_REM_GET(temp);
 864         status = XHCI_TRB_2_ERROR_GET(temp);
 865
 866         temp = le32toh(trb->dwTrb3);
 867         epno = XHCI_TRB_3_EP_GET(temp);
 868         index = XHCI_TRB_3_SLOT_GET(temp);
 869
 870         /* check if error means halted */
 871         halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
 872             status != XHCI_TRB_ERROR_SUCCESS);
 873
 874         DPRINTF("slot=%u epno=%u remainder=%u status=%u\n",
 875             index, epno, remainder, status);
 876
 877         if (index > sc->sc_noslot) {
 878                 DPRINTF("Invalid slot.\n");
 879                 return;
 880         }
 881
 882         if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
 883                 DPRINTF("Invalid endpoint.\n");
 884                 return;
 885         }
 886
 887         /* try to find the USB transfer that generated the event */
 888         for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
 889                 struct usb_xfer *xfer;
 890                 struct xhci_td *td;
 891                 struct xhci_endpoint_ext *pepext;
 892
 893                 pepext = &sc->sc_hw.devs[index].endp[epno];
 894
 895                 xfer = pepext->xfer[i];
 896                 if (xfer == NULL)
 897                         continue;
 898
 899                 td = xfer->td_transfer_cache;
 900
 901                 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
 902                         (long long)td_event,
 903                         (long long)td->td_self,
 904                         (long long)td->td_self + sizeof(td->td_trb));
 905
 906                 /*
 907                  * NOTE: Some XHCI implementations might not trigger
 908                  * an event on the last LINK TRB so we need to
 909                  * consider both the last and second last event
 910                  * address as conditions for a successful transfer.
 911                  *
 912                  * NOTE: We assume that the XHCI will only trigger one
 913                  * event per chain of TRBs.
 914                  */
 915
 916                 offset = td_event - td->td_self;
 917
 918                 if (offset >= 0 &&
 919                     offset < (int64_t)sizeof(td->td_trb)) {
 920
 921                         usb_pc_cpu_invalidate(td->page_cache);
 922
 923                         /* compute rest of remainder, if any */
 924                         for (i = (offset / 16) + 1; i < td->ntrb; i++) {
 925                                 temp = le32toh(td->td_trb[i].dwTrb2);
 926                                 remainder += XHCI_TRB_2_BYTES_GET(temp);
 927                         }
 928
 929                         DPRINTFN(5, "New remainder: %u\n", remainder);
 930
 931                         /* clear isochronous transfer errors */
 932                         if (xfer->flags_int.isochronous_xfr) {
 933                                 if (halted) {
 934                                         halted = 0;
 935                                         status = XHCI_TRB_ERROR_SUCCESS;
 936                                         remainder = td->len;
 937                                 }
 938                         }
 939
 940                         /* "td->remainder" is verified later */
 941                         td->remainder = remainder;
 942                         td->status = status;
 943
 944                         usb_pc_cpu_flush(td->page_cache);
 945
 946                         /*
 947                          * 1) Last transfer descriptor makes the
 948                          * transfer done
 949                          */
 950                         if (((void *)td) == xfer->td_transfer_last) {
 951                                 DPRINTF("TD is last\n");
 952                                 xhci_generic_done(xfer);
 953                                 break;
 954                         }
 955
 956                         /*
 957                          * 2) Any kind of error makes the transfer
 958                          * done
 959                          */
 960                         if (halted) {
 961                                 DPRINTF("TD has I/O error\n");
 962                                 xhci_generic_done(xfer);
 963                                 break;
 964                         }
 965
 966                         /*
 967                          * 3) If there is no alternate next transfer,
 968                          * a short packet also makes the transfer done
 969                          */
 970                         if (td->remainder > 0) {
 971                                 if (td->alt_next == NULL) {
 972                                         DPRINTF(
 973                                             "short TD has no alternate next\n");
 974                                         xhci_generic_done(xfer);
 975                                         break;
 976                                 }
 977                                 DPRINTF("TD has short pkt\n");
 978                                 if (xfer->flags_int.short_frames_ok ||
 979                                     xfer->flags_int.isochronous_xfr ||
 980                                     xfer->flags_int.control_xfr) {
 981                                         /* follow the alt next */
 982                                         xfer->td_transfer_cache = td->alt_next;
 983                                         xhci_activate_transfer(xfer);
 984                                         break;
 985                                 }
 986                                 xhci_skip_transfer(xfer);
 987                                 xhci_generic_done(xfer);
 988                                 break;
 989                         }
 990
 991                         /*
 992                          * 4) Transfer complete - go to next TD
 993                          */
 994                         DPRINTF("Following next TD\n");
 995                         xfer->td_transfer_cache = td->obj_next;
 996                         xhci_activate_transfer(xfer);
 997                         break;          /* there should only be one match */
 998                 }
 999         }
1000 }
1001
1002 static int
1003 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
1004 {
1005         if (sc->sc_cmd_addr == trb->qwTrb0) {
1006                 DPRINTF("Received command event\n");
1007                 sc->sc_cmd_result[0] = trb->dwTrb2;
1008                 sc->sc_cmd_result[1] = trb->dwTrb3;
1009                 cv_signal(&sc->sc_cmd_cv);
1010                 return (1);     /* command match */
1011         }
1012         return (0);
1013 }
1014
1015 static int
1016 xhci_interrupt_poll(struct xhci_softc *sc)
1017 {
1018         struct usb_page_search buf_res;
1019         struct xhci_hw_root *phwr;
1020         uint64_t addr;
1021         uint32_t temp;
1022         int retval = 0;
1023         uint16_t i;
1024         uint8_t event;
1025         uint8_t j;
1026         uint8_t k;
1027         uint8_t t;
1028
1029         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1030
1031         phwr = buf_res.buffer;
1032
1033         /* Receive any events */
1034
1035         usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1036
1037         i = sc->sc_event_idx;
1038         j = sc->sc_event_ccs;
1039         t = 2;
1040
1041         while (1) {
1042
1043                 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1044
1045                 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1046
1047                 if (j != k)
1048                         break;
1049
1050                 event = XHCI_TRB_3_TYPE_GET(temp);
1051
1052                 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1053                     i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1054                     (long)le32toh(phwr->hwr_events[i].dwTrb2),
1055                     (long)le32toh(phwr->hwr_events[i].dwTrb3));
1056
1057                 switch (event) {
1058                 case XHCI_TRB_EVENT_TRANSFER:
1059                         xhci_check_transfer(sc, &phwr->hwr_events[i]);
1060                         break;
1061                 case XHCI_TRB_EVENT_CMD_COMPLETE:
1062                         retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1063                         break;
1064                 default:
1065                         DPRINTF("Unhandled event = %u\n", event);
1066                         break;
1067                 }
1068
1069                 i++;
1070
1071                 if (i == XHCI_MAX_EVENTS) {
1072                         i = 0;
1073                         j ^= 1;
1074
1075                         /* check for timeout */
1076                         if (!--t)
1077                                 break;
1078                 }
1079         }
1080
1081         sc->sc_event_idx = i;
1082         sc->sc_event_ccs = j;
1083
1084         /*
1085          * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1086          * latched. That means to activate the register we need to
1087          * write both the low and high double word of the 64-bit
1088          * register.
1089          */
1090
1091         addr = buf_res.physaddr;
1092         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1093
1094         /* try to clear busy bit */
1095         addr |= XHCI_ERDP_LO_BUSY;
1096
1097         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1098         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1099
1100         return (retval);
1101 }
1102
1103 static usb_error_t
1104 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1105     uint16_t timeout_ms)
1106 {
1107         struct usb_page_search buf_res;
1108         struct xhci_hw_root *phwr;
1109         uint64_t addr;
1110         uint32_t temp;
1111         uint8_t i;
1112         uint8_t j;
1113         uint8_t timeout = 0;
1114         int err;
1115
1116         XHCI_CMD_ASSERT_LOCKED(sc);
1117
1118         /* get hardware root structure */
1119
1120         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1121
1122         phwr = buf_res.buffer;
1123
1124         /* Queue command */
1125
1126         USB_BUS_LOCK(&sc->sc_bus);
1127 retry:
1128         i = sc->sc_command_idx;
1129         j = sc->sc_command_ccs;
1130
1131         DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1132             i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1133             (long long)le64toh(trb->qwTrb0),
1134             (long)le32toh(trb->dwTrb2),
1135             (long)le32toh(trb->dwTrb3));
1136
1137         phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1138         phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1139
1140         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1141
1142         temp = trb->dwTrb3;
1143
1144         if (j)
1145                 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1146         else
1147                 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1148
1149         temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1150
1151         phwr->hwr_commands[i].dwTrb3 = temp;
1152
1153         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1154
1155         addr = buf_res.physaddr;
1156         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1157
1158         sc->sc_cmd_addr = htole64(addr);
1159
1160         i++;
1161
1162         if (i == (XHCI_MAX_COMMANDS - 1)) {
1163
1164                 if (j) {
1165                         temp = htole32(XHCI_TRB_3_TC_BIT |
1166                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1167                             XHCI_TRB_3_CYCLE_BIT);
1168                 } else {
1169                         temp = htole32(XHCI_TRB_3_TC_BIT |
1170                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1171                 }
1172
1173                 phwr->hwr_commands[i].dwTrb3 = temp;
1174
1175                 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1176
1177                 i = 0;
1178                 j ^= 1;
1179         }
1180
1181         sc->sc_command_idx = i;
1182         sc->sc_command_ccs = j;
1183
1184         XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1185
1186         err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1187             USB_MS_TO_TICKS(timeout_ms));
1188
1189         /*
1190          * In some error cases event interrupts are not generated.
1191          * Poll one time to see if the command has completed.
1192          */
1193         if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1194                 DPRINTF("Command was completed when polling\n");
1195                 err = 0;
1196         }
1197         if (err != 0) {
1198                 DPRINTF("Command timeout!\n");
1199                 /*
1200                  * After some weeks of continuous operation, it has
1201                  * been observed that the ASMedia Technology, ASM1042
1202                  * SuperSpeed USB Host Controller can suddenly stop
1203                  * accepting commands via the command queue. Try to
1204                  * first reset the command queue. If that fails do a
1205                  * host controller reset.
1206                  */
1207                 if (timeout == 0 &&
1208                     xhci_reset_command_queue_locked(sc) == 0) {
1209                         temp = le32toh(trb->dwTrb3);
1210
1211                         /*
1212                          * Avoid infinite XHCI reset loops if the set
1213                          * address command fails to respond due to a
1214                          * non-enumerating device:
1215                          */
1216                         if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE &&
1217                             (temp & XHCI_TRB_3_BSR_BIT) == 0) {
1218                                 DPRINTF("Set address timeout\n");
1219                         } else {
1220                                 timeout = 1;
1221                                 goto retry;
1222                         }
1223                 } else {
1224                         DPRINTF("Controller reset!\n");
1225                         usb_bus_reset_async_locked(&sc->sc_bus);
1226                 }
1227                 err = USB_ERR_TIMEOUT;
1228                 trb->dwTrb2 = 0;
1229                 trb->dwTrb3 = 0;
1230         } else {
1231                 temp = le32toh(sc->sc_cmd_result[0]);
1232                 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1233                         err = USB_ERR_IOERROR;
1234
1235                 trb->dwTrb2 = sc->sc_cmd_result[0];
1236                 trb->dwTrb3 = sc->sc_cmd_result[1];
1237         }
1238
1239         USB_BUS_UNLOCK(&sc->sc_bus);
1240
1241         return (err);
1242 }
1243
1244 #if 0
1245 static usb_error_t
1246 xhci_cmd_nop(struct xhci_softc *sc)
1247 {
1248         struct xhci_trb trb;
1249         uint32_t temp;
1250
1251         DPRINTF("\n");
1252
1253         trb.qwTrb0 = 0;
1254         trb.dwTrb2 = 0;
1255         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1256
1257         trb.dwTrb3 = htole32(temp);
1258
1259         return (xhci_do_command(sc, &trb, 100 /* ms */));
1260 }
1261 #endif
1262
1263 static usb_error_t
1264 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1265 {
1266         struct xhci_trb trb;
1267         uint32_t temp;
1268         usb_error_t err;
1269
1270         DPRINTF("\n");
1271
1272         trb.qwTrb0 = 0;
1273         trb.dwTrb2 = 0;
1274         trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1275
1276         err = xhci_do_command(sc, &trb, 100 /* ms */);
1277         if (err)
1278                 goto done;
1279
1280         temp = le32toh(trb.dwTrb3);
1281
1282         *pslot = XHCI_TRB_3_SLOT_GET(temp);
1283
1284 done:
1285         return (err);
1286 }
1287
1288 static usb_error_t
1289 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1290 {
1291         struct xhci_trb trb;
1292         uint32_t temp;
1293
1294         DPRINTF("\n");
1295
1296         trb.qwTrb0 = 0;
1297         trb.dwTrb2 = 0;
1298         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1299             XHCI_TRB_3_SLOT_SET(slot_id);
1300
1301         trb.dwTrb3 = htole32(temp);
1302
1303         return (xhci_do_command(sc, &trb, 100 /* ms */));
1304 }
1305
1306 static usb_error_t
1307 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1308     uint8_t bsr, uint8_t slot_id)
1309 {
1310         struct xhci_trb trb;
1311         uint32_t temp;
1312
1313         DPRINTF("\n");
1314
1315         trb.qwTrb0 = htole64(input_ctx);
1316         trb.dwTrb2 = 0;
1317         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1318             XHCI_TRB_3_SLOT_SET(slot_id);
1319
1320         if (bsr)
1321                 temp |= XHCI_TRB_3_BSR_BIT;
1322
1323         trb.dwTrb3 = htole32(temp);
1324
1325         return (xhci_do_command(sc, &trb, 500 /* ms */));
1326 }
1327
1328 static usb_error_t
1329 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1330 {
1331         struct usb_page_search buf_inp;
1332         struct usb_page_search buf_dev;
1333         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1334         struct xhci_hw_dev *hdev;
1335         struct xhci_dev_ctx *pdev;
1336         struct xhci_endpoint_ext *pepext;
1337         uint32_t temp;
1338         uint16_t mps;
1339         usb_error_t err;
1340         uint8_t index;
1341
1342         /* the root HUB case is not handled here */
1343         if (udev->parent_hub == NULL)
1344                 return (USB_ERR_INVAL);
1345
1346         index = udev->controller_slot_id;
1347
1348         hdev =  &sc->sc_hw.devs[index];
1349
1350         if (mtx != NULL)
1351                 mtx_unlock(mtx);
1352
1353         XHCI_CMD_LOCK(sc);
1354
1355         switch (hdev->state) {
1356         case XHCI_ST_DEFAULT:
1357         case XHCI_ST_ENABLED:
1358
1359                 hdev->state = XHCI_ST_ENABLED;
1360
1361                 /* set configure mask to slot and EP0 */
1362                 xhci_configure_mask(udev, 3, 0);
1363
1364                 /* configure input slot context structure */
1365                 err = xhci_configure_device(udev);
1366
1367                 if (err != 0) {
1368                         DPRINTF("Could not configure device\n");
1369                         break;
1370                 }
1371
1372                 /* configure input endpoint context structure */
1373                 switch (udev->speed) {
1374                 case USB_SPEED_LOW:
1375                 case USB_SPEED_FULL:
1376                         mps = 8;
1377                         break;
1378                 case USB_SPEED_HIGH:
1379                         mps = 64;
1380                         break;
1381                 default:
1382                         mps = 512;
1383                         break;
1384                 }
1385
1386                 pepext = xhci_get_endpoint_ext(udev,
1387                     &udev->ctrl_ep_desc);
1388
1389                 /* ensure the control endpoint is setup again */
1390                 USB_BUS_LOCK(udev->bus);
1391                 pepext->trb_halted = 1;
1392                 pepext->trb_running = 0;
1393                 USB_BUS_UNLOCK(udev->bus);
1394
1395                 err = xhci_configure_endpoint(udev,
1396                     &udev->ctrl_ep_desc, pepext,
1397                     0, 1, 1, 0, mps, mps);
1398
1399                 if (err != 0) {
1400                         DPRINTF("Could not configure default endpoint\n");
1401                         break;
1402                 }
1403
1404                 /* execute set address command */
1405                 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1406
1407                 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1408                     (address == 0), index);
1409
1410                 if (err != 0) {
1411                         temp = le32toh(sc->sc_cmd_result[0]);
1412                         if (address == 0 && sc->sc_port_route != NULL &&
1413                             XHCI_TRB_2_ERROR_GET(temp) ==
1414                             XHCI_TRB_ERROR_PARAMETER) {
1415                                 /* LynxPoint XHCI - ports are not switchable */
1416                                 /* Un-route all ports from the XHCI */
1417                                 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1418                         }
1419                         DPRINTF("Could not set address "
1420                             "for slot %u.\n", index);
1421                         if (address != 0)
1422                                 break;
1423                 }
1424
1425                 /* update device address to new value */
1426
1427                 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1428                 pdev = buf_dev.buffer;
1429                 usb_pc_cpu_invalidate(&hdev->device_pc);
1430
1431                 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1432                 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1433
1434                 /* update device state to new value */
1435
1436                 if (address != 0)
1437                         hdev->state = XHCI_ST_ADDRESSED;
1438                 else
1439                         hdev->state = XHCI_ST_DEFAULT;
1440                 break;
1441
1442         default:
1443                 DPRINTF("Wrong state for set address.\n");
1444                 err = USB_ERR_IOERROR;
1445                 break;
1446         }
1447         XHCI_CMD_UNLOCK(sc);
1448
1449         if (mtx != NULL)
1450                 mtx_lock(mtx);
1451
1452         return (err);
1453 }
1454
1455 static usb_error_t
1456 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1457     uint8_t deconfigure, uint8_t slot_id)
1458 {
1459         struct xhci_trb trb;
1460         uint32_t temp;
1461
1462         DPRINTF("\n");
1463
1464         trb.qwTrb0 = htole64(input_ctx);
1465         trb.dwTrb2 = 0;
1466         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1467             XHCI_TRB_3_SLOT_SET(slot_id);
1468
1469         if (deconfigure)
1470                 temp |= XHCI_TRB_3_DCEP_BIT;
1471
1472         trb.dwTrb3 = htole32(temp);
1473
1474         return (xhci_do_command(sc, &trb, 100 /* ms */));
1475 }
1476
1477 static usb_error_t
1478 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1479     uint8_t slot_id)
1480 {
1481         struct xhci_trb trb;
1482         uint32_t temp;
1483
1484         DPRINTF("\n");
1485
1486         trb.qwTrb0 = htole64(input_ctx);
1487         trb.dwTrb2 = 0;
1488         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1489             XHCI_TRB_3_SLOT_SET(slot_id);
1490         trb.dwTrb3 = htole32(temp);
1491
1492         return (xhci_do_command(sc, &trb, 100 /* ms */));
1493 }
1494
1495 static usb_error_t
1496 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1497     uint8_t ep_id, uint8_t slot_id)
1498 {
1499         struct xhci_trb trb;
1500         uint32_t temp;
1501
1502         DPRINTF("\n");
1503
1504         trb.qwTrb0 = 0;
1505         trb.dwTrb2 = 0;
1506         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1507             XHCI_TRB_3_SLOT_SET(slot_id) |
1508             XHCI_TRB_3_EP_SET(ep_id);
1509
1510         if (preserve)
1511                 temp |= XHCI_TRB_3_PRSV_BIT;
1512
1513         trb.dwTrb3 = htole32(temp);
1514
1515         return (xhci_do_command(sc, &trb, 100 /* ms */));
1516 }
1517
1518 static usb_error_t
1519 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1520     uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1521 {
1522         struct xhci_trb trb;
1523         uint32_t temp;
1524
1525         DPRINTF("\n");
1526
1527         trb.qwTrb0 = htole64(dequeue_ptr);
1528
1529         temp = XHCI_TRB_2_STREAM_SET(stream_id);
1530         trb.dwTrb2 = htole32(temp);
1531
1532         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1533             XHCI_TRB_3_SLOT_SET(slot_id) |
1534             XHCI_TRB_3_EP_SET(ep_id);
1535         trb.dwTrb3 = htole32(temp);
1536
1537         return (xhci_do_command(sc, &trb, 100 /* ms */));
1538 }
1539
1540 static usb_error_t
1541 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1542     uint8_t ep_id, uint8_t slot_id)
1543 {
1544         struct xhci_trb trb;
1545         uint32_t temp;
1546
1547         DPRINTF("\n");
1548
1549         trb.qwTrb0 = 0;
1550         trb.dwTrb2 = 0;
1551         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1552             XHCI_TRB_3_SLOT_SET(slot_id) |
1553             XHCI_TRB_3_EP_SET(ep_id);
1554
1555         if (suspend)
1556                 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1557
1558         trb.dwTrb3 = htole32(temp);
1559
1560         return (xhci_do_command(sc, &trb, 100 /* ms */));
1561 }
1562
1563 static usb_error_t
1564 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1565 {
1566         struct xhci_trb trb;
1567         uint32_t temp;
1568
1569         DPRINTF("\n");
1570
1571         trb.qwTrb0 = 0;
1572         trb.dwTrb2 = 0;
1573         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1574             XHCI_TRB_3_SLOT_SET(slot_id);
1575
1576         trb.dwTrb3 = htole32(temp);
1577
1578         return (xhci_do_command(sc, &trb, 100 /* ms */));
1579 }
1580
1581 /*------------------------------------------------------------------------*
1582  *      xhci_interrupt - XHCI interrupt handler
1583  *------------------------------------------------------------------------*/
1584 void
1585 xhci_interrupt(struct xhci_softc *sc)
1586 {
1587         uint32_t status;
1588         uint32_t temp;
1589
1590         USB_BUS_LOCK(&sc->sc_bus);
1591
1592         status = XREAD4(sc, oper, XHCI_USBSTS);
1593
1594         /* acknowledge interrupts, if any */
1595         if (status != 0) {
1596                 XWRITE4(sc, oper, XHCI_USBSTS, status);
1597                 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1598         }
1599
1600         temp = XREAD4(sc, runt, XHCI_IMAN(0));
1601
1602         /* force clearing of pending interrupts */
1603         if (temp & XHCI_IMAN_INTR_PEND)
1604                 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1605
1606         /* check for event(s) */
1607         xhci_interrupt_poll(sc);
1608
1609         if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1610             XHCI_STS_HSE | XHCI_STS_HCE)) {
1611
1612                 if (status & XHCI_STS_PCD) {
1613                         xhci_root_intr(sc);
1614                 }
1615
1616                 if (status & XHCI_STS_HCH) {
1617                         printf("%s: host controller halted\n",
1618                             __FUNCTION__);
1619                 }
1620
1621                 if (status & XHCI_STS_HSE) {
1622                         printf("%s: host system error\n",
1623                             __FUNCTION__);
1624                 }
1625
1626                 if (status & XHCI_STS_HCE) {
1627                         printf("%s: host controller error\n",
1628                            __FUNCTION__);
1629                 }
1630         }
1631         USB_BUS_UNLOCK(&sc->sc_bus);
1632 }
1633
1634 /*------------------------------------------------------------------------*
1635  *      xhci_timeout - XHCI timeout handler
1636  *------------------------------------------------------------------------*/
1637 static void
1638 xhci_timeout(void *arg)
1639 {
1640         struct usb_xfer *xfer = arg;
1641
1642         DPRINTF("xfer=%p\n", xfer);
1643
1644         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1645
1646         /* transfer is transferred */
1647         xhci_device_done(xfer, USB_ERR_TIMEOUT);
1648 }
1649
1650 static void
1651 xhci_do_poll(struct usb_bus *bus)
1652 {
1653         struct xhci_softc *sc = XHCI_BUS2SC(bus);
1654
1655         USB_BUS_LOCK(&sc->sc_bus);
1656         xhci_interrupt_poll(sc);
1657         USB_BUS_UNLOCK(&sc->sc_bus);
1658 }
1659
1660 static void
1661 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1662 {
1663         struct usb_page_search buf_res;
1664         struct xhci_td *td;
1665         struct xhci_td *td_next;
1666         struct xhci_td *td_alt_next;
1667         struct xhci_td *td_first;
1668         uint32_t buf_offset;
1669         uint32_t average;
1670         uint32_t len_old;
1671         uint32_t npkt_off;
1672         uint32_t dword;
1673         uint8_t shortpkt_old;
1674         uint8_t precompute;
1675         uint8_t x;
1676
1677         td_alt_next = NULL;
1678         buf_offset = 0;
1679         shortpkt_old = temp->shortpkt;
1680         len_old = temp->len;
1681         npkt_off = 0;
1682         precompute = 1;
1683
1684 restart:
1685
1686         td = temp->td;
1687         td_next = td_first = temp->td_next;
1688
1689         while (1) {
1690
1691                 if (temp->len == 0) {
1692
1693                         if (temp->shortpkt)
1694                                 break;
1695
1696                         /* send a Zero Length Packet, ZLP, last */
1697
1698                         temp->shortpkt = 1;
1699                         average = 0;
1700
1701                 } else {
1702
1703                         average = temp->average;
1704
1705                         if (temp->len < average) {
1706                                 if (temp->len % temp->max_packet_size) {
1707                                         temp->shortpkt = 1;
1708                                 }
1709                                 average = temp->len;
1710                         }
1711                 }
1712
1713                 if (td_next == NULL)
1714                         panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1715
1716                 /* get next TD */
1717
1718                 td = td_next;
1719                 td_next = td->obj_next;
1720
1721                 /* check if we are pre-computing */
1722
1723                 if (precompute) {
1724
1725                         /* update remaining length */
1726
1727                         temp->len -= average;
1728
1729                         continue;
1730                 }
1731                 /* fill out current TD */
1732
1733                 td->len = average;
1734                 td->remainder = 0;
1735                 td->status = 0;
1736
1737                 /* update remaining length */
1738
1739                 temp->len -= average;
1740
1741                 /* reset TRB index */
1742
1743                 x = 0;
1744
1745                 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1746                         /* immediate data */
1747
1748                         if (average > 8)
1749                                 average = 8;
1750
1751                         td->td_trb[0].qwTrb0 = 0;
1752
1753                         usbd_copy_out(temp->pc, temp->offset + buf_offset,
1754                            (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1755                            average);
1756
1757                         dword = XHCI_TRB_2_BYTES_SET(8) |
1758                             XHCI_TRB_2_TDSZ_SET(0) |
1759                             XHCI_TRB_2_IRQ_SET(0);
1760
1761                         td->td_trb[0].dwTrb2 = htole32(dword);
1762
1763                         dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1764                           XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1765
1766                         /* check wLength */
1767                         if (td->td_trb[0].qwTrb0 &
1768                            htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1769                                 if (td->td_trb[0].qwTrb0 &
1770                                     htole64(XHCI_TRB_0_DIR_IN_MASK))
1771                                         dword |= XHCI_TRB_3_TRT_IN;
1772                                 else
1773                                         dword |= XHCI_TRB_3_TRT_OUT;
1774                         }
1775
1776                         td->td_trb[0].dwTrb3 = htole32(dword);
1777 #ifdef USB_DEBUG
1778                         xhci_dump_trb(&td->td_trb[x]);
1779 #endif
1780                         x++;
1781
1782                 } else do {
1783
1784                         uint32_t npkt;
1785
1786                         /* fill out buffer pointers */
1787
1788                         if (average == 0) {
1789                                 memset(&buf_res, 0, sizeof(buf_res));
1790                         } else {
1791                                 usbd_get_page(temp->pc, temp->offset +
1792                                     buf_offset, &buf_res);
1793
1794                                 /* get length to end of page */
1795                                 if (buf_res.length > average)
1796                                         buf_res.length = average;
1797
1798                                 /* check for maximum length */
1799                                 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1800                                         buf_res.length = XHCI_TD_PAGE_SIZE;
1801
1802                                 npkt_off += buf_res.length;
1803                         }
1804
1805                         /* setup npkt */
1806                         npkt = (len_old - npkt_off + temp->max_packet_size - 1) /
1807                             temp->max_packet_size;
1808
1809                         if (npkt == 0)
1810                                 npkt = 1;
1811                         else if (npkt > 31)
1812                                 npkt = 31;
1813
1814                         /* fill out TRB's */
1815                         td->td_trb[x].qwTrb0 =
1816                             htole64((uint64_t)buf_res.physaddr);
1817
1818                         dword =
1819                           XHCI_TRB_2_BYTES_SET(buf_res.length) |
1820                           XHCI_TRB_2_TDSZ_SET(npkt) |
1821                           XHCI_TRB_2_IRQ_SET(0);
1822
1823                         td->td_trb[x].dwTrb2 = htole32(dword);
1824
1825                         switch (temp->trb_type) {
1826                         case XHCI_TRB_TYPE_ISOCH:
1827                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1828                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1829                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1830                                 if (td != td_first) {
1831                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1832                                 } else if (temp->do_isoc_sync != 0) {
1833                                         temp->do_isoc_sync = 0;
1834                                         /* wait until "isoc_frame" */
1835                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1836                                             XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1837                                 } else {
1838                                         /* start data transfer at next interval */
1839                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1840                                             XHCI_TRB_3_ISO_SIA_BIT;
1841                                 }
1842                                 if (temp->direction == UE_DIR_IN)
1843                                         dword |= XHCI_TRB_3_ISP_BIT;
1844                                 break;
1845                         case XHCI_TRB_TYPE_DATA_STAGE:
1846                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1847                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE);
1848                                 if (temp->direction == UE_DIR_IN)
1849                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1850                                 /*
1851                                  * Section 3.2.9 in the XHCI
1852                                  * specification about control
1853                                  * transfers says that we should use a
1854                                  * normal-TRB if there are more TRBs
1855                                  * extending the data-stage
1856                                  * TRB. Update the "trb_type".
1857                                  */
1858                                 temp->trb_type = XHCI_TRB_TYPE_NORMAL;
1859                                 break;
1860                         case XHCI_TRB_TYPE_STATUS_STAGE:
1861                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1862                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE);
1863                                 if (temp->direction == UE_DIR_IN)
1864                                         dword |= XHCI_TRB_3_DIR_IN;
1865                                 break;
1866                         default:        /* XHCI_TRB_TYPE_NORMAL */
1867                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1868                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1869                                 if (temp->direction == UE_DIR_IN)
1870                                         dword |= XHCI_TRB_3_ISP_BIT;
1871                                 break;
1872                         }
1873                         td->td_trb[x].dwTrb3 = htole32(dword);
1874
1875                         average -= buf_res.length;
1876                         buf_offset += buf_res.length;
1877 #ifdef USB_DEBUG
1878                         xhci_dump_trb(&td->td_trb[x]);
1879 #endif
1880                         x++;
1881
1882                 } while (average != 0);
1883
1884                 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1885
1886                 /* store number of data TRB's */
1887
1888                 td->ntrb = x;
1889
1890                 DPRINTF("NTRB=%u\n", x);
1891
1892                 /* fill out link TRB */
1893
1894                 if (td_next != NULL) {
1895                         /* link the current TD with the next one */
1896                         td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1897                         DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1898                 } else {
1899                         /* this field will get updated later */
1900                         DPRINTF("NOLINK\n");
1901                 }
1902
1903                 dword = XHCI_TRB_2_IRQ_SET(0);
1904
1905                 td->td_trb[x].dwTrb2 = htole32(dword);
1906
1907                 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1908                     XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1909                     /*
1910                      * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1911                      * frame only receives a single short packet event
1912                      * by setting the CHAIN bit in the LINK field. In
1913                      * addition some XHCI controllers have problems
1914                      * sending a ZLP unless the CHAIN-BIT is set in
1915                      * the LINK TRB.
1916                      */
1917                     XHCI_TRB_3_CHAIN_BIT;
1918
1919                 td->td_trb[x].dwTrb3 = htole32(dword);
1920
1921                 td->alt_next = td_alt_next;
1922 #ifdef USB_DEBUG
1923                 xhci_dump_trb(&td->td_trb[x]);
1924 #endif
1925                 usb_pc_cpu_flush(td->page_cache);
1926         }
1927
1928         if (precompute) {
1929                 precompute = 0;
1930
1931                 /* setup alt next pointer, if any */
1932                 if (temp->last_frame) {
1933                         td_alt_next = NULL;
1934                 } else {
1935                         /* we use this field internally */
1936                         td_alt_next = td_next;
1937                 }
1938
1939                 /* restore */
1940                 temp->shortpkt = shortpkt_old;
1941                 temp->len = len_old;
1942                 goto restart;
1943         }
1944
1945         /*
1946          * Remove cycle bit from the first TRB if we are
1947          * stepping them:
1948          */
1949         if (temp->step_td != 0) {
1950                 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1951                 usb_pc_cpu_flush(td_first->page_cache);
1952         }
1953
1954         /* clear TD SIZE to zero, hence this is the last TRB */
1955         /* remove chain bit because this is the last data TRB in the chain */
1956         td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1957         td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1958         /* remove CHAIN-BIT from last LINK TRB */
1959         td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1960
1961         usb_pc_cpu_flush(td->page_cache);
1962
1963         temp->td = td;
1964         temp->td_next = td_next;
1965 }
1966
1967 static void
1968 xhci_setup_generic_chain(struct usb_xfer *xfer)
1969 {
1970         struct xhci_std_temp temp;
1971         struct xhci_td *td;
1972         uint32_t x;
1973         uint32_t y;
1974         uint8_t mult;
1975
1976         temp.do_isoc_sync = 0;
1977         temp.step_td = 0;
1978         temp.tbc = 0;
1979         temp.tlbpc = 0;
1980         temp.average = xfer->max_hc_frame_size;
1981         temp.max_packet_size = xfer->max_packet_size;
1982         temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
1983         temp.pc = NULL;
1984         temp.last_frame = 0;
1985         temp.offset = 0;
1986         temp.multishort = xfer->flags_int.isochronous_xfr ||
1987             xfer->flags_int.control_xfr ||
1988             xfer->flags_int.short_frames_ok;
1989
1990         /* toggle the DMA set we are using */
1991         xfer->flags_int.curr_dma_set ^= 1;
1992
1993         /* get next DMA set */
1994         td = xfer->td_start[xfer->flags_int.curr_dma_set];
1995
1996         temp.td = NULL;
1997         temp.td_next = td;
1998
1999         xfer->td_transfer_first = td;
2000         xfer->td_transfer_cache = td;
2001
2002         if (xfer->flags_int.isochronous_xfr) {
2003                 uint8_t shift;
2004
2005                 /* compute multiplier for ISOCHRONOUS transfers */
2006                 mult = xfer->endpoint->ecomp ?
2007                     (xfer->endpoint->ecomp->bmAttributes & 3) : 0;
2008                 /* check for USB 2.0 multiplier */
2009                 if (mult == 0) {
2010                         mult = (xfer->endpoint->edesc->
2011                             wMaxPacketSize[1] >> 3) & 3;
2012                 }
2013                 /* range check */
2014                 if (mult > 2)
2015                         mult = 3;
2016                 else
2017                         mult++;
2018
2019                 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
2020
2021                 DPRINTF("MFINDEX=0x%08x\n", x);
2022
2023                 switch (usbd_get_speed(xfer->xroot->udev)) {
2024                 case USB_SPEED_FULL:
2025                         shift = 3;
2026                         temp.isoc_delta = 8;    /* 1ms */
2027                         x += temp.isoc_delta - 1;
2028                         x &= ~(temp.isoc_delta - 1);
2029                         break;
2030                 default:
2031                         shift = usbd_xfer_get_fps_shift(xfer);
2032                         temp.isoc_delta = 1U << shift;
2033                         x += temp.isoc_delta - 1;
2034                         x &= ~(temp.isoc_delta - 1);
2035                         /* simple frame load balancing */
2036                         x += xfer->endpoint->usb_uframe;
2037                         break;
2038                 }
2039
2040                 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
2041
2042                 if ((xfer->endpoint->is_synced == 0) ||
2043                     (y < (xfer->nframes << shift)) ||
2044                     (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
2045                         /*
2046                          * If there is data underflow or the pipe
2047                          * queue is empty we schedule the transfer a
2048                          * few frames ahead of the current frame
2049                          * position. Else two isochronous transfers
2050                          * might overlap.
2051                          */
2052                         xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2053                         xfer->endpoint->is_synced = 1;
2054                         temp.do_isoc_sync = 1;
2055
2056                         DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2057                 }
2058
2059                 /* compute isochronous completion time */
2060
2061                 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2062
2063                 xfer->isoc_time_complete =
2064                     usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2065                     (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2066
2067                 x = 0;
2068                 temp.isoc_frame = xfer->endpoint->isoc_next;
2069                 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2070
2071                 xfer->endpoint->isoc_next += xfer->nframes << shift;
2072
2073         } else if (xfer->flags_int.control_xfr) {
2074
2075                 /* check if we should prepend a setup message */
2076
2077                 if (xfer->flags_int.control_hdr) {
2078
2079                         temp.len = xfer->frlengths[0];
2080                         temp.pc = xfer->frbuffers + 0;
2081                         temp.shortpkt = temp.len ? 1 : 0;
2082                         temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2083                         temp.direction = 0;
2084
2085                         /* check for last frame */
2086                         if (xfer->nframes == 1) {
2087                                 /* no STATUS stage yet, SETUP is last */
2088                                 if (xfer->flags_int.control_act)
2089                                         temp.last_frame = 1;
2090                         }
2091
2092                         xhci_setup_generic_chain_sub(&temp);
2093                 }
2094                 x = 1;
2095                 mult = 1;
2096                 temp.isoc_delta = 0;
2097                 temp.isoc_frame = 0;
2098                 temp.trb_type = xfer->flags_int.control_did_data ?
2099                     XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE;
2100         } else {
2101                 x = 0;
2102                 mult = 1;
2103                 temp.isoc_delta = 0;
2104                 temp.isoc_frame = 0;
2105                 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2106         }
2107
2108         if (x != xfer->nframes) {
2109                 /* setup page_cache pointer */
2110                 temp.pc = xfer->frbuffers + x;
2111                 /* set endpoint direction */
2112                 temp.direction = UE_GET_DIR(xfer->endpointno);
2113         }
2114
2115         while (x != xfer->nframes) {
2116
2117                 /* DATA0 / DATA1 message */
2118
2119                 temp.len = xfer->frlengths[x];
2120                 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2121                     x != 0 && temp.multishort == 0);
2122
2123                 x++;
2124
2125                 if (x == xfer->nframes) {
2126                         if (xfer->flags_int.control_xfr) {
2127                                 /* no STATUS stage yet, DATA is last */
2128                                 if (xfer->flags_int.control_act)
2129                                         temp.last_frame = 1;
2130                         } else {
2131                                 temp.last_frame = 1;
2132                         }
2133                 }
2134                 if (temp.len == 0) {
2135
2136                         /* make sure that we send an USB packet */
2137
2138                         temp.shortpkt = 0;
2139
2140                         temp.tbc = 0;
2141                         temp.tlbpc = mult - 1;
2142
2143                 } else if (xfer->flags_int.isochronous_xfr) {
2144
2145                         uint8_t tdpc;
2146
2147                         /*
2148                          * Isochronous transfers don't have short
2149                          * packet termination:
2150                          */
2151
2152                         temp.shortpkt = 1;
2153
2154                         /* isochronous transfers have a transfer limit */
2155
2156                         if (temp.len > xfer->max_frame_size)
2157                                 temp.len = xfer->max_frame_size;
2158
2159                         /* compute TD packet count */
2160                         tdpc = (temp.len + xfer->max_packet_size - 1) /
2161                             xfer->max_packet_size;
2162
2163                         temp.tbc = ((tdpc + mult - 1) / mult) - 1;
2164                         temp.tlbpc = (tdpc % mult);
2165
2166                         if (temp.tlbpc == 0)
2167                                 temp.tlbpc = mult - 1;
2168                         else
2169                                 temp.tlbpc--;
2170                 } else {
2171
2172                         /* regular data transfer */
2173
2174                         temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2175                 }
2176
2177                 xhci_setup_generic_chain_sub(&temp);
2178
2179                 if (xfer->flags_int.isochronous_xfr) {
2180                         temp.offset += xfer->frlengths[x - 1];
2181                         temp.isoc_frame += temp.isoc_delta;
2182                 } else {
2183                         /* get next Page Cache pointer */
2184                         temp.pc = xfer->frbuffers + x;
2185                 }
2186         }
2187
2188         /* check if we should append a status stage */
2189
2190         if (xfer->flags_int.control_xfr &&
2191             !xfer->flags_int.control_act) {
2192
2193                 /*
2194                  * Send a DATA1 message and invert the current
2195                  * endpoint direction.
2196                  */
2197                 temp.step_td = (xfer->nframes != 0);
2198                 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2199                 temp.len = 0;
2200                 temp.pc = NULL;
2201                 temp.shortpkt = 0;
2202                 temp.last_frame = 1;
2203                 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2204
2205                 xhci_setup_generic_chain_sub(&temp);
2206         }
2207
2208         td = temp.td;
2209
2210         /* must have at least one frame! */
2211
2212         xfer->td_transfer_last = td;
2213
2214         DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2215 }
2216
2217 static void
2218 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2219 {
2220         struct usb_page_search buf_res;
2221         struct xhci_dev_ctx_addr *pdctxa;
2222
2223         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2224
2225         pdctxa = buf_res.buffer;
2226
2227         DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2228
2229         pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2230
2231         usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2232 }
2233
2234 static usb_error_t
2235 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2236 {
2237         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2238         struct usb_page_search buf_inp;
2239         struct xhci_input_dev_ctx *pinp;
2240         uint32_t temp;
2241         uint8_t index;
2242         uint8_t x;
2243
2244         index = udev->controller_slot_id;
2245
2246         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2247
2248         pinp = buf_inp.buffer;
2249
2250         if (drop) {
2251                 mask &= XHCI_INCTX_NON_CTRL_MASK;
2252                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2253                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2254         } else {
2255                 /*
2256                  * Some hardware requires that we drop the endpoint
2257                  * context before adding it again:
2258                  */
2259                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0,
2260                     mask & XHCI_INCTX_NON_CTRL_MASK);
2261
2262                 /* Add new endpoint context */
2263                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2264
2265                 /* find most significant set bit */
2266                 for (x = 31; x != 1; x--) {
2267                         if (mask & (1 << x))
2268                                 break;
2269                 }
2270
2271                 /* adjust */
2272                 x--;
2273
2274                 /* figure out the maximum number of contexts */
2275                 if (x > sc->sc_hw.devs[index].context_num)
2276                         sc->sc_hw.devs[index].context_num = x;
2277                 else
2278                         x = sc->sc_hw.devs[index].context_num;
2279
2280                 /* update number of contexts */
2281                 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2282                 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2283                 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2284                 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2285         }
2286         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2287         return (0);
2288 }
2289
2290 static usb_error_t
2291 xhci_configure_endpoint(struct usb_device *udev,
2292     struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext,
2293     uint16_t interval, uint8_t max_packet_count,
2294     uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size,
2295     uint16_t max_frame_size)
2296 {
2297         struct usb_page_search buf_inp;
2298         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2299         struct xhci_input_dev_ctx *pinp;
2300         uint64_t ring_addr = pepext->physaddr;
2301         uint32_t temp;
2302         uint8_t index;
2303         uint8_t epno;
2304         uint8_t type;
2305
2306         index = udev->controller_slot_id;
2307
2308         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2309
2310         pinp = buf_inp.buffer;
2311
2312         epno = edesc->bEndpointAddress;
2313         type = edesc->bmAttributes & UE_XFERTYPE;
2314
2315         if (type == UE_CONTROL)
2316                 epno |= UE_DIR_IN;
2317
2318         epno = XHCI_EPNO2EPID(epno);
2319
2320         if (epno == 0)
2321                 return (USB_ERR_NO_PIPE);               /* invalid */
2322
2323         if (max_packet_count == 0)
2324                 return (USB_ERR_BAD_BUFSIZE);
2325
2326         max_packet_count--;
2327
2328         if (mult == 0)
2329                 return (USB_ERR_BAD_BUFSIZE);
2330
2331         /* store bMaxPacketSize for control endpoints */
2332         pepext->trb_ep_maxp = edesc->wMaxPacketSize[0];
2333         usb_pc_cpu_flush(pepext->page_cache);
2334
2335         temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2336             XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2337             XHCI_EPCTX_0_LSA_SET(0);
2338
2339         switch (udev->speed) {
2340         case USB_SPEED_FULL:
2341         case USB_SPEED_LOW:
2342                 /* 1ms -> 125us */
2343                 fps_shift += 3;
2344                 break;
2345         default:
2346                 break;
2347         }
2348
2349         switch (type) {
2350         case UE_INTERRUPT:
2351                 if (fps_shift > 3)
2352                         fps_shift--;
2353                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2354                 break;
2355         case UE_ISOCHRONOUS:
2356                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2357
2358                 switch (udev->speed) {
2359                 case USB_SPEED_SUPER:
2360                         if (mult > 3)
2361                                 mult = 3;
2362                         temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2363                         max_packet_count /= mult;
2364                         break;
2365                 default:
2366                         break;
2367                 }
2368                 break;
2369         default:
2370                 break;
2371         }
2372
2373         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2374
2375         temp =
2376             XHCI_EPCTX_1_HID_SET(0) |
2377             XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2378             XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2379
2380         /*
2381          * Always enable the "three strikes and you are gone" feature
2382          * except for ISOCHRONOUS endpoints. This is suggested by
2383          * section 4.3.3 in the XHCI specification about device slot
2384          * initialisation.
2385          */
2386         if (type != UE_ISOCHRONOUS)
2387                 temp |= XHCI_EPCTX_1_CERR_SET(3);
2388
2389         switch (type) {
2390         case UE_CONTROL:
2391                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2392                 break;
2393         case UE_ISOCHRONOUS:
2394                 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2395                 break;
2396         case UE_BULK:
2397                 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2398                 break;
2399         default:
2400                 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2401                 break;
2402         }
2403
2404         /* check for IN direction */
2405         if (epno & 1)
2406                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2407
2408         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2409
2410         ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2411
2412         xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2413
2414         switch (edesc->bmAttributes & UE_XFERTYPE) {
2415         case UE_INTERRUPT:
2416         case UE_ISOCHRONOUS:
2417                 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2418                     XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2419                     max_frame_size));
2420                 break;
2421         case UE_CONTROL:
2422                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2423                 break;
2424         default:
2425                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2426                 break;
2427         }
2428
2429         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2430
2431 #ifdef USB_DEBUG
2432         xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2433 #endif
2434         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2435
2436         return (0);             /* success */
2437 }
2438
2439 static usb_error_t
2440 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2441 {
2442         struct xhci_endpoint_ext *pepext;
2443         struct usb_endpoint_ss_comp_descriptor *ecomp;
2444
2445         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2446             xfer->endpoint->edesc);
2447
2448         ecomp = xfer->endpoint->ecomp;
2449
2450         pepext->trb[0].dwTrb3 = 0;      /* halt any transfers */
2451         usb_pc_cpu_flush(pepext->page_cache);
2452
2453         return (xhci_configure_endpoint(xfer->xroot->udev,
2454             xfer->endpoint->edesc, pepext,
2455             xfer->interval, xfer->max_packet_count,
2456             (ecomp != NULL) ? (ecomp->bmAttributes & 3) + 1 : 1,
2457             usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2458             xfer->max_frame_size));
2459 }
2460
2461 static usb_error_t
2462 xhci_configure_device(struct usb_device *udev)
2463 {
2464         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2465         struct usb_page_search buf_inp;
2466         struct usb_page_cache *pcinp;
2467         struct xhci_input_dev_ctx *pinp;
2468         struct usb_device *hubdev;
2469         uint32_t temp;
2470         uint32_t route;
2471         uint32_t rh_port;
2472         uint8_t is_hub;
2473         uint8_t index;
2474         uint8_t depth;
2475
2476         index = udev->controller_slot_id;
2477
2478         DPRINTF("index=%u\n", index);
2479
2480         pcinp = &sc->sc_hw.devs[index].input_pc;
2481
2482         usbd_get_page(pcinp, 0, &buf_inp);
2483
2484         pinp = buf_inp.buffer;
2485
2486         rh_port = 0;
2487         route = 0;
2488
2489         /* figure out route string and root HUB port number */
2490
2491         for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2492
2493                 if (hubdev->parent_hub == NULL)
2494                         break;
2495
2496                 depth = hubdev->parent_hub->depth;
2497
2498                 /*
2499                  * NOTE: HS/FS/LS devices and the SS root HUB can have
2500                  * more than 15 ports
2501                  */
2502
2503                 rh_port = hubdev->port_no;
2504
2505                 if (depth == 0)
2506                         break;
2507
2508                 if (rh_port > 15)
2509                         rh_port = 15;
2510
2511                 if (depth < 6)
2512                         route |= rh_port << (4 * (depth - 1));
2513         }
2514
2515         DPRINTF("Route=0x%08x\n", route);
2516
2517         temp = XHCI_SCTX_0_ROUTE_SET(route) |
2518             XHCI_SCTX_0_CTX_NUM_SET(
2519             sc->sc_hw.devs[index].context_num + 1);
2520
2521         switch (udev->speed) {
2522         case USB_SPEED_LOW:
2523                 temp |= XHCI_SCTX_0_SPEED_SET(2);
2524                 if (udev->parent_hs_hub != NULL &&
2525                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2526                     UDPROTO_HSHUBMTT) {
2527                         DPRINTF("Device inherits MTT\n");
2528                         temp |= XHCI_SCTX_0_MTT_SET(1);
2529                 }
2530                 break;
2531         case USB_SPEED_HIGH:
2532                 temp |= XHCI_SCTX_0_SPEED_SET(3);
2533                 if (sc->sc_hw.devs[index].nports != 0 &&
2534                     udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2535                         DPRINTF("HUB supports MTT\n");
2536                         temp |= XHCI_SCTX_0_MTT_SET(1);
2537                 }
2538                 break;
2539         case USB_SPEED_FULL:
2540                 temp |= XHCI_SCTX_0_SPEED_SET(1);
2541                 if (udev->parent_hs_hub != NULL &&
2542                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2543                     UDPROTO_HSHUBMTT) {
2544                         DPRINTF("Device inherits MTT\n");
2545                         temp |= XHCI_SCTX_0_MTT_SET(1);
2546                 }
2547                 break;
2548         default:
2549                 temp |= XHCI_SCTX_0_SPEED_SET(4);
2550                 break;
2551         }
2552
2553         is_hub = sc->sc_hw.devs[index].nports != 0 &&
2554             (udev->speed == USB_SPEED_SUPER ||
2555             udev->speed == USB_SPEED_HIGH);
2556
2557         if (is_hub)
2558                 temp |= XHCI_SCTX_0_HUB_SET(1);
2559
2560         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2561
2562         temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2563
2564         if (is_hub) {
2565                 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2566                     sc->sc_hw.devs[index].nports);
2567         }
2568
2569         switch (udev->speed) {
2570         case USB_SPEED_SUPER:
2571                 switch (sc->sc_hw.devs[index].state) {
2572                 case XHCI_ST_ADDRESSED:
2573                 case XHCI_ST_CONFIGURED:
2574                         /* enable power save */
2575                         temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2576                         break;
2577                 default:
2578                         /* disable power save */
2579                         break;
2580                 }
2581                 break;
2582         default:
2583                 break;
2584         }
2585
2586         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2587
2588         temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2589
2590         if (is_hub) {
2591                 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2592                     sc->sc_hw.devs[index].tt);
2593         }
2594
2595         hubdev = udev->parent_hs_hub;
2596
2597         /* check if we should activate the transaction translator */
2598         switch (udev->speed) {
2599         case USB_SPEED_FULL:
2600         case USB_SPEED_LOW:
2601                 if (hubdev != NULL) {
2602                         temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2603                             hubdev->controller_slot_id);
2604                         temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2605                             udev->hs_port_no);
2606                 }
2607                 break;
2608         default:
2609                 break;
2610         }
2611
2612         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2613
2614         /*
2615          * These fields should be initialized to zero, according to
2616          * XHCI section 6.2.2 - slot context:
2617          */
2618         temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2619             XHCI_SCTX_3_SLOT_STATE_SET(0);
2620
2621         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2622
2623 #ifdef USB_DEBUG
2624         xhci_dump_device(sc, &pinp->ctx_slot);
2625 #endif
2626         usb_pc_cpu_flush(pcinp);
2627
2628         return (0);             /* success */
2629 }
2630
2631 static usb_error_t
2632 xhci_alloc_device_ext(struct usb_device *udev)
2633 {
2634         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2635         struct usb_page_search buf_dev;
2636         struct usb_page_search buf_ep;
2637         struct xhci_trb *trb;
2638         struct usb_page_cache *pc;
2639         struct usb_page *pg;
2640         uint64_t addr;
2641         uint8_t index;
2642         uint8_t i;
2643
2644         index = udev->controller_slot_id;
2645
2646         pc = &sc->sc_hw.devs[index].device_pc;
2647         pg = &sc->sc_hw.devs[index].device_pg;
2648
2649         /* need to initialize the page cache */
2650         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2651
2652         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2653             (2 * sizeof(struct xhci_dev_ctx)) :
2654             sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2655                 goto error;
2656
2657         usbd_get_page(pc, 0, &buf_dev);
2658
2659         pc = &sc->sc_hw.devs[index].input_pc;
2660         pg = &sc->sc_hw.devs[index].input_pg;
2661
2662         /* need to initialize the page cache */
2663         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2664
2665         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2666             (2 * sizeof(struct xhci_input_dev_ctx)) :
2667             sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2668                 goto error;
2669         }
2670
2671         pc = &sc->sc_hw.devs[index].endpoint_pc;
2672         pg = &sc->sc_hw.devs[index].endpoint_pg;
2673
2674         /* need to initialize the page cache */
2675         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2676
2677         if (usb_pc_alloc_mem(pc, pg,
2678             sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) {
2679                 goto error;
2680         }
2681
2682         /* initialise all endpoint LINK TRBs */
2683
2684         for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2685
2686                 /* lookup endpoint TRB ring */
2687                 usbd_get_page(pc, (uintptr_t)&
2688                     ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep);
2689
2690                 /* get TRB pointer */
2691                 trb = buf_ep.buffer;
2692                 trb += XHCI_MAX_TRANSFERS - 1;
2693
2694                 /* get TRB start address */
2695                 addr = buf_ep.physaddr;
2696
2697                 /* create LINK TRB */
2698                 trb->qwTrb0 = htole64(addr);
2699                 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2700                 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2701                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2702         }
2703
2704         usb_pc_cpu_flush(pc);
2705
2706         xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2707
2708         return (0);
2709
2710 error:
2711         xhci_free_device_ext(udev);
2712
2713         return (USB_ERR_NOMEM);
2714 }
2715
2716 static void
2717 xhci_free_device_ext(struct usb_device *udev)
2718 {
2719         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2720         uint8_t index;
2721
2722         index = udev->controller_slot_id;
2723         xhci_set_slot_pointer(sc, index, 0);
2724
2725         usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2726         usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2727         usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc);
2728 }
2729
2730 static struct xhci_endpoint_ext *
2731 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2732 {
2733         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2734         struct xhci_endpoint_ext *pepext;
2735         struct usb_page_cache *pc;
2736         struct usb_page_search buf_ep;
2737         uint8_t epno;
2738         uint8_t index;
2739
2740         epno = edesc->bEndpointAddress;
2741         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2742                 epno |= UE_DIR_IN;
2743
2744         epno = XHCI_EPNO2EPID(epno);
2745
2746         index = udev->controller_slot_id;
2747
2748         pc = &sc->sc_hw.devs[index].endpoint_pc;
2749
2750         usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->trb[epno][0], &buf_ep);
2751
2752         pepext = &sc->sc_hw.devs[index].endp[epno];
2753         pepext->page_cache = pc;
2754         pepext->trb = buf_ep.buffer;
2755         pepext->physaddr = buf_ep.physaddr;
2756
2757         return (pepext);
2758 }
2759
2760 static void
2761 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2762 {
2763         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2764         uint8_t epno;
2765         uint8_t index;
2766
2767         epno = xfer->endpointno;
2768         if (xfer->flags_int.control_xfr)
2769                 epno |= UE_DIR_IN;
2770
2771         epno = XHCI_EPNO2EPID(epno);
2772         index = xfer->xroot->udev->controller_slot_id;
2773
2774         if (xfer->xroot->udev->flags.self_suspended == 0) {
2775                 XWRITE4(sc, door, XHCI_DOORBELL(index),
2776                     epno | XHCI_DB_SID_SET(/*xfer->stream_id*/ 0));
2777         }
2778 }
2779
2780 static void
2781 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2782 {
2783         struct xhci_endpoint_ext *pepext;
2784
2785         if (xfer->flags_int.bandwidth_reclaimed) {
2786                 xfer->flags_int.bandwidth_reclaimed = 0;
2787
2788                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2789                     xfer->endpoint->edesc);
2790
2791                 pepext->trb_used--;
2792
2793                 pepext->xfer[xfer->qh_pos] = NULL;
2794
2795                 if (error && pepext->trb_running != 0) {
2796                         pepext->trb_halted = 1;
2797                         pepext->trb_running = 0;
2798                 }
2799         }
2800 }
2801
2802 static usb_error_t
2803 xhci_transfer_insert(struct usb_xfer *xfer)
2804 {
2805         struct xhci_td *td_first;
2806         struct xhci_td *td_last;
2807         struct xhci_trb *trb_link;
2808         struct xhci_endpoint_ext *pepext;
2809         uint64_t addr;
2810         uint8_t i;
2811         uint8_t inext;
2812         uint8_t trb_limit;
2813
2814         DPRINTFN(8, "\n");
2815
2816         /* check if already inserted */
2817         if (xfer->flags_int.bandwidth_reclaimed) {
2818                 DPRINTFN(8, "Already in schedule\n");
2819                 return (0);
2820         }
2821
2822         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2823             xfer->endpoint->edesc);
2824
2825         td_first = xfer->td_transfer_first;
2826         td_last = xfer->td_transfer_last;
2827         addr = pepext->physaddr;
2828
2829         switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2830         case UE_CONTROL:
2831         case UE_INTERRUPT:
2832                 /* single buffered */
2833                 trb_limit = 1;
2834                 break;
2835         default:
2836                 /* multi buffered */
2837                 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2838                 break;
2839         }
2840
2841         if (pepext->trb_used >= trb_limit) {
2842                 DPRINTFN(8, "Too many TDs queued.\n");
2843                 return (USB_ERR_NOMEM);
2844         }
2845
2846         /* check if bMaxPacketSize changed */
2847         if (xfer->flags_int.control_xfr != 0 &&
2848             pepext->trb_ep_maxp != xfer->endpoint->edesc->wMaxPacketSize[0]) {
2849
2850                 DPRINTFN(8, "Reconfigure control endpoint\n");
2851
2852                 /* force driver to reconfigure endpoint */
2853                 pepext->trb_halted = 1;
2854                 pepext->trb_running = 0;
2855         }
2856
2857         /* check for stopped condition, after putting transfer on interrupt queue */
2858         if (pepext->trb_running == 0) {
2859                 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2860
2861                 DPRINTFN(8, "Not running\n");
2862
2863                 /* start configuration */
2864                 (void)usb_proc_msignal(&sc->sc_config_proc,
2865                     &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2866                 return (0);
2867         }
2868
2869         pepext->trb_used++;
2870
2871         /* get current TRB index */
2872         i = pepext->trb_index;
2873
2874         /* get next TRB index */
2875         inext = (i + 1);
2876
2877         /* the last entry of the ring is a hardcoded link TRB */
2878         if (inext >= (XHCI_MAX_TRANSFERS - 1))
2879                 inext = 0;
2880
2881         /* compute terminating return address */
2882         addr += inext * sizeof(struct xhci_trb);
2883
2884         /* compute link TRB pointer */
2885         trb_link = td_last->td_trb + td_last->ntrb;
2886
2887         /* update next pointer of last link TRB */
2888         trb_link->qwTrb0 = htole64(addr);
2889         trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2890         trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2891             XHCI_TRB_3_CYCLE_BIT |
2892             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2893
2894 #ifdef USB_DEBUG
2895         xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2896 #endif
2897         usb_pc_cpu_flush(td_last->page_cache);
2898
2899         /* write ahead chain end marker */
2900
2901         pepext->trb[inext].qwTrb0 = 0;
2902         pepext->trb[inext].dwTrb2 = 0;
2903         pepext->trb[inext].dwTrb3 = 0;
2904
2905         /* update next pointer of link TRB */
2906
2907         pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2908         pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2909
2910 #ifdef USB_DEBUG
2911         xhci_dump_trb(&pepext->trb[i]);
2912 #endif
2913         usb_pc_cpu_flush(pepext->page_cache);
2914
2915         /* toggle cycle bit which activates the transfer chain */
2916
2917         pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2918             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2919
2920         usb_pc_cpu_flush(pepext->page_cache);
2921
2922         DPRINTF("qh_pos = %u\n", i);
2923
2924         pepext->xfer[i] = xfer;
2925
2926         xfer->qh_pos = i;
2927
2928         xfer->flags_int.bandwidth_reclaimed = 1;
2929
2930         pepext->trb_index = inext;
2931
2932         xhci_endpoint_doorbell(xfer);
2933
2934         return (0);
2935 }
2936
2937 static void
2938 xhci_root_intr(struct xhci_softc *sc)
2939 {
2940         uint16_t i;
2941
2942         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2943
2944         /* clear any old interrupt data */
2945         memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2946
2947         for (i = 1; i <= sc->sc_noport; i++) {
2948                 /* pick out CHANGE bits from the status register */
2949                 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
2950                     XHCI_PS_CSC | XHCI_PS_PEC |
2951                     XHCI_PS_OCC | XHCI_PS_WRC |
2952                     XHCI_PS_PRC | XHCI_PS_PLC |
2953                     XHCI_PS_CEC)) {
2954                         sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2955                         DPRINTF("port %d changed\n", i);
2956                 }
2957         }
2958         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2959             sizeof(sc->sc_hub_idata));
2960 }
2961
2962 /*------------------------------------------------------------------------*
2963  *      xhci_device_done - XHCI done handler
2964  *
2965  * NOTE: This function can be called two times in a row on
2966  * the same USB transfer. From close and from interrupt.
2967  *------------------------------------------------------------------------*/
2968 static void
2969 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
2970 {
2971         DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2972             xfer, xfer->endpoint, error);
2973
2974         /* remove transfer from HW queue */
2975         xhci_transfer_remove(xfer, error);
2976
2977         /* dequeue transfer and start next transfer */
2978         usbd_transfer_done(xfer, error);
2979 }
2980
2981 /*------------------------------------------------------------------------*
2982  * XHCI data transfer support (generic type)
2983  *------------------------------------------------------------------------*/
2984 static void
2985 xhci_device_generic_open(struct usb_xfer *xfer)
2986 {
2987         if (xfer->flags_int.isochronous_xfr) {
2988                 switch (xfer->xroot->udev->speed) {
2989                 case USB_SPEED_FULL:
2990                         break;
2991                 default:
2992                         usb_hs_bandwidth_alloc(xfer);
2993                         break;
2994                 }
2995         }
2996 }
2997
2998 static void
2999 xhci_device_generic_close(struct usb_xfer *xfer)
3000 {
3001         DPRINTF("\n");
3002
3003         xhci_device_done(xfer, USB_ERR_CANCELLED);
3004
3005         if (xfer->flags_int.isochronous_xfr) {
3006                 switch (xfer->xroot->udev->speed) {
3007                 case USB_SPEED_FULL:
3008                         break;
3009                 default:
3010                         usb_hs_bandwidth_free(xfer);
3011                         break;
3012                 }
3013         }
3014 }
3015
3016 static void
3017 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
3018     struct usb_xfer *enter_xfer)
3019 {
3020         struct usb_xfer *xfer;
3021
3022         /* check if there is a current transfer */
3023         xfer = ep->endpoint_q.curr;
3024         if (xfer == NULL)
3025                 return;
3026
3027         /*
3028          * Check if the current transfer is started and then pickup
3029          * the next one, if any. Else wait for next start event due to
3030          * block on failure feature.
3031          */
3032         if (!xfer->flags_int.bandwidth_reclaimed)
3033                 return;
3034
3035         xfer = TAILQ_FIRST(&ep->endpoint_q.head);
3036         if (xfer == NULL) {
3037                 /*
3038                  * In case of enter we have to consider that the
3039                  * transfer is queued by the USB core after the enter
3040                  * method is called.
3041                  */
3042                 xfer = enter_xfer;
3043
3044                 if (xfer == NULL)
3045                         return;
3046         }
3047
3048         /* try to multi buffer */
3049         xhci_transfer_insert(xfer);
3050 }
3051
3052 static void
3053 xhci_device_generic_enter(struct usb_xfer *xfer)
3054 {
3055         DPRINTF("\n");
3056
3057         /* setup TD's and QH */
3058         xhci_setup_generic_chain(xfer);
3059
3060         xhci_device_generic_multi_enter(xfer->endpoint, xfer);
3061 }
3062
3063 static void
3064 xhci_device_generic_start(struct usb_xfer *xfer)
3065 {
3066         DPRINTF("\n");
3067
3068         /* try to insert xfer on HW queue */
3069         xhci_transfer_insert(xfer);
3070
3071         /* try to multi buffer */
3072         xhci_device_generic_multi_enter(xfer->endpoint, NULL);
3073
3074         /* add transfer last on interrupt queue */
3075         usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3076
3077         /* start timeout, if any */
3078         if (xfer->timeout != 0)
3079                 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3080 }
3081
3082 struct usb_pipe_methods xhci_device_generic_methods =
3083 {
3084         .open = xhci_device_generic_open,
3085         .close = xhci_device_generic_close,
3086         .enter = xhci_device_generic_enter,
3087         .start = xhci_device_generic_start,
3088 };
3089
3090 /*------------------------------------------------------------------------*
3091  * xhci root HUB support
3092  *------------------------------------------------------------------------*
3093  * Simulate a hardware HUB by handling all the necessary requests.
3094  *------------------------------------------------------------------------*/
3095
3096 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3097
3098 static const
3099 struct usb_device_descriptor xhci_devd =
3100 {
3101         .bLength = sizeof(xhci_devd),
3102         .bDescriptorType = UDESC_DEVICE,        /* type */
3103         HSETW(.bcdUSB, 0x0300),                 /* USB version */
3104         .bDeviceClass = UDCLASS_HUB,            /* class */
3105         .bDeviceSubClass = UDSUBCLASS_HUB,      /* subclass */
3106         .bDeviceProtocol = UDPROTO_SSHUB,       /* protocol */
3107         .bMaxPacketSize = 9,                    /* max packet size */
3108         HSETW(.idVendor, 0x0000),               /* vendor */
3109         HSETW(.idProduct, 0x0000),              /* product */
3110         HSETW(.bcdDevice, 0x0100),              /* device version */
3111         .iManufacturer = 1,
3112         .iProduct = 2,
3113         .iSerialNumber = 0,
3114         .bNumConfigurations = 1,                /* # of configurations */
3115 };
3116
3117 static const
3118 struct xhci_bos_desc xhci_bosd = {
3119         .bosd = {
3120                 .bLength = sizeof(xhci_bosd.bosd),
3121                 .bDescriptorType = UDESC_BOS,
3122                 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3123                 .bNumDeviceCaps = 3,
3124         },
3125         .usb2extd = {
3126                 .bLength = sizeof(xhci_bosd.usb2extd),
3127                 .bDescriptorType = 1,
3128                 .bDevCapabilityType = 2,
3129                 .bmAttributes[0] = 2,
3130         },
3131         .usbdcd = {
3132                 .bLength = sizeof(xhci_bosd.usbdcd),
3133                 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3134                 .bDevCapabilityType = 3,
3135                 .bmAttributes = 0, /* XXX */
3136                 HSETW(.wSpeedsSupported, 0x000C),
3137                 .bFunctionalitySupport = 8,
3138                 .bU1DevExitLat = 255,   /* dummy - not used */
3139                 .wU2DevExitLat = { 0x00, 0x08 },
3140         },
3141         .cidd = {
3142                 .bLength = sizeof(xhci_bosd.cidd),
3143                 .bDescriptorType = 1,
3144                 .bDevCapabilityType = 4,
3145                 .bReserved = 0,
3146                 .bContainerID = 0, /* XXX */
3147         },
3148 };
3149
3150 static const
3151 struct xhci_config_desc xhci_confd = {
3152         .confd = {
3153                 .bLength = sizeof(xhci_confd.confd),
3154                 .bDescriptorType = UDESC_CONFIG,
3155                 .wTotalLength[0] = sizeof(xhci_confd),
3156                 .bNumInterface = 1,
3157                 .bConfigurationValue = 1,
3158                 .iConfiguration = 0,
3159                 .bmAttributes = UC_SELF_POWERED,
3160                 .bMaxPower = 0          /* max power */
3161         },
3162         .ifcd = {
3163                 .bLength = sizeof(xhci_confd.ifcd),
3164                 .bDescriptorType = UDESC_INTERFACE,
3165                 .bNumEndpoints = 1,
3166                 .bInterfaceClass = UICLASS_HUB,
3167                 .bInterfaceSubClass = UISUBCLASS_HUB,
3168                 .bInterfaceProtocol = 0,
3169         },
3170         .endpd = {
3171                 .bLength = sizeof(xhci_confd.endpd),
3172                 .bDescriptorType = UDESC_ENDPOINT,
3173                 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3174                 .bmAttributes = UE_INTERRUPT,
3175                 .wMaxPacketSize[0] = 2,         /* max 15 ports */
3176                 .bInterval = 255,
3177         },
3178         .endpcd = {
3179                 .bLength = sizeof(xhci_confd.endpcd),
3180                 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3181                 .bMaxBurst = 0,
3182                 .bmAttributes = 0,
3183         },
3184 };
3185
3186 static const
3187 struct usb_hub_ss_descriptor xhci_hubd = {
3188         .bLength = sizeof(xhci_hubd),
3189         .bDescriptorType = UDESC_SS_HUB,
3190 };
3191
3192 static usb_error_t
3193 xhci_roothub_exec(struct usb_device *udev,
3194     struct usb_device_request *req, const void **pptr, uint16_t *plength)
3195 {
3196         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3197         const char *str_ptr;
3198         const void *ptr;
3199         uint32_t port;
3200         uint32_t v;
3201         uint16_t len;
3202         uint16_t i;
3203         uint16_t value;
3204         uint16_t index;
3205         uint8_t j;
3206         usb_error_t err;
3207
3208         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3209
3210         /* buffer reset */
3211         ptr = (const void *)&sc->sc_hub_desc;
3212         len = 0;
3213         err = 0;
3214
3215         value = UGETW(req->wValue);
3216         index = UGETW(req->wIndex);
3217
3218         DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3219             "wValue=0x%04x wIndex=0x%04x\n",
3220             req->bmRequestType, req->bRequest,
3221             UGETW(req->wLength), value, index);
3222
3223 #define C(x,y) ((x) | ((y) << 8))
3224         switch (C(req->bRequest, req->bmRequestType)) {
3225         case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3226         case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3227         case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3228                 /*
3229                  * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3230                  * for the integrated root hub.
3231                  */
3232                 break;
3233         case C(UR_GET_CONFIG, UT_READ_DEVICE):
3234                 len = 1;
3235                 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3236                 break;
3237         case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3238                 switch (value >> 8) {
3239                 case UDESC_DEVICE:
3240                         if ((value & 0xff) != 0) {
3241                                 err = USB_ERR_IOERROR;
3242                                 goto done;
3243                         }
3244                         len = sizeof(xhci_devd);
3245                         ptr = (const void *)&xhci_devd;
3246                         break;
3247
3248                 case UDESC_BOS:
3249                         if ((value & 0xff) != 0) {
3250                                 err = USB_ERR_IOERROR;
3251                                 goto done;
3252                         }
3253                         len = sizeof(xhci_bosd);
3254                         ptr = (const void *)&xhci_bosd;
3255                         break;
3256
3257                 case UDESC_CONFIG:
3258                         if ((value & 0xff) != 0) {
3259                                 err = USB_ERR_IOERROR;
3260                                 goto done;
3261                         }
3262                         len = sizeof(xhci_confd);
3263                         ptr = (const void *)&xhci_confd;
3264                         break;
3265
3266                 case UDESC_STRING:
3267                         switch (value & 0xff) {
3268                         case 0: /* Language table */
3269                                 str_ptr = "\001";
3270                                 break;
3271
3272                         case 1: /* Vendor */
3273                                 str_ptr = sc->sc_vendor;
3274                                 break;
3275
3276                         case 2: /* Product */
3277                                 str_ptr = "XHCI root HUB";
3278                                 break;
3279
3280                         default:
3281                                 str_ptr = "";
3282                                 break;
3283                         }
3284
3285                         len = usb_make_str_desc(
3286                             sc->sc_hub_desc.temp,
3287                             sizeof(sc->sc_hub_desc.temp),
3288                             str_ptr);
3289                         break;
3290
3291                 default:
3292                         err = USB_ERR_IOERROR;
3293                         goto done;
3294                 }
3295                 break;
3296         case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3297                 len = 1;
3298                 sc->sc_hub_desc.temp[0] = 0;
3299                 break;
3300         case C(UR_GET_STATUS, UT_READ_DEVICE):
3301                 len = 2;
3302                 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3303                 break;
3304         case C(UR_GET_STATUS, UT_READ_INTERFACE):
3305         case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3306                 len = 2;
3307                 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3308                 break;
3309         case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3310                 if (value >= XHCI_MAX_DEVICES) {
3311                         err = USB_ERR_IOERROR;
3312                         goto done;
3313                 }
3314                 break;
3315         case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3316                 if (value != 0 && value != 1) {
3317                         err = USB_ERR_IOERROR;
3318                         goto done;
3319                 }
3320                 sc->sc_conf = value;
3321                 break;
3322         case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3323                 break;
3324         case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3325         case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3326         case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3327                 err = USB_ERR_IOERROR;
3328                 goto done;
3329         case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3330                 break;
3331         case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3332                 break;
3333                 /* Hub requests */
3334         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3335                 break;
3336         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3337                 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3338
3339                 if ((index < 1) ||
3340                     (index > sc->sc_noport)) {
3341                         err = USB_ERR_IOERROR;
3342                         goto done;
3343                 }
3344                 port = XHCI_PORTSC(index);
3345
3346                 v = XREAD4(sc, oper, port);
3347                 i = XHCI_PS_PLS_GET(v);
3348                 v &= ~XHCI_PS_CLEAR;
3349
3350                 switch (value) {
3351                 case UHF_C_BH_PORT_RESET:
3352                         XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3353                         break;
3354                 case UHF_C_PORT_CONFIG_ERROR:
3355                         XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3356                         break;
3357                 case UHF_C_PORT_SUSPEND:
3358                 case UHF_C_PORT_LINK_STATE:
3359                         XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3360                         break;
3361                 case UHF_C_PORT_CONNECTION:
3362                         XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3363                         break;
3364                 case UHF_C_PORT_ENABLE:
3365                         XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3366                         break;
3367                 case UHF_C_PORT_OVER_CURRENT:
3368                         XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3369                         break;
3370                 case UHF_C_PORT_RESET:
3371                         XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3372                         break;
3373                 case UHF_PORT_ENABLE:
3374                         XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3375                         break;
3376                 case UHF_PORT_POWER:
3377                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3378                         break;
3379                 case UHF_PORT_INDICATOR:
3380                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3381                         break;
3382                 case UHF_PORT_SUSPEND:
3383
3384                         /* U3 -> U15 */
3385                         if (i == 3) {
3386                                 XWRITE4(sc, oper, port, v |
3387                                     XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3388                         }
3389
3390                         /* wait 20ms for resume sequence to complete */
3391                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3392
3393                         /* U0 */
3394                         XWRITE4(sc, oper, port, v |
3395                             XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3396                         break;
3397                 default:
3398                         err = USB_ERR_IOERROR;
3399                         goto done;
3400                 }
3401                 break;
3402
3403         case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3404                 if ((value & 0xff) != 0) {
3405                         err = USB_ERR_IOERROR;
3406                         goto done;
3407                 }
3408
3409                 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3410
3411                 sc->sc_hub_desc.hubd = xhci_hubd;
3412
3413                 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3414
3415                 if (XHCI_HCS0_PPC(v))
3416                         i = UHD_PWR_INDIVIDUAL;
3417                 else
3418                         i = UHD_PWR_GANGED;
3419
3420                 if (XHCI_HCS0_PIND(v))
3421                         i |= UHD_PORT_IND;
3422
3423                 i |= UHD_OC_INDIVIDUAL;
3424
3425                 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3426
3427                 /* see XHCI section 5.4.9: */
3428                 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3429
3430                 for (j = 1; j <= sc->sc_noport; j++) {
3431
3432                         v = XREAD4(sc, oper, XHCI_PORTSC(j));
3433                         if (v & XHCI_PS_DR) {
3434                                 sc->sc_hub_desc.hubd.
3435                                     DeviceRemovable[j / 8] |= 1U << (j % 8);
3436                         }
3437                 }
3438                 len = sc->sc_hub_desc.hubd.bLength;
3439                 break;
3440
3441         case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3442                 len = 16;
3443                 memset(sc->sc_hub_desc.temp, 0, 16);
3444                 break;
3445
3446         case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3447                 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3448
3449                 if ((index < 1) ||
3450                     (index > sc->sc_noport)) {
3451                         err = USB_ERR_IOERROR;
3452                         goto done;
3453                 }
3454
3455                 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3456
3457                 DPRINTFN(9, "port status=0x%08x\n", v);
3458
3459                 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3460
3461                 switch (XHCI_PS_SPEED_GET(v)) {
3462                 case 3:
3463                         i |= UPS_HIGH_SPEED;
3464                         break;
3465                 case 2:
3466                         i |= UPS_LOW_SPEED;
3467                         break;
3468                 case 1:
3469                         /* FULL speed */
3470                         break;
3471                 default:
3472                         i |= UPS_OTHER_SPEED;
3473                         break;
3474                 }
3475
3476                 if (v & XHCI_PS_CCS)
3477                         i |= UPS_CURRENT_CONNECT_STATUS;
3478                 if (v & XHCI_PS_PED)
3479                         i |= UPS_PORT_ENABLED;
3480                 if (v & XHCI_PS_OCA)
3481                         i |= UPS_OVERCURRENT_INDICATOR;
3482                 if (v & XHCI_PS_PR)
3483                         i |= UPS_RESET;
3484                 if (v & XHCI_PS_PP) {
3485                         /*
3486                          * The USB 3.0 RH is using the
3487                          * USB 2.0's power bit
3488                          */
3489                         i |= UPS_PORT_POWER;
3490                 }
3491                 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3492
3493                 i = 0;
3494                 if (v & XHCI_PS_CSC)
3495                         i |= UPS_C_CONNECT_STATUS;
3496                 if (v & XHCI_PS_PEC)
3497                         i |= UPS_C_PORT_ENABLED;
3498                 if (v & XHCI_PS_OCC)
3499                         i |= UPS_C_OVERCURRENT_INDICATOR;
3500                 if (v & XHCI_PS_WRC)
3501                         i |= UPS_C_BH_PORT_RESET;
3502                 if (v & XHCI_PS_PRC)
3503                         i |= UPS_C_PORT_RESET;
3504                 if (v & XHCI_PS_PLC)
3505                         i |= UPS_C_PORT_LINK_STATE;
3506                 if (v & XHCI_PS_CEC)
3507                         i |= UPS_C_PORT_CONFIG_ERROR;
3508
3509                 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3510                 len = sizeof(sc->sc_hub_desc.ps);
3511                 break;
3512
3513         case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3514                 err = USB_ERR_IOERROR;
3515                 goto done;
3516
3517         case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3518                 break;
3519
3520         case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3521
3522                 i = index >> 8;
3523                 index &= 0x00FF;
3524
3525                 if ((index < 1) ||
3526                     (index > sc->sc_noport)) {
3527                         err = USB_ERR_IOERROR;
3528                         goto done;
3529                 }
3530
3531                 port = XHCI_PORTSC(index);
3532                 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3533
3534                 switch (value) {
3535                 case UHF_PORT_U1_TIMEOUT:
3536                         if (XHCI_PS_SPEED_GET(v) != 4) {
3537                                 err = USB_ERR_IOERROR;
3538                                 goto done;
3539                         }
3540                         port = XHCI_PORTPMSC(index);
3541                         v = XREAD4(sc, oper, port);
3542                         v &= ~XHCI_PM3_U1TO_SET(0xFF);
3543                         v |= XHCI_PM3_U1TO_SET(i);
3544                         XWRITE4(sc, oper, port, v);
3545                         break;
3546                 case UHF_PORT_U2_TIMEOUT:
3547                         if (XHCI_PS_SPEED_GET(v) != 4) {
3548                                 err = USB_ERR_IOERROR;
3549                                 goto done;
3550                         }
3551                         port = XHCI_PORTPMSC(index);
3552                         v = XREAD4(sc, oper, port);
3553                         v &= ~XHCI_PM3_U2TO_SET(0xFF);
3554                         v |= XHCI_PM3_U2TO_SET(i);
3555                         XWRITE4(sc, oper, port, v);
3556                         break;
3557                 case UHF_BH_PORT_RESET:
3558                         XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3559                         break;
3560                 case UHF_PORT_LINK_STATE:
3561                         XWRITE4(sc, oper, port, v |
3562                             XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3563                         /* 4ms settle time */
3564                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3565                         break;
3566                 case UHF_PORT_ENABLE:
3567                         DPRINTFN(3, "set port enable %d\n", index);
3568                         break;
3569                 case UHF_PORT_SUSPEND:
3570                         DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3571                         j = XHCI_PS_SPEED_GET(v);
3572                         if ((j < 1) || (j > 3)) {
3573                                 /* non-supported speed */
3574                                 err = USB_ERR_IOERROR;
3575                                 goto done;
3576                         }
3577                         XWRITE4(sc, oper, port, v |
3578                             XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3579                         break;
3580                 case UHF_PORT_RESET:
3581                         DPRINTFN(6, "reset port %d\n", index);
3582                         XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3583                         break;
3584                 case UHF_PORT_POWER:
3585                         DPRINTFN(3, "set port power %d\n", index);
3586                         XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3587                         break;
3588                 case UHF_PORT_TEST:
3589                         DPRINTFN(3, "set port test %d\n", index);
3590                         break;
3591                 case UHF_PORT_INDICATOR:
3592                         DPRINTFN(3, "set port indicator %d\n", index);
3593
3594                         v &= ~XHCI_PS_PIC_SET(3);
3595                         v |= XHCI_PS_PIC_SET(1);
3596
3597                         XWRITE4(sc, oper, port, v);
3598                         break;
3599                 default:
3600                         err = USB_ERR_IOERROR;
3601                         goto done;
3602                 }
3603                 break;
3604
3605         case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3606         case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3607         case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3608         case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3609                 break;
3610         default:
3611                 err = USB_ERR_IOERROR;
3612                 goto done;
3613         }
3614 done:
3615         *plength = len;
3616         *pptr = ptr;
3617         return (err);
3618 }
3619
3620 static void
3621 xhci_xfer_setup(struct usb_setup_params *parm)
3622 {
3623         struct usb_page_search page_info;
3624         struct usb_page_cache *pc;
3625         struct xhci_softc *sc;
3626         struct usb_xfer *xfer;
3627         void *last_obj;
3628         uint32_t ntd;
3629         uint32_t n;
3630
3631         sc = XHCI_BUS2SC(parm->udev->bus);
3632         xfer = parm->curr_xfer;
3633
3634         /*
3635          * The proof for the "ntd" formula is illustrated like this:
3636          *
3637          * +------------------------------------+
3638          * |                                    |
3639          * |         |remainder ->              |
3640          * |   +-----+---+                      |
3641          * |   | xxx | x | frm 0                |
3642          * |   +-----+---++                     |
3643          * |   | xxx | xx | frm 1               |
3644          * |   +-----+----+                     |
3645          * |            ...                     |
3646          * +------------------------------------+
3647          *
3648          * "xxx" means a completely full USB transfer descriptor
3649          *
3650          * "x" and "xx" means a short USB packet
3651          *
3652          * For the remainder of an USB transfer modulo
3653          * "max_data_length" we need two USB transfer descriptors.
3654          * One to transfer the remaining data and one to finalise with
3655          * a zero length packet in case the "force_short_xfer" flag is
3656          * set. We only need two USB transfer descriptors in the case
3657          * where the transfer length of the first one is a factor of
3658          * "max_frame_size". The rest of the needed USB transfer
3659          * descriptors is given by the buffer size divided by the
3660          * maximum data payload.
3661          */
3662         parm->hc_max_packet_size = 0x400;
3663         parm->hc_max_packet_count = 16 * 3;
3664         parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3665
3666         xfer->flags_int.bdma_enable = 1;
3667
3668         usbd_transfer_setup_sub(parm);
3669
3670         if (xfer->flags_int.isochronous_xfr) {
3671                 ntd = ((1 * xfer->nframes)
3672                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3673         } else if (xfer->flags_int.control_xfr) {
3674                 ntd = ((2 * xfer->nframes) + 1  /* STATUS */
3675                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3676         } else {
3677                 ntd = ((2 * xfer->nframes)
3678                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3679         }
3680
3681 alloc_dma_set:
3682
3683         if (parm->err)
3684                 return;
3685
3686         /*
3687          * Allocate queue heads and transfer descriptors
3688          */
3689         last_obj = NULL;
3690
3691         if (usbd_transfer_setup_sub_malloc(
3692             parm, &pc, sizeof(struct xhci_td),
3693             XHCI_TD_ALIGN, ntd)) {
3694                 parm->err = USB_ERR_NOMEM;
3695                 return;
3696         }
3697         if (parm->buf) {
3698                 for (n = 0; n != ntd; n++) {
3699                         struct xhci_td *td;
3700
3701                         usbd_get_page(pc + n, 0, &page_info);
3702
3703                         td = page_info.buffer;
3704
3705                         /* init TD */
3706                         td->td_self = page_info.physaddr;
3707                         td->obj_next = last_obj;
3708                         td->page_cache = pc + n;
3709
3710                         last_obj = td;
3711
3712                         usb_pc_cpu_flush(pc + n);
3713                 }
3714         }
3715         xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3716
3717         if (!xfer->flags_int.curr_dma_set) {
3718                 xfer->flags_int.curr_dma_set = 1;
3719                 goto alloc_dma_set;
3720         }
3721 }
3722
3723 static usb_error_t
3724 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3725 {
3726         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3727         struct usb_page_search buf_inp;
3728         struct usb_device *udev;
3729         struct xhci_endpoint_ext *pepext;
3730         struct usb_endpoint_descriptor *edesc;
3731         struct usb_page_cache *pcinp;
3732         usb_error_t err;
3733         uint8_t index;
3734         uint8_t epno;
3735
3736         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3737             xfer->endpoint->edesc);
3738
3739         udev = xfer->xroot->udev;
3740         index = udev->controller_slot_id;
3741
3742         pcinp = &sc->sc_hw.devs[index].input_pc;
3743
3744         usbd_get_page(pcinp, 0, &buf_inp);
3745
3746         edesc = xfer->endpoint->edesc;
3747
3748         epno = edesc->bEndpointAddress;
3749
3750         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3751                 epno |= UE_DIR_IN;
3752
3753         epno = XHCI_EPNO2EPID(epno);
3754
3755         if (epno == 0)
3756                 return (USB_ERR_NO_PIPE);               /* invalid */
3757
3758         XHCI_CMD_LOCK(sc);
3759
3760         /* configure endpoint */
3761
3762         err = xhci_configure_endpoint_by_xfer(xfer);
3763
3764         if (err != 0) {
3765                 XHCI_CMD_UNLOCK(sc);
3766                 return (err);
3767         }
3768
3769         /*
3770          * Get the endpoint into the stopped state according to the
3771          * endpoint context state diagram in the XHCI specification:
3772          */
3773
3774         err = xhci_cmd_stop_ep(sc, 0, epno, index);
3775
3776         if (err != 0)
3777                 DPRINTF("Could not stop endpoint %u\n", epno);
3778
3779         err = xhci_cmd_reset_ep(sc, 0, epno, index);
3780
3781         if (err != 0)
3782                 DPRINTF("Could not reset endpoint %u\n", epno);
3783
3784         err = xhci_cmd_set_tr_dequeue_ptr(sc, pepext->physaddr |
3785             XHCI_EPCTX_2_DCS_SET(1), 0, epno, index);
3786
3787         if (err != 0)
3788                 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3789
3790         /*
3791          * Get the endpoint into the running state according to the
3792          * endpoint context state diagram in the XHCI specification:
3793          */
3794
3795         xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3796
3797         err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3798
3799         if (err != 0)
3800                 DPRINTF("Could not configure endpoint %u\n", epno);
3801
3802         err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3803
3804         if (err != 0)
3805                 DPRINTF("Could not configure endpoint %u\n", epno);
3806
3807         XHCI_CMD_UNLOCK(sc);
3808
3809         return (0);
3810 }
3811
3812 static void
3813 xhci_xfer_unsetup(struct usb_xfer *xfer)
3814 {
3815         return;
3816 }
3817
3818 static void
3819 xhci_start_dma_delay(struct usb_xfer *xfer)
3820 {
3821         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3822
3823         /* put transfer on interrupt queue (again) */
3824         usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3825
3826         (void)usb_proc_msignal(&sc->sc_config_proc,
3827             &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3828 }
3829
3830 static void
3831 xhci_configure_msg(struct usb_proc_msg *pm)
3832 {
3833         struct xhci_softc *sc;
3834         struct xhci_endpoint_ext *pepext;
3835         struct usb_xfer *xfer;
3836
3837         sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3838
3839 restart:
3840         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3841
3842                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3843                     xfer->endpoint->edesc);
3844
3845                 if ((pepext->trb_halted != 0) ||
3846                     (pepext->trb_running == 0)) {
3847
3848                         uint8_t i;
3849
3850                         /* clear halted and running */
3851                         pepext->trb_halted = 0;
3852                         pepext->trb_running = 0;
3853
3854                         /* nuke remaining buffered transfers */
3855
3856                         for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
3857                                 /*
3858                                  * NOTE: We need to use the timeout
3859                                  * error code here else existing
3860                                  * isochronous clients can get
3861                                  * confused:
3862                                  */
3863                                 if (pepext->xfer[i] != NULL) {
3864                                         xhci_device_done(pepext->xfer[i],
3865                                             USB_ERR_TIMEOUT);
3866                                 }
3867                         }
3868
3869                         /*
3870                          * NOTE: The USB transfer cannot vanish in
3871                          * this state!
3872                          */
3873
3874                         USB_BUS_UNLOCK(&sc->sc_bus);
3875
3876                         xhci_configure_reset_endpoint(xfer);
3877
3878                         USB_BUS_LOCK(&sc->sc_bus);
3879
3880                         /* check if halted is still cleared */
3881                         if (pepext->trb_halted == 0) {
3882                                 pepext->trb_running = 1;
3883                                 pepext->trb_index = 0;
3884                         }
3885                         goto restart;
3886                 }
3887
3888                 if (xfer->flags_int.did_dma_delay) {
3889
3890                         /* remove transfer from interrupt queue (again) */
3891                         usbd_transfer_dequeue(xfer);
3892
3893                         /* we are finally done */
3894                         usb_dma_delay_done_cb(xfer);
3895
3896                         /* queue changed - restart */
3897                         goto restart;
3898                 }
3899         }
3900
3901         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3902
3903                 /* try to insert xfer on HW queue */
3904                 xhci_transfer_insert(xfer);
3905
3906                 /* try to multi buffer */
3907                 xhci_device_generic_multi_enter(xfer->endpoint, NULL);
3908         }
3909 }
3910
3911 static void
3912 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3913     struct usb_endpoint *ep)
3914 {
3915         struct xhci_endpoint_ext *pepext;
3916
3917         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3918             ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
3919
3920         if (udev->flags.usb_mode != USB_MODE_HOST) {
3921                 /* not supported */
3922                 return;
3923         }
3924         if (udev->parent_hub == NULL) {
3925                 /* root HUB has special endpoint handling */
3926                 return;
3927         }
3928
3929         ep->methods = &xhci_device_generic_methods;
3930
3931         pepext = xhci_get_endpoint_ext(udev, edesc);
3932
3933         USB_BUS_LOCK(udev->bus);
3934         pepext->trb_halted = 1;
3935         pepext->trb_running = 0;
3936         USB_BUS_UNLOCK(udev->bus);
3937 }
3938
3939 static void
3940 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
3941 {
3942
3943 }
3944
3945 static void
3946 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3947 {
3948         struct xhci_endpoint_ext *pepext;
3949
3950         DPRINTF("\n");
3951
3952         if (udev->flags.usb_mode != USB_MODE_HOST) {
3953                 /* not supported */
3954                 return;
3955         }
3956         if (udev->parent_hub == NULL) {
3957                 /* root HUB has special endpoint handling */
3958                 return;
3959         }
3960
3961         pepext = xhci_get_endpoint_ext(udev, ep->edesc);
3962
3963         USB_BUS_LOCK(udev->bus);
3964         pepext->trb_halted = 1;
3965         pepext->trb_running = 0;
3966         USB_BUS_UNLOCK(udev->bus);
3967 }
3968
3969 static usb_error_t
3970 xhci_device_init(struct usb_device *udev)
3971 {
3972         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3973         usb_error_t err;
3974         uint8_t temp;
3975
3976         /* no init for root HUB */
3977         if (udev->parent_hub == NULL)
3978                 return (0);
3979
3980         XHCI_CMD_LOCK(sc);
3981
3982         /* set invalid default */
3983
3984         udev->controller_slot_id = sc->sc_noslot + 1;
3985
3986         /* try to get a new slot ID from the XHCI */
3987
3988         err = xhci_cmd_enable_slot(sc, &temp);
3989
3990         if (err) {
3991                 XHCI_CMD_UNLOCK(sc);
3992                 return (err);
3993         }
3994
3995         if (temp > sc->sc_noslot) {
3996                 XHCI_CMD_UNLOCK(sc);
3997                 return (USB_ERR_BAD_ADDRESS);
3998         }
3999
4000         if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
4001                 DPRINTF("slot %u already allocated.\n", temp);
4002                 XHCI_CMD_UNLOCK(sc);
4003                 return (USB_ERR_BAD_ADDRESS);
4004         }
4005
4006         /* store slot ID for later reference */
4007
4008         udev->controller_slot_id = temp;
4009
4010         /* reset data structure */
4011
4012         memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
4013
4014         /* set mark slot allocated */
4015
4016         sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
4017
4018         err = xhci_alloc_device_ext(udev);
4019
4020         XHCI_CMD_UNLOCK(sc);
4021
4022         /* get device into default state */
4023
4024         if (err == 0)
4025                 err = xhci_set_address(udev, NULL, 0);
4026
4027         return (err);
4028 }
4029
4030 static void
4031 xhci_device_uninit(struct usb_device *udev)
4032 {
4033         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4034         uint8_t index;
4035
4036         /* no init for root HUB */
4037         if (udev->parent_hub == NULL)
4038                 return;
4039
4040         XHCI_CMD_LOCK(sc);
4041
4042         index = udev->controller_slot_id;
4043
4044         if (index <= sc->sc_noslot) {
4045                 xhci_cmd_disable_slot(sc, index);
4046                 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
4047
4048                 /* free device extension */
4049                 xhci_free_device_ext(udev);
4050         }
4051
4052         XHCI_CMD_UNLOCK(sc);
4053 }
4054
4055 static void
4056 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4057 {
4058         /*
4059          * Wait until the hardware has finished any possible use of
4060          * the transfer descriptor(s)
4061          */
4062         *pus = 2048;                    /* microseconds */
4063 }
4064
4065 static void
4066 xhci_device_resume(struct usb_device *udev)
4067 {
4068         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4069         uint8_t index;
4070         uint8_t n;
4071         uint8_t p;
4072
4073         DPRINTF("\n");
4074
4075         /* check for root HUB */
4076         if (udev->parent_hub == NULL)
4077                 return;
4078
4079         index = udev->controller_slot_id;
4080
4081         XHCI_CMD_LOCK(sc);
4082
4083         /* blindly resume all endpoints */
4084
4085         USB_BUS_LOCK(udev->bus);
4086
4087         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4088                 for (p = 0; p != 1 /*XHCI_MAX_STREAMS*/; p++) {
4089                         XWRITE4(sc, door, XHCI_DOORBELL(index),
4090                             n | XHCI_DB_SID_SET(p));
4091                 }
4092         }
4093
4094         USB_BUS_UNLOCK(udev->bus);
4095
4096         XHCI_CMD_UNLOCK(sc);
4097 }
4098
4099 static void
4100 xhci_device_suspend(struct usb_device *udev)
4101 {
4102         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4103         uint8_t index;
4104         uint8_t n;
4105         usb_error_t err;
4106
4107         DPRINTF("\n");
4108
4109         /* check for root HUB */
4110         if (udev->parent_hub == NULL)
4111                 return;
4112
4113         index = udev->controller_slot_id;
4114
4115         XHCI_CMD_LOCK(sc);
4116
4117         /* blindly suspend all endpoints */
4118
4119         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4120                 err = xhci_cmd_stop_ep(sc, 1, n, index);
4121                 if (err != 0) {
4122                         DPRINTF("Failed to suspend endpoint "
4123                             "%u on slot %u (ignored).\n", n, index);
4124                 }
4125         }
4126
4127         XHCI_CMD_UNLOCK(sc);
4128 }
4129
4130 static void
4131 xhci_set_hw_power(struct usb_bus *bus)
4132 {
4133         DPRINTF("\n");
4134 }
4135
4136 static void
4137 xhci_device_state_change(struct usb_device *udev)
4138 {
4139         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4140         struct usb_page_search buf_inp;
4141         usb_error_t err;
4142         uint8_t index;
4143
4144         /* check for root HUB */
4145         if (udev->parent_hub == NULL)
4146                 return;
4147
4148         index = udev->controller_slot_id;
4149
4150         DPRINTF("\n");
4151
4152         if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4153                 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4154                     &sc->sc_hw.devs[index].tt);
4155                 if (err != 0)
4156                         sc->sc_hw.devs[index].nports = 0;
4157         }
4158
4159         XHCI_CMD_LOCK(sc);
4160
4161         switch (usb_get_device_state(udev)) {
4162         case USB_STATE_POWERED:
4163                 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4164                         break;
4165
4166                 /* set default state */
4167                 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4168
4169                 /* reset number of contexts */
4170                 sc->sc_hw.devs[index].context_num = 0;
4171
4172                 err = xhci_cmd_reset_dev(sc, index);
4173
4174                 if (err != 0) {
4175                         DPRINTF("Device reset failed "
4176                             "for slot %u.\n", index);
4177                 }
4178                 break;
4179
4180         case USB_STATE_ADDRESSED:
4181                 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4182                         break;
4183
4184                 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4185
4186                 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4187
4188                 if (err) {
4189                         DPRINTF("Failed to deconfigure "
4190                             "slot %u.\n", index);
4191                 }
4192                 break;
4193
4194         case USB_STATE_CONFIGURED:
4195                 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4196                         break;
4197
4198                 /* set configured state */
4199                 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4200
4201                 /* reset number of contexts */
4202                 sc->sc_hw.devs[index].context_num = 0;
4203
4204                 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4205
4206                 xhci_configure_mask(udev, 3, 0);
4207
4208                 err = xhci_configure_device(udev);
4209                 if (err != 0) {
4210                         DPRINTF("Could not configure device "
4211                             "at slot %u.\n", index);
4212                 }
4213
4214                 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4215                 if (err != 0) {
4216                         DPRINTF("Could not evaluate device "
4217                             "context at slot %u.\n", index);
4218                 }
4219                 break;
4220
4221         default:
4222                 break;
4223         }
4224         XHCI_CMD_UNLOCK(sc);
4225 }
4226
4227 struct usb_bus_methods xhci_bus_methods = {
4228         .endpoint_init = xhci_ep_init,
4229         .endpoint_uninit = xhci_ep_uninit,
4230         .xfer_setup = xhci_xfer_setup,
4231         .xfer_unsetup = xhci_xfer_unsetup,
4232         .get_dma_delay = xhci_get_dma_delay,
4233         .device_init = xhci_device_init,
4234         .device_uninit = xhci_device_uninit,
4235         .device_resume = xhci_device_resume,
4236         .device_suspend = xhci_device_suspend,
4237         .set_hw_power = xhci_set_hw_power,
4238         .roothub_exec = xhci_roothub_exec,
4239         .xfer_poll = xhci_do_poll,
4240         .start_dma_delay = xhci_start_dma_delay,
4241         .set_address = xhci_set_address,
4242         .clear_stall = xhci_ep_clear_stall,
4243         .device_state_change = xhci_device_state_change,
4244         .set_hw_power_sleep = xhci_set_hw_power_sleep,
4245 };