2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
29 * The XHCI 1.0 spec can be found at
30 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
31 * and the USB 3.0 spec at
32 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
36 * A few words about the design implementation: This driver emulates
37 * the concept about TDs which is found in EHCI specification. This
38 * way we avoid too much diveration among USB drivers.
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
44 #include <sys/stdint.h>
45 #include <sys/stddef.h>
46 #include <sys/param.h>
47 #include <sys/queue.h>
48 #include <sys/types.h>
49 #include <sys/systm.h>
50 #include <sys/kernel.h>
52 #include <sys/module.h>
54 #include <sys/mutex.h>
55 #include <sys/condvar.h>
56 #include <sys/sysctl.h>
58 #include <sys/unistd.h>
59 #include <sys/callout.h>
60 #include <sys/malloc.h>
63 #include <dev/usb/usb.h>
64 #include <dev/usb/usbdi.h>
66 #define USB_DEBUG_VAR xhcidebug
68 #include <dev/usb/usb_core.h>
69 #include <dev/usb/usb_debug.h>
70 #include <dev/usb/usb_busdma.h>
71 #include <dev/usb/usb_process.h>
72 #include <dev/usb/usb_transfer.h>
73 #include <dev/usb/usb_device.h>
74 #include <dev/usb/usb_hub.h>
75 #include <dev/usb/usb_util.h>
77 #include <dev/usb/usb_controller.h>
78 #include <dev/usb/usb_bus.h>
79 #include <dev/usb/controller/xhci.h>
80 #include <dev/usb/controller/xhcireg.h>
82 #define XHCI_BUS2SC(bus) \
83 ((struct xhci_softc *)(((uint8_t *)(bus)) - \
84 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
90 SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
91 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
92 &xhcidebug, 0, "Debug level");
93 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
94 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN,
95 &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller");
96 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
101 #define XHCI_INTR_ENDPT 1
103 struct xhci_std_temp {
104 struct xhci_softc *sc;
105 struct usb_page_cache *pc;
107 struct xhci_td *td_next;
110 uint32_t max_packet_size;
122 uint8_t do_isoc_sync;
125 static void xhci_do_poll(struct usb_bus *);
126 static void xhci_device_done(struct usb_xfer *, usb_error_t);
127 static void xhci_root_intr(struct xhci_softc *);
128 static void xhci_free_device_ext(struct usb_device *);
129 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
130 struct usb_endpoint_descriptor *);
131 static usb_proc_callback_t xhci_configure_msg;
132 static usb_error_t xhci_configure_device(struct usb_device *);
133 static usb_error_t xhci_configure_endpoint(struct usb_device *,
134 struct usb_endpoint_descriptor *, uint64_t, uint16_t,
135 uint8_t, uint8_t, uint8_t, uint16_t, uint16_t);
136 static usb_error_t xhci_configure_mask(struct usb_device *,
138 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
140 static void xhci_endpoint_doorbell(struct usb_xfer *);
141 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
142 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
143 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
145 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
148 extern struct usb_bus_methods xhci_bus_methods;
152 xhci_dump_trb(struct xhci_trb *trb)
154 DPRINTFN(5, "trb = %p\n", trb);
155 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
156 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
157 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
161 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
163 DPRINTFN(5, "pep = %p\n", pep);
164 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
165 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
166 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
167 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
168 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
169 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
170 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
174 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
176 DPRINTFN(5, "psl = %p\n", psl);
177 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
178 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
179 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
180 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
185 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
187 struct xhci_softc *sc = XHCI_BUS2SC(bus);
190 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
191 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
193 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
194 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
196 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) {
197 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
198 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
203 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
205 if (sc->sc_ctx_is_64_byte) {
207 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
208 /* all contexts are initially 32-bytes */
209 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
210 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
216 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
218 if (sc->sc_ctx_is_64_byte) {
220 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
221 /* all contexts are initially 32-bytes */
222 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
223 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
225 return (le32toh(*ptr));
229 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
231 if (sc->sc_ctx_is_64_byte) {
233 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
234 /* all contexts are initially 32-bytes */
235 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
236 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
243 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
245 if (sc->sc_ctx_is_64_byte) {
247 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
248 /* all contexts are initially 32-bytes */
249 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
250 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
252 return (le64toh(*ptr));
257 xhci_reset_command_queue_locked(struct xhci_softc *sc)
259 struct usb_page_search buf_res;
260 struct xhci_hw_root *phwr;
266 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
267 if (temp & XHCI_CRCR_LO_CRR) {
268 DPRINTF("Command ring running\n");
269 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
272 * Try to abort the last command as per section
273 * 4.6.1.2 "Aborting a Command" of the XHCI
277 /* stop and cancel */
278 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
279 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
281 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
282 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
285 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
287 /* check if command ring is still running */
288 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
289 if (temp & XHCI_CRCR_LO_CRR) {
290 DPRINTF("Comand ring still running\n");
291 return (USB_ERR_IOERROR);
295 /* reset command ring */
296 sc->sc_command_ccs = 1;
297 sc->sc_command_idx = 0;
299 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
301 /* setup command ring control base address */
302 addr = buf_res.physaddr;
303 phwr = buf_res.buffer;
304 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
306 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
308 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
309 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
311 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
313 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
314 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
320 xhci_start_controller(struct xhci_softc *sc)
322 struct usb_page_search buf_res;
323 struct xhci_hw_root *phwr;
324 struct xhci_dev_ctx_addr *pdctxa;
332 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
333 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
334 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
336 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
337 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
338 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
340 sc->sc_event_ccs = 1;
341 sc->sc_event_idx = 0;
342 sc->sc_command_ccs = 1;
343 sc->sc_command_idx = 0;
345 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
347 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
349 DPRINTF("HCS0 = 0x%08x\n", temp);
351 if (XHCI_HCS0_CSZ(temp)) {
352 sc->sc_ctx_is_64_byte = 1;
353 device_printf(sc->sc_bus.parent, "64 byte context size.\n");
355 sc->sc_ctx_is_64_byte = 0;
356 device_printf(sc->sc_bus.parent, "32 byte context size.\n");
359 /* Reset controller */
360 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
362 for (i = 0; i != 100; i++) {
363 usb_pause_mtx(NULL, hz / 100);
364 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
365 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
371 device_printf(sc->sc_bus.parent, "Controller "
373 return (USB_ERR_IOERROR);
376 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
377 device_printf(sc->sc_bus.parent, "Controller does "
378 "not support 4K page size.\n");
379 return (USB_ERR_IOERROR);
382 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
384 i = XHCI_HCS1_N_PORTS(temp);
387 device_printf(sc->sc_bus.parent, "Invalid number "
388 "of ports: %u\n", i);
389 return (USB_ERR_IOERROR);
393 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
395 if (sc->sc_noslot > XHCI_MAX_DEVICES)
396 sc->sc_noslot = XHCI_MAX_DEVICES;
398 /* setup number of device slots */
400 DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
401 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
403 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
405 DPRINTF("Max slots: %u\n", sc->sc_noslot);
407 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
409 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
411 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
412 device_printf(sc->sc_bus.parent, "XHCI request "
413 "too many scratchpads\n");
414 return (USB_ERR_NOMEM);
417 DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
419 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
421 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
422 XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
424 temp = XREAD4(sc, oper, XHCI_USBSTS);
426 /* clear interrupts */
427 XWRITE4(sc, oper, XHCI_USBSTS, temp);
428 /* disable all device notifications */
429 XWRITE4(sc, oper, XHCI_DNCTRL, 0);
431 /* setup device context base address */
432 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
433 pdctxa = buf_res.buffer;
434 memset(pdctxa, 0, sizeof(*pdctxa));
436 addr = buf_res.physaddr;
437 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
439 /* slot 0 points to the table of scratchpad pointers */
440 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
442 for (i = 0; i != sc->sc_noscratch; i++) {
443 struct usb_page_search buf_scp;
444 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
445 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
448 addr = buf_res.physaddr;
450 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
451 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
452 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
453 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
455 /* Setup event table size */
457 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
459 DPRINTF("HCS2=0x%08x\n", temp);
461 temp = XHCI_HCS2_ERST_MAX(temp);
463 if (temp > XHCI_MAX_RSEG)
464 temp = XHCI_MAX_RSEG;
466 sc->sc_erst_max = temp;
468 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
469 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp);
471 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp));
473 /* Check if we should use the default IMOD value */
474 if (sc->sc_imod_default == 0)
475 sc->sc_imod_default = XHCI_IMOD_DEFAULT;
477 /* Setup interrupt rate */
478 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default);
480 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
482 phwr = buf_res.buffer;
483 addr = buf_res.physaddr;
484 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
486 /* reset hardware root structure */
487 memset(phwr, 0, sizeof(*phwr));
489 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
490 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
492 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
494 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
495 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
497 addr = (uint64_t)buf_res.physaddr;
499 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
501 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
502 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
504 /* Setup interrupter registers */
506 temp = XREAD4(sc, runt, XHCI_IMAN(0));
507 temp |= XHCI_IMAN_INTR_ENA;
508 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
510 /* setup command ring control base address */
511 addr = buf_res.physaddr;
512 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
514 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
516 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
517 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
519 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
521 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
524 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
525 XHCI_CMD_INTE | XHCI_CMD_HSEE);
527 for (i = 0; i != 100; i++) {
528 usb_pause_mtx(NULL, hz / 100);
529 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
534 XWRITE4(sc, oper, XHCI_USBCMD, 0);
535 device_printf(sc->sc_bus.parent, "Run timeout.\n");
536 return (USB_ERR_IOERROR);
539 /* catch any lost interrupts */
540 xhci_do_poll(&sc->sc_bus);
542 if (sc->sc_port_route != NULL) {
543 /* Route all ports to the XHCI by default */
544 sc->sc_port_route(sc->sc_bus.parent,
545 ~xhciroute, xhciroute);
551 xhci_halt_controller(struct xhci_softc *sc)
559 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
560 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
561 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
563 /* Halt controller */
564 XWRITE4(sc, oper, XHCI_USBCMD, 0);
566 for (i = 0; i != 100; i++) {
567 usb_pause_mtx(NULL, hz / 100);
568 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
574 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
575 return (USB_ERR_IOERROR);
581 xhci_init(struct xhci_softc *sc, device_t self)
583 /* initialise some bus fields */
584 sc->sc_bus.parent = self;
586 /* set the bus revision */
587 sc->sc_bus.usbrev = USB_REV_3_0;
589 /* set up the bus struct */
590 sc->sc_bus.methods = &xhci_bus_methods;
592 /* setup devices array */
593 sc->sc_bus.devices = sc->sc_devices;
594 sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
596 /* setup command queue mutex and condition varible */
597 cv_init(&sc->sc_cmd_cv, "CMDQ");
598 sx_init(&sc->sc_cmd_sx, "CMDQ lock");
600 /* get all DMA memory */
601 if (usb_bus_mem_alloc_all(&sc->sc_bus,
602 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
606 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
607 sc->sc_config_msg[0].bus = &sc->sc_bus;
608 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
609 sc->sc_config_msg[1].bus = &sc->sc_bus;
611 if (usb_proc_create(&sc->sc_config_proc,
612 &sc->sc_bus.bus_mtx, device_get_nameunit(self), USB_PRI_MED)) {
613 printf("WARNING: Creation of XHCI configure "
614 "callback process failed.\n");
620 xhci_uninit(struct xhci_softc *sc)
622 usb_proc_free(&sc->sc_config_proc);
624 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
626 cv_destroy(&sc->sc_cmd_cv);
627 sx_destroy(&sc->sc_cmd_sx);
631 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
633 struct xhci_softc *sc = XHCI_BUS2SC(bus);
636 case USB_HW_POWER_SUSPEND:
637 DPRINTF("Stopping the XHCI\n");
638 xhci_halt_controller(sc);
640 case USB_HW_POWER_SHUTDOWN:
641 DPRINTF("Stopping the XHCI\n");
642 xhci_halt_controller(sc);
644 case USB_HW_POWER_RESUME:
645 DPRINTF("Starting the XHCI\n");
646 xhci_start_controller(sc);
654 xhci_generic_done_sub(struct usb_xfer *xfer)
657 struct xhci_td *td_alt_next;
661 td = xfer->td_transfer_cache;
662 td_alt_next = td->alt_next;
664 if (xfer->aframes != xfer->nframes)
665 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
669 usb_pc_cpu_invalidate(td->page_cache);
674 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
675 xfer, (unsigned int)xfer->aframes,
676 (unsigned int)xfer->nframes,
677 (unsigned int)len, (unsigned int)td->len,
678 (unsigned int)status);
681 * Verify the status length and
682 * add the length to "frlengths[]":
685 /* should not happen */
686 DPRINTF("Invalid status length, "
687 "0x%04x/0x%04x bytes\n", len, td->len);
688 status = XHCI_TRB_ERROR_LENGTH;
689 } else if (xfer->aframes != xfer->nframes) {
690 xfer->frlengths[xfer->aframes] += td->len - len;
692 /* Check for last transfer */
693 if (((void *)td) == xfer->td_transfer_last) {
697 /* Check for transfer error */
698 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
699 status != XHCI_TRB_ERROR_SUCCESS) {
700 /* the transfer is finished */
704 /* Check for short transfer */
706 if (xfer->flags_int.short_frames_ok ||
707 xfer->flags_int.isochronous_xfr ||
708 xfer->flags_int.control_xfr) {
709 /* follow alt next */
712 /* the transfer is finished */
719 if (td->alt_next != td_alt_next) {
720 /* this USB frame is complete */
725 /* update transfer cache */
727 xfer->td_transfer_cache = td;
729 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
730 (status != XHCI_TRB_ERROR_SHORT_PKT &&
731 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
732 USB_ERR_NORMAL_COMPLETION);
736 xhci_generic_done(struct usb_xfer *xfer)
740 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
741 xfer, xfer->endpoint);
745 xfer->td_transfer_cache = xfer->td_transfer_first;
747 if (xfer->flags_int.control_xfr) {
749 if (xfer->flags_int.control_hdr)
750 err = xhci_generic_done_sub(xfer);
754 if (xfer->td_transfer_cache == NULL)
758 while (xfer->aframes != xfer->nframes) {
760 err = xhci_generic_done_sub(xfer);
763 if (xfer->td_transfer_cache == NULL)
767 if (xfer->flags_int.control_xfr &&
768 !xfer->flags_int.control_act)
769 err = xhci_generic_done_sub(xfer);
771 /* transfer is complete */
772 xhci_device_done(xfer, err);
776 xhci_activate_transfer(struct usb_xfer *xfer)
780 td = xfer->td_transfer_cache;
782 usb_pc_cpu_invalidate(td->page_cache);
784 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
786 /* activate the transfer */
788 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
789 usb_pc_cpu_flush(td->page_cache);
791 xhci_endpoint_doorbell(xfer);
796 xhci_skip_transfer(struct usb_xfer *xfer)
799 struct xhci_td *td_last;
801 td = xfer->td_transfer_cache;
802 td_last = xfer->td_transfer_last;
806 usb_pc_cpu_invalidate(td->page_cache);
808 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
810 usb_pc_cpu_invalidate(td_last->page_cache);
812 /* copy LINK TRB to current waiting location */
814 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
815 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
816 usb_pc_cpu_flush(td->page_cache);
818 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
819 usb_pc_cpu_flush(td->page_cache);
821 xhci_endpoint_doorbell(xfer);
825 /*------------------------------------------------------------------------*
826 * xhci_check_transfer
827 *------------------------------------------------------------------------*/
829 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
842 td_event = le64toh(trb->qwTrb0);
843 temp = le32toh(trb->dwTrb2);
845 remainder = XHCI_TRB_2_REM_GET(temp);
846 status = XHCI_TRB_2_ERROR_GET(temp);
848 temp = le32toh(trb->dwTrb3);
849 epno = XHCI_TRB_3_EP_GET(temp);
850 index = XHCI_TRB_3_SLOT_GET(temp);
852 /* check if error means halted */
853 halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
854 status != XHCI_TRB_ERROR_SUCCESS);
856 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n",
857 index, epno, remainder, status);
859 if (index > sc->sc_noslot) {
860 DPRINTF("Invalid slot.\n");
864 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
865 DPRINTF("Invalid endpoint.\n");
869 /* try to find the USB transfer that generated the event */
870 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
871 struct usb_xfer *xfer;
873 struct xhci_endpoint_ext *pepext;
875 pepext = &sc->sc_hw.devs[index].endp[epno];
877 xfer = pepext->xfer[i];
881 td = xfer->td_transfer_cache;
883 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
885 (long long)td->td_self,
886 (long long)td->td_self + sizeof(td->td_trb));
889 * NOTE: Some XHCI implementations might not trigger
890 * an event on the last LINK TRB so we need to
891 * consider both the last and second last event
892 * address as conditions for a successful transfer.
894 * NOTE: We assume that the XHCI will only trigger one
895 * event per chain of TRBs.
898 offset = td_event - td->td_self;
901 offset < (int64_t)sizeof(td->td_trb)) {
903 usb_pc_cpu_invalidate(td->page_cache);
905 /* compute rest of remainder, if any */
906 for (i = (offset / 16) + 1; i < td->ntrb; i++) {
907 temp = le32toh(td->td_trb[i].dwTrb2);
908 remainder += XHCI_TRB_2_BYTES_GET(temp);
911 DPRINTFN(5, "New remainder: %u\n", remainder);
913 /* clear isochronous transfer errors */
914 if (xfer->flags_int.isochronous_xfr) {
917 status = XHCI_TRB_ERROR_SUCCESS;
922 /* "td->remainder" is verified later */
923 td->remainder = remainder;
926 usb_pc_cpu_flush(td->page_cache);
929 * 1) Last transfer descriptor makes the
932 if (((void *)td) == xfer->td_transfer_last) {
933 DPRINTF("TD is last\n");
934 xhci_generic_done(xfer);
939 * 2) Any kind of error makes the transfer
943 DPRINTF("TD has I/O error\n");
944 xhci_generic_done(xfer);
949 * 3) If there is no alternate next transfer,
950 * a short packet also makes the transfer done
952 if (td->remainder > 0) {
953 if (td->alt_next == NULL) {
955 "short TD has no alternate next\n");
956 xhci_generic_done(xfer);
959 DPRINTF("TD has short pkt\n");
960 if (xfer->flags_int.short_frames_ok ||
961 xfer->flags_int.isochronous_xfr ||
962 xfer->flags_int.control_xfr) {
963 /* follow the alt next */
964 xfer->td_transfer_cache = td->alt_next;
965 xhci_activate_transfer(xfer);
968 xhci_skip_transfer(xfer);
969 xhci_generic_done(xfer);
974 * 4) Transfer complete - go to next TD
976 DPRINTF("Following next TD\n");
977 xfer->td_transfer_cache = td->obj_next;
978 xhci_activate_transfer(xfer);
979 break; /* there should only be one match */
985 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
987 if (sc->sc_cmd_addr == trb->qwTrb0) {
988 DPRINTF("Received command event\n");
989 sc->sc_cmd_result[0] = trb->dwTrb2;
990 sc->sc_cmd_result[1] = trb->dwTrb3;
991 cv_signal(&sc->sc_cmd_cv);
992 return (1); /* command match */
998 xhci_interrupt_poll(struct xhci_softc *sc)
1000 struct usb_page_search buf_res;
1001 struct xhci_hw_root *phwr;
1011 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1013 phwr = buf_res.buffer;
1015 /* Receive any events */
1017 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1019 i = sc->sc_event_idx;
1020 j = sc->sc_event_ccs;
1025 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1027 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1032 event = XHCI_TRB_3_TYPE_GET(temp);
1034 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1035 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1036 (long)le32toh(phwr->hwr_events[i].dwTrb2),
1037 (long)le32toh(phwr->hwr_events[i].dwTrb3));
1040 case XHCI_TRB_EVENT_TRANSFER:
1041 xhci_check_transfer(sc, &phwr->hwr_events[i]);
1043 case XHCI_TRB_EVENT_CMD_COMPLETE:
1044 retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1047 DPRINTF("Unhandled event = %u\n", event);
1053 if (i == XHCI_MAX_EVENTS) {
1057 /* check for timeout */
1063 sc->sc_event_idx = i;
1064 sc->sc_event_ccs = j;
1067 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1068 * latched. That means to activate the register we need to
1069 * write both the low and high double word of the 64-bit
1073 addr = (uint32_t)buf_res.physaddr;
1074 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1076 /* try to clear busy bit */
1077 addr |= XHCI_ERDP_LO_BUSY;
1079 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1080 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1086 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1087 uint16_t timeout_ms)
1089 struct usb_page_search buf_res;
1090 struct xhci_hw_root *phwr;
1095 uint8_t timeout = 0;
1098 XHCI_CMD_ASSERT_LOCKED(sc);
1100 /* get hardware root structure */
1102 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1104 phwr = buf_res.buffer;
1108 USB_BUS_LOCK(&sc->sc_bus);
1110 i = sc->sc_command_idx;
1111 j = sc->sc_command_ccs;
1113 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1114 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1115 (long long)le64toh(trb->qwTrb0),
1116 (long)le32toh(trb->dwTrb2),
1117 (long)le32toh(trb->dwTrb3));
1119 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1120 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1122 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1127 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1129 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1131 temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1133 phwr->hwr_commands[i].dwTrb3 = temp;
1135 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1137 addr = buf_res.physaddr;
1138 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1140 sc->sc_cmd_addr = htole64(addr);
1144 if (i == (XHCI_MAX_COMMANDS - 1)) {
1147 temp = htole32(XHCI_TRB_3_TC_BIT |
1148 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1149 XHCI_TRB_3_CYCLE_BIT);
1151 temp = htole32(XHCI_TRB_3_TC_BIT |
1152 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1155 phwr->hwr_commands[i].dwTrb3 = temp;
1157 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1163 sc->sc_command_idx = i;
1164 sc->sc_command_ccs = j;
1166 XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1168 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1169 USB_MS_TO_TICKS(timeout_ms));
1172 * In some error cases event interrupts are not generated.
1173 * Poll one time to see if the command has completed.
1175 if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1176 DPRINTF("Command was completed when polling\n");
1180 DPRINTF("Command timeout!\n");
1182 * After some weeks of continuous operation, it has
1183 * been observed that the ASMedia Technology, ASM1042
1184 * SuperSpeed USB Host Controller can suddenly stop
1185 * accepting commands via the command queue. Try to
1186 * first reset the command queue. If that fails do a
1187 * host controller reset.
1190 xhci_reset_command_queue_locked(sc) == 0) {
1191 temp = le32toh(trb->dwTrb3);
1194 * Avoid infinite XHCI reset loops if the set
1195 * address command fails to respond due to a
1196 * non-enumerating device:
1198 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE &&
1199 (temp & XHCI_TRB_3_BSR_BIT) == 0) {
1200 DPRINTF("Set address timeout\n");
1206 DPRINTF("Controller reset!\n");
1207 usb_bus_reset_async_locked(&sc->sc_bus);
1209 err = USB_ERR_TIMEOUT;
1213 temp = le32toh(sc->sc_cmd_result[0]);
1214 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1215 err = USB_ERR_IOERROR;
1217 trb->dwTrb2 = sc->sc_cmd_result[0];
1218 trb->dwTrb3 = sc->sc_cmd_result[1];
1221 USB_BUS_UNLOCK(&sc->sc_bus);
1228 xhci_cmd_nop(struct xhci_softc *sc)
1230 struct xhci_trb trb;
1237 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1239 trb.dwTrb3 = htole32(temp);
1241 return (xhci_do_command(sc, &trb, 100 /* ms */));
1246 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1248 struct xhci_trb trb;
1256 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1258 err = xhci_do_command(sc, &trb, 100 /* ms */);
1262 temp = le32toh(trb.dwTrb3);
1264 *pslot = XHCI_TRB_3_SLOT_GET(temp);
1271 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1273 struct xhci_trb trb;
1280 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1281 XHCI_TRB_3_SLOT_SET(slot_id);
1283 trb.dwTrb3 = htole32(temp);
1285 return (xhci_do_command(sc, &trb, 100 /* ms */));
1289 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1290 uint8_t bsr, uint8_t slot_id)
1292 struct xhci_trb trb;
1297 trb.qwTrb0 = htole64(input_ctx);
1299 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1300 XHCI_TRB_3_SLOT_SET(slot_id);
1303 temp |= XHCI_TRB_3_BSR_BIT;
1305 trb.dwTrb3 = htole32(temp);
1307 return (xhci_do_command(sc, &trb, 500 /* ms */));
1311 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1313 struct usb_page_search buf_inp;
1314 struct usb_page_search buf_dev;
1315 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1316 struct xhci_hw_dev *hdev;
1317 struct xhci_dev_ctx *pdev;
1318 struct xhci_endpoint_ext *pepext;
1324 /* the root HUB case is not handled here */
1325 if (udev->parent_hub == NULL)
1326 return (USB_ERR_INVAL);
1328 index = udev->controller_slot_id;
1330 hdev = &sc->sc_hw.devs[index];
1337 switch (hdev->state) {
1338 case XHCI_ST_DEFAULT:
1339 case XHCI_ST_ENABLED:
1341 hdev->state = XHCI_ST_ENABLED;
1343 /* set configure mask to slot and EP0 */
1344 xhci_configure_mask(udev, 3, 0);
1346 /* configure input slot context structure */
1347 err = xhci_configure_device(udev);
1350 DPRINTF("Could not configure device\n");
1354 /* configure input endpoint context structure */
1355 switch (udev->speed) {
1357 case USB_SPEED_FULL:
1360 case USB_SPEED_HIGH:
1368 pepext = xhci_get_endpoint_ext(udev,
1369 &udev->ctrl_ep_desc);
1370 err = xhci_configure_endpoint(udev,
1371 &udev->ctrl_ep_desc, pepext->physaddr,
1372 0, 1, 1, 0, mps, mps);
1375 DPRINTF("Could not configure default endpoint\n");
1379 /* execute set address command */
1380 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1382 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1383 (address == 0), index);
1386 temp = le32toh(sc->sc_cmd_result[0]);
1387 if (address == 0 && sc->sc_port_route != NULL &&
1388 XHCI_TRB_2_ERROR_GET(temp) ==
1389 XHCI_TRB_ERROR_PARAMETER) {
1390 /* LynxPoint XHCI - ports are not switchable */
1391 /* Un-route all ports from the XHCI */
1392 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1394 DPRINTF("Could not set address "
1395 "for slot %u.\n", index);
1400 /* update device address to new value */
1402 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1403 pdev = buf_dev.buffer;
1404 usb_pc_cpu_invalidate(&hdev->device_pc);
1406 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1407 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1409 /* update device state to new value */
1412 hdev->state = XHCI_ST_ADDRESSED;
1414 hdev->state = XHCI_ST_DEFAULT;
1418 DPRINTF("Wrong state for set address.\n");
1419 err = USB_ERR_IOERROR;
1422 XHCI_CMD_UNLOCK(sc);
1431 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1432 uint8_t deconfigure, uint8_t slot_id)
1434 struct xhci_trb trb;
1439 trb.qwTrb0 = htole64(input_ctx);
1441 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1442 XHCI_TRB_3_SLOT_SET(slot_id);
1445 temp |= XHCI_TRB_3_DCEP_BIT;
1447 trb.dwTrb3 = htole32(temp);
1449 return (xhci_do_command(sc, &trb, 100 /* ms */));
1453 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1456 struct xhci_trb trb;
1461 trb.qwTrb0 = htole64(input_ctx);
1463 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1464 XHCI_TRB_3_SLOT_SET(slot_id);
1465 trb.dwTrb3 = htole32(temp);
1467 return (xhci_do_command(sc, &trb, 100 /* ms */));
1471 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1472 uint8_t ep_id, uint8_t slot_id)
1474 struct xhci_trb trb;
1481 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1482 XHCI_TRB_3_SLOT_SET(slot_id) |
1483 XHCI_TRB_3_EP_SET(ep_id);
1486 temp |= XHCI_TRB_3_PRSV_BIT;
1488 trb.dwTrb3 = htole32(temp);
1490 return (xhci_do_command(sc, &trb, 100 /* ms */));
1494 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1495 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1497 struct xhci_trb trb;
1502 trb.qwTrb0 = htole64(dequeue_ptr);
1504 temp = XHCI_TRB_2_STREAM_SET(stream_id);
1505 trb.dwTrb2 = htole32(temp);
1507 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1508 XHCI_TRB_3_SLOT_SET(slot_id) |
1509 XHCI_TRB_3_EP_SET(ep_id);
1510 trb.dwTrb3 = htole32(temp);
1512 return (xhci_do_command(sc, &trb, 100 /* ms */));
1516 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1517 uint8_t ep_id, uint8_t slot_id)
1519 struct xhci_trb trb;
1526 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1527 XHCI_TRB_3_SLOT_SET(slot_id) |
1528 XHCI_TRB_3_EP_SET(ep_id);
1531 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1533 trb.dwTrb3 = htole32(temp);
1535 return (xhci_do_command(sc, &trb, 100 /* ms */));
1539 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1541 struct xhci_trb trb;
1548 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1549 XHCI_TRB_3_SLOT_SET(slot_id);
1551 trb.dwTrb3 = htole32(temp);
1553 return (xhci_do_command(sc, &trb, 100 /* ms */));
1556 /*------------------------------------------------------------------------*
1557 * xhci_interrupt - XHCI interrupt handler
1558 *------------------------------------------------------------------------*/
1560 xhci_interrupt(struct xhci_softc *sc)
1565 USB_BUS_LOCK(&sc->sc_bus);
1567 status = XREAD4(sc, oper, XHCI_USBSTS);
1569 /* acknowledge interrupts, if any */
1571 XWRITE4(sc, oper, XHCI_USBSTS, status);
1572 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1575 temp = XREAD4(sc, runt, XHCI_IMAN(0));
1577 /* force clearing of pending interrupts */
1578 if (temp & XHCI_IMAN_INTR_PEND)
1579 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1581 /* check for event(s) */
1582 xhci_interrupt_poll(sc);
1584 if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1585 XHCI_STS_HSE | XHCI_STS_HCE)) {
1587 if (status & XHCI_STS_PCD) {
1591 if (status & XHCI_STS_HCH) {
1592 printf("%s: host controller halted\n",
1596 if (status & XHCI_STS_HSE) {
1597 printf("%s: host system error\n",
1601 if (status & XHCI_STS_HCE) {
1602 printf("%s: host controller error\n",
1606 USB_BUS_UNLOCK(&sc->sc_bus);
1609 /*------------------------------------------------------------------------*
1610 * xhci_timeout - XHCI timeout handler
1611 *------------------------------------------------------------------------*/
1613 xhci_timeout(void *arg)
1615 struct usb_xfer *xfer = arg;
1617 DPRINTF("xfer=%p\n", xfer);
1619 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1621 /* transfer is transferred */
1622 xhci_device_done(xfer, USB_ERR_TIMEOUT);
1626 xhci_do_poll(struct usb_bus *bus)
1628 struct xhci_softc *sc = XHCI_BUS2SC(bus);
1630 USB_BUS_LOCK(&sc->sc_bus);
1631 xhci_interrupt_poll(sc);
1632 USB_BUS_UNLOCK(&sc->sc_bus);
1636 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1638 struct usb_page_search buf_res;
1640 struct xhci_td *td_next;
1641 struct xhci_td *td_alt_next;
1642 struct xhci_td *td_first;
1643 uint32_t buf_offset;
1648 uint8_t shortpkt_old;
1654 shortpkt_old = temp->shortpkt;
1655 len_old = temp->len;
1662 td_next = td_first = temp->td_next;
1666 if (temp->len == 0) {
1671 /* send a Zero Length Packet, ZLP, last */
1678 average = temp->average;
1680 if (temp->len < average) {
1681 if (temp->len % temp->max_packet_size) {
1684 average = temp->len;
1688 if (td_next == NULL)
1689 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1694 td_next = td->obj_next;
1696 /* check if we are pre-computing */
1700 /* update remaining length */
1702 temp->len -= average;
1706 /* fill out current TD */
1712 /* update remaining length */
1714 temp->len -= average;
1716 /* reset TRB index */
1720 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1721 /* immediate data */
1726 td->td_trb[0].qwTrb0 = 0;
1728 usbd_copy_out(temp->pc, temp->offset + buf_offset,
1729 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1732 dword = XHCI_TRB_2_BYTES_SET(8) |
1733 XHCI_TRB_2_TDSZ_SET(0) |
1734 XHCI_TRB_2_IRQ_SET(0);
1736 td->td_trb[0].dwTrb2 = htole32(dword);
1738 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1739 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1742 if (td->td_trb[0].qwTrb0 &
1743 htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1744 if (td->td_trb[0].qwTrb0 &
1745 htole64(XHCI_TRB_0_DIR_IN_MASK))
1746 dword |= XHCI_TRB_3_TRT_IN;
1748 dword |= XHCI_TRB_3_TRT_OUT;
1751 td->td_trb[0].dwTrb3 = htole32(dword);
1753 xhci_dump_trb(&td->td_trb[x]);
1761 /* fill out buffer pointers */
1764 memset(&buf_res, 0, sizeof(buf_res));
1766 usbd_get_page(temp->pc, temp->offset +
1767 buf_offset, &buf_res);
1769 /* get length to end of page */
1770 if (buf_res.length > average)
1771 buf_res.length = average;
1773 /* check for maximum length */
1774 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1775 buf_res.length = XHCI_TD_PAGE_SIZE;
1777 npkt_off += buf_res.length;
1781 npkt = (len_old - npkt_off + temp->max_packet_size - 1) /
1782 temp->max_packet_size;
1789 /* fill out TRB's */
1790 td->td_trb[x].qwTrb0 =
1791 htole64((uint64_t)buf_res.physaddr);
1794 XHCI_TRB_2_BYTES_SET(buf_res.length) |
1795 XHCI_TRB_2_TDSZ_SET(npkt) |
1796 XHCI_TRB_2_IRQ_SET(0);
1798 td->td_trb[x].dwTrb2 = htole32(dword);
1800 switch (temp->trb_type) {
1801 case XHCI_TRB_TYPE_ISOCH:
1802 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1803 XHCI_TRB_3_TBC_SET(temp->tbc) |
1804 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1805 if (td != td_first) {
1806 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1807 } else if (temp->do_isoc_sync != 0) {
1808 temp->do_isoc_sync = 0;
1809 /* wait until "isoc_frame" */
1810 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1811 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1813 /* start data transfer at next interval */
1814 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1815 XHCI_TRB_3_ISO_SIA_BIT;
1817 if (temp->direction == UE_DIR_IN)
1818 dword |= XHCI_TRB_3_ISP_BIT;
1820 case XHCI_TRB_TYPE_DATA_STAGE:
1821 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1822 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE);
1823 if (temp->direction == UE_DIR_IN)
1824 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1826 case XHCI_TRB_TYPE_STATUS_STAGE:
1827 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1828 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE);
1829 if (temp->direction == UE_DIR_IN)
1830 dword |= XHCI_TRB_3_DIR_IN;
1832 default: /* XHCI_TRB_TYPE_NORMAL */
1833 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1834 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1835 if (temp->direction == UE_DIR_IN)
1836 dword |= XHCI_TRB_3_ISP_BIT;
1839 td->td_trb[x].dwTrb3 = htole32(dword);
1841 average -= buf_res.length;
1842 buf_offset += buf_res.length;
1844 xhci_dump_trb(&td->td_trb[x]);
1848 } while (average != 0);
1850 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1852 /* store number of data TRB's */
1856 DPRINTF("NTRB=%u\n", x);
1858 /* fill out link TRB */
1860 if (td_next != NULL) {
1861 /* link the current TD with the next one */
1862 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1863 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1865 /* this field will get updated later */
1866 DPRINTF("NOLINK\n");
1869 dword = XHCI_TRB_2_IRQ_SET(0);
1871 td->td_trb[x].dwTrb2 = htole32(dword);
1873 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1874 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1876 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1877 * frame only receives a single short packet event
1878 * by setting the CHAIN bit in the LINK field. In
1879 * addition some XHCI controllers have problems
1880 * sending a ZLP unless the CHAIN-BIT is set in
1883 XHCI_TRB_3_CHAIN_BIT;
1885 td->td_trb[x].dwTrb3 = htole32(dword);
1887 td->alt_next = td_alt_next;
1889 xhci_dump_trb(&td->td_trb[x]);
1891 usb_pc_cpu_flush(td->page_cache);
1897 /* setup alt next pointer, if any */
1898 if (temp->last_frame) {
1901 /* we use this field internally */
1902 td_alt_next = td_next;
1906 temp->shortpkt = shortpkt_old;
1907 temp->len = len_old;
1912 * Remove cycle bit from the first TRB if we are
1915 if (temp->step_td != 0) {
1916 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1917 usb_pc_cpu_flush(td_first->page_cache);
1920 /* clear TD SIZE to zero, hence this is the last TRB */
1921 /* remove chain bit because this is the last data TRB in the chain */
1922 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1923 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1924 /* remove CHAIN-BIT from last LINK TRB */
1925 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1927 usb_pc_cpu_flush(td->page_cache);
1930 temp->td_next = td_next;
1934 xhci_setup_generic_chain(struct usb_xfer *xfer)
1936 struct xhci_std_temp temp;
1942 temp.do_isoc_sync = 0;
1946 temp.average = xfer->max_hc_frame_size;
1947 temp.max_packet_size = xfer->max_packet_size;
1948 temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
1950 temp.last_frame = 0;
1952 temp.multishort = xfer->flags_int.isochronous_xfr ||
1953 xfer->flags_int.control_xfr ||
1954 xfer->flags_int.short_frames_ok;
1956 /* toggle the DMA set we are using */
1957 xfer->flags_int.curr_dma_set ^= 1;
1959 /* get next DMA set */
1960 td = xfer->td_start[xfer->flags_int.curr_dma_set];
1965 xfer->td_transfer_first = td;
1966 xfer->td_transfer_cache = td;
1968 if (xfer->flags_int.isochronous_xfr) {
1971 /* compute multiplier for ISOCHRONOUS transfers */
1972 mult = xfer->endpoint->ecomp ?
1973 (xfer->endpoint->ecomp->bmAttributes & 3) : 0;
1974 /* check for USB 2.0 multiplier */
1976 mult = (xfer->endpoint->edesc->
1977 wMaxPacketSize[1] >> 3) & 3;
1985 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
1987 DPRINTF("MFINDEX=0x%08x\n", x);
1989 switch (usbd_get_speed(xfer->xroot->udev)) {
1990 case USB_SPEED_FULL:
1992 temp.isoc_delta = 8; /* 1ms */
1993 x += temp.isoc_delta - 1;
1994 x &= ~(temp.isoc_delta - 1);
1997 shift = usbd_xfer_get_fps_shift(xfer);
1998 temp.isoc_delta = 1U << shift;
1999 x += temp.isoc_delta - 1;
2000 x &= ~(temp.isoc_delta - 1);
2001 /* simple frame load balancing */
2002 x += xfer->endpoint->usb_uframe;
2006 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
2008 if ((xfer->endpoint->is_synced == 0) ||
2009 (y < (xfer->nframes << shift)) ||
2010 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
2012 * If there is data underflow or the pipe
2013 * queue is empty we schedule the transfer a
2014 * few frames ahead of the current frame
2015 * position. Else two isochronous transfers
2018 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2019 xfer->endpoint->is_synced = 1;
2020 temp.do_isoc_sync = 1;
2022 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2025 /* compute isochronous completion time */
2027 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2029 xfer->isoc_time_complete =
2030 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2031 (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2034 temp.isoc_frame = xfer->endpoint->isoc_next;
2035 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2037 xfer->endpoint->isoc_next += xfer->nframes << shift;
2039 } else if (xfer->flags_int.control_xfr) {
2041 /* check if we should prepend a setup message */
2043 if (xfer->flags_int.control_hdr) {
2045 temp.len = xfer->frlengths[0];
2046 temp.pc = xfer->frbuffers + 0;
2047 temp.shortpkt = temp.len ? 1 : 0;
2048 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2051 /* check for last frame */
2052 if (xfer->nframes == 1) {
2053 /* no STATUS stage yet, SETUP is last */
2054 if (xfer->flags_int.control_act)
2055 temp.last_frame = 1;
2058 xhci_setup_generic_chain_sub(&temp);
2062 temp.isoc_delta = 0;
2063 temp.isoc_frame = 0;
2064 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE;
2068 temp.isoc_delta = 0;
2069 temp.isoc_frame = 0;
2070 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2073 if (x != xfer->nframes) {
2074 /* setup page_cache pointer */
2075 temp.pc = xfer->frbuffers + x;
2076 /* set endpoint direction */
2077 temp.direction = UE_GET_DIR(xfer->endpointno);
2080 while (x != xfer->nframes) {
2082 /* DATA0 / DATA1 message */
2084 temp.len = xfer->frlengths[x];
2085 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2086 x != 0 && temp.multishort == 0);
2090 if (x == xfer->nframes) {
2091 if (xfer->flags_int.control_xfr) {
2092 /* no STATUS stage yet, DATA is last */
2093 if (xfer->flags_int.control_act)
2094 temp.last_frame = 1;
2096 temp.last_frame = 1;
2099 if (temp.len == 0) {
2101 /* make sure that we send an USB packet */
2106 temp.tlbpc = mult - 1;
2108 } else if (xfer->flags_int.isochronous_xfr) {
2113 * Isochronous transfers don't have short
2114 * packet termination:
2119 /* isochronous transfers have a transfer limit */
2121 if (temp.len > xfer->max_frame_size)
2122 temp.len = xfer->max_frame_size;
2124 /* compute TD packet count */
2125 tdpc = (temp.len + xfer->max_packet_size - 1) /
2126 xfer->max_packet_size;
2128 temp.tbc = ((tdpc + mult - 1) / mult) - 1;
2129 temp.tlbpc = (tdpc % mult);
2131 if (temp.tlbpc == 0)
2132 temp.tlbpc = mult - 1;
2137 /* regular data transfer */
2139 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2142 xhci_setup_generic_chain_sub(&temp);
2144 if (xfer->flags_int.isochronous_xfr) {
2145 temp.offset += xfer->frlengths[x - 1];
2146 temp.isoc_frame += temp.isoc_delta;
2148 /* get next Page Cache pointer */
2149 temp.pc = xfer->frbuffers + x;
2153 /* check if we should append a status stage */
2155 if (xfer->flags_int.control_xfr &&
2156 !xfer->flags_int.control_act) {
2159 * Send a DATA1 message and invert the current
2160 * endpoint direction.
2162 temp.step_td = (xfer->nframes != 0);
2163 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2167 temp.last_frame = 1;
2168 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2170 xhci_setup_generic_chain_sub(&temp);
2175 /* must have at least one frame! */
2177 xfer->td_transfer_last = td;
2179 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2183 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2185 struct usb_page_search buf_res;
2186 struct xhci_dev_ctx_addr *pdctxa;
2188 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2190 pdctxa = buf_res.buffer;
2192 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2194 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2196 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2200 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2202 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2203 struct usb_page_search buf_inp;
2204 struct xhci_input_dev_ctx *pinp;
2209 index = udev->controller_slot_id;
2211 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2213 pinp = buf_inp.buffer;
2216 mask &= XHCI_INCTX_NON_CTRL_MASK;
2217 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2218 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2221 * Some hardware requires that we drop the endpoint
2222 * context before adding it again:
2224 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0,
2225 mask & XHCI_INCTX_NON_CTRL_MASK);
2227 /* Add new endpoint context */
2228 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2230 /* find most significant set bit */
2231 for (x = 31; x != 1; x--) {
2232 if (mask & (1 << x))
2239 /* figure out maximum */
2240 if (x > sc->sc_hw.devs[index].context_num) {
2241 sc->sc_hw.devs[index].context_num = x;
2242 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2243 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2244 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2245 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2252 xhci_configure_endpoint(struct usb_device *udev,
2253 struct usb_endpoint_descriptor *edesc, uint64_t ring_addr,
2254 uint16_t interval, uint8_t max_packet_count, uint8_t mult,
2255 uint8_t fps_shift, uint16_t max_packet_size, uint16_t max_frame_size)
2257 struct usb_page_search buf_inp;
2258 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2259 struct xhci_input_dev_ctx *pinp;
2265 index = udev->controller_slot_id;
2267 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2269 pinp = buf_inp.buffer;
2271 epno = edesc->bEndpointAddress;
2272 type = edesc->bmAttributes & UE_XFERTYPE;
2274 if (type == UE_CONTROL)
2277 epno = XHCI_EPNO2EPID(epno);
2280 return (USB_ERR_NO_PIPE); /* invalid */
2282 if (max_packet_count == 0)
2283 return (USB_ERR_BAD_BUFSIZE);
2288 return (USB_ERR_BAD_BUFSIZE);
2290 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2291 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2292 XHCI_EPCTX_0_LSA_SET(0);
2294 switch (udev->speed) {
2295 case USB_SPEED_FULL:
2308 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2310 case UE_ISOCHRONOUS:
2311 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2313 switch (udev->speed) {
2314 case USB_SPEED_SUPER:
2317 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2318 max_packet_count /= mult;
2328 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2331 XHCI_EPCTX_1_HID_SET(0) |
2332 XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2333 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2335 if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) {
2336 if (type != UE_ISOCHRONOUS)
2337 temp |= XHCI_EPCTX_1_CERR_SET(3);
2342 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2344 case UE_ISOCHRONOUS:
2345 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2348 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2351 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2355 /* check for IN direction */
2357 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2359 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2361 ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2363 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2365 switch (edesc->bmAttributes & UE_XFERTYPE) {
2367 case UE_ISOCHRONOUS:
2368 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2369 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2373 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2376 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2380 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2383 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2385 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2387 return (0); /* success */
2391 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2393 struct xhci_endpoint_ext *pepext;
2394 struct usb_endpoint_ss_comp_descriptor *ecomp;
2396 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2397 xfer->endpoint->edesc);
2399 ecomp = xfer->endpoint->ecomp;
2401 pepext->trb[0].dwTrb3 = 0; /* halt any transfers */
2402 usb_pc_cpu_flush(pepext->page_cache);
2404 return (xhci_configure_endpoint(xfer->xroot->udev,
2405 xfer->endpoint->edesc, pepext->physaddr,
2406 xfer->interval, xfer->max_packet_count,
2407 (ecomp != NULL) ? (ecomp->bmAttributes & 3) + 1 : 1,
2408 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2409 xfer->max_frame_size));
2413 xhci_configure_device(struct usb_device *udev)
2415 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2416 struct usb_page_search buf_inp;
2417 struct usb_page_cache *pcinp;
2418 struct xhci_input_dev_ctx *pinp;
2419 struct usb_device *hubdev;
2427 index = udev->controller_slot_id;
2429 DPRINTF("index=%u\n", index);
2431 pcinp = &sc->sc_hw.devs[index].input_pc;
2433 usbd_get_page(pcinp, 0, &buf_inp);
2435 pinp = buf_inp.buffer;
2440 /* figure out route string and root HUB port number */
2442 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2444 if (hubdev->parent_hub == NULL)
2447 depth = hubdev->parent_hub->depth;
2450 * NOTE: HS/FS/LS devices and the SS root HUB can have
2451 * more than 15 ports
2454 rh_port = hubdev->port_no;
2463 route |= rh_port << (4 * (depth - 1));
2466 DPRINTF("Route=0x%08x\n", route);
2468 temp = XHCI_SCTX_0_ROUTE_SET(route) |
2469 XHCI_SCTX_0_CTX_NUM_SET(
2470 sc->sc_hw.devs[index].context_num + 1);
2472 switch (udev->speed) {
2474 temp |= XHCI_SCTX_0_SPEED_SET(2);
2475 if (udev->parent_hs_hub != NULL &&
2476 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2478 DPRINTF("Device inherits MTT\n");
2479 temp |= XHCI_SCTX_0_MTT_SET(1);
2482 case USB_SPEED_HIGH:
2483 temp |= XHCI_SCTX_0_SPEED_SET(3);
2484 if (sc->sc_hw.devs[index].nports != 0 &&
2485 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2486 DPRINTF("HUB supports MTT\n");
2487 temp |= XHCI_SCTX_0_MTT_SET(1);
2490 case USB_SPEED_FULL:
2491 temp |= XHCI_SCTX_0_SPEED_SET(1);
2492 if (udev->parent_hs_hub != NULL &&
2493 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2495 DPRINTF("Device inherits MTT\n");
2496 temp |= XHCI_SCTX_0_MTT_SET(1);
2500 temp |= XHCI_SCTX_0_SPEED_SET(4);
2504 is_hub = sc->sc_hw.devs[index].nports != 0 &&
2505 (udev->speed == USB_SPEED_SUPER ||
2506 udev->speed == USB_SPEED_HIGH);
2509 temp |= XHCI_SCTX_0_HUB_SET(1);
2511 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2513 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2516 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2517 sc->sc_hw.devs[index].nports);
2520 switch (udev->speed) {
2521 case USB_SPEED_SUPER:
2522 switch (sc->sc_hw.devs[index].state) {
2523 case XHCI_ST_ADDRESSED:
2524 case XHCI_ST_CONFIGURED:
2525 /* enable power save */
2526 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2529 /* disable power save */
2537 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2539 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2542 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2543 sc->sc_hw.devs[index].tt);
2546 hubdev = udev->parent_hs_hub;
2548 /* check if we should activate the transaction translator */
2549 switch (udev->speed) {
2550 case USB_SPEED_FULL:
2552 if (hubdev != NULL) {
2553 temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2554 hubdev->controller_slot_id);
2555 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2563 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2566 * These fields should be initialized to zero, according to
2567 * XHCI section 6.2.2 - slot context:
2569 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2570 XHCI_SCTX_3_SLOT_STATE_SET(0);
2572 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2575 xhci_dump_device(sc, &pinp->ctx_slot);
2577 usb_pc_cpu_flush(pcinp);
2579 return (0); /* success */
2583 xhci_alloc_device_ext(struct usb_device *udev)
2585 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2586 struct usb_page_search buf_dev;
2587 struct usb_page_search buf_ep;
2588 struct xhci_trb *trb;
2589 struct usb_page_cache *pc;
2590 struct usb_page *pg;
2595 index = udev->controller_slot_id;
2597 pc = &sc->sc_hw.devs[index].device_pc;
2598 pg = &sc->sc_hw.devs[index].device_pg;
2600 /* need to initialize the page cache */
2601 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2603 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2604 (2 * sizeof(struct xhci_dev_ctx)) :
2605 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2608 usbd_get_page(pc, 0, &buf_dev);
2610 pc = &sc->sc_hw.devs[index].input_pc;
2611 pg = &sc->sc_hw.devs[index].input_pg;
2613 /* need to initialize the page cache */
2614 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2616 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2617 (2 * sizeof(struct xhci_input_dev_ctx)) :
2618 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2622 pc = &sc->sc_hw.devs[index].endpoint_pc;
2623 pg = &sc->sc_hw.devs[index].endpoint_pg;
2625 /* need to initialize the page cache */
2626 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2628 if (usb_pc_alloc_mem(pc, pg,
2629 sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) {
2633 /* initialise all endpoint LINK TRBs */
2635 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2637 /* lookup endpoint TRB ring */
2638 usbd_get_page(pc, (uintptr_t)&
2639 ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep);
2641 /* get TRB pointer */
2642 trb = buf_ep.buffer;
2643 trb += XHCI_MAX_TRANSFERS - 1;
2645 /* get TRB start address */
2646 addr = buf_ep.physaddr;
2648 /* create LINK TRB */
2649 trb->qwTrb0 = htole64(addr);
2650 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2651 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2652 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2655 usb_pc_cpu_flush(pc);
2657 xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2662 xhci_free_device_ext(udev);
2664 return (USB_ERR_NOMEM);
2668 xhci_free_device_ext(struct usb_device *udev)
2670 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2673 index = udev->controller_slot_id;
2674 xhci_set_slot_pointer(sc, index, 0);
2676 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2677 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2678 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc);
2681 static struct xhci_endpoint_ext *
2682 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2684 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2685 struct xhci_endpoint_ext *pepext;
2686 struct usb_page_cache *pc;
2687 struct usb_page_search buf_ep;
2691 epno = edesc->bEndpointAddress;
2692 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2695 epno = XHCI_EPNO2EPID(epno);
2697 index = udev->controller_slot_id;
2699 pc = &sc->sc_hw.devs[index].endpoint_pc;
2701 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->trb[epno][0], &buf_ep);
2703 pepext = &sc->sc_hw.devs[index].endp[epno];
2704 pepext->page_cache = pc;
2705 pepext->trb = buf_ep.buffer;
2706 pepext->physaddr = buf_ep.physaddr;
2712 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2714 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2718 epno = xfer->endpointno;
2719 if (xfer->flags_int.control_xfr)
2722 epno = XHCI_EPNO2EPID(epno);
2723 index = xfer->xroot->udev->controller_slot_id;
2725 if (xfer->xroot->udev->flags.self_suspended == 0) {
2726 XWRITE4(sc, door, XHCI_DOORBELL(index),
2727 epno | XHCI_DB_SID_SET(/*xfer->stream_id*/ 0));
2732 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2734 struct xhci_endpoint_ext *pepext;
2736 if (xfer->flags_int.bandwidth_reclaimed) {
2737 xfer->flags_int.bandwidth_reclaimed = 0;
2739 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2740 xfer->endpoint->edesc);
2744 pepext->xfer[xfer->qh_pos] = NULL;
2746 if (error && pepext->trb_running != 0) {
2747 pepext->trb_halted = 1;
2748 pepext->trb_running = 0;
2754 xhci_transfer_insert(struct usb_xfer *xfer)
2756 struct xhci_td *td_first;
2757 struct xhci_td *td_last;
2758 struct xhci_trb *trb_link;
2759 struct xhci_endpoint_ext *pepext;
2767 /* check if already inserted */
2768 if (xfer->flags_int.bandwidth_reclaimed) {
2769 DPRINTFN(8, "Already in schedule\n");
2773 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2774 xfer->endpoint->edesc);
2776 td_first = xfer->td_transfer_first;
2777 td_last = xfer->td_transfer_last;
2778 addr = pepext->physaddr;
2780 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2783 /* single buffered */
2787 /* multi buffered */
2788 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2792 if (pepext->trb_used >= trb_limit) {
2793 DPRINTFN(8, "Too many TDs queued.\n");
2794 return (USB_ERR_NOMEM);
2797 /* check for stopped condition, after putting transfer on interrupt queue */
2798 if (pepext->trb_running == 0) {
2799 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2801 DPRINTFN(8, "Not running\n");
2803 /* start configuration */
2804 (void)usb_proc_msignal(&sc->sc_config_proc,
2805 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2811 /* get current TRB index */
2812 i = pepext->trb_index;
2814 /* get next TRB index */
2817 /* the last entry of the ring is a hardcoded link TRB */
2818 if (inext >= (XHCI_MAX_TRANSFERS - 1))
2821 /* compute terminating return address */
2822 addr += inext * sizeof(struct xhci_trb);
2824 /* compute link TRB pointer */
2825 trb_link = td_last->td_trb + td_last->ntrb;
2827 /* update next pointer of last link TRB */
2828 trb_link->qwTrb0 = htole64(addr);
2829 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2830 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2831 XHCI_TRB_3_CYCLE_BIT |
2832 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2835 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2837 usb_pc_cpu_flush(td_last->page_cache);
2839 /* write ahead chain end marker */
2841 pepext->trb[inext].qwTrb0 = 0;
2842 pepext->trb[inext].dwTrb2 = 0;
2843 pepext->trb[inext].dwTrb3 = 0;
2845 /* update next pointer of link TRB */
2847 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2848 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2851 xhci_dump_trb(&pepext->trb[i]);
2853 usb_pc_cpu_flush(pepext->page_cache);
2855 /* toggle cycle bit which activates the transfer chain */
2857 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2858 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2860 usb_pc_cpu_flush(pepext->page_cache);
2862 DPRINTF("qh_pos = %u\n", i);
2864 pepext->xfer[i] = xfer;
2868 xfer->flags_int.bandwidth_reclaimed = 1;
2870 pepext->trb_index = inext;
2872 xhci_endpoint_doorbell(xfer);
2878 xhci_root_intr(struct xhci_softc *sc)
2882 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2884 /* clear any old interrupt data */
2885 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2887 for (i = 1; i <= sc->sc_noport; i++) {
2888 /* pick out CHANGE bits from the status register */
2889 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
2890 XHCI_PS_CSC | XHCI_PS_PEC |
2891 XHCI_PS_OCC | XHCI_PS_WRC |
2892 XHCI_PS_PRC | XHCI_PS_PLC |
2894 sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2895 DPRINTF("port %d changed\n", i);
2898 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2899 sizeof(sc->sc_hub_idata));
2902 /*------------------------------------------------------------------------*
2903 * xhci_device_done - XHCI done handler
2905 * NOTE: This function can be called two times in a row on
2906 * the same USB transfer. From close and from interrupt.
2907 *------------------------------------------------------------------------*/
2909 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
2911 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2912 xfer, xfer->endpoint, error);
2914 /* remove transfer from HW queue */
2915 xhci_transfer_remove(xfer, error);
2917 /* dequeue transfer and start next transfer */
2918 usbd_transfer_done(xfer, error);
2921 /*------------------------------------------------------------------------*
2922 * XHCI data transfer support (generic type)
2923 *------------------------------------------------------------------------*/
2925 xhci_device_generic_open(struct usb_xfer *xfer)
2927 if (xfer->flags_int.isochronous_xfr) {
2928 switch (xfer->xroot->udev->speed) {
2929 case USB_SPEED_FULL:
2932 usb_hs_bandwidth_alloc(xfer);
2939 xhci_device_generic_close(struct usb_xfer *xfer)
2943 xhci_device_done(xfer, USB_ERR_CANCELLED);
2945 if (xfer->flags_int.isochronous_xfr) {
2946 switch (xfer->xroot->udev->speed) {
2947 case USB_SPEED_FULL:
2950 usb_hs_bandwidth_free(xfer);
2957 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
2958 struct usb_xfer *enter_xfer)
2960 struct usb_xfer *xfer;
2962 /* check if there is a current transfer */
2963 xfer = ep->endpoint_q.curr;
2968 * Check if the current transfer is started and then pickup
2969 * the next one, if any. Else wait for next start event due to
2970 * block on failure feature.
2972 if (!xfer->flags_int.bandwidth_reclaimed)
2975 xfer = TAILQ_FIRST(&ep->endpoint_q.head);
2978 * In case of enter we have to consider that the
2979 * transfer is queued by the USB core after the enter
2988 /* try to multi buffer */
2989 xhci_transfer_insert(xfer);
2993 xhci_device_generic_enter(struct usb_xfer *xfer)
2997 /* setup TD's and QH */
2998 xhci_setup_generic_chain(xfer);
3000 xhci_device_generic_multi_enter(xfer->endpoint, xfer);
3004 xhci_device_generic_start(struct usb_xfer *xfer)
3008 /* try to insert xfer on HW queue */
3009 xhci_transfer_insert(xfer);
3011 /* try to multi buffer */
3012 xhci_device_generic_multi_enter(xfer->endpoint, NULL);
3014 /* add transfer last on interrupt queue */
3015 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3017 /* start timeout, if any */
3018 if (xfer->timeout != 0)
3019 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3022 struct usb_pipe_methods xhci_device_generic_methods =
3024 .open = xhci_device_generic_open,
3025 .close = xhci_device_generic_close,
3026 .enter = xhci_device_generic_enter,
3027 .start = xhci_device_generic_start,
3030 /*------------------------------------------------------------------------*
3031 * xhci root HUB support
3032 *------------------------------------------------------------------------*
3033 * Simulate a hardware HUB by handling all the necessary requests.
3034 *------------------------------------------------------------------------*/
3036 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3039 struct usb_device_descriptor xhci_devd =
3041 .bLength = sizeof(xhci_devd),
3042 .bDescriptorType = UDESC_DEVICE, /* type */
3043 HSETW(.bcdUSB, 0x0300), /* USB version */
3044 .bDeviceClass = UDCLASS_HUB, /* class */
3045 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */
3046 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */
3047 .bMaxPacketSize = 9, /* max packet size */
3048 HSETW(.idVendor, 0x0000), /* vendor */
3049 HSETW(.idProduct, 0x0000), /* product */
3050 HSETW(.bcdDevice, 0x0100), /* device version */
3054 .bNumConfigurations = 1, /* # of configurations */
3058 struct xhci_bos_desc xhci_bosd = {
3060 .bLength = sizeof(xhci_bosd.bosd),
3061 .bDescriptorType = UDESC_BOS,
3062 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3063 .bNumDeviceCaps = 3,
3066 .bLength = sizeof(xhci_bosd.usb2extd),
3067 .bDescriptorType = 1,
3068 .bDevCapabilityType = 2,
3069 .bmAttributes[0] = 2,
3072 .bLength = sizeof(xhci_bosd.usbdcd),
3073 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3074 .bDevCapabilityType = 3,
3075 .bmAttributes = 0, /* XXX */
3076 HSETW(.wSpeedsSupported, 0x000C),
3077 .bFunctionalitySupport = 8,
3078 .bU1DevExitLat = 255, /* dummy - not used */
3079 .wU2DevExitLat = { 0x00, 0x08 },
3082 .bLength = sizeof(xhci_bosd.cidd),
3083 .bDescriptorType = 1,
3084 .bDevCapabilityType = 4,
3086 .bContainerID = 0, /* XXX */
3091 struct xhci_config_desc xhci_confd = {
3093 .bLength = sizeof(xhci_confd.confd),
3094 .bDescriptorType = UDESC_CONFIG,
3095 .wTotalLength[0] = sizeof(xhci_confd),
3097 .bConfigurationValue = 1,
3098 .iConfiguration = 0,
3099 .bmAttributes = UC_SELF_POWERED,
3100 .bMaxPower = 0 /* max power */
3103 .bLength = sizeof(xhci_confd.ifcd),
3104 .bDescriptorType = UDESC_INTERFACE,
3106 .bInterfaceClass = UICLASS_HUB,
3107 .bInterfaceSubClass = UISUBCLASS_HUB,
3108 .bInterfaceProtocol = 0,
3111 .bLength = sizeof(xhci_confd.endpd),
3112 .bDescriptorType = UDESC_ENDPOINT,
3113 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3114 .bmAttributes = UE_INTERRUPT,
3115 .wMaxPacketSize[0] = 2, /* max 15 ports */
3119 .bLength = sizeof(xhci_confd.endpcd),
3120 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3127 struct usb_hub_ss_descriptor xhci_hubd = {
3128 .bLength = sizeof(xhci_hubd),
3129 .bDescriptorType = UDESC_SS_HUB,
3133 xhci_roothub_exec(struct usb_device *udev,
3134 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3136 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3137 const char *str_ptr;
3148 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3151 ptr = (const void *)&sc->sc_hub_desc;
3155 value = UGETW(req->wValue);
3156 index = UGETW(req->wIndex);
3158 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3159 "wValue=0x%04x wIndex=0x%04x\n",
3160 req->bmRequestType, req->bRequest,
3161 UGETW(req->wLength), value, index);
3163 #define C(x,y) ((x) | ((y) << 8))
3164 switch (C(req->bRequest, req->bmRequestType)) {
3165 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3166 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3167 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3169 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3170 * for the integrated root hub.
3173 case C(UR_GET_CONFIG, UT_READ_DEVICE):
3175 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3177 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3178 switch (value >> 8) {
3180 if ((value & 0xff) != 0) {
3181 err = USB_ERR_IOERROR;
3184 len = sizeof(xhci_devd);
3185 ptr = (const void *)&xhci_devd;
3189 if ((value & 0xff) != 0) {
3190 err = USB_ERR_IOERROR;
3193 len = sizeof(xhci_bosd);
3194 ptr = (const void *)&xhci_bosd;
3198 if ((value & 0xff) != 0) {
3199 err = USB_ERR_IOERROR;
3202 len = sizeof(xhci_confd);
3203 ptr = (const void *)&xhci_confd;
3207 switch (value & 0xff) {
3208 case 0: /* Language table */
3212 case 1: /* Vendor */
3213 str_ptr = sc->sc_vendor;
3216 case 2: /* Product */
3217 str_ptr = "XHCI root HUB";
3225 len = usb_make_str_desc(
3226 sc->sc_hub_desc.temp,
3227 sizeof(sc->sc_hub_desc.temp),
3232 err = USB_ERR_IOERROR;
3236 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3238 sc->sc_hub_desc.temp[0] = 0;
3240 case C(UR_GET_STATUS, UT_READ_DEVICE):
3242 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3244 case C(UR_GET_STATUS, UT_READ_INTERFACE):
3245 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3247 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3249 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3250 if (value >= XHCI_MAX_DEVICES) {
3251 err = USB_ERR_IOERROR;
3255 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3256 if (value != 0 && value != 1) {
3257 err = USB_ERR_IOERROR;
3260 sc->sc_conf = value;
3262 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3264 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3265 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3266 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3267 err = USB_ERR_IOERROR;
3269 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3271 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3274 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3276 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3277 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3280 (index > sc->sc_noport)) {
3281 err = USB_ERR_IOERROR;
3284 port = XHCI_PORTSC(index);
3286 v = XREAD4(sc, oper, port);
3287 i = XHCI_PS_PLS_GET(v);
3288 v &= ~XHCI_PS_CLEAR;
3291 case UHF_C_BH_PORT_RESET:
3292 XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3294 case UHF_C_PORT_CONFIG_ERROR:
3295 XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3297 case UHF_C_PORT_SUSPEND:
3298 case UHF_C_PORT_LINK_STATE:
3299 XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3301 case UHF_C_PORT_CONNECTION:
3302 XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3304 case UHF_C_PORT_ENABLE:
3305 XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3307 case UHF_C_PORT_OVER_CURRENT:
3308 XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3310 case UHF_C_PORT_RESET:
3311 XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3313 case UHF_PORT_ENABLE:
3314 XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3316 case UHF_PORT_POWER:
3317 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3319 case UHF_PORT_INDICATOR:
3320 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3322 case UHF_PORT_SUSPEND:
3326 XWRITE4(sc, oper, port, v |
3327 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3330 /* wait 20ms for resume sequence to complete */
3331 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3334 XWRITE4(sc, oper, port, v |
3335 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3338 err = USB_ERR_IOERROR;
3343 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3344 if ((value & 0xff) != 0) {
3345 err = USB_ERR_IOERROR;
3349 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3351 sc->sc_hub_desc.hubd = xhci_hubd;
3353 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3355 if (XHCI_HCS0_PPC(v))
3356 i = UHD_PWR_INDIVIDUAL;
3360 if (XHCI_HCS0_PIND(v))
3363 i |= UHD_OC_INDIVIDUAL;
3365 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3367 /* see XHCI section 5.4.9: */
3368 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3370 for (j = 1; j <= sc->sc_noport; j++) {
3372 v = XREAD4(sc, oper, XHCI_PORTSC(j));
3373 if (v & XHCI_PS_DR) {
3374 sc->sc_hub_desc.hubd.
3375 DeviceRemovable[j / 8] |= 1U << (j % 8);
3378 len = sc->sc_hub_desc.hubd.bLength;
3381 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3383 memset(sc->sc_hub_desc.temp, 0, 16);
3386 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3387 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3390 (index > sc->sc_noport)) {
3391 err = USB_ERR_IOERROR;
3395 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3397 DPRINTFN(9, "port status=0x%08x\n", v);
3399 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3401 switch (XHCI_PS_SPEED_GET(v)) {
3403 i |= UPS_HIGH_SPEED;
3412 i |= UPS_OTHER_SPEED;
3416 if (v & XHCI_PS_CCS)
3417 i |= UPS_CURRENT_CONNECT_STATUS;
3418 if (v & XHCI_PS_PED)
3419 i |= UPS_PORT_ENABLED;
3420 if (v & XHCI_PS_OCA)
3421 i |= UPS_OVERCURRENT_INDICATOR;
3424 if (v & XHCI_PS_PP) {
3426 * The USB 3.0 RH is using the
3427 * USB 2.0's power bit
3429 i |= UPS_PORT_POWER;
3431 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3434 if (v & XHCI_PS_CSC)
3435 i |= UPS_C_CONNECT_STATUS;
3436 if (v & XHCI_PS_PEC)
3437 i |= UPS_C_PORT_ENABLED;
3438 if (v & XHCI_PS_OCC)
3439 i |= UPS_C_OVERCURRENT_INDICATOR;
3440 if (v & XHCI_PS_WRC)
3441 i |= UPS_C_BH_PORT_RESET;
3442 if (v & XHCI_PS_PRC)
3443 i |= UPS_C_PORT_RESET;
3444 if (v & XHCI_PS_PLC)
3445 i |= UPS_C_PORT_LINK_STATE;
3446 if (v & XHCI_PS_CEC)
3447 i |= UPS_C_PORT_CONFIG_ERROR;
3449 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3450 len = sizeof(sc->sc_hub_desc.ps);
3453 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3454 err = USB_ERR_IOERROR;
3457 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3460 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3466 (index > sc->sc_noport)) {
3467 err = USB_ERR_IOERROR;
3471 port = XHCI_PORTSC(index);
3472 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3475 case UHF_PORT_U1_TIMEOUT:
3476 if (XHCI_PS_SPEED_GET(v) != 4) {
3477 err = USB_ERR_IOERROR;
3480 port = XHCI_PORTPMSC(index);
3481 v = XREAD4(sc, oper, port);
3482 v &= ~XHCI_PM3_U1TO_SET(0xFF);
3483 v |= XHCI_PM3_U1TO_SET(i);
3484 XWRITE4(sc, oper, port, v);
3486 case UHF_PORT_U2_TIMEOUT:
3487 if (XHCI_PS_SPEED_GET(v) != 4) {
3488 err = USB_ERR_IOERROR;
3491 port = XHCI_PORTPMSC(index);
3492 v = XREAD4(sc, oper, port);
3493 v &= ~XHCI_PM3_U2TO_SET(0xFF);
3494 v |= XHCI_PM3_U2TO_SET(i);
3495 XWRITE4(sc, oper, port, v);
3497 case UHF_BH_PORT_RESET:
3498 XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3500 case UHF_PORT_LINK_STATE:
3501 XWRITE4(sc, oper, port, v |
3502 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3503 /* 4ms settle time */
3504 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3506 case UHF_PORT_ENABLE:
3507 DPRINTFN(3, "set port enable %d\n", index);
3509 case UHF_PORT_SUSPEND:
3510 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3511 j = XHCI_PS_SPEED_GET(v);
3512 if ((j < 1) || (j > 3)) {
3513 /* non-supported speed */
3514 err = USB_ERR_IOERROR;
3517 XWRITE4(sc, oper, port, v |
3518 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3520 case UHF_PORT_RESET:
3521 DPRINTFN(6, "reset port %d\n", index);
3522 XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3524 case UHF_PORT_POWER:
3525 DPRINTFN(3, "set port power %d\n", index);
3526 XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3529 DPRINTFN(3, "set port test %d\n", index);
3531 case UHF_PORT_INDICATOR:
3532 DPRINTFN(3, "set port indicator %d\n", index);
3534 v &= ~XHCI_PS_PIC_SET(3);
3535 v |= XHCI_PS_PIC_SET(1);
3537 XWRITE4(sc, oper, port, v);
3540 err = USB_ERR_IOERROR;
3545 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3546 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3547 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3548 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3551 err = USB_ERR_IOERROR;
3561 xhci_xfer_setup(struct usb_setup_params *parm)
3563 struct usb_page_search page_info;
3564 struct usb_page_cache *pc;
3565 struct xhci_softc *sc;
3566 struct usb_xfer *xfer;
3571 sc = XHCI_BUS2SC(parm->udev->bus);
3572 xfer = parm->curr_xfer;
3575 * The proof for the "ntd" formula is illustrated like this:
3577 * +------------------------------------+
3581 * | | xxx | x | frm 0 |
3583 * | | xxx | xx | frm 1 |
3586 * +------------------------------------+
3588 * "xxx" means a completely full USB transfer descriptor
3590 * "x" and "xx" means a short USB packet
3592 * For the remainder of an USB transfer modulo
3593 * "max_data_length" we need two USB transfer descriptors.
3594 * One to transfer the remaining data and one to finalise with
3595 * a zero length packet in case the "force_short_xfer" flag is
3596 * set. We only need two USB transfer descriptors in the case
3597 * where the transfer length of the first one is a factor of
3598 * "max_frame_size". The rest of the needed USB transfer
3599 * descriptors is given by the buffer size divided by the
3600 * maximum data payload.
3602 parm->hc_max_packet_size = 0x400;
3603 parm->hc_max_packet_count = 16 * 3;
3604 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3606 xfer->flags_int.bdma_enable = 1;
3608 usbd_transfer_setup_sub(parm);
3610 if (xfer->flags_int.isochronous_xfr) {
3611 ntd = ((1 * xfer->nframes)
3612 + (xfer->max_data_length / xfer->max_hc_frame_size));
3613 } else if (xfer->flags_int.control_xfr) {
3614 ntd = ((2 * xfer->nframes) + 1 /* STATUS */
3615 + (xfer->max_data_length / xfer->max_hc_frame_size));
3617 ntd = ((2 * xfer->nframes)
3618 + (xfer->max_data_length / xfer->max_hc_frame_size));
3627 * Allocate queue heads and transfer descriptors
3631 if (usbd_transfer_setup_sub_malloc(
3632 parm, &pc, sizeof(struct xhci_td),
3633 XHCI_TD_ALIGN, ntd)) {
3634 parm->err = USB_ERR_NOMEM;
3638 for (n = 0; n != ntd; n++) {
3641 usbd_get_page(pc + n, 0, &page_info);
3643 td = page_info.buffer;
3646 td->td_self = page_info.physaddr;
3647 td->obj_next = last_obj;
3648 td->page_cache = pc + n;
3652 usb_pc_cpu_flush(pc + n);
3655 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3657 if (!xfer->flags_int.curr_dma_set) {
3658 xfer->flags_int.curr_dma_set = 1;
3664 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3666 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3667 struct usb_page_search buf_inp;
3668 struct usb_device *udev;
3669 struct xhci_endpoint_ext *pepext;
3670 struct usb_endpoint_descriptor *edesc;
3671 struct usb_page_cache *pcinp;
3676 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3677 xfer->endpoint->edesc);
3679 udev = xfer->xroot->udev;
3680 index = udev->controller_slot_id;
3682 pcinp = &sc->sc_hw.devs[index].input_pc;
3684 usbd_get_page(pcinp, 0, &buf_inp);
3686 edesc = xfer->endpoint->edesc;
3688 epno = edesc->bEndpointAddress;
3690 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3693 epno = XHCI_EPNO2EPID(epno);
3696 return (USB_ERR_NO_PIPE); /* invalid */
3700 /* configure endpoint */
3702 err = xhci_configure_endpoint_by_xfer(xfer);
3705 XHCI_CMD_UNLOCK(sc);
3710 * Get the endpoint into the stopped state according to the
3711 * endpoint context state diagram in the XHCI specification:
3714 err = xhci_cmd_stop_ep(sc, 0, epno, index);
3717 DPRINTF("Could not stop endpoint %u\n", epno);
3719 err = xhci_cmd_reset_ep(sc, 0, epno, index);
3722 DPRINTF("Could not reset endpoint %u\n", epno);
3724 err = xhci_cmd_set_tr_dequeue_ptr(sc, pepext->physaddr |
3725 XHCI_EPCTX_2_DCS_SET(1), 0, epno, index);
3728 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3731 * Get the endpoint into the running state according to the
3732 * endpoint context state diagram in the XHCI specification:
3735 xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3737 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3740 DPRINTF("Could not configure endpoint %u\n", epno);
3742 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3745 DPRINTF("Could not configure endpoint %u\n", epno);
3747 XHCI_CMD_UNLOCK(sc);
3753 xhci_xfer_unsetup(struct usb_xfer *xfer)
3759 xhci_start_dma_delay(struct usb_xfer *xfer)
3761 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3763 /* put transfer on interrupt queue (again) */
3764 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3766 (void)usb_proc_msignal(&sc->sc_config_proc,
3767 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3771 xhci_configure_msg(struct usb_proc_msg *pm)
3773 struct xhci_softc *sc;
3774 struct xhci_endpoint_ext *pepext;
3775 struct usb_xfer *xfer;
3777 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3780 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3782 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3783 xfer->endpoint->edesc);
3785 if ((pepext->trb_halted != 0) ||
3786 (pepext->trb_running == 0)) {
3790 /* clear halted and running */
3791 pepext->trb_halted = 0;
3792 pepext->trb_running = 0;
3794 /* nuke remaining buffered transfers */
3796 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
3798 * NOTE: We need to use the timeout
3799 * error code here else existing
3800 * isochronous clients can get
3803 if (pepext->xfer[i] != NULL) {
3804 xhci_device_done(pepext->xfer[i],
3810 * NOTE: The USB transfer cannot vanish in
3814 USB_BUS_UNLOCK(&sc->sc_bus);
3816 xhci_configure_reset_endpoint(xfer);
3818 USB_BUS_LOCK(&sc->sc_bus);
3820 /* check if halted is still cleared */
3821 if (pepext->trb_halted == 0) {
3822 pepext->trb_running = 1;
3823 pepext->trb_index = 0;
3828 if (xfer->flags_int.did_dma_delay) {
3830 /* remove transfer from interrupt queue (again) */
3831 usbd_transfer_dequeue(xfer);
3833 /* we are finally done */
3834 usb_dma_delay_done_cb(xfer);
3836 /* queue changed - restart */
3841 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3843 /* try to insert xfer on HW queue */
3844 xhci_transfer_insert(xfer);
3846 /* try to multi buffer */
3847 xhci_device_generic_multi_enter(xfer->endpoint, NULL);
3852 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3853 struct usb_endpoint *ep)
3855 struct xhci_endpoint_ext *pepext;
3857 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3858 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
3860 if (udev->flags.usb_mode != USB_MODE_HOST) {
3864 if (udev->parent_hub == NULL) {
3865 /* root HUB has special endpoint handling */
3869 ep->methods = &xhci_device_generic_methods;
3871 pepext = xhci_get_endpoint_ext(udev, edesc);
3873 USB_BUS_LOCK(udev->bus);
3874 pepext->trb_halted = 1;
3875 pepext->trb_running = 0;
3876 USB_BUS_UNLOCK(udev->bus);
3880 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
3886 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3888 struct xhci_endpoint_ext *pepext;
3892 if (udev->flags.usb_mode != USB_MODE_HOST) {
3896 if (udev->parent_hub == NULL) {
3897 /* root HUB has special endpoint handling */
3901 pepext = xhci_get_endpoint_ext(udev, ep->edesc);
3903 USB_BUS_LOCK(udev->bus);
3904 pepext->trb_halted = 1;
3905 pepext->trb_running = 0;
3906 USB_BUS_UNLOCK(udev->bus);
3910 xhci_device_init(struct usb_device *udev)
3912 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3916 /* no init for root HUB */
3917 if (udev->parent_hub == NULL)
3922 /* set invalid default */
3924 udev->controller_slot_id = sc->sc_noslot + 1;
3926 /* try to get a new slot ID from the XHCI */
3928 err = xhci_cmd_enable_slot(sc, &temp);
3931 XHCI_CMD_UNLOCK(sc);
3935 if (temp > sc->sc_noslot) {
3936 XHCI_CMD_UNLOCK(sc);
3937 return (USB_ERR_BAD_ADDRESS);
3940 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
3941 DPRINTF("slot %u already allocated.\n", temp);
3942 XHCI_CMD_UNLOCK(sc);
3943 return (USB_ERR_BAD_ADDRESS);
3946 /* store slot ID for later reference */
3948 udev->controller_slot_id = temp;
3950 /* reset data structure */
3952 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
3954 /* set mark slot allocated */
3956 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
3958 err = xhci_alloc_device_ext(udev);
3960 XHCI_CMD_UNLOCK(sc);
3962 /* get device into default state */
3965 err = xhci_set_address(udev, NULL, 0);
3971 xhci_device_uninit(struct usb_device *udev)
3973 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3976 /* no init for root HUB */
3977 if (udev->parent_hub == NULL)
3982 index = udev->controller_slot_id;
3984 if (index <= sc->sc_noslot) {
3985 xhci_cmd_disable_slot(sc, index);
3986 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
3988 /* free device extension */
3989 xhci_free_device_ext(udev);
3992 XHCI_CMD_UNLOCK(sc);
3996 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
3999 * Wait until the hardware has finished any possible use of
4000 * the transfer descriptor(s)
4002 *pus = 2048; /* microseconds */
4006 xhci_device_resume(struct usb_device *udev)
4008 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4015 /* check for root HUB */
4016 if (udev->parent_hub == NULL)
4019 index = udev->controller_slot_id;
4023 /* blindly resume all endpoints */
4025 USB_BUS_LOCK(udev->bus);
4027 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4028 for (p = 0; p != 1 /*XHCI_MAX_STREAMS*/; p++) {
4029 XWRITE4(sc, door, XHCI_DOORBELL(index),
4030 n | XHCI_DB_SID_SET(p));
4034 USB_BUS_UNLOCK(udev->bus);
4036 XHCI_CMD_UNLOCK(sc);
4040 xhci_device_suspend(struct usb_device *udev)
4042 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4049 /* check for root HUB */
4050 if (udev->parent_hub == NULL)
4053 index = udev->controller_slot_id;
4057 /* blindly suspend all endpoints */
4059 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4060 err = xhci_cmd_stop_ep(sc, 1, n, index);
4062 DPRINTF("Failed to suspend endpoint "
4063 "%u on slot %u (ignored).\n", n, index);
4067 XHCI_CMD_UNLOCK(sc);
4071 xhci_set_hw_power(struct usb_bus *bus)
4077 xhci_device_state_change(struct usb_device *udev)
4079 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4080 struct usb_page_search buf_inp;
4084 /* check for root HUB */
4085 if (udev->parent_hub == NULL)
4088 index = udev->controller_slot_id;
4092 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4093 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4094 &sc->sc_hw.devs[index].tt);
4096 sc->sc_hw.devs[index].nports = 0;
4101 switch (usb_get_device_state(udev)) {
4102 case USB_STATE_POWERED:
4103 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4106 /* set default state */
4107 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4109 /* reset number of contexts */
4110 sc->sc_hw.devs[index].context_num = 0;
4112 err = xhci_cmd_reset_dev(sc, index);
4115 DPRINTF("Device reset failed "
4116 "for slot %u.\n", index);
4120 case USB_STATE_ADDRESSED:
4121 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4124 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4126 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4129 DPRINTF("Failed to deconfigure "
4130 "slot %u.\n", index);
4134 case USB_STATE_CONFIGURED:
4135 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4138 /* set configured state */
4139 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4141 /* reset number of contexts */
4142 sc->sc_hw.devs[index].context_num = 0;
4144 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4146 xhci_configure_mask(udev, 3, 0);
4148 err = xhci_configure_device(udev);
4150 DPRINTF("Could not configure device "
4151 "at slot %u.\n", index);
4154 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4156 DPRINTF("Could not evaluate device "
4157 "context at slot %u.\n", index);
4164 XHCI_CMD_UNLOCK(sc);
4167 struct usb_bus_methods xhci_bus_methods = {
4168 .endpoint_init = xhci_ep_init,
4169 .endpoint_uninit = xhci_ep_uninit,
4170 .xfer_setup = xhci_xfer_setup,
4171 .xfer_unsetup = xhci_xfer_unsetup,
4172 .get_dma_delay = xhci_get_dma_delay,
4173 .device_init = xhci_device_init,
4174 .device_uninit = xhci_device_uninit,
4175 .device_resume = xhci_device_resume,
4176 .device_suspend = xhci_device_suspend,
4177 .set_hw_power = xhci_set_hw_power,
4178 .roothub_exec = xhci_roothub_exec,
4179 .xfer_poll = xhci_do_poll,
4180 .start_dma_delay = xhci_start_dma_delay,
4181 .set_address = xhci_set_address,
4182 .clear_stall = xhci_ep_clear_stall,
4183 .device_state_change = xhci_device_state_change,
4184 .set_hw_power_sleep = xhci_set_hw_power_sleep,