sys/dev/usb/controller/xhci.c

   1 /*-
   2  * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  */
  25
  26 /*
  27  * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
  28  *
  29  * The XHCI 1.0 spec can be found at
  30  * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
  31  * and the USB 3.0 spec at
  32  * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
  33  */
  34
  35 /*
  36  * A few words about the design implementation: This driver emulates
  37  * the concept about TDs which is found in EHCI specification. This
  38  * way we avoid too much diveration among USB drivers.
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include <sys/stdint.h>
  45 #include <sys/stddef.h>
  46 #include <sys/param.h>
  47 #include <sys/queue.h>
  48 #include <sys/types.h>
  49 #include <sys/systm.h>
  50 #include <sys/kernel.h>
  51 #include <sys/bus.h>
  52 #include <sys/module.h>
  53 #include <sys/lock.h>
  54 #include <sys/mutex.h>
  55 #include <sys/condvar.h>
  56 #include <sys/sysctl.h>
  57 #include <sys/sx.h>
  58 #include <sys/unistd.h>
  59 #include <sys/callout.h>
  60 #include <sys/malloc.h>
  61 #include <sys/priv.h>
  62
  63 #include <dev/usb/usb.h>
  64 #include <dev/usb/usbdi.h>
  65
  66 #define USB_DEBUG_VAR xhcidebug
  67
  68 #include <dev/usb/usb_core.h>
  69 #include <dev/usb/usb_debug.h>
  70 #include <dev/usb/usb_busdma.h>
  71 #include <dev/usb/usb_process.h>
  72 #include <dev/usb/usb_transfer.h>
  73 #include <dev/usb/usb_device.h>
  74 #include <dev/usb/usb_hub.h>
  75 #include <dev/usb/usb_util.h>
  76
  77 #include <dev/usb/usb_controller.h>
  78 #include <dev/usb/usb_bus.h>
  79 #include <dev/usb/controller/xhci.h>
  80 #include <dev/usb/controller/xhcireg.h>
  81
  82 #define XHCI_BUS2SC(bus) \
  83    ((struct xhci_softc *)(((uint8_t *)(bus)) - \
  84     ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
  85
  86 #ifdef USB_DEBUG
  87 static int xhcidebug;
  88 static int xhciroute;
  89
  90 SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
  91 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
  92     &xhcidebug, 0, "Debug level");
  93 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
  94 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN,
  95     &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller");
  96 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
  97 #endif
  98
  99 #define XHCI_INTR_ENDPT 1
 100
 101 struct xhci_std_temp {
 102         struct xhci_softc       *sc;
 103         struct usb_page_cache   *pc;
 104         struct xhci_td          *td;
 105         struct xhci_td          *td_next;
 106         uint32_t                len;
 107         uint32_t                offset;
 108         uint32_t                max_packet_size;
 109         uint32_t                average;
 110         uint16_t                isoc_delta;
 111         uint16_t                isoc_frame;
 112         uint8_t                 shortpkt;
 113         uint8_t                 multishort;
 114         uint8_t                 last_frame;
 115         uint8_t                 trb_type;
 116         uint8_t                 direction;
 117         uint8_t                 tbc;
 118         uint8_t                 tlbpc;
 119         uint8_t                 step_td;
 120         uint8_t                 do_isoc_sync;
 121 };
 122
 123 static void     xhci_do_poll(struct usb_bus *);
 124 static void     xhci_device_done(struct usb_xfer *, usb_error_t);
 125 static void     xhci_root_intr(struct xhci_softc *);
 126 static void     xhci_free_device_ext(struct usb_device *);
 127 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
 128                     struct usb_endpoint_descriptor *);
 129 static usb_proc_callback_t xhci_configure_msg;
 130 static usb_error_t xhci_configure_device(struct usb_device *);
 131 static usb_error_t xhci_configure_endpoint(struct usb_device *,
 132                     struct usb_endpoint_descriptor *, uint64_t, uint16_t,
 133                     uint8_t, uint8_t, uint8_t, uint16_t, uint16_t);
 134 static usb_error_t xhci_configure_mask(struct usb_device *,
 135                     uint32_t, uint8_t);
 136 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
 137                     uint64_t, uint8_t);
 138 static void xhci_endpoint_doorbell(struct usb_xfer *);
 139 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
 140 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
 141 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
 142 #ifdef USB_DEBUG
 143 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
 144 #endif
 145
 146 extern struct usb_bus_methods xhci_bus_methods;
 147
 148 #ifdef USB_DEBUG
 149 static void
 150 xhci_dump_trb(struct xhci_trb *trb)
 151 {
 152         DPRINTFN(5, "trb = %p\n", trb);
 153         DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
 154         DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
 155         DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
 156 }
 157
 158 static void
 159 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
 160 {
 161         DPRINTFN(5, "pep = %p\n", pep);
 162         DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
 163         DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
 164         DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
 165         DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
 166         DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
 167         DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
 168         DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
 169 }
 170
 171 static void
 172 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
 173 {
 174         DPRINTFN(5, "psl = %p\n", psl);
 175         DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
 176         DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
 177         DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
 178         DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
 179 }
 180 #endif
 181
 182 uint32_t
 183 xhci_get_port_route(void)
 184 {
 185 #ifdef USB_DEBUG
 186         return (0xFFFFFFFFU ^ ((uint32_t)xhciroute));
 187 #else
 188         return (0xFFFFFFFFU);
 189 #endif
 190 }
 191
 192 static void
 193 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
 194 {
 195         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 196         uint8_t i;
 197
 198         cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
 199            sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
 200
 201         cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
 202            sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
 203
 204         for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) {
 205                 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
 206                     XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
 207         }
 208 }
 209
 210 static void
 211 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
 212 {
 213         if (sc->sc_ctx_is_64_byte) {
 214                 uint32_t offset;
 215                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 216                 /* all contexts are initially 32-bytes */
 217                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 218                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 219         }
 220         *ptr = htole32(val);
 221 }
 222
 223 static uint32_t
 224 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
 225 {
 226         if (sc->sc_ctx_is_64_byte) {
 227                 uint32_t offset;
 228                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 229                 /* all contexts are initially 32-bytes */
 230                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 231                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 232         }
 233         return (le32toh(*ptr));
 234 }
 235
 236 static void
 237 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
 238 {
 239         if (sc->sc_ctx_is_64_byte) {
 240                 uint32_t offset;
 241                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 242                 /* all contexts are initially 32-bytes */
 243                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 244                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 245         }
 246         *ptr = htole64(val);
 247 }
 248
 249 #ifdef USB_DEBUG
 250 static uint64_t
 251 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
 252 {
 253         if (sc->sc_ctx_is_64_byte) {
 254                 uint32_t offset;
 255                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 256                 /* all contexts are initially 32-bytes */
 257                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 258                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 259         }
 260         return (le64toh(*ptr));
 261 }
 262 #endif
 263
 264 usb_error_t
 265 xhci_start_controller(struct xhci_softc *sc)
 266 {
 267         struct usb_page_search buf_res;
 268         struct xhci_hw_root *phwr;
 269         struct xhci_dev_ctx_addr *pdctxa;
 270         uint64_t addr;
 271         uint32_t temp;
 272         uint16_t i;
 273
 274         DPRINTF("\n");
 275
 276         sc->sc_capa_off = 0;
 277         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 278         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
 279         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 280
 281         DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
 282         DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
 283         DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
 284
 285         sc->sc_event_ccs = 1;
 286         sc->sc_event_idx = 0;
 287         sc->sc_command_ccs = 1;
 288         sc->sc_command_idx = 0;
 289
 290         DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
 291
 292         temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
 293
 294         DPRINTF("HCS0 = 0x%08x\n", temp);
 295
 296         if (XHCI_HCS0_CSZ(temp)) {
 297                 sc->sc_ctx_is_64_byte = 1;
 298                 device_printf(sc->sc_bus.parent, "64 byte context size.\n");
 299         } else {
 300                 sc->sc_ctx_is_64_byte = 0;
 301                 device_printf(sc->sc_bus.parent, "32 byte context size.\n");
 302         }
 303
 304         /* Reset controller */
 305         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
 306
 307         for (i = 0; i != 100; i++) {
 308                 usb_pause_mtx(NULL, hz / 100);
 309                 temp = XREAD4(sc, oper, XHCI_USBCMD) &
 310                     (XHCI_CMD_HCRST | XHCI_STS_CNR);
 311                 if (!temp)
 312                         break;
 313         }
 314
 315         if (temp) {
 316                 device_printf(sc->sc_bus.parent, "Controller "
 317                     "reset timeout.\n");
 318                 return (USB_ERR_IOERROR);
 319         }
 320
 321         if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
 322                 device_printf(sc->sc_bus.parent, "Controller does "
 323                     "not support 4K page size.\n");
 324                 return (USB_ERR_IOERROR);
 325         }
 326
 327         temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
 328
 329         i = XHCI_HCS1_N_PORTS(temp);
 330
 331         if (i == 0) {
 332                 device_printf(sc->sc_bus.parent, "Invalid number "
 333                     "of ports: %u\n", i);
 334                 return (USB_ERR_IOERROR);
 335         }
 336
 337         sc->sc_noport = i;
 338         sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
 339
 340         if (sc->sc_noslot > XHCI_MAX_DEVICES)
 341                 sc->sc_noslot = XHCI_MAX_DEVICES;
 342
 343         /* setup number of device slots */
 344
 345         DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
 346             XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
 347
 348         XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
 349
 350         DPRINTF("Max slots: %u\n", sc->sc_noslot);
 351
 352         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 353
 354         sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
 355
 356         if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
 357                 device_printf(sc->sc_bus.parent, "XHCI request "
 358                     "too many scratchpads\n");
 359                 return (USB_ERR_NOMEM);
 360         }
 361
 362         DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
 363
 364         temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
 365
 366         sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
 367             XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
 368
 369         temp = XREAD4(sc, oper, XHCI_USBSTS);
 370
 371         /* clear interrupts */
 372         XWRITE4(sc, oper, XHCI_USBSTS, temp);
 373         /* disable all device notifications */
 374         XWRITE4(sc, oper, XHCI_DNCTRL, 0);
 375
 376         /* setup device context base address */
 377         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
 378         pdctxa = buf_res.buffer;
 379         memset(pdctxa, 0, sizeof(*pdctxa));
 380
 381         addr = buf_res.physaddr;
 382         addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
 383
 384         /* slot 0 points to the table of scratchpad pointers */
 385         pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
 386
 387         for (i = 0; i != sc->sc_noscratch; i++) {
 388                 struct usb_page_search buf_scp;
 389                 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
 390                 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
 391         }
 392
 393         addr = buf_res.physaddr;
 394
 395         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 396         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 397         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 398         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 399
 400         /* Setup event table size */
 401
 402         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 403
 404         DPRINTF("HCS2=0x%08x\n", temp);
 405
 406         temp = XHCI_HCS2_ERST_MAX(temp);
 407         temp = 1U << temp;
 408         if (temp > XHCI_MAX_RSEG)
 409                 temp = XHCI_MAX_RSEG;
 410
 411         sc->sc_erst_max = temp;
 412
 413         DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
 414             XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp);
 415
 416         XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp));
 417
 418         /* Setup interrupt rate */
 419         XWRITE4(sc, runt, XHCI_IMOD(0), XHCI_IMOD_DEFAULT);
 420
 421         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 422
 423         phwr = buf_res.buffer;
 424         addr = buf_res.physaddr;
 425         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
 426
 427         /* reset hardware root structure */
 428         memset(phwr, 0, sizeof(*phwr));
 429
 430         phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
 431         phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
 432
 433         DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
 434
 435         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
 436         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
 437
 438         addr = (uint64_t)buf_res.physaddr;
 439
 440         DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
 441
 442         XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
 443         XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
 444
 445         /* Setup interrupter registers */
 446
 447         temp = XREAD4(sc, runt, XHCI_IMAN(0));
 448         temp |= XHCI_IMAN_INTR_ENA;
 449         XWRITE4(sc, runt, XHCI_IMAN(0), temp);
 450
 451         /* setup command ring control base address */
 452         addr = buf_res.physaddr;
 453         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 454
 455         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 456
 457         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 458         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 459
 460         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 461
 462         usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 463
 464         /* Go! */
 465         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
 466             XHCI_CMD_INTE | XHCI_CMD_HSEE);
 467
 468         for (i = 0; i != 100; i++) {
 469                 usb_pause_mtx(NULL, hz / 100);
 470                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 471                 if (!temp)
 472                         break;
 473         }
 474         if (temp) {
 475                 XWRITE4(sc, oper, XHCI_USBCMD, 0);
 476                 device_printf(sc->sc_bus.parent, "Run timeout.\n");
 477                 return (USB_ERR_IOERROR);
 478         }
 479
 480         /* catch any lost interrupts */
 481         xhci_do_poll(&sc->sc_bus);
 482
 483         return (0);
 484 }
 485
 486 usb_error_t
 487 xhci_halt_controller(struct xhci_softc *sc)
 488 {
 489         uint32_t temp;
 490         uint16_t i;
 491
 492         DPRINTF("\n");
 493
 494         sc->sc_capa_off = 0;
 495         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 496         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
 497         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 498
 499         /* Halt controller */
 500         XWRITE4(sc, oper, XHCI_USBCMD, 0);
 501
 502         for (i = 0; i != 100; i++) {
 503                 usb_pause_mtx(NULL, hz / 100);
 504                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 505                 if (temp)
 506                         break;
 507         }
 508
 509         if (!temp) {
 510                 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
 511                 return (USB_ERR_IOERROR);
 512         }
 513         return (0);
 514 }
 515
 516 usb_error_t
 517 xhci_init(struct xhci_softc *sc, device_t self)
 518 {
 519         /* initialise some bus fields */
 520         sc->sc_bus.parent = self;
 521
 522         /* set the bus revision */
 523         sc->sc_bus.usbrev = USB_REV_3_0;
 524
 525         /* set up the bus struct */
 526         sc->sc_bus.methods = &xhci_bus_methods;
 527
 528         /* setup devices array */
 529         sc->sc_bus.devices = sc->sc_devices;
 530         sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
 531
 532         /* setup command queue mutex and condition varible */
 533         cv_init(&sc->sc_cmd_cv, "CMDQ");
 534         sx_init(&sc->sc_cmd_sx, "CMDQ lock");
 535
 536         /* get all DMA memory */
 537         if (usb_bus_mem_alloc_all(&sc->sc_bus,
 538             USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
 539                 return (ENOMEM);
 540         }
 541
 542         sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
 543         sc->sc_config_msg[0].bus = &sc->sc_bus;
 544         sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
 545         sc->sc_config_msg[1].bus = &sc->sc_bus;
 546
 547         if (usb_proc_create(&sc->sc_config_proc,
 548             &sc->sc_bus.bus_mtx, device_get_nameunit(self), USB_PRI_MED)) {
 549                 printf("WARNING: Creation of XHCI configure "
 550                     "callback process failed.\n");
 551         }
 552         return (0);
 553 }
 554
 555 void
 556 xhci_uninit(struct xhci_softc *sc)
 557 {
 558         usb_proc_free(&sc->sc_config_proc);
 559
 560         usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 561
 562         cv_destroy(&sc->sc_cmd_cv);
 563         sx_destroy(&sc->sc_cmd_sx);
 564 }
 565
 566 static void
 567 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
 568 {
 569         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 570
 571         switch (state) {
 572         case USB_HW_POWER_SUSPEND:
 573                 DPRINTF("Stopping the XHCI\n");
 574                 xhci_halt_controller(sc);
 575                 break;
 576         case USB_HW_POWER_SHUTDOWN:
 577                 DPRINTF("Stopping the XHCI\n");
 578                 xhci_halt_controller(sc);
 579                 break;
 580         case USB_HW_POWER_RESUME:
 581                 DPRINTF("Starting the XHCI\n");
 582                 xhci_start_controller(sc);
 583                 break;
 584         default:
 585                 break;
 586         }
 587 }
 588
 589 static usb_error_t
 590 xhci_generic_done_sub(struct usb_xfer *xfer)
 591 {
 592         struct xhci_td *td;
 593         struct xhci_td *td_alt_next;
 594         uint32_t len;
 595         uint8_t status;
 596
 597         td = xfer->td_transfer_cache;
 598         td_alt_next = td->alt_next;
 599
 600         if (xfer->aframes != xfer->nframes)
 601                 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
 602
 603         while (1) {
 604
 605                 usb_pc_cpu_invalidate(td->page_cache);
 606
 607                 status = td->status;
 608                 len = td->remainder;
 609
 610                 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
 611                     xfer, (unsigned int)xfer->aframes,
 612                     (unsigned int)xfer->nframes,
 613                     (unsigned int)len, (unsigned int)td->len,
 614                     (unsigned int)status);
 615
 616                 /*
 617                  * Verify the status length and
 618                  * add the length to "frlengths[]":
 619                  */
 620                 if (len > td->len) {
 621                         /* should not happen */
 622                         DPRINTF("Invalid status length, "
 623                             "0x%04x/0x%04x bytes\n", len, td->len);
 624                         status = XHCI_TRB_ERROR_LENGTH;
 625                 } else if (xfer->aframes != xfer->nframes) {
 626                         xfer->frlengths[xfer->aframes] += td->len - len;
 627                 }
 628                 /* Check for last transfer */
 629                 if (((void *)td) == xfer->td_transfer_last) {
 630                         td = NULL;
 631                         break;
 632                 }
 633                 /* Check for transfer error */
 634                 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
 635                     status != XHCI_TRB_ERROR_SUCCESS) {
 636                         /* the transfer is finished */
 637                         td = NULL;
 638                         break;
 639                 }
 640                 /* Check for short transfer */
 641                 if (len > 0) {
 642                         if (xfer->flags_int.short_frames_ok ||
 643                             xfer->flags_int.isochronous_xfr ||
 644                             xfer->flags_int.control_xfr) {
 645                                 /* follow alt next */
 646                                 td = td->alt_next;
 647                         } else {
 648                                 /* the transfer is finished */
 649                                 td = NULL;
 650                         }
 651                         break;
 652                 }
 653                 td = td->obj_next;
 654
 655                 if (td->alt_next != td_alt_next) {
 656                         /* this USB frame is complete */
 657                         break;
 658                 }
 659         }
 660
 661         /* update transfer cache */
 662
 663         xfer->td_transfer_cache = td;
 664
 665         return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
 666             (status != XHCI_TRB_ERROR_SHORT_PKT &&
 667             status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
 668             USB_ERR_NORMAL_COMPLETION);
 669 }
 670
 671 static void
 672 xhci_generic_done(struct usb_xfer *xfer)
 673 {
 674         usb_error_t err = 0;
 675
 676         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
 677             xfer, xfer->endpoint);
 678
 679         /* reset scanner */
 680
 681         xfer->td_transfer_cache = xfer->td_transfer_first;
 682
 683         if (xfer->flags_int.control_xfr) {
 684
 685                 if (xfer->flags_int.control_hdr)
 686                         err = xhci_generic_done_sub(xfer);
 687
 688                 xfer->aframes = 1;
 689
 690                 if (xfer->td_transfer_cache == NULL)
 691                         goto done;
 692         }
 693
 694         while (xfer->aframes != xfer->nframes) {
 695
 696                 err = xhci_generic_done_sub(xfer);
 697                 xfer->aframes++;
 698
 699                 if (xfer->td_transfer_cache == NULL)
 700                         goto done;
 701         }
 702
 703         if (xfer->flags_int.control_xfr &&
 704             !xfer->flags_int.control_act)
 705                 err = xhci_generic_done_sub(xfer);
 706 done:
 707         /* transfer is complete */
 708         xhci_device_done(xfer, err);
 709 }
 710
 711 static void
 712 xhci_activate_transfer(struct usb_xfer *xfer)
 713 {
 714         struct xhci_td *td;
 715
 716         td = xfer->td_transfer_cache;
 717
 718         usb_pc_cpu_invalidate(td->page_cache);
 719
 720         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 721
 722                 /* activate the transfer */
 723
 724                 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
 725                 usb_pc_cpu_flush(td->page_cache);
 726
 727                 xhci_endpoint_doorbell(xfer);
 728         }
 729 }
 730
 731 static void
 732 xhci_skip_transfer(struct usb_xfer *xfer)
 733 {
 734         struct xhci_td *td;
 735         struct xhci_td *td_last;
 736
 737         td = xfer->td_transfer_cache;
 738         td_last = xfer->td_transfer_last;
 739
 740         td = td->alt_next;
 741
 742         usb_pc_cpu_invalidate(td->page_cache);
 743
 744         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 745
 746                 usb_pc_cpu_invalidate(td_last->page_cache);
 747
 748                 /* copy LINK TRB to current waiting location */
 749
 750                 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
 751                 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
 752                 usb_pc_cpu_flush(td->page_cache);
 753
 754                 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
 755                 usb_pc_cpu_flush(td->page_cache);
 756
 757                 xhci_endpoint_doorbell(xfer);
 758         }
 759 }
 760
 761 /*------------------------------------------------------------------------*
 762  *      xhci_check_transfer
 763  *------------------------------------------------------------------------*/
 764 static void
 765 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
 766 {
 767         int64_t offset;
 768         uint64_t td_event;
 769         uint32_t temp;
 770         uint32_t remainder;
 771         uint8_t status;
 772         uint8_t halted;
 773         uint8_t epno;
 774         uint8_t index;
 775         uint8_t i;
 776
 777         /* decode TRB */
 778         td_event = le64toh(trb->qwTrb0);
 779         temp = le32toh(trb->dwTrb2);
 780
 781         remainder = XHCI_TRB_2_REM_GET(temp);
 782         status = XHCI_TRB_2_ERROR_GET(temp);
 783
 784         temp = le32toh(trb->dwTrb3);
 785         epno = XHCI_TRB_3_EP_GET(temp);
 786         index = XHCI_TRB_3_SLOT_GET(temp);
 787
 788         /* check if error means halted */
 789         halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
 790             status != XHCI_TRB_ERROR_SUCCESS);
 791
 792         DPRINTF("slot=%u epno=%u remainder=%u status=%u\n",
 793             index, epno, remainder, status);
 794
 795         if (index > sc->sc_noslot) {
 796                 DPRINTF("Invalid slot.\n");
 797                 return;
 798         }
 799
 800         if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
 801                 DPRINTF("Invalid endpoint.\n");
 802                 return;
 803         }
 804
 805         /* try to find the USB transfer that generated the event */
 806         for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
 807                 struct usb_xfer *xfer;
 808                 struct xhci_td *td;
 809                 struct xhci_endpoint_ext *pepext;
 810
 811                 pepext = &sc->sc_hw.devs[index].endp[epno];
 812
 813                 xfer = pepext->xfer[i];
 814                 if (xfer == NULL)
 815                         continue;
 816
 817                 td = xfer->td_transfer_cache;
 818
 819                 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
 820                         (long long)td_event,
 821                         (long long)td->td_self,
 822                         (long long)td->td_self + sizeof(td->td_trb));
 823
 824                 /*
 825                  * NOTE: Some XHCI implementations might not trigger
 826                  * an event on the last LINK TRB so we need to
 827                  * consider both the last and second last event
 828                  * address as conditions for a successful transfer.
 829                  *
 830                  * NOTE: We assume that the XHCI will only trigger one
 831                  * event per chain of TRBs.
 832                  */
 833
 834                 offset = td_event - td->td_self;
 835
 836                 if (offset >= 0 &&
 837                     offset < (int64_t)sizeof(td->td_trb)) {
 838
 839                         usb_pc_cpu_invalidate(td->page_cache);
 840
 841                         /* compute rest of remainder, if any */
 842                         for (i = (offset / 16) + 1; i < td->ntrb; i++) {
 843                                 temp = le32toh(td->td_trb[i].dwTrb2);
 844                                 remainder += XHCI_TRB_2_BYTES_GET(temp);
 845                         }
 846
 847                         DPRINTFN(5, "New remainder: %u\n", remainder);
 848
 849                         /* clear isochronous transfer errors */
 850                         if (xfer->flags_int.isochronous_xfr) {
 851                                 if (halted) {
 852                                         halted = 0;
 853                                         status = XHCI_TRB_ERROR_SUCCESS;
 854                                         remainder = td->len;
 855                                 }
 856                         }
 857
 858                         /* "td->remainder" is verified later */
 859                         td->remainder = remainder;
 860                         td->status = status;
 861
 862                         usb_pc_cpu_flush(td->page_cache);
 863
 864                         /*
 865                          * 1) Last transfer descriptor makes the
 866                          * transfer done
 867                          */
 868                         if (((void *)td) == xfer->td_transfer_last) {
 869                                 DPRINTF("TD is last\n");
 870                                 xhci_generic_done(xfer);
 871                                 break;
 872                         }
 873
 874                         /*
 875                          * 2) Any kind of error makes the transfer
 876                          * done
 877                          */
 878                         if (halted) {
 879                                 DPRINTF("TD has I/O error\n");
 880                                 xhci_generic_done(xfer);
 881                                 break;
 882                         }
 883
 884                         /*
 885                          * 3) If there is no alternate next transfer,
 886                          * a short packet also makes the transfer done
 887                          */
 888                         if (td->remainder > 0) {
 889                                 if (td->alt_next == NULL) {
 890                                         DPRINTF(
 891                                             "short TD has no alternate next\n");
 892                                         xhci_generic_done(xfer);
 893                                         break;
 894                                 }
 895                                 DPRINTF("TD has short pkt\n");
 896                                 if (xfer->flags_int.short_frames_ok ||
 897                                     xfer->flags_int.isochronous_xfr ||
 898                                     xfer->flags_int.control_xfr) {
 899                                         /* follow the alt next */
 900                                         xfer->td_transfer_cache = td->alt_next;
 901                                         xhci_activate_transfer(xfer);
 902                                         break;
 903                                 }
 904                                 xhci_skip_transfer(xfer);
 905                                 xhci_generic_done(xfer);
 906                                 break;
 907                         }
 908
 909                         /*
 910                          * 4) Transfer complete - go to next TD
 911                          */
 912                         DPRINTF("Following next TD\n");
 913                         xfer->td_transfer_cache = td->obj_next;
 914                         xhci_activate_transfer(xfer);
 915                         break;          /* there should only be one match */
 916                 }
 917         }
 918 }
 919
 920 static void
 921 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
 922 {
 923         if (sc->sc_cmd_addr == trb->qwTrb0) {
 924                 DPRINTF("Received command event\n");
 925                 sc->sc_cmd_result[0] = trb->dwTrb2;
 926                 sc->sc_cmd_result[1] = trb->dwTrb3;
 927                 cv_signal(&sc->sc_cmd_cv);
 928         }
 929 }
 930
 931 static void
 932 xhci_interrupt_poll(struct xhci_softc *sc)
 933 {
 934         struct usb_page_search buf_res;
 935         struct xhci_hw_root *phwr;
 936         uint64_t addr;
 937         uint32_t temp;
 938         uint16_t i;
 939         uint8_t event;
 940         uint8_t j;
 941         uint8_t k;
 942         uint8_t t;
 943
 944         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 945
 946         phwr = buf_res.buffer;
 947
 948         /* Receive any events */
 949
 950         usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
 951
 952         i = sc->sc_event_idx;
 953         j = sc->sc_event_ccs;
 954         t = 2;
 955
 956         while (1) {
 957
 958                 temp = le32toh(phwr->hwr_events[i].dwTrb3);
 959
 960                 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
 961
 962                 if (j != k)
 963                         break;
 964
 965                 event = XHCI_TRB_3_TYPE_GET(temp);
 966
 967                 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
 968                     i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
 969                     (long)le32toh(phwr->hwr_events[i].dwTrb2),
 970                     (long)le32toh(phwr->hwr_events[i].dwTrb3));
 971
 972                 switch (event) {
 973                 case XHCI_TRB_EVENT_TRANSFER:
 974                         xhci_check_transfer(sc, &phwr->hwr_events[i]);
 975                         break;
 976                 case XHCI_TRB_EVENT_CMD_COMPLETE:
 977                         xhci_check_command(sc, &phwr->hwr_events[i]);
 978                         break;
 979                 default:
 980                         DPRINTF("Unhandled event = %u\n", event);
 981                         break;
 982                 }
 983
 984                 i++;
 985
 986                 if (i == XHCI_MAX_EVENTS) {
 987                         i = 0;
 988                         j ^= 1;
 989
 990                         /* check for timeout */
 991                         if (!--t)
 992                                 break;
 993                 }
 994         }
 995
 996         sc->sc_event_idx = i;
 997         sc->sc_event_ccs = j;
 998
 999         /*
1000          * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1001          * latched. That means to activate the register we need to
1002          * write both the low and high double word of the 64-bit
1003          * register.
1004          */
1005
1006         addr = (uint32_t)buf_res.physaddr;
1007         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1008
1009         /* try to clear busy bit */
1010         addr |= XHCI_ERDP_LO_BUSY;
1011
1012         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1013         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1014 }
1015
1016 static usb_error_t
1017 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1018     uint16_t timeout_ms)
1019 {
1020         struct usb_page_search buf_res;
1021         struct xhci_hw_root *phwr;
1022         uint64_t addr;
1023         uint32_t temp;
1024         uint8_t i;
1025         uint8_t j;
1026         int err;
1027
1028         XHCI_CMD_ASSERT_LOCKED(sc);
1029
1030         /* get hardware root structure */
1031
1032         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1033
1034         phwr = buf_res.buffer;
1035
1036         /* Queue command */
1037
1038         USB_BUS_LOCK(&sc->sc_bus);
1039
1040         i = sc->sc_command_idx;
1041         j = sc->sc_command_ccs;
1042
1043         DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1044             i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1045             (long long)le64toh(trb->qwTrb0),
1046             (long)le32toh(trb->dwTrb2),
1047             (long)le32toh(trb->dwTrb3));
1048
1049         phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1050         phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1051
1052         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1053
1054         temp = trb->dwTrb3;
1055
1056         if (j)
1057                 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1058         else
1059                 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1060
1061         temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1062
1063         phwr->hwr_commands[i].dwTrb3 = temp;
1064
1065         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1066
1067         addr = buf_res.physaddr;
1068         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1069
1070         sc->sc_cmd_addr = htole64(addr);
1071
1072         i++;
1073
1074         if (i == (XHCI_MAX_COMMANDS - 1)) {
1075
1076                 if (j) {
1077                         temp = htole32(XHCI_TRB_3_TC_BIT |
1078                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1079                             XHCI_TRB_3_CYCLE_BIT);
1080                 } else {
1081                         temp = htole32(XHCI_TRB_3_TC_BIT |
1082                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1083                 }
1084
1085                 phwr->hwr_commands[i].dwTrb3 = temp;
1086
1087                 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1088
1089                 i = 0;
1090                 j ^= 1;
1091         }
1092
1093         sc->sc_command_idx = i;
1094         sc->sc_command_ccs = j;
1095
1096         XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1097
1098         err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1099             USB_MS_TO_TICKS(timeout_ms));
1100
1101         if (err) {
1102                 DPRINTFN(0, "Command timeout!\n");
1103                 err = USB_ERR_TIMEOUT;
1104                 trb->dwTrb2 = 0;
1105                 trb->dwTrb3 = 0;
1106         } else {
1107                 temp = le32toh(sc->sc_cmd_result[0]);
1108                 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1109                         err = USB_ERR_IOERROR;
1110
1111                 trb->dwTrb2 = sc->sc_cmd_result[0];
1112                 trb->dwTrb3 = sc->sc_cmd_result[1];
1113         }
1114
1115         USB_BUS_UNLOCK(&sc->sc_bus);
1116
1117         return (err);
1118 }
1119
1120 #if 0
1121 static usb_error_t
1122 xhci_cmd_nop(struct xhci_softc *sc)
1123 {
1124         struct xhci_trb trb;
1125         uint32_t temp;
1126
1127         DPRINTF("\n");
1128
1129         trb.qwTrb0 = 0;
1130         trb.dwTrb2 = 0;
1131         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1132
1133         trb.dwTrb3 = htole32(temp);
1134
1135         return (xhci_do_command(sc, &trb, 100 /* ms */));
1136 }
1137 #endif
1138
1139 static usb_error_t
1140 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1141 {
1142         struct xhci_trb trb;
1143         uint32_t temp;
1144         usb_error_t err;
1145
1146         DPRINTF("\n");
1147
1148         trb.qwTrb0 = 0;
1149         trb.dwTrb2 = 0;
1150         trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1151
1152         err = xhci_do_command(sc, &trb, 100 /* ms */);
1153         if (err)
1154                 goto done;
1155
1156         temp = le32toh(trb.dwTrb3);
1157
1158         *pslot = XHCI_TRB_3_SLOT_GET(temp);
1159
1160 done:
1161         return (err);
1162 }
1163
1164 static usb_error_t
1165 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1166 {
1167         struct xhci_trb trb;
1168         uint32_t temp;
1169
1170         DPRINTF("\n");
1171
1172         trb.qwTrb0 = 0;
1173         trb.dwTrb2 = 0;
1174         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1175             XHCI_TRB_3_SLOT_SET(slot_id);
1176
1177         trb.dwTrb3 = htole32(temp);
1178
1179         return (xhci_do_command(sc, &trb, 100 /* ms */));
1180 }
1181
1182 static usb_error_t
1183 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1184     uint8_t bsr, uint8_t slot_id)
1185 {
1186         struct xhci_trb trb;
1187         uint32_t temp;
1188
1189         DPRINTF("\n");
1190
1191         trb.qwTrb0 = htole64(input_ctx);
1192         trb.dwTrb2 = 0;
1193         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1194             XHCI_TRB_3_SLOT_SET(slot_id);
1195
1196         if (bsr)
1197                 temp |= XHCI_TRB_3_BSR_BIT;
1198
1199         trb.dwTrb3 = htole32(temp);
1200
1201         return (xhci_do_command(sc, &trb, 500 /* ms */));
1202 }
1203
1204 static usb_error_t
1205 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1206 {
1207         struct usb_page_search buf_inp;
1208         struct usb_page_search buf_dev;
1209         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1210         struct xhci_hw_dev *hdev;
1211         struct xhci_dev_ctx *pdev;
1212         struct xhci_endpoint_ext *pepext;
1213         uint32_t temp;
1214         uint16_t mps;
1215         usb_error_t err;
1216         uint8_t index;
1217
1218         /* the root HUB case is not handled here */
1219         if (udev->parent_hub == NULL)
1220                 return (USB_ERR_INVAL);
1221
1222         index = udev->controller_slot_id;
1223
1224         hdev =  &sc->sc_hw.devs[index];
1225
1226         if (mtx != NULL)
1227                 mtx_unlock(mtx);
1228
1229         XHCI_CMD_LOCK(sc);
1230
1231         switch (hdev->state) {
1232         case XHCI_ST_DEFAULT:
1233         case XHCI_ST_ENABLED:
1234
1235                 hdev->state = XHCI_ST_ENABLED;
1236
1237                 /* set configure mask to slot and EP0 */
1238                 xhci_configure_mask(udev, 3, 0);
1239
1240                 /* configure input slot context structure */
1241                 err = xhci_configure_device(udev);
1242
1243                 if (err != 0) {
1244                         DPRINTF("Could not configure device\n");
1245                         break;
1246                 }
1247
1248                 /* configure input endpoint context structure */
1249                 switch (udev->speed) {
1250                 case USB_SPEED_LOW:
1251                 case USB_SPEED_FULL:
1252                         mps = 8;
1253                         break;
1254                 case USB_SPEED_HIGH:
1255                         mps = 64;
1256                         break;
1257                 default:
1258                         mps = 512;
1259                         break;
1260                 }
1261
1262                 pepext = xhci_get_endpoint_ext(udev,
1263                     &udev->ctrl_ep_desc);
1264                 err = xhci_configure_endpoint(udev,
1265                     &udev->ctrl_ep_desc, pepext->physaddr,
1266                     0, 1, 1, 0, mps, mps);
1267
1268                 if (err != 0) {
1269                         DPRINTF("Could not configure default endpoint\n");
1270                         break;
1271                 }
1272
1273                 /* execute set address command */
1274                 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1275
1276                 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1277                     (address == 0), index);
1278
1279                 if (err != 0) {
1280                         DPRINTF("Could not set address "
1281                             "for slot %u.\n", index);
1282                         if (address != 0)
1283                                 break;
1284                 }
1285
1286                 /* update device address to new value */
1287
1288                 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1289                 pdev = buf_dev.buffer;
1290                 usb_pc_cpu_invalidate(&hdev->device_pc);
1291
1292                 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1293                 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1294
1295                 /* update device state to new value */
1296
1297                 if (address != 0)
1298                         hdev->state = XHCI_ST_ADDRESSED;
1299                 else
1300                         hdev->state = XHCI_ST_DEFAULT;
1301                 break;
1302
1303         default:
1304                 DPRINTF("Wrong state for set address.\n");
1305                 err = USB_ERR_IOERROR;
1306                 break;
1307         }
1308         XHCI_CMD_UNLOCK(sc);
1309
1310         if (mtx != NULL)
1311                 mtx_lock(mtx);
1312
1313         return (err);
1314 }
1315
1316 static usb_error_t
1317 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1318     uint8_t deconfigure, uint8_t slot_id)
1319 {
1320         struct xhci_trb trb;
1321         uint32_t temp;
1322
1323         DPRINTF("\n");
1324
1325         trb.qwTrb0 = htole64(input_ctx);
1326         trb.dwTrb2 = 0;
1327         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1328             XHCI_TRB_3_SLOT_SET(slot_id);
1329
1330         if (deconfigure)
1331                 temp |= XHCI_TRB_3_DCEP_BIT;
1332
1333         trb.dwTrb3 = htole32(temp);
1334
1335         return (xhci_do_command(sc, &trb, 100 /* ms */));
1336 }
1337
1338 static usb_error_t
1339 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1340     uint8_t slot_id)
1341 {
1342         struct xhci_trb trb;
1343         uint32_t temp;
1344
1345         DPRINTF("\n");
1346
1347         trb.qwTrb0 = htole64(input_ctx);
1348         trb.dwTrb2 = 0;
1349         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1350             XHCI_TRB_3_SLOT_SET(slot_id);
1351         trb.dwTrb3 = htole32(temp);
1352
1353         return (xhci_do_command(sc, &trb, 100 /* ms */));
1354 }
1355
1356 static usb_error_t
1357 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1358     uint8_t ep_id, uint8_t slot_id)
1359 {
1360         struct xhci_trb trb;
1361         uint32_t temp;
1362
1363         DPRINTF("\n");
1364
1365         trb.qwTrb0 = 0;
1366         trb.dwTrb2 = 0;
1367         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1368             XHCI_TRB_3_SLOT_SET(slot_id) |
1369             XHCI_TRB_3_EP_SET(ep_id);
1370
1371         if (preserve)
1372                 temp |= XHCI_TRB_3_PRSV_BIT;
1373
1374         trb.dwTrb3 = htole32(temp);
1375
1376         return (xhci_do_command(sc, &trb, 100 /* ms */));
1377 }
1378
1379 static usb_error_t
1380 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1381     uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1382 {
1383         struct xhci_trb trb;
1384         uint32_t temp;
1385
1386         DPRINTF("\n");
1387
1388         trb.qwTrb0 = htole64(dequeue_ptr);
1389
1390         temp = XHCI_TRB_2_STREAM_SET(stream_id);
1391         trb.dwTrb2 = htole32(temp);
1392
1393         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1394             XHCI_TRB_3_SLOT_SET(slot_id) |
1395             XHCI_TRB_3_EP_SET(ep_id);
1396         trb.dwTrb3 = htole32(temp);
1397
1398         return (xhci_do_command(sc, &trb, 100 /* ms */));
1399 }
1400
1401 static usb_error_t
1402 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1403     uint8_t ep_id, uint8_t slot_id)
1404 {
1405         struct xhci_trb trb;
1406         uint32_t temp;
1407
1408         DPRINTF("\n");
1409
1410         trb.qwTrb0 = 0;
1411         trb.dwTrb2 = 0;
1412         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1413             XHCI_TRB_3_SLOT_SET(slot_id) |
1414             XHCI_TRB_3_EP_SET(ep_id);
1415
1416         if (suspend)
1417                 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1418
1419         trb.dwTrb3 = htole32(temp);
1420
1421         return (xhci_do_command(sc, &trb, 100 /* ms */));
1422 }
1423
1424 static usb_error_t
1425 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1426 {
1427         struct xhci_trb trb;
1428         uint32_t temp;
1429
1430         DPRINTF("\n");
1431
1432         trb.qwTrb0 = 0;
1433         trb.dwTrb2 = 0;
1434         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1435             XHCI_TRB_3_SLOT_SET(slot_id);
1436
1437         trb.dwTrb3 = htole32(temp);
1438
1439         return (xhci_do_command(sc, &trb, 100 /* ms */));
1440 }
1441
1442 /*------------------------------------------------------------------------*
1443  *      xhci_interrupt - XHCI interrupt handler
1444  *------------------------------------------------------------------------*/
1445 void
1446 xhci_interrupt(struct xhci_softc *sc)
1447 {
1448         uint32_t status;
1449         uint32_t iman;
1450
1451         USB_BUS_LOCK(&sc->sc_bus);
1452
1453         status = XREAD4(sc, oper, XHCI_USBSTS);
1454         if (status == 0)
1455                 goto done;
1456
1457         /* acknowledge interrupts */
1458
1459         XWRITE4(sc, oper, XHCI_USBSTS, status);
1460
1461         DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1462
1463         if (status & XHCI_STS_EINT) {
1464
1465                 /* acknowledge pending event */
1466                 iman = XREAD4(sc, runt, XHCI_IMAN(0));
1467
1468                 /* reset interrupt */
1469                 XWRITE4(sc, runt, XHCI_IMAN(0), iman);
1470
1471                 DPRINTFN(16, "real interrupt (iman=0x%08x)\n", iman);
1472
1473                 /* check for event(s) */
1474                 xhci_interrupt_poll(sc);
1475         }
1476
1477         if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1478             XHCI_STS_HSE | XHCI_STS_HCE)) {
1479
1480                 if (status & XHCI_STS_PCD) {
1481                         xhci_root_intr(sc);
1482                 }
1483
1484                 if (status & XHCI_STS_HCH) {
1485                         printf("%s: host controller halted\n",
1486                             __FUNCTION__);
1487                 }
1488
1489                 if (status & XHCI_STS_HSE) {
1490                         printf("%s: host system error\n",
1491                             __FUNCTION__);
1492                 }
1493
1494                 if (status & XHCI_STS_HCE) {
1495                         printf("%s: host controller error\n",
1496                            __FUNCTION__);
1497                 }
1498         }
1499 done:
1500         USB_BUS_UNLOCK(&sc->sc_bus);
1501 }
1502
1503 /*------------------------------------------------------------------------*
1504  *      xhci_timeout - XHCI timeout handler
1505  *------------------------------------------------------------------------*/
1506 static void
1507 xhci_timeout(void *arg)
1508 {
1509         struct usb_xfer *xfer = arg;
1510
1511         DPRINTF("xfer=%p\n", xfer);
1512
1513         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1514
1515         /* transfer is transferred */
1516         xhci_device_done(xfer, USB_ERR_TIMEOUT);
1517 }
1518
1519 static void
1520 xhci_do_poll(struct usb_bus *bus)
1521 {
1522         struct xhci_softc *sc = XHCI_BUS2SC(bus);
1523
1524         USB_BUS_LOCK(&sc->sc_bus);
1525         xhci_interrupt_poll(sc);
1526         USB_BUS_UNLOCK(&sc->sc_bus);
1527 }
1528
1529 static void
1530 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1531 {
1532         struct usb_page_search buf_res;
1533         struct xhci_td *td;
1534         struct xhci_td *td_next;
1535         struct xhci_td *td_alt_next;
1536         uint32_t buf_offset;
1537         uint32_t average;
1538         uint32_t len_old;
1539         uint32_t dword;
1540         uint8_t shortpkt_old;
1541         uint8_t precompute;
1542         uint8_t x;
1543
1544         td_alt_next = NULL;
1545         buf_offset = 0;
1546         shortpkt_old = temp->shortpkt;
1547         len_old = temp->len;
1548         precompute = 1;
1549
1550 restart:
1551
1552         td = temp->td;
1553         td_next = temp->td_next;
1554
1555         while (1) {
1556
1557                 if (temp->len == 0) {
1558
1559                         if (temp->shortpkt)
1560                                 break;
1561
1562                         /* send a Zero Length Packet, ZLP, last */
1563
1564                         temp->shortpkt = 1;
1565                         average = 0;
1566
1567                 } else {
1568
1569                         average = temp->average;
1570
1571                         if (temp->len < average) {
1572                                 if (temp->len % temp->max_packet_size) {
1573                                         temp->shortpkt = 1;
1574                                 }
1575                                 average = temp->len;
1576                         }
1577                 }
1578
1579                 if (td_next == NULL)
1580                         panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1581
1582                 /* get next TD */
1583
1584                 td = td_next;
1585                 td_next = td->obj_next;
1586
1587                 /* check if we are pre-computing */
1588
1589                 if (precompute) {
1590
1591                         /* update remaining length */
1592
1593                         temp->len -= average;
1594
1595                         continue;
1596                 }
1597                 /* fill out current TD */
1598
1599                 td->len = average;
1600                 td->remainder = 0;
1601                 td->status = 0;
1602
1603                 /* update remaining length */
1604
1605                 temp->len -= average;
1606
1607                 /* reset TRB index */
1608
1609                 x = 0;
1610
1611                 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1612                         /* immediate data */
1613
1614                         if (average > 8)
1615                                 average = 8;
1616
1617                         td->td_trb[0].qwTrb0 = 0;
1618
1619                         usbd_copy_out(temp->pc, temp->offset + buf_offset,
1620                            (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1621                            average);
1622
1623                         dword = XHCI_TRB_2_BYTES_SET(8) |
1624                             XHCI_TRB_2_TDSZ_SET(0) |
1625                             XHCI_TRB_2_IRQ_SET(0);
1626
1627                         td->td_trb[0].dwTrb2 = htole32(dword);
1628
1629                         dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1630                           XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1631
1632                         /* check wLength */
1633                         if (td->td_trb[0].qwTrb0 &
1634                            htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1635                                 if (td->td_trb[0].qwTrb0 & htole64(1))
1636                                         dword |= XHCI_TRB_3_TRT_IN;
1637                                 else
1638                                         dword |= XHCI_TRB_3_TRT_OUT;
1639                         }
1640
1641                         td->td_trb[0].dwTrb3 = htole32(dword);
1642 #ifdef USB_DEBUG
1643                         xhci_dump_trb(&td->td_trb[x]);
1644 #endif
1645                         x++;
1646
1647                 } else do {
1648
1649                         uint32_t npkt;
1650
1651                         /* fill out buffer pointers */
1652
1653                         if (average == 0) {
1654                                 npkt = 1;
1655                                 memset(&buf_res, 0, sizeof(buf_res));
1656                         } else {
1657                                 usbd_get_page(temp->pc, temp->offset +
1658                                     buf_offset, &buf_res);
1659
1660                                 /* get length to end of page */
1661                                 if (buf_res.length > average)
1662                                         buf_res.length = average;
1663
1664                                 /* check for maximum length */
1665                                 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1666                                         buf_res.length = XHCI_TD_PAGE_SIZE;
1667
1668                                 /* setup npkt */
1669                                 npkt = (average + temp->max_packet_size - 1) /
1670                                     temp->max_packet_size;
1671
1672                                 if (npkt > 31)
1673                                         npkt = 31;
1674                         }
1675
1676                         /* fill out TRB's */
1677                         td->td_trb[x].qwTrb0 =
1678                             htole64((uint64_t)buf_res.physaddr);
1679
1680                         dword =
1681                           XHCI_TRB_2_BYTES_SET(buf_res.length) |
1682                           XHCI_TRB_2_TDSZ_SET(npkt) |
1683                           XHCI_TRB_2_IRQ_SET(0);
1684
1685                         td->td_trb[x].dwTrb2 = htole32(dword);
1686
1687                         dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1688                           XHCI_TRB_3_TYPE_SET(temp->trb_type) |
1689                           (temp->do_isoc_sync ?
1690                            XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8) :
1691                            XHCI_TRB_3_ISO_SIA_BIT) |
1692                           XHCI_TRB_3_TBC_SET(temp->tbc) |
1693                           XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1694
1695                         temp->do_isoc_sync = 0;
1696
1697                         if (temp->direction == UE_DIR_IN) {
1698                                 dword |= XHCI_TRB_3_DIR_IN;
1699
1700                                 /*
1701                                  * NOTE: Only the SETUP stage should
1702                                  * use the IDT bit. Else transactions
1703                                  * can be sent using the wrong data
1704                                  * toggle value.
1705                                  */
1706                                 if (temp->trb_type !=
1707                                     XHCI_TRB_TYPE_SETUP_STAGE &&
1708                                     temp->trb_type !=
1709                                     XHCI_TRB_TYPE_STATUS_STAGE)
1710                                         dword |= XHCI_TRB_3_ISP_BIT;
1711                         }
1712
1713                         td->td_trb[x].dwTrb3 = htole32(dword);
1714
1715                         average -= buf_res.length;
1716                         buf_offset += buf_res.length;
1717 #ifdef USB_DEBUG
1718                         xhci_dump_trb(&td->td_trb[x]);
1719 #endif
1720                         x++;
1721
1722                 } while (average != 0);
1723
1724                 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1725
1726                 /* store number of data TRB's */
1727
1728                 td->ntrb = x;
1729
1730                 DPRINTF("NTRB=%u\n", x);
1731
1732                 /* fill out link TRB */
1733
1734                 if (td_next != NULL) {
1735                         /* link the current TD with the next one */
1736                         td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1737                         DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1738                 } else {
1739                         /* this field will get updated later */
1740                         DPRINTF("NOLINK\n");
1741                 }
1742
1743                 dword = XHCI_TRB_2_IRQ_SET(0);
1744
1745                 td->td_trb[x].dwTrb2 = htole32(dword);
1746
1747                 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1748                     XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT;
1749
1750                 td->td_trb[x].dwTrb3 = htole32(dword);
1751
1752                 td->alt_next = td_alt_next;
1753 #ifdef USB_DEBUG
1754                 xhci_dump_trb(&td->td_trb[x]);
1755 #endif
1756                 usb_pc_cpu_flush(td->page_cache);
1757         }
1758
1759         if (precompute) {
1760                 precompute = 0;
1761
1762                 /* setup alt next pointer, if any */
1763                 if (temp->last_frame) {
1764                         td_alt_next = NULL;
1765                 } else {
1766                         /* we use this field internally */
1767                         td_alt_next = td_next;
1768                 }
1769
1770                 /* restore */
1771                 temp->shortpkt = shortpkt_old;
1772                 temp->len = len_old;
1773                 goto restart;
1774         }
1775
1776         /* remove cycle bit from first if we are stepping the TRBs */
1777         if (temp->step_td)
1778                 td->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1779
1780         /* remove chain bit because this is the last TRB in the chain */
1781         td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1782         td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1783
1784         usb_pc_cpu_flush(td->page_cache);
1785
1786         temp->td = td;
1787         temp->td_next = td_next;
1788 }
1789
1790 static void
1791 xhci_setup_generic_chain(struct usb_xfer *xfer)
1792 {
1793         struct xhci_std_temp temp;
1794         struct xhci_td *td;
1795         uint32_t x;
1796         uint32_t y;
1797         uint8_t mult;
1798
1799         temp.do_isoc_sync = 0;
1800         temp.step_td = 0;
1801         temp.tbc = 0;
1802         temp.tlbpc = 0;
1803         temp.average = xfer->max_hc_frame_size;
1804         temp.max_packet_size = xfer->max_packet_size;
1805         temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
1806         temp.pc = NULL;
1807         temp.last_frame = 0;
1808         temp.offset = 0;
1809         temp.multishort = xfer->flags_int.isochronous_xfr ||
1810             xfer->flags_int.control_xfr ||
1811             xfer->flags_int.short_frames_ok;
1812
1813         /* toggle the DMA set we are using */
1814         xfer->flags_int.curr_dma_set ^= 1;
1815
1816         /* get next DMA set */
1817         td = xfer->td_start[xfer->flags_int.curr_dma_set];
1818
1819         temp.td = NULL;
1820         temp.td_next = td;
1821
1822         xfer->td_transfer_first = td;
1823         xfer->td_transfer_cache = td;
1824
1825         if (xfer->flags_int.isochronous_xfr) {
1826                 uint8_t shift;
1827
1828                 /* compute multiplier for ISOCHRONOUS transfers */
1829                 mult = xfer->endpoint->ecomp ?
1830                     (xfer->endpoint->ecomp->bmAttributes & 3) : 0;
1831                 /* check for USB 2.0 multiplier */
1832                 if (mult == 0) {
1833                         mult = (xfer->endpoint->edesc->
1834                             wMaxPacketSize[1] >> 3) & 3;
1835                 }
1836                 /* range check */
1837                 if (mult > 2)
1838                         mult = 3;
1839                 else
1840                         mult++;
1841
1842                 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
1843
1844                 DPRINTF("MFINDEX=0x%08x\n", x);
1845
1846                 switch (usbd_get_speed(xfer->xroot->udev)) {
1847                 case USB_SPEED_FULL:
1848                         shift = 3;
1849                         temp.isoc_delta = 8;    /* 1ms */
1850                         x += temp.isoc_delta - 1;
1851                         x &= ~(temp.isoc_delta - 1);
1852                         break;
1853                 default:
1854                         shift = usbd_xfer_get_fps_shift(xfer);
1855                         temp.isoc_delta = 1U << shift;
1856                         x += temp.isoc_delta - 1;
1857                         x &= ~(temp.isoc_delta - 1);
1858                         /* simple frame load balancing */
1859                         x += xfer->endpoint->usb_uframe;
1860                         break;
1861                 }
1862
1863                 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
1864
1865                 if ((xfer->endpoint->is_synced == 0) ||
1866                     (y < (xfer->nframes << shift)) ||
1867                     (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
1868                         /*
1869                          * If there is data underflow or the pipe
1870                          * queue is empty we schedule the transfer a
1871                          * few frames ahead of the current frame
1872                          * position. Else two isochronous transfers
1873                          * might overlap.
1874                          */
1875                         xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
1876                         xfer->endpoint->is_synced = 1;
1877                         temp.do_isoc_sync = 1;
1878
1879                         DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
1880                 }
1881
1882                 /* compute isochronous completion time */
1883
1884                 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
1885
1886                 xfer->isoc_time_complete =
1887                     usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
1888                     (y / 8) + (((xfer->nframes << shift) + 7) / 8);
1889
1890                 x = 0;
1891                 temp.isoc_frame = xfer->endpoint->isoc_next;
1892                 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
1893
1894                 xfer->endpoint->isoc_next += xfer->nframes << shift;
1895
1896         } else if (xfer->flags_int.control_xfr) {
1897
1898                 /* check if we should prepend a setup message */
1899
1900                 if (xfer->flags_int.control_hdr) {
1901
1902                         temp.len = xfer->frlengths[0];
1903                         temp.pc = xfer->frbuffers + 0;
1904                         temp.shortpkt = temp.len ? 1 : 0;
1905                         temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
1906                         temp.direction = 0;
1907
1908                         /* check for last frame */
1909                         if (xfer->nframes == 1) {
1910                                 /* no STATUS stage yet, SETUP is last */
1911                                 if (xfer->flags_int.control_act)
1912                                         temp.last_frame = 1;
1913                         }
1914
1915                         xhci_setup_generic_chain_sub(&temp);
1916                 }
1917                 x = 1;
1918                 mult = 1;
1919                 temp.isoc_delta = 0;
1920                 temp.isoc_frame = 0;
1921                 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE;
1922         } else {
1923                 x = 0;
1924                 mult = 1;
1925                 temp.isoc_delta = 0;
1926                 temp.isoc_frame = 0;
1927                 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
1928         }
1929
1930         if (x != xfer->nframes) {
1931                 /* setup page_cache pointer */
1932                 temp.pc = xfer->frbuffers + x;
1933                 /* set endpoint direction */
1934                 temp.direction = UE_GET_DIR(xfer->endpointno);
1935         }
1936
1937         while (x != xfer->nframes) {
1938
1939                 /* DATA0 / DATA1 message */
1940
1941                 temp.len = xfer->frlengths[x];
1942                 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
1943                     x != 0 && temp.multishort == 0);
1944
1945                 x++;
1946
1947                 if (x == xfer->nframes) {
1948                         if (xfer->flags_int.control_xfr) {
1949                                 /* no STATUS stage yet, DATA is last */
1950                                 if (xfer->flags_int.control_act)
1951                                         temp.last_frame = 1;
1952                         } else {
1953                                 temp.last_frame = 1;
1954                         }
1955                 }
1956                 if (temp.len == 0) {
1957
1958                         /* make sure that we send an USB packet */
1959
1960                         temp.shortpkt = 0;
1961
1962                         temp.tbc = 0;
1963                         temp.tlbpc = mult - 1;
1964
1965                 } else if (xfer->flags_int.isochronous_xfr) {
1966
1967                         uint8_t tdpc;
1968
1969                         /*
1970                          * Isochronous transfers don't have short
1971                          * packet termination:
1972                          */
1973
1974                         temp.shortpkt = 1;
1975
1976                         /* isochronous transfers have a transfer limit */
1977
1978                         if (temp.len > xfer->max_frame_size)
1979                                 temp.len = xfer->max_frame_size;
1980
1981                         /* compute TD packet count */
1982                         tdpc = (temp.len + xfer->max_packet_size - 1) /
1983                             xfer->max_packet_size;
1984
1985                         temp.tbc = ((tdpc + mult - 1) / mult) - 1;
1986                         temp.tlbpc = (tdpc % mult);
1987
1988                         if (temp.tlbpc == 0)
1989                                 temp.tlbpc = mult - 1;
1990                         else
1991                                 temp.tlbpc--;
1992                 } else {
1993
1994                         /* regular data transfer */
1995
1996                         temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
1997                 }
1998
1999                 xhci_setup_generic_chain_sub(&temp);
2000
2001                 if (xfer->flags_int.isochronous_xfr) {
2002                         temp.offset += xfer->frlengths[x - 1];
2003                         temp.isoc_frame += temp.isoc_delta;
2004                 } else {
2005                         /* get next Page Cache pointer */
2006                         temp.pc = xfer->frbuffers + x;
2007                 }
2008         }
2009
2010         /* check if we should append a status stage */
2011
2012         if (xfer->flags_int.control_xfr &&
2013             !xfer->flags_int.control_act) {
2014
2015                 /*
2016                  * Send a DATA1 message and invert the current
2017                  * endpoint direction.
2018                  */
2019                 temp.step_td = (xfer->nframes != 0);
2020                 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2021                 temp.len = 0;
2022                 temp.pc = NULL;
2023                 temp.shortpkt = 0;
2024                 temp.last_frame = 1;
2025                 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2026
2027                 xhci_setup_generic_chain_sub(&temp);
2028         }
2029
2030         td = temp.td;
2031
2032         /* must have at least one frame! */
2033
2034         xfer->td_transfer_last = td;
2035
2036         DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2037 }
2038
2039 static void
2040 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2041 {
2042         struct usb_page_search buf_res;
2043         struct xhci_dev_ctx_addr *pdctxa;
2044
2045         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2046
2047         pdctxa = buf_res.buffer;
2048
2049         DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2050
2051         pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2052
2053         usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2054 }
2055
2056 static usb_error_t
2057 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2058 {
2059         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2060         struct usb_page_search buf_inp;
2061         struct xhci_input_dev_ctx *pinp;
2062         uint32_t temp;
2063         uint8_t index;
2064         uint8_t x;
2065
2066         index = udev->controller_slot_id;
2067
2068         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2069
2070         pinp = buf_inp.buffer;
2071
2072         if (drop) {
2073                 mask &= XHCI_INCTX_NON_CTRL_MASK;
2074                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2075                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2076         } else {
2077                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0);
2078                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2079
2080                 /* find most significant set bit */
2081                 for (x = 31; x != 1; x--) {
2082                         if (mask & (1 << x))
2083                                 break;
2084                 }
2085
2086                 /* adjust */
2087                 x--;
2088
2089                 /* figure out maximum */
2090                 if (x > sc->sc_hw.devs[index].context_num) {
2091                         sc->sc_hw.devs[index].context_num = x;
2092                         temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2093                         temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2094                         temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2095                         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2096                 }
2097         }
2098         return (0);
2099 }
2100
2101 static usb_error_t
2102 xhci_configure_endpoint(struct usb_device *udev,
2103     struct usb_endpoint_descriptor *edesc, uint64_t ring_addr,
2104     uint16_t interval, uint8_t max_packet_count, uint8_t mult,
2105     uint8_t fps_shift, uint16_t max_packet_size, uint16_t max_frame_size)
2106 {
2107         struct usb_page_search buf_inp;
2108         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2109         struct xhci_input_dev_ctx *pinp;
2110         uint32_t temp;
2111         uint8_t index;
2112         uint8_t epno;
2113         uint8_t type;
2114
2115         index = udev->controller_slot_id;
2116
2117         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2118
2119         pinp = buf_inp.buffer;
2120
2121         epno = edesc->bEndpointAddress;
2122         type = edesc->bmAttributes & UE_XFERTYPE;
2123
2124         if (type == UE_CONTROL)
2125                 epno |= UE_DIR_IN;
2126
2127         epno = XHCI_EPNO2EPID(epno);
2128
2129         if (epno == 0)
2130                 return (USB_ERR_NO_PIPE);               /* invalid */
2131
2132         if (max_packet_count == 0)
2133                 return (USB_ERR_BAD_BUFSIZE);
2134
2135         max_packet_count--;
2136
2137         if (mult == 0)
2138                 return (USB_ERR_BAD_BUFSIZE);
2139
2140         temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2141             XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2142             XHCI_EPCTX_0_LSA_SET(0);
2143
2144         switch (udev->speed) {
2145         case USB_SPEED_FULL:
2146         case USB_SPEED_LOW:
2147                 /* 1ms -> 125us */
2148                 fps_shift += 3;
2149                 break;
2150         default:
2151                 break;
2152         }
2153
2154         switch (type) {
2155         case UE_INTERRUPT:
2156                 if (fps_shift > 3)
2157                         fps_shift--;
2158                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2159                 break;
2160         case UE_ISOCHRONOUS:
2161                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2162
2163                 switch (udev->speed) {
2164                 case USB_SPEED_SUPER:
2165                         if (mult > 3)
2166                                 mult = 3;
2167                         temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2168                         max_packet_count /= mult;
2169                         break;
2170                 default:
2171                         break;
2172                 }
2173                 break;
2174         default:
2175                 break;
2176         }
2177
2178         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2179
2180         temp =
2181             XHCI_EPCTX_1_HID_SET(0) |
2182             XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2183             XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2184
2185         if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) {
2186                 if (type != UE_ISOCHRONOUS)
2187                         temp |= XHCI_EPCTX_1_CERR_SET(3);
2188         }
2189
2190         switch (type) {
2191         case UE_CONTROL:
2192                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2193                 break;
2194         case UE_ISOCHRONOUS:
2195                 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2196                 break;
2197         case UE_BULK:
2198                 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2199                 break;
2200         default:
2201                 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2202                 break;
2203         }
2204
2205         /* check for IN direction */
2206         if (epno & 1)
2207                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2208
2209         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2210
2211         ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2212
2213         xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2214
2215         switch (edesc->bmAttributes & UE_XFERTYPE) {
2216         case UE_INTERRUPT:
2217         case UE_ISOCHRONOUS:
2218                 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2219                     XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2220                     max_frame_size));
2221                 break;
2222         case UE_CONTROL:
2223                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2224                 break;
2225         default:
2226                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2227                 break;
2228         }
2229
2230         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2231
2232 #ifdef USB_DEBUG
2233         xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2234 #endif
2235         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2236
2237         return (0);             /* success */
2238 }
2239
2240 static usb_error_t
2241 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2242 {
2243         struct xhci_endpoint_ext *pepext;
2244         struct usb_endpoint_ss_comp_descriptor *ecomp;
2245
2246         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2247             xfer->endpoint->edesc);
2248
2249         ecomp = xfer->endpoint->ecomp;
2250
2251         pepext->trb[0].dwTrb3 = 0;      /* halt any transfers */
2252         usb_pc_cpu_flush(pepext->page_cache);
2253
2254         return (xhci_configure_endpoint(xfer->xroot->udev,
2255             xfer->endpoint->edesc, pepext->physaddr,
2256             xfer->interval, xfer->max_packet_count,
2257             (ecomp != NULL) ? (ecomp->bmAttributes & 3) + 1 : 1,
2258             usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2259             xfer->max_frame_size));
2260 }
2261
2262 static usb_error_t
2263 xhci_configure_device(struct usb_device *udev)
2264 {
2265         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2266         struct usb_page_search buf_inp;
2267         struct usb_page_cache *pcinp;
2268         struct xhci_input_dev_ctx *pinp;
2269         struct usb_device *hubdev;
2270         uint32_t temp;
2271         uint32_t route;
2272         uint32_t rh_port;
2273         uint8_t is_hub;
2274         uint8_t index;
2275         uint8_t depth;
2276
2277         index = udev->controller_slot_id;
2278
2279         DPRINTF("index=%u\n", index);
2280
2281         pcinp = &sc->sc_hw.devs[index].input_pc;
2282
2283         usbd_get_page(pcinp, 0, &buf_inp);
2284
2285         pinp = buf_inp.buffer;
2286
2287         rh_port = 0;
2288         route = 0;
2289
2290         /* figure out route string and root HUB port number */
2291
2292         for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2293
2294                 if (hubdev->parent_hub == NULL)
2295                         break;
2296
2297                 depth = hubdev->parent_hub->depth;
2298
2299                 /*
2300                  * NOTE: HS/FS/LS devices and the SS root HUB can have
2301                  * more than 15 ports
2302                  */
2303
2304                 rh_port = hubdev->port_no;
2305
2306                 if (depth == 0)
2307                         break;
2308
2309                 if (rh_port > 15)
2310                         rh_port = 15;
2311
2312                 if (depth < 6)
2313                         route |= rh_port << (4 * (depth - 1));
2314         }
2315
2316         DPRINTF("Route=0x%08x\n", route);
2317
2318         temp = XHCI_SCTX_0_ROUTE_SET(route) |
2319             XHCI_SCTX_0_CTX_NUM_SET(
2320             sc->sc_hw.devs[index].context_num + 1);
2321
2322         switch (udev->speed) {
2323         case USB_SPEED_LOW:
2324                 temp |= XHCI_SCTX_0_SPEED_SET(2);
2325                 if (udev->parent_hs_hub != NULL &&
2326                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2327                     UDPROTO_HSHUBMTT) {
2328                         DPRINTF("Device inherits MTT\n");
2329                         temp |= XHCI_SCTX_0_MTT_SET(1);
2330                 }
2331                 break;
2332         case USB_SPEED_HIGH:
2333                 temp |= XHCI_SCTX_0_SPEED_SET(3);
2334                 if (sc->sc_hw.devs[index].nports != 0 &&
2335                     udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2336                         DPRINTF("HUB supports MTT\n");
2337                         temp |= XHCI_SCTX_0_MTT_SET(1);
2338                 }
2339                 break;
2340         case USB_SPEED_FULL:
2341                 temp |= XHCI_SCTX_0_SPEED_SET(1);
2342                 if (udev->parent_hs_hub != NULL &&
2343                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2344                     UDPROTO_HSHUBMTT) {
2345                         DPRINTF("Device inherits MTT\n");
2346                         temp |= XHCI_SCTX_0_MTT_SET(1);
2347                 }
2348                 break;
2349         default:
2350                 temp |= XHCI_SCTX_0_SPEED_SET(4);
2351                 break;
2352         }
2353
2354         is_hub = sc->sc_hw.devs[index].nports != 0 &&
2355             (udev->speed == USB_SPEED_SUPER ||
2356             udev->speed == USB_SPEED_HIGH);
2357
2358         if (is_hub)
2359                 temp |= XHCI_SCTX_0_HUB_SET(1);
2360
2361         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2362
2363         temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2364
2365         if (is_hub) {
2366                 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2367                     sc->sc_hw.devs[index].nports);
2368         }
2369
2370         switch (udev->speed) {
2371         case USB_SPEED_SUPER:
2372                 switch (sc->sc_hw.devs[index].state) {
2373                 case XHCI_ST_ADDRESSED:
2374                 case XHCI_ST_CONFIGURED:
2375                         /* enable power save */
2376                         temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2377                         break;
2378                 default:
2379                         /* disable power save */
2380                         break;
2381                 }
2382                 break;
2383         default:
2384                 break;
2385         }
2386
2387         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2388
2389         temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2390
2391         if (is_hub) {
2392                 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2393                     sc->sc_hw.devs[index].tt);
2394         }
2395
2396         hubdev = udev->parent_hs_hub;
2397
2398         /* check if we should activate the transaction translator */
2399         switch (udev->speed) {
2400         case USB_SPEED_FULL:
2401         case USB_SPEED_LOW:
2402                 if (hubdev != NULL) {
2403                         temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2404                             hubdev->controller_slot_id);
2405                         temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2406                             udev->hs_port_no);
2407                 }
2408                 break;
2409         default:
2410                 break;
2411         }
2412
2413         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2414
2415         temp = XHCI_SCTX_3_DEV_ADDR_SET(udev->address) |
2416             XHCI_SCTX_3_SLOT_STATE_SET(0);
2417
2418         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2419
2420 #ifdef USB_DEBUG
2421         xhci_dump_device(sc, &pinp->ctx_slot);
2422 #endif
2423         usb_pc_cpu_flush(pcinp);
2424
2425         return (0);             /* success */
2426 }
2427
2428 static usb_error_t
2429 xhci_alloc_device_ext(struct usb_device *udev)
2430 {
2431         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2432         struct usb_page_search buf_dev;
2433         struct usb_page_search buf_ep;
2434         struct xhci_trb *trb;
2435         struct usb_page_cache *pc;
2436         struct usb_page *pg;
2437         uint64_t addr;
2438         uint8_t index;
2439         uint8_t i;
2440
2441         index = udev->controller_slot_id;
2442
2443         pc = &sc->sc_hw.devs[index].device_pc;
2444         pg = &sc->sc_hw.devs[index].device_pg;
2445
2446         /* need to initialize the page cache */
2447         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2448
2449         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2450             (2 * sizeof(struct xhci_dev_ctx)) :
2451             sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2452                 goto error;
2453
2454         usbd_get_page(pc, 0, &buf_dev);
2455
2456         pc = &sc->sc_hw.devs[index].input_pc;
2457         pg = &sc->sc_hw.devs[index].input_pg;
2458
2459         /* need to initialize the page cache */
2460         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2461
2462         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2463             (2 * sizeof(struct xhci_input_dev_ctx)) :
2464             sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2465                 goto error;
2466         }
2467
2468         pc = &sc->sc_hw.devs[index].endpoint_pc;
2469         pg = &sc->sc_hw.devs[index].endpoint_pg;
2470
2471         /* need to initialize the page cache */
2472         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2473
2474         if (usb_pc_alloc_mem(pc, pg,
2475             sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) {
2476                 goto error;
2477         }
2478
2479         /* initialise all endpoint LINK TRBs */
2480
2481         for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2482
2483                 /* lookup endpoint TRB ring */
2484                 usbd_get_page(pc, (uintptr_t)&
2485                     ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep);
2486
2487                 /* get TRB pointer */
2488                 trb = buf_ep.buffer;
2489                 trb += XHCI_MAX_TRANSFERS - 1;
2490
2491                 /* get TRB start address */
2492                 addr = buf_ep.physaddr;
2493
2494                 /* create LINK TRB */
2495                 trb->qwTrb0 = htole64(addr);
2496                 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2497                 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2498                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2499         }
2500
2501         usb_pc_cpu_flush(pc);
2502
2503         xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2504
2505         return (0);
2506
2507 error:
2508         xhci_free_device_ext(udev);
2509
2510         return (USB_ERR_NOMEM);
2511 }
2512
2513 static void
2514 xhci_free_device_ext(struct usb_device *udev)
2515 {
2516         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2517         uint8_t index;
2518
2519         index = udev->controller_slot_id;
2520         xhci_set_slot_pointer(sc, index, 0);
2521
2522         usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2523         usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2524         usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc);
2525 }
2526
2527 static struct xhci_endpoint_ext *
2528 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2529 {
2530         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2531         struct xhci_endpoint_ext *pepext;
2532         struct usb_page_cache *pc;
2533         struct usb_page_search buf_ep;
2534         uint8_t epno;
2535         uint8_t index;
2536
2537         epno = edesc->bEndpointAddress;
2538         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2539                 epno |= UE_DIR_IN;
2540
2541         epno = XHCI_EPNO2EPID(epno);
2542
2543         index = udev->controller_slot_id;
2544
2545         pc = &sc->sc_hw.devs[index].endpoint_pc;
2546
2547         usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->trb[epno][0], &buf_ep);
2548
2549         pepext = &sc->sc_hw.devs[index].endp[epno];
2550         pepext->page_cache = pc;
2551         pepext->trb = buf_ep.buffer;
2552         pepext->physaddr = buf_ep.physaddr;
2553
2554         return (pepext);
2555 }
2556
2557 static void
2558 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2559 {
2560         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2561         uint8_t epno;
2562         uint8_t index;
2563
2564         epno = xfer->endpointno;
2565         if (xfer->flags_int.control_xfr)
2566                 epno |= UE_DIR_IN;
2567
2568         epno = XHCI_EPNO2EPID(epno);
2569         index = xfer->xroot->udev->controller_slot_id;
2570
2571         if (xfer->xroot->udev->flags.self_suspended == 0) {
2572                 XWRITE4(sc, door, XHCI_DOORBELL(index),
2573                     epno | XHCI_DB_SID_SET(/*xfer->stream_id*/ 0));
2574         }
2575 }
2576
2577 static void
2578 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2579 {
2580         struct xhci_endpoint_ext *pepext;
2581
2582         if (xfer->flags_int.bandwidth_reclaimed) {
2583                 xfer->flags_int.bandwidth_reclaimed = 0;
2584
2585                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2586                     xfer->endpoint->edesc);
2587
2588                 pepext->trb_used--;
2589
2590                 pepext->xfer[xfer->qh_pos] = NULL;
2591
2592                 if (error && pepext->trb_running != 0) {
2593                         pepext->trb_halted = 1;
2594                         pepext->trb_running = 0;
2595                 }
2596         }
2597 }
2598
2599 static usb_error_t
2600 xhci_transfer_insert(struct usb_xfer *xfer)
2601 {
2602         struct xhci_td *td_first;
2603         struct xhci_td *td_last;
2604         struct xhci_endpoint_ext *pepext;
2605         uint64_t addr;
2606         uint8_t i;
2607         uint8_t inext;
2608         uint8_t trb_limit;
2609
2610         DPRINTFN(8, "\n");
2611
2612         /* check if already inserted */
2613         if (xfer->flags_int.bandwidth_reclaimed) {
2614                 DPRINTFN(8, "Already in schedule\n");
2615                 return (0);
2616         }
2617
2618         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2619             xfer->endpoint->edesc);
2620
2621         td_first = xfer->td_transfer_first;
2622         td_last = xfer->td_transfer_last;
2623         addr = pepext->physaddr;
2624
2625         switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2626         case UE_CONTROL:
2627         case UE_INTERRUPT:
2628                 /* single buffered */
2629                 trb_limit = 1;
2630                 break;
2631         default:
2632                 /* multi buffered */
2633                 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2634                 break;
2635         }
2636
2637         if (pepext->trb_used >= trb_limit) {
2638                 DPRINTFN(8, "Too many TDs queued.\n");
2639                 return (USB_ERR_NOMEM);
2640         }
2641
2642         /* check for stopped condition, after putting transfer on interrupt queue */
2643         if (pepext->trb_running == 0) {
2644                 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2645
2646                 DPRINTFN(8, "Not running\n");
2647
2648                 /* start configuration */
2649                 (void)usb_proc_msignal(&sc->sc_config_proc,
2650                     &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2651                 return (0);
2652         }
2653
2654         pepext->trb_used++;
2655
2656         /* get current TRB index */
2657         i = pepext->trb_index;
2658
2659         /* get next TRB index */
2660         inext = (i + 1);
2661
2662         /* the last entry of the ring is a hardcoded link TRB */
2663         if (inext >= (XHCI_MAX_TRANSFERS - 1))
2664                 inext = 0;
2665
2666         /* compute terminating return address */
2667         addr += inext * sizeof(struct xhci_trb);
2668
2669         /* update next pointer of last link TRB */
2670         td_last->td_trb[td_last->ntrb].qwTrb0 = htole64(addr);
2671         td_last->td_trb[td_last->ntrb].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2672         td_last->td_trb[td_last->ntrb].dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2673             XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2674
2675 #ifdef USB_DEBUG
2676         xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2677 #endif
2678         usb_pc_cpu_flush(td_last->page_cache);
2679
2680         /* write ahead chain end marker */
2681
2682         pepext->trb[inext].qwTrb0 = 0;
2683         pepext->trb[inext].dwTrb2 = 0;
2684         pepext->trb[inext].dwTrb3 = 0;
2685
2686         /* update next pointer of link TRB */
2687
2688         pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2689         pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2690
2691 #ifdef USB_DEBUG
2692         xhci_dump_trb(&pepext->trb[i]);
2693 #endif
2694         usb_pc_cpu_flush(pepext->page_cache);
2695
2696         /* toggle cycle bit which activates the transfer chain */
2697
2698         pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2699             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2700
2701         usb_pc_cpu_flush(pepext->page_cache);
2702
2703         DPRINTF("qh_pos = %u\n", i);
2704
2705         pepext->xfer[i] = xfer;
2706
2707         xfer->qh_pos = i;
2708
2709         xfer->flags_int.bandwidth_reclaimed = 1;
2710
2711         pepext->trb_index = inext;
2712
2713         xhci_endpoint_doorbell(xfer);
2714
2715         return (0);
2716 }
2717
2718 static void
2719 xhci_root_intr(struct xhci_softc *sc)
2720 {
2721         uint16_t i;
2722
2723         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2724
2725         /* clear any old interrupt data */
2726         memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2727
2728         for (i = 1; i <= sc->sc_noport; i++) {
2729                 /* pick out CHANGE bits from the status register */
2730                 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
2731                     XHCI_PS_CSC | XHCI_PS_PEC |
2732                     XHCI_PS_OCC | XHCI_PS_WRC |
2733                     XHCI_PS_PRC | XHCI_PS_PLC |
2734                     XHCI_PS_CEC)) {
2735                         sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2736                         DPRINTF("port %d changed\n", i);
2737                 }
2738         }
2739         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2740             sizeof(sc->sc_hub_idata));
2741 }
2742
2743 /*------------------------------------------------------------------------*
2744  *      xhci_device_done - XHCI done handler
2745  *
2746  * NOTE: This function can be called two times in a row on
2747  * the same USB transfer. From close and from interrupt.
2748  *------------------------------------------------------------------------*/
2749 static void
2750 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
2751 {
2752         DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2753             xfer, xfer->endpoint, error);
2754
2755         /* remove transfer from HW queue */
2756         xhci_transfer_remove(xfer, error);
2757
2758         /* dequeue transfer and start next transfer */
2759         usbd_transfer_done(xfer, error);
2760 }
2761
2762 /*------------------------------------------------------------------------*
2763  * XHCI data transfer support (generic type)
2764  *------------------------------------------------------------------------*/
2765 static void
2766 xhci_device_generic_open(struct usb_xfer *xfer)
2767 {
2768         if (xfer->flags_int.isochronous_xfr) {
2769                 switch (xfer->xroot->udev->speed) {
2770                 case USB_SPEED_FULL:
2771                         break;
2772                 default:
2773                         usb_hs_bandwidth_alloc(xfer);
2774                         break;
2775                 }
2776         }
2777 }
2778
2779 static void
2780 xhci_device_generic_close(struct usb_xfer *xfer)
2781 {
2782         DPRINTF("\n");
2783
2784         xhci_device_done(xfer, USB_ERR_CANCELLED);
2785
2786         if (xfer->flags_int.isochronous_xfr) {
2787                 switch (xfer->xroot->udev->speed) {
2788                 case USB_SPEED_FULL:
2789                         break;
2790                 default:
2791                         usb_hs_bandwidth_free(xfer);
2792                         break;
2793                 }
2794         }
2795 }
2796
2797 static void
2798 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
2799     struct usb_xfer *enter_xfer)
2800 {
2801         struct usb_xfer *xfer;
2802
2803         /* check if there is a current transfer */
2804         xfer = ep->endpoint_q.curr;
2805         if (xfer == NULL)
2806                 return;
2807
2808         /*
2809          * Check if the current transfer is started and then pickup
2810          * the next one, if any. Else wait for next start event due to
2811          * block on failure feature.
2812          */
2813         if (!xfer->flags_int.bandwidth_reclaimed)
2814                 return;
2815
2816         xfer = TAILQ_FIRST(&ep->endpoint_q.head);
2817         if (xfer == NULL) {
2818                 /*
2819                  * In case of enter we have to consider that the
2820                  * transfer is queued by the USB core after the enter
2821                  * method is called.
2822                  */
2823                 xfer = enter_xfer;
2824
2825                 if (xfer == NULL)
2826                         return;
2827         }
2828
2829         /* try to multi buffer */
2830         xhci_transfer_insert(xfer);
2831 }
2832
2833 static void
2834 xhci_device_generic_enter(struct usb_xfer *xfer)
2835 {
2836         DPRINTF("\n");
2837
2838         /* setup TD's and QH */
2839         xhci_setup_generic_chain(xfer);
2840
2841         xhci_device_generic_multi_enter(xfer->endpoint, xfer);
2842 }
2843
2844 static void
2845 xhci_device_generic_start(struct usb_xfer *xfer)
2846 {
2847         DPRINTF("\n");
2848
2849         /* try to insert xfer on HW queue */
2850         xhci_transfer_insert(xfer);
2851
2852         /* try to multi buffer */
2853         xhci_device_generic_multi_enter(xfer->endpoint, NULL);
2854
2855         /* add transfer last on interrupt queue */
2856         usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
2857
2858         /* start timeout, if any */
2859         if (xfer->timeout != 0)
2860                 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
2861 }
2862
2863 struct usb_pipe_methods xhci_device_generic_methods =
2864 {
2865         .open = xhci_device_generic_open,
2866         .close = xhci_device_generic_close,
2867         .enter = xhci_device_generic_enter,
2868         .start = xhci_device_generic_start,
2869 };
2870
2871 /*------------------------------------------------------------------------*
2872  * xhci root HUB support
2873  *------------------------------------------------------------------------*
2874  * Simulate a hardware HUB by handling all the necessary requests.
2875  *------------------------------------------------------------------------*/
2876
2877 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
2878
2879 static const
2880 struct usb_device_descriptor xhci_devd =
2881 {
2882         .bLength = sizeof(xhci_devd),
2883         .bDescriptorType = UDESC_DEVICE,        /* type */
2884         HSETW(.bcdUSB, 0x0300),                 /* USB version */
2885         .bDeviceClass = UDCLASS_HUB,            /* class */
2886         .bDeviceSubClass = UDSUBCLASS_HUB,      /* subclass */
2887         .bDeviceProtocol = UDPROTO_SSHUB,       /* protocol */
2888         .bMaxPacketSize = 9,                    /* max packet size */
2889         HSETW(.idVendor, 0x0000),               /* vendor */
2890         HSETW(.idProduct, 0x0000),              /* product */
2891         HSETW(.bcdDevice, 0x0100),              /* device version */
2892         .iManufacturer = 1,
2893         .iProduct = 2,
2894         .iSerialNumber = 0,
2895         .bNumConfigurations = 1,                /* # of configurations */
2896 };
2897
2898 static const
2899 struct xhci_bos_desc xhci_bosd = {
2900         .bosd = {
2901                 .bLength = sizeof(xhci_bosd.bosd),
2902                 .bDescriptorType = UDESC_BOS,
2903                 HSETW(.wTotalLength, sizeof(xhci_bosd)),
2904                 .bNumDeviceCaps = 3,
2905         },
2906         .usb2extd = {
2907                 .bLength = sizeof(xhci_bosd.usb2extd),
2908                 .bDescriptorType = 1,
2909                 .bDevCapabilityType = 2,
2910                 .bmAttributes[0] = 2,
2911         },
2912         .usbdcd = {
2913                 .bLength = sizeof(xhci_bosd.usbdcd),
2914                 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
2915                 .bDevCapabilityType = 3,
2916                 .bmAttributes = 0, /* XXX */
2917                 HSETW(.wSpeedsSupported, 0x000C),
2918                 .bFunctionalitySupport = 8,
2919                 .bU1DevExitLat = 255,   /* dummy - not used */
2920                 .wU2DevExitLat = { 0x00, 0x08 },
2921         },
2922         .cidd = {
2923                 .bLength = sizeof(xhci_bosd.cidd),
2924                 .bDescriptorType = 1,
2925                 .bDevCapabilityType = 4,
2926                 .bReserved = 0,
2927                 .bContainerID = 0, /* XXX */
2928         },
2929 };
2930
2931 static const
2932 struct xhci_config_desc xhci_confd = {
2933         .confd = {
2934                 .bLength = sizeof(xhci_confd.confd),
2935                 .bDescriptorType = UDESC_CONFIG,
2936                 .wTotalLength[0] = sizeof(xhci_confd),
2937                 .bNumInterface = 1,
2938                 .bConfigurationValue = 1,
2939                 .iConfiguration = 0,
2940                 .bmAttributes = UC_SELF_POWERED,
2941                 .bMaxPower = 0          /* max power */
2942         },
2943         .ifcd = {
2944                 .bLength = sizeof(xhci_confd.ifcd),
2945                 .bDescriptorType = UDESC_INTERFACE,
2946                 .bNumEndpoints = 1,
2947                 .bInterfaceClass = UICLASS_HUB,
2948                 .bInterfaceSubClass = UISUBCLASS_HUB,
2949                 .bInterfaceProtocol = 0,
2950         },
2951         .endpd = {
2952                 .bLength = sizeof(xhci_confd.endpd),
2953                 .bDescriptorType = UDESC_ENDPOINT,
2954                 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
2955                 .bmAttributes = UE_INTERRUPT,
2956                 .wMaxPacketSize[0] = 2,         /* max 15 ports */
2957                 .bInterval = 255,
2958         },
2959         .endpcd = {
2960                 .bLength = sizeof(xhci_confd.endpcd),
2961                 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
2962                 .bMaxBurst = 0,
2963                 .bmAttributes = 0,
2964         },
2965 };
2966
2967 static const
2968 struct usb_hub_ss_descriptor xhci_hubd = {
2969         .bLength = sizeof(xhci_hubd),
2970         .bDescriptorType = UDESC_SS_HUB,
2971 };
2972
2973 static usb_error_t
2974 xhci_roothub_exec(struct usb_device *udev,
2975     struct usb_device_request *req, const void **pptr, uint16_t *plength)
2976 {
2977         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2978         const char *str_ptr;
2979         const void *ptr;
2980         uint32_t port;
2981         uint32_t v;
2982         uint16_t len;
2983         uint16_t i;
2984         uint16_t value;
2985         uint16_t index;
2986         uint8_t j;
2987         usb_error_t err;
2988
2989         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2990
2991         /* buffer reset */
2992         ptr = (const void *)&sc->sc_hub_desc;
2993         len = 0;
2994         err = 0;
2995
2996         value = UGETW(req->wValue);
2997         index = UGETW(req->wIndex);
2998
2999         DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3000             "wValue=0x%04x wIndex=0x%04x\n",
3001             req->bmRequestType, req->bRequest,
3002             UGETW(req->wLength), value, index);
3003
3004 #define C(x,y) ((x) | ((y) << 8))
3005         switch (C(req->bRequest, req->bmRequestType)) {
3006         case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3007         case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3008         case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3009                 /*
3010                  * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3011                  * for the integrated root hub.
3012                  */
3013                 break;
3014         case C(UR_GET_CONFIG, UT_READ_DEVICE):
3015                 len = 1;
3016                 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3017                 break;
3018         case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3019                 switch (value >> 8) {
3020                 case UDESC_DEVICE:
3021                         if ((value & 0xff) != 0) {
3022                                 err = USB_ERR_IOERROR;
3023                                 goto done;
3024                         }
3025                         len = sizeof(xhci_devd);
3026                         ptr = (const void *)&xhci_devd;
3027                         break;
3028
3029                 case UDESC_BOS:
3030                         if ((value & 0xff) != 0) {
3031                                 err = USB_ERR_IOERROR;
3032                                 goto done;
3033                         }
3034                         len = sizeof(xhci_bosd);
3035                         ptr = (const void *)&xhci_bosd;
3036                         break;
3037
3038                 case UDESC_CONFIG:
3039                         if ((value & 0xff) != 0) {
3040                                 err = USB_ERR_IOERROR;
3041                                 goto done;
3042                         }
3043                         len = sizeof(xhci_confd);
3044                         ptr = (const void *)&xhci_confd;
3045                         break;
3046
3047                 case UDESC_STRING:
3048                         switch (value & 0xff) {
3049                         case 0: /* Language table */
3050                                 str_ptr = "\001";
3051                                 break;
3052
3053                         case 1: /* Vendor */
3054                                 str_ptr = sc->sc_vendor;
3055                                 break;
3056
3057                         case 2: /* Product */
3058                                 str_ptr = "XHCI root HUB";
3059                                 break;
3060
3061                         default:
3062                                 str_ptr = "";
3063                                 break;
3064                         }
3065
3066                         len = usb_make_str_desc(
3067                             sc->sc_hub_desc.temp,
3068                             sizeof(sc->sc_hub_desc.temp),
3069                             str_ptr);
3070                         break;
3071
3072                 default:
3073                         err = USB_ERR_IOERROR;
3074                         goto done;
3075                 }
3076                 break;
3077         case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3078                 len = 1;
3079                 sc->sc_hub_desc.temp[0] = 0;
3080                 break;
3081         case C(UR_GET_STATUS, UT_READ_DEVICE):
3082                 len = 2;
3083                 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3084                 break;
3085         case C(UR_GET_STATUS, UT_READ_INTERFACE):
3086         case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3087                 len = 2;
3088                 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3089                 break;
3090         case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3091                 if (value >= XHCI_MAX_DEVICES) {
3092                         err = USB_ERR_IOERROR;
3093                         goto done;
3094                 }
3095                 break;
3096         case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3097                 if (value != 0 && value != 1) {
3098                         err = USB_ERR_IOERROR;
3099                         goto done;
3100                 }
3101                 sc->sc_conf = value;
3102                 break;
3103         case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3104                 break;
3105         case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3106         case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3107         case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3108                 err = USB_ERR_IOERROR;
3109                 goto done;
3110         case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3111                 break;
3112         case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3113                 break;
3114                 /* Hub requests */
3115         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3116                 break;
3117         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3118                 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3119
3120                 if ((index < 1) ||
3121                     (index > sc->sc_noport)) {
3122                         err = USB_ERR_IOERROR;
3123                         goto done;
3124                 }
3125                 port = XHCI_PORTSC(index);
3126
3127                 v = XREAD4(sc, oper, port);
3128                 i = XHCI_PS_PLS_GET(v);
3129                 v &= ~XHCI_PS_CLEAR;
3130
3131                 switch (value) {
3132                 case UHF_C_BH_PORT_RESET:
3133                         XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3134                         break;
3135                 case UHF_C_PORT_CONFIG_ERROR:
3136                         XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3137                         break;
3138                 case UHF_C_PORT_SUSPEND:
3139                 case UHF_C_PORT_LINK_STATE:
3140                         XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3141                         break;
3142                 case UHF_C_PORT_CONNECTION:
3143                         XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3144                         break;
3145                 case UHF_C_PORT_ENABLE:
3146                         XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3147                         break;
3148                 case UHF_C_PORT_OVER_CURRENT:
3149                         XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3150                         break;
3151                 case UHF_C_PORT_RESET:
3152                         XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3153                         break;
3154                 case UHF_PORT_ENABLE:
3155                         XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3156                         break;
3157                 case UHF_PORT_POWER:
3158                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3159                         break;
3160                 case UHF_PORT_INDICATOR:
3161                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3162                         break;
3163                 case UHF_PORT_SUSPEND:
3164
3165                         /* U3 -> U15 */
3166                         if (i == 3) {
3167                                 XWRITE4(sc, oper, port, v |
3168                                     XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3169                         }
3170
3171                         /* wait 20ms for resume sequence to complete */
3172                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3173
3174                         /* U0 */
3175                         XWRITE4(sc, oper, port, v |
3176                             XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3177                         break;
3178                 default:
3179                         err = USB_ERR_IOERROR;
3180                         goto done;
3181                 }
3182                 break;
3183
3184         case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3185                 if ((value & 0xff) != 0) {
3186                         err = USB_ERR_IOERROR;
3187                         goto done;
3188                 }
3189
3190                 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3191
3192                 sc->sc_hub_desc.hubd = xhci_hubd;
3193
3194                 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3195
3196                 if (XHCI_HCS0_PPC(v))
3197                         i = UHD_PWR_INDIVIDUAL;
3198                 else
3199                         i = UHD_PWR_GANGED;
3200
3201                 if (XHCI_HCS0_PIND(v))
3202                         i |= UHD_PORT_IND;
3203
3204                 i |= UHD_OC_INDIVIDUAL;
3205
3206                 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3207
3208                 /* see XHCI section 5.4.9: */
3209                 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3210
3211                 for (j = 1; j <= sc->sc_noport; j++) {
3212
3213                         v = XREAD4(sc, oper, XHCI_PORTSC(j));
3214                         if (v & XHCI_PS_DR) {
3215                                 sc->sc_hub_desc.hubd.
3216                                     DeviceRemovable[j / 8] |= 1U << (j % 8);
3217                         }
3218                 }
3219                 len = sc->sc_hub_desc.hubd.bLength;
3220                 break;
3221
3222         case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3223                 len = 16;
3224                 memset(sc->sc_hub_desc.temp, 0, 16);
3225                 break;
3226
3227         case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3228                 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3229
3230                 if ((index < 1) ||
3231                     (index > sc->sc_noport)) {
3232                         err = USB_ERR_IOERROR;
3233                         goto done;
3234                 }
3235
3236                 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3237
3238                 DPRINTFN(9, "port status=0x%08x\n", v);
3239
3240                 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3241
3242                 switch (XHCI_PS_SPEED_GET(v)) {
3243                 case 3:
3244                         i |= UPS_HIGH_SPEED;
3245                         break;
3246                 case 2:
3247                         i |= UPS_LOW_SPEED;
3248                         break;
3249                 case 1:
3250                         /* FULL speed */
3251                         break;
3252                 default:
3253                         i |= UPS_OTHER_SPEED;
3254                         break;
3255                 }
3256
3257                 if (v & XHCI_PS_CCS)
3258                         i |= UPS_CURRENT_CONNECT_STATUS;
3259                 if (v & XHCI_PS_PED)
3260                         i |= UPS_PORT_ENABLED;
3261                 if (v & XHCI_PS_OCA)
3262                         i |= UPS_OVERCURRENT_INDICATOR;
3263                 if (v & XHCI_PS_PR)
3264                         i |= UPS_RESET;
3265                 if (v & XHCI_PS_PP) {
3266                         /*
3267                          * The USB 3.0 RH is using the
3268                          * USB 2.0's power bit
3269                          */
3270                         i |= UPS_PORT_POWER;
3271                 }
3272                 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3273
3274                 i = 0;
3275                 if (v & XHCI_PS_CSC)
3276                         i |= UPS_C_CONNECT_STATUS;
3277                 if (v & XHCI_PS_PEC)
3278                         i |= UPS_C_PORT_ENABLED;
3279                 if (v & XHCI_PS_OCC)
3280                         i |= UPS_C_OVERCURRENT_INDICATOR;
3281                 if (v & XHCI_PS_WRC)
3282                         i |= UPS_C_BH_PORT_RESET;
3283                 if (v & XHCI_PS_PRC)
3284                         i |= UPS_C_PORT_RESET;
3285                 if (v & XHCI_PS_PLC)
3286                         i |= UPS_C_PORT_LINK_STATE;
3287                 if (v & XHCI_PS_CEC)
3288                         i |= UPS_C_PORT_CONFIG_ERROR;
3289
3290                 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3291                 len = sizeof(sc->sc_hub_desc.ps);
3292                 break;
3293
3294         case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3295                 err = USB_ERR_IOERROR;
3296                 goto done;
3297
3298         case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3299                 break;
3300
3301         case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3302
3303                 i = index >> 8;
3304                 index &= 0x00FF;
3305
3306                 if ((index < 1) ||
3307                     (index > sc->sc_noport)) {
3308                         err = USB_ERR_IOERROR;
3309                         goto done;
3310                 }
3311
3312                 port = XHCI_PORTSC(index);
3313                 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3314
3315                 switch (value) {
3316                 case UHF_PORT_U1_TIMEOUT:
3317                         if (XHCI_PS_SPEED_GET(v) != 4) {
3318                                 err = USB_ERR_IOERROR;
3319                                 goto done;
3320                         }
3321                         port = XHCI_PORTPMSC(index);
3322                         v = XREAD4(sc, oper, port);
3323                         v &= ~XHCI_PM3_U1TO_SET(0xFF);
3324                         v |= XHCI_PM3_U1TO_SET(i);
3325                         XWRITE4(sc, oper, port, v);
3326                         break;
3327                 case UHF_PORT_U2_TIMEOUT:
3328                         if (XHCI_PS_SPEED_GET(v) != 4) {
3329                                 err = USB_ERR_IOERROR;
3330                                 goto done;
3331                         }
3332                         port = XHCI_PORTPMSC(index);
3333                         v = XREAD4(sc, oper, port);
3334                         v &= ~XHCI_PM3_U2TO_SET(0xFF);
3335                         v |= XHCI_PM3_U2TO_SET(i);
3336                         XWRITE4(sc, oper, port, v);
3337                         break;
3338                 case UHF_BH_PORT_RESET:
3339                         XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3340                         break;
3341                 case UHF_PORT_LINK_STATE:
3342                         XWRITE4(sc, oper, port, v |
3343                             XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3344                         /* 4ms settle time */
3345                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3346                         break;
3347                 case UHF_PORT_ENABLE:
3348                         DPRINTFN(3, "set port enable %d\n", index);
3349                         break;
3350                 case UHF_PORT_SUSPEND:
3351                         DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3352                         j = XHCI_PS_SPEED_GET(v);
3353                         if ((j < 1) || (j > 3)) {
3354                                 /* non-supported speed */
3355                                 err = USB_ERR_IOERROR;
3356                                 goto done;
3357                         }
3358                         XWRITE4(sc, oper, port, v |
3359                             XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3360                         break;
3361                 case UHF_PORT_RESET:
3362                         DPRINTFN(6, "reset port %d\n", index);
3363                         XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3364                         break;
3365                 case UHF_PORT_POWER:
3366                         DPRINTFN(3, "set port power %d\n", index);
3367                         XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3368                         break;
3369                 case UHF_PORT_TEST:
3370                         DPRINTFN(3, "set port test %d\n", index);
3371                         break;
3372                 case UHF_PORT_INDICATOR:
3373                         DPRINTFN(3, "set port indicator %d\n", index);
3374
3375                         v &= ~XHCI_PS_PIC_SET(3);
3376                         v |= XHCI_PS_PIC_SET(1);
3377
3378                         XWRITE4(sc, oper, port, v);
3379                         break;
3380                 default:
3381                         err = USB_ERR_IOERROR;
3382                         goto done;
3383                 }
3384                 break;
3385
3386         case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3387         case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3388         case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3389         case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3390                 break;
3391         default:
3392                 err = USB_ERR_IOERROR;
3393                 goto done;
3394         }
3395 done:
3396         *plength = len;
3397         *pptr = ptr;
3398         return (err);
3399 }
3400
3401 static void
3402 xhci_xfer_setup(struct usb_setup_params *parm)
3403 {
3404         struct usb_page_search page_info;
3405         struct usb_page_cache *pc;
3406         struct xhci_softc *sc;
3407         struct usb_xfer *xfer;
3408         void *last_obj;
3409         uint32_t ntd;
3410         uint32_t n;
3411
3412         sc = XHCI_BUS2SC(parm->udev->bus);
3413         xfer = parm->curr_xfer;
3414
3415         /*
3416          * The proof for the "ntd" formula is illustrated like this:
3417          *
3418          * +------------------------------------+
3419          * |                                    |
3420          * |         |remainder ->              |
3421          * |   +-----+---+                      |
3422          * |   | xxx | x | frm 0                |
3423          * |   +-----+---++                     |
3424          * |   | xxx | xx | frm 1               |
3425          * |   +-----+----+                     |
3426          * |            ...                     |
3427          * +------------------------------------+
3428          *
3429          * "xxx" means a completely full USB transfer descriptor
3430          *
3431          * "x" and "xx" means a short USB packet
3432          *
3433          * For the remainder of an USB transfer modulo
3434          * "max_data_length" we need two USB transfer descriptors.
3435          * One to transfer the remaining data and one to finalise with
3436          * a zero length packet in case the "force_short_xfer" flag is
3437          * set. We only need two USB transfer descriptors in the case
3438          * where the transfer length of the first one is a factor of
3439          * "max_frame_size". The rest of the needed USB transfer
3440          * descriptors is given by the buffer size divided by the
3441          * maximum data payload.
3442          */
3443         parm->hc_max_packet_size = 0x400;
3444         parm->hc_max_packet_count = 16 * 3;
3445         parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3446
3447         xfer->flags_int.bdma_enable = 1;
3448
3449         usbd_transfer_setup_sub(parm);
3450
3451         if (xfer->flags_int.isochronous_xfr) {
3452                 ntd = ((1 * xfer->nframes)
3453                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3454         } else if (xfer->flags_int.control_xfr) {
3455                 ntd = ((2 * xfer->nframes) + 1  /* STATUS */
3456                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3457         } else {
3458                 ntd = ((2 * xfer->nframes)
3459                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3460         }
3461
3462 alloc_dma_set:
3463
3464         if (parm->err)
3465                 return;
3466
3467         /*
3468          * Allocate queue heads and transfer descriptors
3469          */
3470         last_obj = NULL;
3471
3472         if (usbd_transfer_setup_sub_malloc(
3473             parm, &pc, sizeof(struct xhci_td),
3474             XHCI_TD_ALIGN, ntd)) {
3475                 parm->err = USB_ERR_NOMEM;
3476                 return;
3477         }
3478         if (parm->buf) {
3479                 for (n = 0; n != ntd; n++) {
3480                         struct xhci_td *td;
3481
3482                         usbd_get_page(pc + n, 0, &page_info);
3483
3484                         td = page_info.buffer;
3485
3486                         /* init TD */
3487                         td->td_self = page_info.physaddr;
3488                         td->obj_next = last_obj;
3489                         td->page_cache = pc + n;
3490
3491                         last_obj = td;
3492
3493                         usb_pc_cpu_flush(pc + n);
3494                 }
3495         }
3496         xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3497
3498         if (!xfer->flags_int.curr_dma_set) {
3499                 xfer->flags_int.curr_dma_set = 1;
3500                 goto alloc_dma_set;
3501         }
3502 }
3503
3504 static usb_error_t
3505 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3506 {
3507         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3508         struct usb_page_search buf_inp;
3509         struct usb_device *udev;
3510         struct xhci_endpoint_ext *pepext;
3511         struct usb_endpoint_descriptor *edesc;
3512         struct usb_page_cache *pcinp;
3513         usb_error_t err;
3514         uint8_t index;
3515         uint8_t epno;
3516
3517         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3518             xfer->endpoint->edesc);
3519
3520         udev = xfer->xroot->udev;
3521         index = udev->controller_slot_id;
3522
3523         pcinp = &sc->sc_hw.devs[index].input_pc;
3524
3525         usbd_get_page(pcinp, 0, &buf_inp);
3526
3527         edesc = xfer->endpoint->edesc;
3528
3529         epno = edesc->bEndpointAddress;
3530
3531         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3532                 epno |= UE_DIR_IN;
3533
3534         epno = XHCI_EPNO2EPID(epno);
3535
3536         if (epno == 0)
3537                 return (USB_ERR_NO_PIPE);               /* invalid */
3538
3539         XHCI_CMD_LOCK(sc);
3540
3541         /* configure endpoint */
3542
3543         err = xhci_configure_endpoint_by_xfer(xfer);
3544
3545         if (err != 0) {
3546                 XHCI_CMD_UNLOCK(sc);
3547                 return (err);
3548         }
3549
3550         /*
3551          * Get the endpoint into the stopped state according to the
3552          * endpoint context state diagram in the XHCI specification:
3553          */
3554
3555         err = xhci_cmd_stop_ep(sc, 0, epno, index);
3556
3557         if (err != 0)
3558                 DPRINTF("Could not stop endpoint %u\n", epno);
3559
3560         err = xhci_cmd_reset_ep(sc, 0, epno, index);
3561
3562         if (err != 0)
3563                 DPRINTF("Could not reset endpoint %u\n", epno);
3564
3565         err = xhci_cmd_set_tr_dequeue_ptr(sc, pepext->physaddr |
3566             XHCI_EPCTX_2_DCS_SET(1), 0, epno, index);
3567
3568         if (err != 0)
3569                 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3570
3571         /*
3572          * Get the endpoint into the running state according to the
3573          * endpoint context state diagram in the XHCI specification:
3574          */
3575
3576         xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3577
3578         err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3579
3580         if (err != 0)
3581                 DPRINTF("Could not configure endpoint %u\n", epno);
3582
3583         err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3584
3585         if (err != 0)
3586                 DPRINTF("Could not configure endpoint %u\n", epno);
3587
3588         XHCI_CMD_UNLOCK(sc);
3589
3590         return (0);
3591 }
3592
3593 static void
3594 xhci_xfer_unsetup(struct usb_xfer *xfer)
3595 {
3596         return;
3597 }
3598
3599 static void
3600 xhci_start_dma_delay(struct usb_xfer *xfer)
3601 {
3602         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3603
3604         /* put transfer on interrupt queue (again) */
3605         usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3606
3607         (void)usb_proc_msignal(&sc->sc_config_proc,
3608             &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3609 }
3610
3611 static void
3612 xhci_configure_msg(struct usb_proc_msg *pm)
3613 {
3614         struct xhci_softc *sc;
3615         struct xhci_endpoint_ext *pepext;
3616         struct usb_xfer *xfer;
3617
3618         sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3619
3620 restart:
3621         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3622
3623                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3624                     xfer->endpoint->edesc);
3625
3626                 if ((pepext->trb_halted != 0) ||
3627                     (pepext->trb_running == 0)) {
3628
3629                         uint8_t i;
3630
3631                         /* clear halted and running */
3632                         pepext->trb_halted = 0;
3633                         pepext->trb_running = 0;
3634
3635                         /* nuke remaining buffered transfers */
3636
3637                         for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
3638                                 /*
3639                                  * NOTE: We need to use the timeout
3640                                  * error code here else existing
3641                                  * isochronous clients can get
3642                                  * confused:
3643                                  */
3644                                 if (pepext->xfer[i] != NULL) {
3645                                         xhci_device_done(pepext->xfer[i],
3646                                             USB_ERR_TIMEOUT);
3647                                 }
3648                         }
3649
3650                         /*
3651                          * NOTE: The USB transfer cannot vanish in
3652                          * this state!
3653                          */
3654
3655                         USB_BUS_UNLOCK(&sc->sc_bus);
3656
3657                         xhci_configure_reset_endpoint(xfer);
3658
3659                         USB_BUS_LOCK(&sc->sc_bus);
3660
3661                         /* check if halted is still cleared */
3662                         if (pepext->trb_halted == 0) {
3663                                 pepext->trb_running = 1;
3664                                 pepext->trb_index = 0;
3665                         }
3666                         goto restart;
3667                 }
3668
3669                 if (xfer->flags_int.did_dma_delay) {
3670
3671                         /* remove transfer from interrupt queue (again) */
3672                         usbd_transfer_dequeue(xfer);
3673
3674                         /* we are finally done */
3675                         usb_dma_delay_done_cb(xfer);
3676
3677                         /* queue changed - restart */
3678                         goto restart;
3679                 }
3680         }
3681
3682         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3683
3684                 /* try to insert xfer on HW queue */
3685                 xhci_transfer_insert(xfer);
3686
3687                 /* try to multi buffer */
3688                 xhci_device_generic_multi_enter(xfer->endpoint, NULL);
3689         }
3690 }
3691
3692 static void
3693 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3694     struct usb_endpoint *ep)
3695 {
3696         struct xhci_endpoint_ext *pepext;
3697
3698         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3699             ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
3700
3701         if (udev->flags.usb_mode != USB_MODE_HOST) {
3702                 /* not supported */
3703                 return;
3704         }
3705         if (udev->parent_hub == NULL) {
3706                 /* root HUB has special endpoint handling */
3707                 return;
3708         }
3709
3710         ep->methods = &xhci_device_generic_methods;
3711
3712         pepext = xhci_get_endpoint_ext(udev, edesc);
3713
3714         USB_BUS_LOCK(udev->bus);
3715         pepext->trb_halted = 1;
3716         pepext->trb_running = 0;
3717         USB_BUS_UNLOCK(udev->bus);
3718 }
3719
3720 static void
3721 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
3722 {
3723
3724 }
3725
3726 static void
3727 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3728 {
3729         struct xhci_endpoint_ext *pepext;
3730
3731         DPRINTF("\n");
3732
3733         if (udev->flags.usb_mode != USB_MODE_HOST) {
3734                 /* not supported */
3735                 return;
3736         }
3737         if (udev->parent_hub == NULL) {
3738                 /* root HUB has special endpoint handling */
3739                 return;
3740         }
3741
3742         pepext = xhci_get_endpoint_ext(udev, ep->edesc);
3743
3744         USB_BUS_LOCK(udev->bus);
3745         pepext->trb_halted = 1;
3746         pepext->trb_running = 0;
3747         USB_BUS_UNLOCK(udev->bus);
3748 }
3749
3750 static usb_error_t
3751 xhci_device_init(struct usb_device *udev)
3752 {
3753         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3754         usb_error_t err;
3755         uint8_t temp;
3756
3757         /* no init for root HUB */
3758         if (udev->parent_hub == NULL)
3759                 return (0);
3760
3761         XHCI_CMD_LOCK(sc);
3762
3763         /* set invalid default */
3764
3765         udev->controller_slot_id = sc->sc_noslot + 1;
3766
3767         /* try to get a new slot ID from the XHCI */
3768
3769         err = xhci_cmd_enable_slot(sc, &temp);
3770
3771         if (err) {
3772                 XHCI_CMD_UNLOCK(sc);
3773                 return (err);
3774         }
3775
3776         if (temp > sc->sc_noslot) {
3777                 XHCI_CMD_UNLOCK(sc);
3778                 return (USB_ERR_BAD_ADDRESS);
3779         }
3780
3781         if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
3782                 DPRINTF("slot %u already allocated.\n", temp);
3783                 XHCI_CMD_UNLOCK(sc);
3784                 return (USB_ERR_BAD_ADDRESS);
3785         }
3786
3787         /* store slot ID for later reference */
3788
3789         udev->controller_slot_id = temp;
3790
3791         /* reset data structure */
3792
3793         memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
3794
3795         /* set mark slot allocated */
3796
3797         sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
3798
3799         err = xhci_alloc_device_ext(udev);
3800
3801         XHCI_CMD_UNLOCK(sc);
3802
3803         /* get device into default state */
3804
3805         if (err == 0)
3806                 err = xhci_set_address(udev, NULL, 0);
3807
3808         return (err);
3809 }
3810
3811 static void
3812 xhci_device_uninit(struct usb_device *udev)
3813 {
3814         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3815         uint8_t index;
3816
3817         /* no init for root HUB */
3818         if (udev->parent_hub == NULL)
3819                 return;
3820
3821         XHCI_CMD_LOCK(sc);
3822
3823         index = udev->controller_slot_id;
3824
3825         if (index <= sc->sc_noslot) {
3826                 xhci_cmd_disable_slot(sc, index);
3827                 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
3828
3829                 /* free device extension */
3830                 xhci_free_device_ext(udev);
3831         }
3832
3833         XHCI_CMD_UNLOCK(sc);
3834 }
3835
3836 static void
3837 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
3838 {
3839         /*
3840          * Wait until the hardware has finished any possible use of
3841          * the transfer descriptor(s)
3842          */
3843         *pus = 2048;                    /* microseconds */
3844 }
3845
3846 static void
3847 xhci_device_resume(struct usb_device *udev)
3848 {
3849         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3850         uint8_t index;
3851         uint8_t n;
3852         uint8_t p;
3853
3854         DPRINTF("\n");
3855
3856         /* check for root HUB */
3857         if (udev->parent_hub == NULL)
3858                 return;
3859
3860         index = udev->controller_slot_id;
3861
3862         XHCI_CMD_LOCK(sc);
3863
3864         /* blindly resume all endpoints */
3865
3866         USB_BUS_LOCK(udev->bus);
3867
3868         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
3869                 for (p = 0; p != 1 /*XHCI_MAX_STREAMS*/; p++) {
3870                         XWRITE4(sc, door, XHCI_DOORBELL(index),
3871                             n | XHCI_DB_SID_SET(p));
3872                 }
3873         }
3874
3875         USB_BUS_UNLOCK(udev->bus);
3876
3877         XHCI_CMD_UNLOCK(sc);
3878 }
3879
3880 static void
3881 xhci_device_suspend(struct usb_device *udev)
3882 {
3883         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3884         uint8_t index;
3885         uint8_t n;
3886         usb_error_t err;
3887
3888         DPRINTF("\n");
3889
3890         /* check for root HUB */
3891         if (udev->parent_hub == NULL)
3892                 return;
3893
3894         index = udev->controller_slot_id;
3895
3896         XHCI_CMD_LOCK(sc);
3897
3898         /* blindly suspend all endpoints */
3899
3900         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
3901                 err = xhci_cmd_stop_ep(sc, 1, n, index);
3902                 if (err != 0) {
3903                         DPRINTF("Failed to suspend endpoint "
3904                             "%u on slot %u (ignored).\n", n, index);
3905                 }
3906         }
3907
3908         XHCI_CMD_UNLOCK(sc);
3909 }
3910
3911 static void
3912 xhci_set_hw_power(struct usb_bus *bus)
3913 {
3914         DPRINTF("\n");
3915 }
3916
3917 static void
3918 xhci_device_state_change(struct usb_device *udev)
3919 {
3920         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3921         struct usb_page_search buf_inp;
3922         usb_error_t err;
3923         uint8_t index;
3924
3925         /* check for root HUB */
3926         if (udev->parent_hub == NULL)
3927                 return;
3928
3929         index = udev->controller_slot_id;
3930
3931         DPRINTF("\n");
3932
3933         if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
3934                 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
3935                     &sc->sc_hw.devs[index].tt);
3936                 if (err != 0)
3937                         sc->sc_hw.devs[index].nports = 0;
3938         }
3939
3940         XHCI_CMD_LOCK(sc);
3941
3942         switch (usb_get_device_state(udev)) {
3943         case USB_STATE_POWERED:
3944                 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
3945                         break;
3946
3947                 /* set default state */
3948                 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
3949
3950                 /* reset number of contexts */
3951                 sc->sc_hw.devs[index].context_num = 0;
3952
3953                 err = xhci_cmd_reset_dev(sc, index);
3954
3955                 if (err != 0) {
3956                         DPRINTF("Device reset failed "
3957                             "for slot %u.\n", index);
3958                 }
3959                 break;
3960
3961         case USB_STATE_ADDRESSED:
3962                 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
3963                         break;
3964
3965                 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
3966
3967                 err = xhci_cmd_configure_ep(sc, 0, 1, index);
3968
3969                 if (err) {
3970                         DPRINTF("Failed to deconfigure "
3971                             "slot %u.\n", index);
3972                 }
3973                 break;
3974
3975         case USB_STATE_CONFIGURED:
3976                 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
3977                         break;
3978
3979                 /* set configured state */
3980                 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
3981
3982                 /* reset number of contexts */
3983                 sc->sc_hw.devs[index].context_num = 0;
3984
3985                 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
3986
3987                 xhci_configure_mask(udev, 3, 0);
3988
3989                 err = xhci_configure_device(udev);
3990                 if (err != 0) {
3991                         DPRINTF("Could not configure device "
3992                             "at slot %u.\n", index);
3993                 }
3994
3995                 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3996                 if (err != 0) {
3997                         DPRINTF("Could not evaluate device "
3998                             "context at slot %u.\n", index);
3999                 }
4000                 break;
4001
4002         default:
4003                 break;
4004         }
4005         XHCI_CMD_UNLOCK(sc);
4006 }
4007
4008 struct usb_bus_methods xhci_bus_methods = {
4009         .endpoint_init = xhci_ep_init,
4010         .endpoint_uninit = xhci_ep_uninit,
4011         .xfer_setup = xhci_xfer_setup,
4012         .xfer_unsetup = xhci_xfer_unsetup,
4013         .get_dma_delay = xhci_get_dma_delay,
4014         .device_init = xhci_device_init,
4015         .device_uninit = xhci_device_uninit,
4016         .device_resume = xhci_device_resume,
4017         .device_suspend = xhci_device_suspend,
4018         .set_hw_power = xhci_set_hw_power,
4019         .roothub_exec = xhci_roothub_exec,
4020         .xfer_poll = xhci_do_poll,
4021         .start_dma_delay = xhci_start_dma_delay,
4022         .set_address = xhci_set_address,
4023         .clear_stall = xhci_ep_clear_stall,
4024         .device_state_change = xhci_device_state_change,
4025         .set_hw_power_sleep = xhci_set_hw_power_sleep,
4026 };