sys/dev/usb/controller/xhci.c

   1 /*-
   2  * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  */
  25
  26 /*
  27  * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
  28  *
  29  * The XHCI 1.0 spec can be found at
  30  * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
  31  * and the USB 3.0 spec at
  32  * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
  33  */
  34
  35 /*
  36  * A few words about the design implementation: This driver emulates
  37  * the concept about TDs which is found in EHCI specification. This
  38  * way we avoid too much diveration among USB drivers.
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include <sys/stdint.h>
  45 #include <sys/stddef.h>
  46 #include <sys/param.h>
  47 #include <sys/queue.h>
  48 #include <sys/types.h>
  49 #include <sys/systm.h>
  50 #include <sys/kernel.h>
  51 #include <sys/bus.h>
  52 #include <sys/module.h>
  53 #include <sys/lock.h>
  54 #include <sys/mutex.h>
  55 #include <sys/condvar.h>
  56 #include <sys/sysctl.h>
  57 #include <sys/sx.h>
  58 #include <sys/unistd.h>
  59 #include <sys/callout.h>
  60 #include <sys/malloc.h>
  61 #include <sys/priv.h>
  62
  63 #include <dev/usb/usb.h>
  64 #include <dev/usb/usbdi.h>
  65
  66 #define USB_DEBUG_VAR xhcidebug
  67
  68 #include <dev/usb/usb_core.h>
  69 #include <dev/usb/usb_debug.h>
  70 #include <dev/usb/usb_busdma.h>
  71 #include <dev/usb/usb_process.h>
  72 #include <dev/usb/usb_transfer.h>
  73 #include <dev/usb/usb_device.h>
  74 #include <dev/usb/usb_hub.h>
  75 #include <dev/usb/usb_util.h>
  76
  77 #include <dev/usb/usb_controller.h>
  78 #include <dev/usb/usb_bus.h>
  79 #include <dev/usb/controller/xhci.h>
  80 #include <dev/usb/controller/xhcireg.h>
  81
  82 #define XHCI_BUS2SC(bus) \
  83    ((struct xhci_softc *)(((uint8_t *)(bus)) - \
  84     ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
  85
  86 #ifdef USB_DEBUG
  87 static int xhcidebug;
  88 static int xhciroute;
  89
  90 SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
  91 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
  92     &xhcidebug, 0, "Debug level");
  93 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
  94 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN,
  95     &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller");
  96 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
  97 #endif
  98
  99 #define XHCI_INTR_ENDPT 1
 100
 101 struct xhci_std_temp {
 102         struct xhci_softc       *sc;
 103         struct usb_page_cache   *pc;
 104         struct xhci_td          *td;
 105         struct xhci_td          *td_next;
 106         uint32_t                len;
 107         uint32_t                offset;
 108         uint32_t                max_packet_size;
 109         uint32_t                average;
 110         uint16_t                isoc_delta;
 111         uint16_t                isoc_frame;
 112         uint8_t                 shortpkt;
 113         uint8_t                 multishort;
 114         uint8_t                 last_frame;
 115         uint8_t                 trb_type;
 116         uint8_t                 direction;
 117         uint8_t                 tbc;
 118         uint8_t                 tlbpc;
 119         uint8_t                 step_td;
 120         uint8_t                 do_isoc_sync;
 121 };
 122
 123 static void     xhci_do_poll(struct usb_bus *);
 124 static void     xhci_device_done(struct usb_xfer *, usb_error_t);
 125 static void     xhci_root_intr(struct xhci_softc *);
 126 static void     xhci_free_device_ext(struct usb_device *);
 127 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
 128                     struct usb_endpoint_descriptor *);
 129 static usb_proc_callback_t xhci_configure_msg;
 130 static usb_error_t xhci_configure_device(struct usb_device *);
 131 static usb_error_t xhci_configure_endpoint(struct usb_device *,
 132                     struct usb_endpoint_descriptor *, uint64_t, uint16_t,
 133                     uint8_t, uint8_t, uint8_t, uint16_t, uint16_t);
 134 static usb_error_t xhci_configure_mask(struct usb_device *,
 135                     uint32_t, uint8_t);
 136 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
 137                     uint64_t, uint8_t);
 138 static void xhci_endpoint_doorbell(struct usb_xfer *);
 139 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
 140 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
 141 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
 142 #ifdef USB_DEBUG
 143 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
 144 #endif
 145
 146 extern struct usb_bus_methods xhci_bus_methods;
 147
 148 #ifdef USB_DEBUG
 149 static void
 150 xhci_dump_trb(struct xhci_trb *trb)
 151 {
 152         DPRINTFN(5, "trb = %p\n", trb);
 153         DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
 154         DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
 155         DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
 156 }
 157
 158 static void
 159 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
 160 {
 161         DPRINTFN(5, "pep = %p\n", pep);
 162         DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
 163         DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
 164         DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
 165         DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
 166         DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
 167         DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
 168         DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
 169 }
 170
 171 static void
 172 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
 173 {
 174         DPRINTFN(5, "psl = %p\n", psl);
 175         DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
 176         DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
 177         DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
 178         DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
 179 }
 180 #endif
 181
 182 uint32_t
 183 xhci_get_port_route(void)
 184 {
 185 #ifdef USB_DEBUG
 186         return (0xFFFFFFFFU ^ ((uint32_t)xhciroute));
 187 #else
 188         return (0xFFFFFFFFU);
 189 #endif
 190 }
 191
 192 static void
 193 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
 194 {
 195         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 196         uint8_t i;
 197
 198         cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
 199            sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
 200
 201         cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
 202            sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
 203
 204         for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) {
 205                 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
 206                     XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
 207         }
 208 }
 209
 210 static void
 211 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
 212 {
 213         if (sc->sc_ctx_is_64_byte) {
 214                 uint32_t offset;
 215                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 216                 /* all contexts are initially 32-bytes */
 217                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 218                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 219         }
 220         *ptr = htole32(val);
 221 }
 222
 223 static uint32_t
 224 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
 225 {
 226         if (sc->sc_ctx_is_64_byte) {
 227                 uint32_t offset;
 228                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 229                 /* all contexts are initially 32-bytes */
 230                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 231                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 232         }
 233         return (le32toh(*ptr));
 234 }
 235
 236 static void
 237 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
 238 {
 239         if (sc->sc_ctx_is_64_byte) {
 240                 uint32_t offset;
 241                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 242                 /* all contexts are initially 32-bytes */
 243                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 244                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 245         }
 246         *ptr = htole64(val);
 247 }
 248
 249 #ifdef USB_DEBUG
 250 static uint64_t
 251 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
 252 {
 253         if (sc->sc_ctx_is_64_byte) {
 254                 uint32_t offset;
 255                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 256                 /* all contexts are initially 32-bytes */
 257                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 258                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 259         }
 260         return (le64toh(*ptr));
 261 }
 262 #endif
 263
 264 usb_error_t
 265 xhci_start_controller(struct xhci_softc *sc)
 266 {
 267         struct usb_page_search buf_res;
 268         struct xhci_hw_root *phwr;
 269         struct xhci_dev_ctx_addr *pdctxa;
 270         uint64_t addr;
 271         uint32_t temp;
 272         uint16_t i;
 273
 274         DPRINTF("\n");
 275
 276         sc->sc_capa_off = 0;
 277         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 278         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
 279         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 280
 281         DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
 282         DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
 283         DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
 284
 285         sc->sc_event_ccs = 1;
 286         sc->sc_event_idx = 0;
 287         sc->sc_command_ccs = 1;
 288         sc->sc_command_idx = 0;
 289
 290         DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
 291
 292         temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
 293
 294         DPRINTF("HCS0 = 0x%08x\n", temp);
 295
 296         if (XHCI_HCS0_CSZ(temp)) {
 297                 sc->sc_ctx_is_64_byte = 1;
 298                 device_printf(sc->sc_bus.parent, "64 byte context size.\n");
 299         } else {
 300                 sc->sc_ctx_is_64_byte = 0;
 301                 device_printf(sc->sc_bus.parent, "32 byte context size.\n");
 302         }
 303
 304         /* Reset controller */
 305         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
 306
 307         for (i = 0; i != 100; i++) {
 308                 usb_pause_mtx(NULL, hz / 100);
 309                 temp = XREAD4(sc, oper, XHCI_USBCMD) &
 310                     (XHCI_CMD_HCRST | XHCI_STS_CNR);
 311                 if (!temp)
 312                         break;
 313         }
 314
 315         if (temp) {
 316                 device_printf(sc->sc_bus.parent, "Controller "
 317                     "reset timeout.\n");
 318                 return (USB_ERR_IOERROR);
 319         }
 320
 321         if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
 322                 device_printf(sc->sc_bus.parent, "Controller does "
 323                     "not support 4K page size.\n");
 324                 return (USB_ERR_IOERROR);
 325         }
 326
 327         temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
 328
 329         i = XHCI_HCS1_N_PORTS(temp);
 330
 331         if (i == 0) {
 332                 device_printf(sc->sc_bus.parent, "Invalid number "
 333                     "of ports: %u\n", i);
 334                 return (USB_ERR_IOERROR);
 335         }
 336
 337         sc->sc_noport = i;
 338         sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
 339
 340         if (sc->sc_noslot > XHCI_MAX_DEVICES)
 341                 sc->sc_noslot = XHCI_MAX_DEVICES;
 342
 343         /* setup number of device slots */
 344
 345         DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
 346             XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
 347
 348         XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
 349
 350         DPRINTF("Max slots: %u\n", sc->sc_noslot);
 351
 352         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 353
 354         sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
 355
 356         if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
 357                 device_printf(sc->sc_bus.parent, "XHCI request "
 358                     "too many scratchpads\n");
 359                 return (USB_ERR_NOMEM);
 360         }
 361
 362         DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
 363
 364         temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
 365
 366         sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
 367             XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
 368
 369         temp = XREAD4(sc, oper, XHCI_USBSTS);
 370
 371         /* clear interrupts */
 372         XWRITE4(sc, oper, XHCI_USBSTS, temp);
 373         /* disable all device notifications */
 374         XWRITE4(sc, oper, XHCI_DNCTRL, 0);
 375
 376         /* setup device context base address */
 377         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
 378         pdctxa = buf_res.buffer;
 379         memset(pdctxa, 0, sizeof(*pdctxa));
 380
 381         addr = buf_res.physaddr;
 382         addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
 383
 384         /* slot 0 points to the table of scratchpad pointers */
 385         pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
 386
 387         for (i = 0; i != sc->sc_noscratch; i++) {
 388                 struct usb_page_search buf_scp;
 389                 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
 390                 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
 391         }
 392
 393         addr = buf_res.physaddr;
 394
 395         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 396         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 397         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 398         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 399
 400         /* Setup event table size */
 401
 402         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 403
 404         DPRINTF("HCS2=0x%08x\n", temp);
 405
 406         temp = XHCI_HCS2_ERST_MAX(temp);
 407         temp = 1U << temp;
 408         if (temp > XHCI_MAX_RSEG)
 409                 temp = XHCI_MAX_RSEG;
 410
 411         sc->sc_erst_max = temp;
 412
 413         DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
 414             XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp);
 415
 416         XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp));
 417
 418         /* Setup interrupt rate */
 419         XWRITE4(sc, runt, XHCI_IMOD(0), XHCI_IMOD_DEFAULT);
 420
 421         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 422
 423         phwr = buf_res.buffer;
 424         addr = buf_res.physaddr;
 425         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
 426
 427         /* reset hardware root structure */
 428         memset(phwr, 0, sizeof(*phwr));
 429
 430         phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
 431         phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
 432
 433         DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
 434
 435         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
 436         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
 437
 438         addr = (uint64_t)buf_res.physaddr;
 439
 440         DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
 441
 442         XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
 443         XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
 444
 445         /* Setup interrupter registers */
 446
 447         temp = XREAD4(sc, runt, XHCI_IMAN(0));
 448         temp |= XHCI_IMAN_INTR_ENA;
 449         XWRITE4(sc, runt, XHCI_IMAN(0), temp);
 450
 451         /* setup command ring control base address */
 452         addr = buf_res.physaddr;
 453         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 454
 455         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 456
 457         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 458         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 459
 460         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 461
 462         usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 463
 464         /* Go! */
 465         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
 466             XHCI_CMD_INTE | XHCI_CMD_HSEE);
 467
 468         for (i = 0; i != 100; i++) {
 469                 usb_pause_mtx(NULL, hz / 100);
 470                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 471                 if (!temp)
 472                         break;
 473         }
 474         if (temp) {
 475                 XWRITE4(sc, oper, XHCI_USBCMD, 0);
 476                 device_printf(sc->sc_bus.parent, "Run timeout.\n");
 477                 return (USB_ERR_IOERROR);
 478         }
 479
 480         /* catch any lost interrupts */
 481         xhci_do_poll(&sc->sc_bus);
 482
 483         return (0);
 484 }
 485
 486 usb_error_t
 487 xhci_halt_controller(struct xhci_softc *sc)
 488 {
 489         uint32_t temp;
 490         uint16_t i;
 491
 492         DPRINTF("\n");
 493
 494         sc->sc_capa_off = 0;
 495         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 496         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
 497         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 498
 499         /* Halt controller */
 500         XWRITE4(sc, oper, XHCI_USBCMD, 0);
 501
 502         for (i = 0; i != 100; i++) {
 503                 usb_pause_mtx(NULL, hz / 100);
 504                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 505                 if (temp)
 506                         break;
 507         }
 508
 509         if (!temp) {
 510                 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
 511                 return (USB_ERR_IOERROR);
 512         }
 513         return (0);
 514 }
 515
 516 usb_error_t
 517 xhci_init(struct xhci_softc *sc, device_t self)
 518 {
 519         /* initialise some bus fields */
 520         sc->sc_bus.parent = self;
 521
 522         /* set the bus revision */
 523         sc->sc_bus.usbrev = USB_REV_3_0;
 524
 525         /* set up the bus struct */
 526         sc->sc_bus.methods = &xhci_bus_methods;
 527
 528         /* setup devices array */
 529         sc->sc_bus.devices = sc->sc_devices;
 530         sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
 531
 532         /* setup command queue mutex and condition varible */
 533         cv_init(&sc->sc_cmd_cv, "CMDQ");
 534         sx_init(&sc->sc_cmd_sx, "CMDQ lock");
 535
 536         /* get all DMA memory */
 537         if (usb_bus_mem_alloc_all(&sc->sc_bus,
 538             USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
 539                 return (ENOMEM);
 540         }
 541
 542         sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
 543         sc->sc_config_msg[0].bus = &sc->sc_bus;
 544         sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
 545         sc->sc_config_msg[1].bus = &sc->sc_bus;
 546
 547         if (usb_proc_create(&sc->sc_config_proc,
 548             &sc->sc_bus.bus_mtx, device_get_nameunit(self), USB_PRI_MED)) {
 549                 printf("WARNING: Creation of XHCI configure "
 550                     "callback process failed.\n");
 551         }
 552         return (0);
 553 }
 554
 555 void
 556 xhci_uninit(struct xhci_softc *sc)
 557 {
 558         usb_proc_free(&sc->sc_config_proc);
 559
 560         usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 561
 562         cv_destroy(&sc->sc_cmd_cv);
 563         sx_destroy(&sc->sc_cmd_sx);
 564 }
 565
 566 static void
 567 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
 568 {
 569         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 570
 571         switch (state) {
 572         case USB_HW_POWER_SUSPEND:
 573                 DPRINTF("Stopping the XHCI\n");
 574                 xhci_halt_controller(sc);
 575                 break;
 576         case USB_HW_POWER_SHUTDOWN:
 577                 DPRINTF("Stopping the XHCI\n");
 578                 xhci_halt_controller(sc);
 579                 break;
 580         case USB_HW_POWER_RESUME:
 581                 DPRINTF("Starting the XHCI\n");
 582                 xhci_start_controller(sc);
 583                 break;
 584         default:
 585                 break;
 586         }
 587 }
 588
 589 static usb_error_t
 590 xhci_generic_done_sub(struct usb_xfer *xfer)
 591 {
 592         struct xhci_td *td;
 593         struct xhci_td *td_alt_next;
 594         uint32_t len;
 595         uint8_t status;
 596
 597         td = xfer->td_transfer_cache;
 598         td_alt_next = td->alt_next;
 599
 600         if (xfer->aframes != xfer->nframes)
 601                 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
 602
 603         while (1) {
 604
 605                 usb_pc_cpu_invalidate(td->page_cache);
 606
 607                 status = td->status;
 608                 len = td->remainder;
 609
 610                 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
 611                     xfer, (unsigned int)xfer->aframes,
 612                     (unsigned int)xfer->nframes,
 613                     (unsigned int)len, (unsigned int)td->len,
 614                     (unsigned int)status);
 615
 616                 /*
 617                  * Verify the status length and
 618                  * add the length to "frlengths[]":
 619                  */
 620                 if (len > td->len) {
 621                         /* should not happen */
 622                         DPRINTF("Invalid status length, "
 623                             "0x%04x/0x%04x bytes\n", len, td->len);
 624                         status = XHCI_TRB_ERROR_LENGTH;
 625                 } else if (xfer->aframes != xfer->nframes) {
 626                         xfer->frlengths[xfer->aframes] += td->len - len;
 627                 }
 628                 /* Check for last transfer */
 629                 if (((void *)td) == xfer->td_transfer_last) {
 630                         td = NULL;
 631                         break;
 632                 }
 633                 /* Check for transfer error */
 634                 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
 635                     status != XHCI_TRB_ERROR_SUCCESS) {
 636                         /* the transfer is finished */
 637                         td = NULL;
 638                         break;
 639                 }
 640                 /* Check for short transfer */
 641                 if (len > 0) {
 642                         if (xfer->flags_int.short_frames_ok ||
 643                             xfer->flags_int.isochronous_xfr ||
 644                             xfer->flags_int.control_xfr) {
 645                                 /* follow alt next */
 646                                 td = td->alt_next;
 647                         } else {
 648                                 /* the transfer is finished */
 649                                 td = NULL;
 650                         }
 651                         break;
 652                 }
 653                 td = td->obj_next;
 654
 655                 if (td->alt_next != td_alt_next) {
 656                         /* this USB frame is complete */
 657                         break;
 658                 }
 659         }
 660
 661         /* update transfer cache */
 662
 663         xfer->td_transfer_cache = td;
 664
 665         return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
 666             (status != XHCI_TRB_ERROR_SHORT_PKT &&
 667             status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
 668             USB_ERR_NORMAL_COMPLETION);
 669 }
 670
 671 static void
 672 xhci_generic_done(struct usb_xfer *xfer)
 673 {
 674         usb_error_t err = 0;
 675
 676         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
 677             xfer, xfer->endpoint);
 678
 679         /* reset scanner */
 680
 681         xfer->td_transfer_cache = xfer->td_transfer_first;
 682
 683         if (xfer->flags_int.control_xfr) {
 684
 685                 if (xfer->flags_int.control_hdr)
 686                         err = xhci_generic_done_sub(xfer);
 687
 688                 xfer->aframes = 1;
 689
 690                 if (xfer->td_transfer_cache == NULL)
 691                         goto done;
 692         }
 693
 694         while (xfer->aframes != xfer->nframes) {
 695
 696                 err = xhci_generic_done_sub(xfer);
 697                 xfer->aframes++;
 698
 699                 if (xfer->td_transfer_cache == NULL)
 700                         goto done;
 701         }
 702
 703         if (xfer->flags_int.control_xfr &&
 704             !xfer->flags_int.control_act)
 705                 err = xhci_generic_done_sub(xfer);
 706 done:
 707         /* transfer is complete */
 708         xhci_device_done(xfer, err);
 709 }
 710
 711 static void
 712 xhci_activate_transfer(struct usb_xfer *xfer)
 713 {
 714         struct xhci_td *td;
 715
 716         td = xfer->td_transfer_cache;
 717
 718         usb_pc_cpu_invalidate(td->page_cache);
 719
 720         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 721
 722                 /* activate the transfer */
 723
 724                 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
 725                 usb_pc_cpu_flush(td->page_cache);
 726
 727                 xhci_endpoint_doorbell(xfer);
 728         }
 729 }
 730
 731 static void
 732 xhci_skip_transfer(struct usb_xfer *xfer)
 733 {
 734         struct xhci_td *td;
 735         struct xhci_td *td_last;
 736
 737         td = xfer->td_transfer_cache;
 738         td_last = xfer->td_transfer_last;
 739
 740         td = td->alt_next;
 741
 742         usb_pc_cpu_invalidate(td->page_cache);
 743
 744         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 745
 746                 usb_pc_cpu_invalidate(td_last->page_cache);
 747
 748                 /* copy LINK TRB to current waiting location */
 749
 750                 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
 751                 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
 752                 usb_pc_cpu_flush(td->page_cache);
 753
 754                 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
 755                 usb_pc_cpu_flush(td->page_cache);
 756
 757                 xhci_endpoint_doorbell(xfer);
 758         }
 759 }
 760
 761 /*------------------------------------------------------------------------*
 762  *      xhci_check_transfer
 763  *------------------------------------------------------------------------*/
 764 static void
 765 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
 766 {
 767         int64_t offset;
 768         uint64_t td_event;
 769         uint32_t temp;
 770         uint32_t remainder;
 771         uint8_t status;
 772         uint8_t halted;
 773         uint8_t epno;
 774         uint8_t index;
 775         uint8_t i;
 776
 777         /* decode TRB */
 778         td_event = le64toh(trb->qwTrb0);
 779         temp = le32toh(trb->dwTrb2);
 780
 781         remainder = XHCI_TRB_2_REM_GET(temp);
 782         status = XHCI_TRB_2_ERROR_GET(temp);
 783
 784         temp = le32toh(trb->dwTrb3);
 785         epno = XHCI_TRB_3_EP_GET(temp);
 786         index = XHCI_TRB_3_SLOT_GET(temp);
 787
 788         /* check if error means halted */
 789         halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
 790             status != XHCI_TRB_ERROR_SUCCESS);
 791
 792         DPRINTF("slot=%u epno=%u remainder=%u status=%u\n",
 793             index, epno, remainder, status);
 794
 795         if (index > sc->sc_noslot) {
 796                 DPRINTF("Invalid slot.\n");
 797                 return;
 798         }
 799
 800         if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
 801                 DPRINTF("Invalid endpoint.\n");
 802                 return;
 803         }
 804
 805         /* try to find the USB transfer that generated the event */
 806         for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
 807                 struct usb_xfer *xfer;
 808                 struct xhci_td *td;
 809                 struct xhci_endpoint_ext *pepext;
 810
 811                 pepext = &sc->sc_hw.devs[index].endp[epno];
 812
 813                 xfer = pepext->xfer[i];
 814                 if (xfer == NULL)
 815                         continue;
 816
 817                 td = xfer->td_transfer_cache;
 818
 819                 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
 820                         (long long)td_event,
 821                         (long long)td->td_self,
 822                         (long long)td->td_self + sizeof(td->td_trb));
 823
 824                 /*
 825                  * NOTE: Some XHCI implementations might not trigger
 826                  * an event on the last LINK TRB so we need to
 827                  * consider both the last and second last event
 828                  * address as conditions for a successful transfer.
 829                  *
 830                  * NOTE: We assume that the XHCI will only trigger one
 831                  * event per chain of TRBs.
 832                  */
 833
 834                 offset = td_event - td->td_self;
 835
 836                 if (offset >= 0 &&
 837                     offset < (int64_t)sizeof(td->td_trb)) {
 838
 839                         usb_pc_cpu_invalidate(td->page_cache);
 840
 841                         /* compute rest of remainder, if any */
 842                         for (i = (offset / 16) + 1; i < td->ntrb; i++) {
 843                                 temp = le32toh(td->td_trb[i].dwTrb2);
 844                                 remainder += XHCI_TRB_2_BYTES_GET(temp);
 845                         }
 846
 847                         DPRINTFN(5, "New remainder: %u\n", remainder);
 848
 849                         /* clear isochronous transfer errors */
 850                         if (xfer->flags_int.isochronous_xfr) {
 851                                 if (halted) {
 852                                         halted = 0;
 853                                         status = XHCI_TRB_ERROR_SUCCESS;
 854                                         remainder = td->len;
 855                                 }
 856                         }
 857
 858                         /* "td->remainder" is verified later */
 859                         td->remainder = remainder;
 860                         td->status = status;
 861
 862                         usb_pc_cpu_flush(td->page_cache);
 863
 864                         /*
 865                          * 1) Last transfer descriptor makes the
 866                          * transfer done
 867                          */
 868                         if (((void *)td) == xfer->td_transfer_last) {
 869                                 DPRINTF("TD is last\n");
 870                                 xhci_generic_done(xfer);
 871                                 break;
 872                         }
 873
 874                         /*
 875                          * 2) Any kind of error makes the transfer
 876                          * done
 877                          */
 878                         if (halted) {
 879                                 DPRINTF("TD has I/O error\n");
 880                                 xhci_generic_done(xfer);
 881                                 break;
 882                         }
 883
 884                         /*
 885                          * 3) If there is no alternate next transfer,
 886                          * a short packet also makes the transfer done
 887                          */
 888                         if (td->remainder > 0) {
 889                                 if (td->alt_next == NULL) {
 890                                         DPRINTF(
 891                                             "short TD has no alternate next\n");
 892                                         xhci_generic_done(xfer);
 893                                         break;
 894                                 }
 895                                 DPRINTF("TD has short pkt\n");
 896                                 if (xfer->flags_int.short_frames_ok ||
 897                                     xfer->flags_int.isochronous_xfr ||
 898                                     xfer->flags_int.control_xfr) {
 899                                         /* follow the alt next */
 900                                         xfer->td_transfer_cache = td->alt_next;
 901                                         xhci_activate_transfer(xfer);
 902                                         break;
 903                                 }
 904                                 xhci_skip_transfer(xfer);
 905                                 xhci_generic_done(xfer);
 906                                 break;
 907                         }
 908
 909                         /*
 910                          * 4) Transfer complete - go to next TD
 911                          */
 912                         DPRINTF("Following next TD\n");
 913                         xfer->td_transfer_cache = td->obj_next;
 914                         xhci_activate_transfer(xfer);
 915                         break;          /* there should only be one match */
 916                 }
 917         }
 918 }
 919
 920 static void
 921 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
 922 {
 923         if (sc->sc_cmd_addr == trb->qwTrb0) {
 924                 DPRINTF("Received command event\n");
 925                 sc->sc_cmd_result[0] = trb->dwTrb2;
 926                 sc->sc_cmd_result[1] = trb->dwTrb3;
 927                 cv_signal(&sc->sc_cmd_cv);
 928         }
 929 }
 930
 931 static void
 932 xhci_interrupt_poll(struct xhci_softc *sc)
 933 {
 934         struct usb_page_search buf_res;
 935         struct xhci_hw_root *phwr;
 936         uint64_t addr;
 937         uint32_t temp;
 938         uint16_t i;
 939         uint8_t event;
 940         uint8_t j;
 941         uint8_t k;
 942         uint8_t t;
 943
 944         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 945
 946         phwr = buf_res.buffer;
 947
 948         /* Receive any events */
 949
 950         usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
 951
 952         i = sc->sc_event_idx;
 953         j = sc->sc_event_ccs;
 954         t = 2;
 955
 956         while (1) {
 957
 958                 temp = le32toh(phwr->hwr_events[i].dwTrb3);
 959
 960                 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
 961
 962                 if (j != k)
 963                         break;
 964
 965                 event = XHCI_TRB_3_TYPE_GET(temp);
 966
 967                 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
 968                     i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
 969                     (long)le32toh(phwr->hwr_events[i].dwTrb2),
 970                     (long)le32toh(phwr->hwr_events[i].dwTrb3));
 971
 972                 switch (event) {
 973                 case XHCI_TRB_EVENT_TRANSFER:
 974                         xhci_check_transfer(sc, &phwr->hwr_events[i]);
 975                         break;
 976                 case XHCI_TRB_EVENT_CMD_COMPLETE:
 977                         xhci_check_command(sc, &phwr->hwr_events[i]);
 978                         break;
 979                 default:
 980                         DPRINTF("Unhandled event = %u\n", event);
 981                         break;
 982                 }
 983
 984                 i++;
 985
 986                 if (i == XHCI_MAX_EVENTS) {
 987                         i = 0;
 988                         j ^= 1;
 989
 990                         /* check for timeout */
 991                         if (!--t)
 992                                 break;
 993                 }
 994         }
 995
 996         sc->sc_event_idx = i;
 997         sc->sc_event_ccs = j;
 998
 999         /*
1000          * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1001          * latched. That means to activate the register we need to
1002          * write both the low and high double word of the 64-bit
1003          * register.
1004          */
1005
1006         addr = (uint32_t)buf_res.physaddr;
1007         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1008
1009         /* try to clear busy bit */
1010         addr |= XHCI_ERDP_LO_BUSY;
1011
1012         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1013         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1014 }
1015
1016 static usb_error_t
1017 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1018     uint16_t timeout_ms)
1019 {
1020         struct usb_page_search buf_res;
1021         struct xhci_hw_root *phwr;
1022         uint64_t addr;
1023         uint32_t temp;
1024         uint8_t i;
1025         uint8_t j;
1026         int err;
1027
1028         XHCI_CMD_ASSERT_LOCKED(sc);
1029
1030         /* get hardware root structure */
1031
1032         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1033
1034         phwr = buf_res.buffer;
1035
1036         /* Queue command */
1037
1038         USB_BUS_LOCK(&sc->sc_bus);
1039
1040         i = sc->sc_command_idx;
1041         j = sc->sc_command_ccs;
1042
1043         DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1044             i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1045             (long long)le64toh(trb->qwTrb0),
1046             (long)le32toh(trb->dwTrb2),
1047             (long)le32toh(trb->dwTrb3));
1048
1049         phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1050         phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1051
1052         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1053
1054         temp = trb->dwTrb3;
1055
1056         if (j)
1057                 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1058         else
1059                 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1060
1061         temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1062
1063         phwr->hwr_commands[i].dwTrb3 = temp;
1064
1065         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1066
1067         addr = buf_res.physaddr;
1068         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1069
1070         sc->sc_cmd_addr = htole64(addr);
1071
1072         i++;
1073
1074         if (i == (XHCI_MAX_COMMANDS - 1)) {
1075
1076                 if (j) {
1077                         temp = htole32(XHCI_TRB_3_TC_BIT |
1078                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1079                             XHCI_TRB_3_CYCLE_BIT);
1080                 } else {
1081                         temp = htole32(XHCI_TRB_3_TC_BIT |
1082                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1083                 }
1084
1085                 phwr->hwr_commands[i].dwTrb3 = temp;
1086
1087                 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1088
1089                 i = 0;
1090                 j ^= 1;
1091         }
1092
1093         sc->sc_command_idx = i;
1094         sc->sc_command_ccs = j;
1095
1096         XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1097
1098         err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1099             USB_MS_TO_TICKS(timeout_ms));
1100
1101         if (err) {
1102                 DPRINTFN(0, "Command timeout!\n");
1103                 err = USB_ERR_TIMEOUT;
1104                 trb->dwTrb2 = 0;
1105                 trb->dwTrb3 = 0;
1106         } else {
1107                 temp = le32toh(sc->sc_cmd_result[0]);
1108                 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1109                         err = USB_ERR_IOERROR;
1110
1111                 trb->dwTrb2 = sc->sc_cmd_result[0];
1112                 trb->dwTrb3 = sc->sc_cmd_result[1];
1113         }
1114
1115         USB_BUS_UNLOCK(&sc->sc_bus);
1116
1117         return (err);
1118 }
1119
1120 #if 0
1121 static usb_error_t
1122 xhci_cmd_nop(struct xhci_softc *sc)
1123 {
1124         struct xhci_trb trb;
1125         uint32_t temp;
1126
1127         DPRINTF("\n");
1128
1129         trb.qwTrb0 = 0;
1130         trb.dwTrb2 = 0;
1131         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1132
1133         trb.dwTrb3 = htole32(temp);
1134
1135         return (xhci_do_command(sc, &trb, 100 /* ms */));
1136 }
1137 #endif
1138
1139 static usb_error_t
1140 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1141 {
1142         struct xhci_trb trb;
1143         uint32_t temp;
1144         usb_error_t err;
1145
1146         DPRINTF("\n");
1147
1148         trb.qwTrb0 = 0;
1149         trb.dwTrb2 = 0;
1150         trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1151
1152         err = xhci_do_command(sc, &trb, 100 /* ms */);
1153         if (err)
1154                 goto done;
1155
1156         temp = le32toh(trb.dwTrb3);
1157
1158         *pslot = XHCI_TRB_3_SLOT_GET(temp);
1159
1160 done:
1161         return (err);
1162 }
1163
1164 static usb_error_t
1165 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1166 {
1167         struct xhci_trb trb;
1168         uint32_t temp;
1169
1170         DPRINTF("\n");
1171
1172         trb.qwTrb0 = 0;
1173         trb.dwTrb2 = 0;
1174         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1175             XHCI_TRB_3_SLOT_SET(slot_id);
1176
1177         trb.dwTrb3 = htole32(temp);
1178
1179         return (xhci_do_command(sc, &trb, 100 /* ms */));
1180 }
1181
1182 static usb_error_t
1183 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1184     uint8_t bsr, uint8_t slot_id)
1185 {
1186         struct xhci_trb trb;
1187         uint32_t temp;
1188
1189         DPRINTF("\n");
1190
1191         trb.qwTrb0 = htole64(input_ctx);
1192         trb.dwTrb2 = 0;
1193         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1194             XHCI_TRB_3_SLOT_SET(slot_id);
1195
1196         if (bsr)
1197                 temp |= XHCI_TRB_3_BSR_BIT;
1198
1199         trb.dwTrb3 = htole32(temp);
1200
1201         return (xhci_do_command(sc, &trb, 500 /* ms */));
1202 }
1203
1204 static usb_error_t
1205 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1206 {
1207         struct usb_page_search buf_inp;
1208         struct usb_page_search buf_dev;
1209         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1210         struct xhci_hw_dev *hdev;
1211         struct xhci_dev_ctx *pdev;
1212         struct xhci_endpoint_ext *pepext;
1213         uint32_t temp;
1214         uint16_t mps;
1215         usb_error_t err;
1216         uint8_t index;
1217
1218         /* the root HUB case is not handled here */
1219         if (udev->parent_hub == NULL)
1220                 return (USB_ERR_INVAL);
1221
1222         index = udev->controller_slot_id;
1223
1224         hdev =  &sc->sc_hw.devs[index];
1225
1226         if (mtx != NULL)
1227                 mtx_unlock(mtx);
1228
1229         XHCI_CMD_LOCK(sc);
1230
1231         switch (hdev->state) {
1232         case XHCI_ST_DEFAULT:
1233         case XHCI_ST_ENABLED:
1234
1235                 hdev->state = XHCI_ST_ENABLED;
1236
1237                 /* set configure mask to slot and EP0 */
1238                 xhci_configure_mask(udev, 3, 0);
1239
1240                 /* configure input slot context structure */
1241                 err = xhci_configure_device(udev);
1242
1243                 if (err != 0) {
1244                         DPRINTF("Could not configure device\n");
1245                         break;
1246                 }
1247
1248                 /* configure input endpoint context structure */
1249                 switch (udev->speed) {
1250                 case USB_SPEED_LOW:
1251                 case USB_SPEED_FULL:
1252                         mps = 8;
1253                         break;
1254                 case USB_SPEED_HIGH:
1255                         mps = 64;
1256                         break;
1257                 default:
1258                         mps = 512;
1259                         break;
1260                 }
1261
1262                 pepext = xhci_get_endpoint_ext(udev,
1263                     &udev->ctrl_ep_desc);
1264                 err = xhci_configure_endpoint(udev,
1265                     &udev->ctrl_ep_desc, pepext->physaddr,
1266                     0, 1, 1, 0, mps, mps);
1267
1268                 if (err != 0) {
1269                         DPRINTF("Could not configure default endpoint\n");
1270                         break;
1271                 }
1272
1273                 /* execute set address command */
1274                 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1275
1276                 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1277                     (address == 0), index);
1278
1279                 if (err != 0) {
1280                         DPRINTF("Could not set address "
1281                             "for slot %u.\n", index);
1282                         if (address != 0)
1283                                 break;
1284                 }
1285
1286                 /* update device address to new value */
1287
1288                 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1289                 pdev = buf_dev.buffer;
1290                 usb_pc_cpu_invalidate(&hdev->device_pc);
1291
1292                 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1293                 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1294
1295                 /* update device state to new value */
1296
1297                 if (address != 0)
1298                         hdev->state = XHCI_ST_ADDRESSED;
1299                 else
1300                         hdev->state = XHCI_ST_DEFAULT;
1301                 break;
1302
1303         default:
1304                 DPRINTF("Wrong state for set address.\n");
1305                 err = USB_ERR_IOERROR;
1306                 break;
1307         }
1308         XHCI_CMD_UNLOCK(sc);
1309
1310         if (mtx != NULL)
1311                 mtx_lock(mtx);
1312
1313         return (err);
1314 }
1315
1316 static usb_error_t
1317 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1318     uint8_t deconfigure, uint8_t slot_id)
1319 {
1320         struct xhci_trb trb;
1321         uint32_t temp;
1322
1323         DPRINTF("\n");
1324
1325         trb.qwTrb0 = htole64(input_ctx);
1326         trb.dwTrb2 = 0;
1327         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1328             XHCI_TRB_3_SLOT_SET(slot_id);
1329
1330         if (deconfigure)
1331                 temp |= XHCI_TRB_3_DCEP_BIT;
1332
1333         trb.dwTrb3 = htole32(temp);
1334
1335         return (xhci_do_command(sc, &trb, 100 /* ms */));
1336 }
1337
1338 static usb_error_t
1339 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1340     uint8_t slot_id)
1341 {
1342         struct xhci_trb trb;
1343         uint32_t temp;
1344
1345         DPRINTF("\n");
1346
1347         trb.qwTrb0 = htole64(input_ctx);
1348         trb.dwTrb2 = 0;
1349         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1350             XHCI_TRB_3_SLOT_SET(slot_id);
1351         trb.dwTrb3 = htole32(temp);
1352
1353         return (xhci_do_command(sc, &trb, 100 /* ms */));
1354 }
1355
1356 static usb_error_t
1357 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1358     uint8_t ep_id, uint8_t slot_id)
1359 {
1360         struct xhci_trb trb;
1361         uint32_t temp;
1362
1363         DPRINTF("\n");
1364
1365         trb.qwTrb0 = 0;
1366         trb.dwTrb2 = 0;
1367         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1368             XHCI_TRB_3_SLOT_SET(slot_id) |
1369             XHCI_TRB_3_EP_SET(ep_id);
1370
1371         if (preserve)
1372                 temp |= XHCI_TRB_3_PRSV_BIT;
1373
1374         trb.dwTrb3 = htole32(temp);
1375
1376         return (xhci_do_command(sc, &trb, 100 /* ms */));
1377 }
1378
1379 static usb_error_t
1380 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1381     uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1382 {
1383         struct xhci_trb trb;
1384         uint32_t temp;
1385
1386         DPRINTF("\n");
1387
1388         trb.qwTrb0 = htole64(dequeue_ptr);
1389
1390         temp = XHCI_TRB_2_STREAM_SET(stream_id);
1391         trb.dwTrb2 = htole32(temp);
1392
1393         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1394             XHCI_TRB_3_SLOT_SET(slot_id) |
1395             XHCI_TRB_3_EP_SET(ep_id);
1396         trb.dwTrb3 = htole32(temp);
1397
1398         return (xhci_do_command(sc, &trb, 100 /* ms */));
1399 }
1400
1401 static usb_error_t
1402 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1403     uint8_t ep_id, uint8_t slot_id)
1404 {
1405         struct xhci_trb trb;
1406         uint32_t temp;
1407
1408         DPRINTF("\n");
1409
1410         trb.qwTrb0 = 0;
1411         trb.dwTrb2 = 0;
1412         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1413             XHCI_TRB_3_SLOT_SET(slot_id) |
1414             XHCI_TRB_3_EP_SET(ep_id);
1415
1416         if (suspend)
1417                 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1418
1419         trb.dwTrb3 = htole32(temp);
1420
1421         return (xhci_do_command(sc, &trb, 100 /* ms */));
1422 }
1423
1424 static usb_error_t
1425 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1426 {
1427         struct xhci_trb trb;
1428         uint32_t temp;
1429
1430         DPRINTF("\n");
1431
1432         trb.qwTrb0 = 0;
1433         trb.dwTrb2 = 0;
1434         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1435             XHCI_TRB_3_SLOT_SET(slot_id);
1436
1437         trb.dwTrb3 = htole32(temp);
1438
1439         return (xhci_do_command(sc, &trb, 100 /* ms */));
1440 }
1441
1442 /*------------------------------------------------------------------------*
1443  *      xhci_interrupt - XHCI interrupt handler
1444  *------------------------------------------------------------------------*/
1445 void
1446 xhci_interrupt(struct xhci_softc *sc)
1447 {
1448         uint32_t status;
1449         uint32_t iman;
1450
1451         USB_BUS_LOCK(&sc->sc_bus);
1452
1453         status = XREAD4(sc, oper, XHCI_USBSTS);
1454         if (status == 0)
1455                 goto done;
1456
1457         /* acknowledge interrupts */
1458
1459         XWRITE4(sc, oper, XHCI_USBSTS, status);
1460
1461         DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1462
1463         if (status & XHCI_STS_EINT) {
1464
1465                 /* acknowledge pending event */
1466                 iman = XREAD4(sc, runt, XHCI_IMAN(0));
1467
1468                 /* reset interrupt */
1469                 XWRITE4(sc, runt, XHCI_IMAN(0), iman);
1470
1471                 DPRINTFN(16, "real interrupt (iman=0x%08x)\n", iman);
1472
1473                 /* check for event(s) */
1474                 xhci_interrupt_poll(sc);
1475         }
1476
1477         if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1478             XHCI_STS_HSE | XHCI_STS_HCE)) {
1479
1480                 if (status & XHCI_STS_PCD) {
1481                         xhci_root_intr(sc);
1482                 }
1483
1484                 if (status & XHCI_STS_HCH) {
1485                         printf("%s: host controller halted\n",
1486                             __FUNCTION__);
1487                 }
1488
1489                 if (status & XHCI_STS_HSE) {
1490                         printf("%s: host system error\n",
1491                             __FUNCTION__);
1492                 }
1493
1494                 if (status & XHCI_STS_HCE) {
1495                         printf("%s: host controller error\n",
1496                            __FUNCTION__);
1497                 }
1498         }
1499 done:
1500         USB_BUS_UNLOCK(&sc->sc_bus);
1501 }
1502
1503 /*------------------------------------------------------------------------*
1504  *      xhci_timeout - XHCI timeout handler
1505  *------------------------------------------------------------------------*/
1506 static void
1507 xhci_timeout(void *arg)
1508 {
1509         struct usb_xfer *xfer = arg;
1510
1511         DPRINTF("xfer=%p\n", xfer);
1512
1513         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1514
1515         /* transfer is transferred */
1516         xhci_device_done(xfer, USB_ERR_TIMEOUT);
1517 }
1518
1519 static void
1520 xhci_do_poll(struct usb_bus *bus)
1521 {
1522         struct xhci_softc *sc = XHCI_BUS2SC(bus);
1523
1524         USB_BUS_LOCK(&sc->sc_bus);
1525         xhci_interrupt_poll(sc);
1526         USB_BUS_UNLOCK(&sc->sc_bus);
1527 }
1528
1529 static void
1530 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1531 {
1532         struct usb_page_search buf_res;
1533         struct xhci_td *td;
1534         struct xhci_td *td_next;
1535         struct xhci_td *td_alt_next;
1536         struct xhci_td *td_first;
1537         uint32_t buf_offset;
1538         uint32_t average;
1539         uint32_t len_old;
1540         uint32_t npkt_off;
1541         uint32_t dword;
1542         uint8_t shortpkt_old;
1543         uint8_t precompute;
1544         uint8_t x;
1545
1546         td_alt_next = NULL;
1547         buf_offset = 0;
1548         shortpkt_old = temp->shortpkt;
1549         len_old = temp->len;
1550         npkt_off = 0;
1551         precompute = 1;
1552
1553 restart:
1554
1555         td = temp->td;
1556         td_next = td_first = temp->td_next;
1557
1558         while (1) {
1559
1560                 if (temp->len == 0) {
1561
1562                         if (temp->shortpkt)
1563                                 break;
1564
1565                         /* send a Zero Length Packet, ZLP, last */
1566
1567                         temp->shortpkt = 1;
1568                         average = 0;
1569
1570                 } else {
1571
1572                         average = temp->average;
1573
1574                         if (temp->len < average) {
1575                                 if (temp->len % temp->max_packet_size) {
1576                                         temp->shortpkt = 1;
1577                                 }
1578                                 average = temp->len;
1579                         }
1580                 }
1581
1582                 if (td_next == NULL)
1583                         panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1584
1585                 /* get next TD */
1586
1587                 td = td_next;
1588                 td_next = td->obj_next;
1589
1590                 /* check if we are pre-computing */
1591
1592                 if (precompute) {
1593
1594                         /* update remaining length */
1595
1596                         temp->len -= average;
1597
1598                         continue;
1599                 }
1600                 /* fill out current TD */
1601
1602                 td->len = average;
1603                 td->remainder = 0;
1604                 td->status = 0;
1605
1606                 /* update remaining length */
1607
1608                 temp->len -= average;
1609
1610                 /* reset TRB index */
1611
1612                 x = 0;
1613
1614                 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1615                         /* immediate data */
1616
1617                         if (average > 8)
1618                                 average = 8;
1619
1620                         td->td_trb[0].qwTrb0 = 0;
1621
1622                         usbd_copy_out(temp->pc, temp->offset + buf_offset,
1623                            (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1624                            average);
1625
1626                         dword = XHCI_TRB_2_BYTES_SET(8) |
1627                             XHCI_TRB_2_TDSZ_SET(0) |
1628                             XHCI_TRB_2_IRQ_SET(0);
1629
1630                         td->td_trb[0].dwTrb2 = htole32(dword);
1631
1632                         dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1633                           XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1634
1635                         /* check wLength */
1636                         if (td->td_trb[0].qwTrb0 &
1637                            htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1638                                 if (td->td_trb[0].qwTrb0 & htole64(1))
1639                                         dword |= XHCI_TRB_3_TRT_IN;
1640                                 else
1641                                         dword |= XHCI_TRB_3_TRT_OUT;
1642                         }
1643
1644                         td->td_trb[0].dwTrb3 = htole32(dword);
1645 #ifdef USB_DEBUG
1646                         xhci_dump_trb(&td->td_trb[x]);
1647 #endif
1648                         x++;
1649
1650                 } else do {
1651
1652                         uint32_t npkt;
1653
1654                         /* fill out buffer pointers */
1655
1656                         if (average == 0) {
1657                                 npkt = 0;
1658                                 memset(&buf_res, 0, sizeof(buf_res));
1659                         } else {
1660                                 usbd_get_page(temp->pc, temp->offset +
1661                                     buf_offset, &buf_res);
1662
1663                                 /* get length to end of page */
1664                                 if (buf_res.length > average)
1665                                         buf_res.length = average;
1666
1667                                 /* check for maximum length */
1668                                 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1669                                         buf_res.length = XHCI_TD_PAGE_SIZE;
1670
1671                                 npkt_off += buf_res.length;
1672
1673                                 /* setup npkt */
1674                                 npkt = (len_old - npkt_off + temp->max_packet_size - 1) /
1675                                     temp->max_packet_size;
1676
1677                                 if (npkt > 31)
1678                                         npkt = 31;
1679                         }
1680
1681                         /* fill out TRB's */
1682                         td->td_trb[x].qwTrb0 =
1683                             htole64((uint64_t)buf_res.physaddr);
1684
1685                         dword =
1686                           XHCI_TRB_2_BYTES_SET(buf_res.length) |
1687                           XHCI_TRB_2_TDSZ_SET(npkt) |
1688                           XHCI_TRB_2_IRQ_SET(0);
1689
1690                         td->td_trb[x].dwTrb2 = htole32(dword);
1691
1692                         switch (temp->trb_type) {
1693                         case XHCI_TRB_TYPE_ISOCH:
1694                                 /* BEI: Interrupts are inhibited until EOT */
1695                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1696                                     XHCI_TRB_3_BEI_BIT |
1697                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1698                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1699                                 if (td != td_first) {
1700                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1701                                 } else if (temp->do_isoc_sync != 0) {
1702                                         temp->do_isoc_sync = 0;
1703                                         /* wait until "isoc_frame" */
1704                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1705                                             XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1706                                 } else {
1707                                         /* start data transfer at next interval */
1708                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1709                                             XHCI_TRB_3_ISO_SIA_BIT;
1710                                 }
1711                                 if (temp->direction == UE_DIR_IN)
1712                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1713                                 break;
1714                         case XHCI_TRB_TYPE_DATA_STAGE:
1715                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1716                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) |
1717                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1718                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1719                                 if (temp->direction == UE_DIR_IN)
1720                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1721                                 break;
1722                         case XHCI_TRB_TYPE_STATUS_STAGE:
1723                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1724                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) |
1725                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1726                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1727                                 if (temp->direction == UE_DIR_IN)
1728                                         dword |= XHCI_TRB_3_DIR_IN;
1729                                 break;
1730                         default:        /* XHCI_TRB_TYPE_NORMAL */
1731                                 /* BEI: Interrupts are inhibited until EOT */
1732                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1733                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) |
1734                                     XHCI_TRB_3_BEI_BIT |
1735                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1736                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1737                                 if (temp->direction == UE_DIR_IN)
1738                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1739                                 break;
1740                         }
1741                         td->td_trb[x].dwTrb3 = htole32(dword);
1742
1743                         average -= buf_res.length;
1744                         buf_offset += buf_res.length;
1745 #ifdef USB_DEBUG
1746                         xhci_dump_trb(&td->td_trb[x]);
1747 #endif
1748                         x++;
1749
1750                 } while (average != 0);
1751
1752                 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1753
1754                 /* store number of data TRB's */
1755
1756                 td->ntrb = x;
1757
1758                 DPRINTF("NTRB=%u\n", x);
1759
1760                 /* fill out link TRB */
1761
1762                 if (td_next != NULL) {
1763                         /* link the current TD with the next one */
1764                         td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1765                         DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1766                 } else {
1767                         /* this field will get updated later */
1768                         DPRINTF("NOLINK\n");
1769                 }
1770
1771                 dword = XHCI_TRB_2_IRQ_SET(0);
1772
1773                 td->td_trb[x].dwTrb2 = htole32(dword);
1774
1775                 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1776                     XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT;
1777
1778                 td->td_trb[x].dwTrb3 = htole32(dword);
1779
1780                 td->alt_next = td_alt_next;
1781 #ifdef USB_DEBUG
1782                 xhci_dump_trb(&td->td_trb[x]);
1783 #endif
1784                 usb_pc_cpu_flush(td->page_cache);
1785         }
1786
1787         if (precompute) {
1788                 precompute = 0;
1789
1790                 /* setup alt next pointer, if any */
1791                 if (temp->last_frame) {
1792                         td_alt_next = NULL;
1793                 } else {
1794                         /* we use this field internally */
1795                         td_alt_next = td_next;
1796                 }
1797
1798                 /* restore */
1799                 temp->shortpkt = shortpkt_old;
1800                 temp->len = len_old;
1801                 goto restart;
1802         }
1803
1804         /*
1805          * Remove cycle bit from the first TRB if we are
1806          * stepping them:
1807          */
1808         if (temp->step_td != 0) {
1809                 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1810                 usb_pc_cpu_flush(td_first->page_cache);
1811         }
1812
1813         /* remove chain bit because this is the last TRB in the chain */
1814         td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1815         td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1816
1817         usb_pc_cpu_flush(td->page_cache);
1818
1819         temp->td = td;
1820         temp->td_next = td_next;
1821 }
1822
1823 static void
1824 xhci_setup_generic_chain(struct usb_xfer *xfer)
1825 {
1826         struct xhci_std_temp temp;
1827         struct xhci_td *td;
1828         uint32_t x;
1829         uint32_t y;
1830         uint8_t mult;
1831
1832         temp.do_isoc_sync = 0;
1833         temp.step_td = 0;
1834         temp.tbc = 0;
1835         temp.tlbpc = 0;
1836         temp.average = xfer->max_hc_frame_size;
1837         temp.max_packet_size = xfer->max_packet_size;
1838         temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
1839         temp.pc = NULL;
1840         temp.last_frame = 0;
1841         temp.offset = 0;
1842         temp.multishort = xfer->flags_int.isochronous_xfr ||
1843             xfer->flags_int.control_xfr ||
1844             xfer->flags_int.short_frames_ok;
1845
1846         /* toggle the DMA set we are using */
1847         xfer->flags_int.curr_dma_set ^= 1;
1848
1849         /* get next DMA set */
1850         td = xfer->td_start[xfer->flags_int.curr_dma_set];
1851
1852         temp.td = NULL;
1853         temp.td_next = td;
1854
1855         xfer->td_transfer_first = td;
1856         xfer->td_transfer_cache = td;
1857
1858         if (xfer->flags_int.isochronous_xfr) {
1859                 uint8_t shift;
1860
1861                 /* compute multiplier for ISOCHRONOUS transfers */
1862                 mult = xfer->endpoint->ecomp ?
1863                     (xfer->endpoint->ecomp->bmAttributes & 3) : 0;
1864                 /* check for USB 2.0 multiplier */
1865                 if (mult == 0) {
1866                         mult = (xfer->endpoint->edesc->
1867                             wMaxPacketSize[1] >> 3) & 3;
1868                 }
1869                 /* range check */
1870                 if (mult > 2)
1871                         mult = 3;
1872                 else
1873                         mult++;
1874
1875                 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
1876
1877                 DPRINTF("MFINDEX=0x%08x\n", x);
1878
1879                 switch (usbd_get_speed(xfer->xroot->udev)) {
1880                 case USB_SPEED_FULL:
1881                         shift = 3;
1882                         temp.isoc_delta = 8;    /* 1ms */
1883                         x += temp.isoc_delta - 1;
1884                         x &= ~(temp.isoc_delta - 1);
1885                         break;
1886                 default:
1887                         shift = usbd_xfer_get_fps_shift(xfer);
1888                         temp.isoc_delta = 1U << shift;
1889                         x += temp.isoc_delta - 1;
1890                         x &= ~(temp.isoc_delta - 1);
1891                         /* simple frame load balancing */
1892                         x += xfer->endpoint->usb_uframe;
1893                         break;
1894                 }
1895
1896                 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
1897
1898                 if ((xfer->endpoint->is_synced == 0) ||
1899                     (y < (xfer->nframes << shift)) ||
1900                     (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
1901                         /*
1902                          * If there is data underflow or the pipe
1903                          * queue is empty we schedule the transfer a
1904                          * few frames ahead of the current frame
1905                          * position. Else two isochronous transfers
1906                          * might overlap.
1907                          */
1908                         xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
1909                         xfer->endpoint->is_synced = 1;
1910                         temp.do_isoc_sync = 1;
1911
1912                         DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
1913                 }
1914
1915                 /* compute isochronous completion time */
1916
1917                 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
1918
1919                 xfer->isoc_time_complete =
1920                     usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
1921                     (y / 8) + (((xfer->nframes << shift) + 7) / 8);
1922
1923                 x = 0;
1924                 temp.isoc_frame = xfer->endpoint->isoc_next;
1925                 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
1926
1927                 xfer->endpoint->isoc_next += xfer->nframes << shift;
1928
1929         } else if (xfer->flags_int.control_xfr) {
1930
1931                 /* check if we should prepend a setup message */
1932
1933                 if (xfer->flags_int.control_hdr) {
1934
1935                         temp.len = xfer->frlengths[0];
1936                         temp.pc = xfer->frbuffers + 0;
1937                         temp.shortpkt = temp.len ? 1 : 0;
1938                         temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
1939                         temp.direction = 0;
1940
1941                         /* check for last frame */
1942                         if (xfer->nframes == 1) {
1943                                 /* no STATUS stage yet, SETUP is last */
1944                                 if (xfer->flags_int.control_act)
1945                                         temp.last_frame = 1;
1946                         }
1947
1948                         xhci_setup_generic_chain_sub(&temp);
1949                 }
1950                 x = 1;
1951                 mult = 1;
1952                 temp.isoc_delta = 0;
1953                 temp.isoc_frame = 0;
1954                 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE;
1955         } else {
1956                 x = 0;
1957                 mult = 1;
1958                 temp.isoc_delta = 0;
1959                 temp.isoc_frame = 0;
1960                 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
1961         }
1962
1963         if (x != xfer->nframes) {
1964                 /* setup page_cache pointer */
1965                 temp.pc = xfer->frbuffers + x;
1966                 /* set endpoint direction */
1967                 temp.direction = UE_GET_DIR(xfer->endpointno);
1968         }
1969
1970         while (x != xfer->nframes) {
1971
1972                 /* DATA0 / DATA1 message */
1973
1974                 temp.len = xfer->frlengths[x];
1975                 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
1976                     x != 0 && temp.multishort == 0);
1977
1978                 x++;
1979
1980                 if (x == xfer->nframes) {
1981                         if (xfer->flags_int.control_xfr) {
1982                                 /* no STATUS stage yet, DATA is last */
1983                                 if (xfer->flags_int.control_act)
1984                                         temp.last_frame = 1;
1985                         } else {
1986                                 temp.last_frame = 1;
1987                         }
1988                 }
1989                 if (temp.len == 0) {
1990
1991                         /* make sure that we send an USB packet */
1992
1993                         temp.shortpkt = 0;
1994
1995                         temp.tbc = 0;
1996                         temp.tlbpc = mult - 1;
1997
1998                 } else if (xfer->flags_int.isochronous_xfr) {
1999
2000                         uint8_t tdpc;
2001
2002                         /*
2003                          * Isochronous transfers don't have short
2004                          * packet termination:
2005                          */
2006
2007                         temp.shortpkt = 1;
2008
2009                         /* isochronous transfers have a transfer limit */
2010
2011                         if (temp.len > xfer->max_frame_size)
2012                                 temp.len = xfer->max_frame_size;
2013
2014                         /* compute TD packet count */
2015                         tdpc = (temp.len + xfer->max_packet_size - 1) /
2016                             xfer->max_packet_size;
2017
2018                         temp.tbc = ((tdpc + mult - 1) / mult) - 1;
2019                         temp.tlbpc = (tdpc % mult);
2020
2021                         if (temp.tlbpc == 0)
2022                                 temp.tlbpc = mult - 1;
2023                         else
2024                                 temp.tlbpc--;
2025                 } else {
2026
2027                         /* regular data transfer */
2028
2029                         temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2030                 }
2031
2032                 xhci_setup_generic_chain_sub(&temp);
2033
2034                 if (xfer->flags_int.isochronous_xfr) {
2035                         temp.offset += xfer->frlengths[x - 1];
2036                         temp.isoc_frame += temp.isoc_delta;
2037                 } else {
2038                         /* get next Page Cache pointer */
2039                         temp.pc = xfer->frbuffers + x;
2040                 }
2041         }
2042
2043         /* check if we should append a status stage */
2044
2045         if (xfer->flags_int.control_xfr &&
2046             !xfer->flags_int.control_act) {
2047
2048                 /*
2049                  * Send a DATA1 message and invert the current
2050                  * endpoint direction.
2051                  */
2052                 temp.step_td = (xfer->nframes != 0);
2053                 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2054                 temp.len = 0;
2055                 temp.pc = NULL;
2056                 temp.shortpkt = 0;
2057                 temp.last_frame = 1;
2058                 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2059
2060                 xhci_setup_generic_chain_sub(&temp);
2061         }
2062
2063         td = temp.td;
2064
2065         /* must have at least one frame! */
2066
2067         xfer->td_transfer_last = td;
2068
2069         DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2070 }
2071
2072 static void
2073 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2074 {
2075         struct usb_page_search buf_res;
2076         struct xhci_dev_ctx_addr *pdctxa;
2077
2078         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2079
2080         pdctxa = buf_res.buffer;
2081
2082         DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2083
2084         pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2085
2086         usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2087 }
2088
2089 static usb_error_t
2090 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2091 {
2092         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2093         struct usb_page_search buf_inp;
2094         struct xhci_input_dev_ctx *pinp;
2095         uint32_t temp;
2096         uint8_t index;
2097         uint8_t x;
2098
2099         index = udev->controller_slot_id;
2100
2101         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2102
2103         pinp = buf_inp.buffer;
2104
2105         if (drop) {
2106                 mask &= XHCI_INCTX_NON_CTRL_MASK;
2107                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2108                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2109         } else {
2110                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0);
2111                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2112
2113                 /* find most significant set bit */
2114                 for (x = 31; x != 1; x--) {
2115                         if (mask & (1 << x))
2116                                 break;
2117                 }
2118
2119                 /* adjust */
2120                 x--;
2121
2122                 /* figure out maximum */
2123                 if (x > sc->sc_hw.devs[index].context_num) {
2124                         sc->sc_hw.devs[index].context_num = x;
2125                         temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2126                         temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2127                         temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2128                         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2129                 }
2130         }
2131         return (0);
2132 }
2133
2134 static usb_error_t
2135 xhci_configure_endpoint(struct usb_device *udev,
2136     struct usb_endpoint_descriptor *edesc, uint64_t ring_addr,
2137     uint16_t interval, uint8_t max_packet_count, uint8_t mult,
2138     uint8_t fps_shift, uint16_t max_packet_size, uint16_t max_frame_size)
2139 {
2140         struct usb_page_search buf_inp;
2141         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2142         struct xhci_input_dev_ctx *pinp;
2143         uint32_t temp;
2144         uint8_t index;
2145         uint8_t epno;
2146         uint8_t type;
2147
2148         index = udev->controller_slot_id;
2149
2150         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2151
2152         pinp = buf_inp.buffer;
2153
2154         epno = edesc->bEndpointAddress;
2155         type = edesc->bmAttributes & UE_XFERTYPE;
2156
2157         if (type == UE_CONTROL)
2158                 epno |= UE_DIR_IN;
2159
2160         epno = XHCI_EPNO2EPID(epno);
2161
2162         if (epno == 0)
2163                 return (USB_ERR_NO_PIPE);               /* invalid */
2164
2165         if (max_packet_count == 0)
2166                 return (USB_ERR_BAD_BUFSIZE);
2167
2168         max_packet_count--;
2169
2170         if (mult == 0)
2171                 return (USB_ERR_BAD_BUFSIZE);
2172
2173         temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2174             XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2175             XHCI_EPCTX_0_LSA_SET(0);
2176
2177         switch (udev->speed) {
2178         case USB_SPEED_FULL:
2179         case USB_SPEED_LOW:
2180                 /* 1ms -> 125us */
2181                 fps_shift += 3;
2182                 break;
2183         default:
2184                 break;
2185         }
2186
2187         switch (type) {
2188         case UE_INTERRUPT:
2189                 if (fps_shift > 3)
2190                         fps_shift--;
2191                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2192                 break;
2193         case UE_ISOCHRONOUS:
2194                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2195
2196                 switch (udev->speed) {
2197                 case USB_SPEED_SUPER:
2198                         if (mult > 3)
2199                                 mult = 3;
2200                         temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2201                         max_packet_count /= mult;
2202                         break;
2203                 default:
2204                         break;
2205                 }
2206                 break;
2207         default:
2208                 break;
2209         }
2210
2211         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2212
2213         temp =
2214             XHCI_EPCTX_1_HID_SET(0) |
2215             XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2216             XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2217
2218         if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) {
2219                 if (type != UE_ISOCHRONOUS)
2220                         temp |= XHCI_EPCTX_1_CERR_SET(3);
2221         }
2222
2223         switch (type) {
2224         case UE_CONTROL:
2225                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2226                 break;
2227         case UE_ISOCHRONOUS:
2228                 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2229                 break;
2230         case UE_BULK:
2231                 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2232                 break;
2233         default:
2234                 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2235                 break;
2236         }
2237
2238         /* check for IN direction */
2239         if (epno & 1)
2240                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2241
2242         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2243
2244         ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2245
2246         xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2247
2248         switch (edesc->bmAttributes & UE_XFERTYPE) {
2249         case UE_INTERRUPT:
2250         case UE_ISOCHRONOUS:
2251                 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2252                     XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2253                     max_frame_size));
2254                 break;
2255         case UE_CONTROL:
2256                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2257                 break;
2258         default:
2259                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2260                 break;
2261         }
2262
2263         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2264
2265 #ifdef USB_DEBUG
2266         xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2267 #endif
2268         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2269
2270         return (0);             /* success */
2271 }
2272
2273 static usb_error_t
2274 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2275 {
2276         struct xhci_endpoint_ext *pepext;
2277         struct usb_endpoint_ss_comp_descriptor *ecomp;
2278
2279         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2280             xfer->endpoint->edesc);
2281
2282         ecomp = xfer->endpoint->ecomp;
2283
2284         pepext->trb[0].dwTrb3 = 0;      /* halt any transfers */
2285         usb_pc_cpu_flush(pepext->page_cache);
2286
2287         return (xhci_configure_endpoint(xfer->xroot->udev,
2288             xfer->endpoint->edesc, pepext->physaddr,
2289             xfer->interval, xfer->max_packet_count,
2290             (ecomp != NULL) ? (ecomp->bmAttributes & 3) + 1 : 1,
2291             usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2292             xfer->max_frame_size));
2293 }
2294
2295 static usb_error_t
2296 xhci_configure_device(struct usb_device *udev)
2297 {
2298         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2299         struct usb_page_search buf_inp;
2300         struct usb_page_cache *pcinp;
2301         struct xhci_input_dev_ctx *pinp;
2302         struct usb_device *hubdev;
2303         uint32_t temp;
2304         uint32_t route;
2305         uint32_t rh_port;
2306         uint8_t is_hub;
2307         uint8_t index;
2308         uint8_t depth;
2309
2310         index = udev->controller_slot_id;
2311
2312         DPRINTF("index=%u\n", index);
2313
2314         pcinp = &sc->sc_hw.devs[index].input_pc;
2315
2316         usbd_get_page(pcinp, 0, &buf_inp);
2317
2318         pinp = buf_inp.buffer;
2319
2320         rh_port = 0;
2321         route = 0;
2322
2323         /* figure out route string and root HUB port number */
2324
2325         for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2326
2327                 if (hubdev->parent_hub == NULL)
2328                         break;
2329
2330                 depth = hubdev->parent_hub->depth;
2331
2332                 /*
2333                  * NOTE: HS/FS/LS devices and the SS root HUB can have
2334                  * more than 15 ports
2335                  */
2336
2337                 rh_port = hubdev->port_no;
2338
2339                 if (depth == 0)
2340                         break;
2341
2342                 if (rh_port > 15)
2343                         rh_port = 15;
2344
2345                 if (depth < 6)
2346                         route |= rh_port << (4 * (depth - 1));
2347         }
2348
2349         DPRINTF("Route=0x%08x\n", route);
2350
2351         temp = XHCI_SCTX_0_ROUTE_SET(route) |
2352             XHCI_SCTX_0_CTX_NUM_SET(
2353             sc->sc_hw.devs[index].context_num + 1);
2354
2355         switch (udev->speed) {
2356         case USB_SPEED_LOW:
2357                 temp |= XHCI_SCTX_0_SPEED_SET(2);
2358                 if (udev->parent_hs_hub != NULL &&
2359                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2360                     UDPROTO_HSHUBMTT) {
2361                         DPRINTF("Device inherits MTT\n");
2362                         temp |= XHCI_SCTX_0_MTT_SET(1);
2363                 }
2364                 break;
2365         case USB_SPEED_HIGH:
2366                 temp |= XHCI_SCTX_0_SPEED_SET(3);
2367                 if (sc->sc_hw.devs[index].nports != 0 &&
2368                     udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2369                         DPRINTF("HUB supports MTT\n");
2370                         temp |= XHCI_SCTX_0_MTT_SET(1);
2371                 }
2372                 break;
2373         case USB_SPEED_FULL:
2374                 temp |= XHCI_SCTX_0_SPEED_SET(1);
2375                 if (udev->parent_hs_hub != NULL &&
2376                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2377                     UDPROTO_HSHUBMTT) {
2378                         DPRINTF("Device inherits MTT\n");
2379                         temp |= XHCI_SCTX_0_MTT_SET(1);
2380                 }
2381                 break;
2382         default:
2383                 temp |= XHCI_SCTX_0_SPEED_SET(4);
2384                 break;
2385         }
2386
2387         is_hub = sc->sc_hw.devs[index].nports != 0 &&
2388             (udev->speed == USB_SPEED_SUPER ||
2389             udev->speed == USB_SPEED_HIGH);
2390
2391         if (is_hub)
2392                 temp |= XHCI_SCTX_0_HUB_SET(1);
2393
2394         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2395
2396         temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2397
2398         if (is_hub) {
2399                 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2400                     sc->sc_hw.devs[index].nports);
2401         }
2402
2403         switch (udev->speed) {
2404         case USB_SPEED_SUPER:
2405                 switch (sc->sc_hw.devs[index].state) {
2406                 case XHCI_ST_ADDRESSED:
2407                 case XHCI_ST_CONFIGURED:
2408                         /* enable power save */
2409                         temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2410                         break;
2411                 default:
2412                         /* disable power save */
2413                         break;
2414                 }
2415                 break;
2416         default:
2417                 break;
2418         }
2419
2420         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2421
2422         temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2423
2424         if (is_hub) {
2425                 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2426                     sc->sc_hw.devs[index].tt);
2427         }
2428
2429         hubdev = udev->parent_hs_hub;
2430
2431         /* check if we should activate the transaction translator */
2432         switch (udev->speed) {
2433         case USB_SPEED_FULL:
2434         case USB_SPEED_LOW:
2435                 if (hubdev != NULL) {
2436                         temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2437                             hubdev->controller_slot_id);
2438                         temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2439                             udev->hs_port_no);
2440                 }
2441                 break;
2442         default:
2443                 break;
2444         }
2445
2446         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2447
2448         temp = XHCI_SCTX_3_DEV_ADDR_SET(udev->address) |
2449             XHCI_SCTX_3_SLOT_STATE_SET(0);
2450
2451         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2452
2453 #ifdef USB_DEBUG
2454         xhci_dump_device(sc, &pinp->ctx_slot);
2455 #endif
2456         usb_pc_cpu_flush(pcinp);
2457
2458         return (0);             /* success */
2459 }
2460
2461 static usb_error_t
2462 xhci_alloc_device_ext(struct usb_device *udev)
2463 {
2464         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2465         struct usb_page_search buf_dev;
2466         struct usb_page_search buf_ep;
2467         struct xhci_trb *trb;
2468         struct usb_page_cache *pc;
2469         struct usb_page *pg;
2470         uint64_t addr;
2471         uint8_t index;
2472         uint8_t i;
2473
2474         index = udev->controller_slot_id;
2475
2476         pc = &sc->sc_hw.devs[index].device_pc;
2477         pg = &sc->sc_hw.devs[index].device_pg;
2478
2479         /* need to initialize the page cache */
2480         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2481
2482         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2483             (2 * sizeof(struct xhci_dev_ctx)) :
2484             sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2485                 goto error;
2486
2487         usbd_get_page(pc, 0, &buf_dev);
2488
2489         pc = &sc->sc_hw.devs[index].input_pc;
2490         pg = &sc->sc_hw.devs[index].input_pg;
2491
2492         /* need to initialize the page cache */
2493         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2494
2495         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2496             (2 * sizeof(struct xhci_input_dev_ctx)) :
2497             sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2498                 goto error;
2499         }
2500
2501         pc = &sc->sc_hw.devs[index].endpoint_pc;
2502         pg = &sc->sc_hw.devs[index].endpoint_pg;
2503
2504         /* need to initialize the page cache */
2505         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2506
2507         if (usb_pc_alloc_mem(pc, pg,
2508             sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) {
2509                 goto error;
2510         }
2511
2512         /* initialise all endpoint LINK TRBs */
2513
2514         for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2515
2516                 /* lookup endpoint TRB ring */
2517                 usbd_get_page(pc, (uintptr_t)&
2518                     ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep);
2519
2520                 /* get TRB pointer */
2521                 trb = buf_ep.buffer;
2522                 trb += XHCI_MAX_TRANSFERS - 1;
2523
2524                 /* get TRB start address */
2525                 addr = buf_ep.physaddr;
2526
2527                 /* create LINK TRB */
2528                 trb->qwTrb0 = htole64(addr);
2529                 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2530                 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2531                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2532         }
2533
2534         usb_pc_cpu_flush(pc);
2535
2536         xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2537
2538         return (0);
2539
2540 error:
2541         xhci_free_device_ext(udev);
2542
2543         return (USB_ERR_NOMEM);
2544 }
2545
2546 static void
2547 xhci_free_device_ext(struct usb_device *udev)
2548 {
2549         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2550         uint8_t index;
2551
2552         index = udev->controller_slot_id;
2553         xhci_set_slot_pointer(sc, index, 0);
2554
2555         usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2556         usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2557         usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc);
2558 }
2559
2560 static struct xhci_endpoint_ext *
2561 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2562 {
2563         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2564         struct xhci_endpoint_ext *pepext;
2565         struct usb_page_cache *pc;
2566         struct usb_page_search buf_ep;
2567         uint8_t epno;
2568         uint8_t index;
2569
2570         epno = edesc->bEndpointAddress;
2571         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2572                 epno |= UE_DIR_IN;
2573
2574         epno = XHCI_EPNO2EPID(epno);
2575
2576         index = udev->controller_slot_id;
2577
2578         pc = &sc->sc_hw.devs[index].endpoint_pc;
2579
2580         usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->trb[epno][0], &buf_ep);
2581
2582         pepext = &sc->sc_hw.devs[index].endp[epno];
2583         pepext->page_cache = pc;
2584         pepext->trb = buf_ep.buffer;
2585         pepext->physaddr = buf_ep.physaddr;
2586
2587         return (pepext);
2588 }
2589
2590 static void
2591 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2592 {
2593         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2594         uint8_t epno;
2595         uint8_t index;
2596
2597         epno = xfer->endpointno;
2598         if (xfer->flags_int.control_xfr)
2599                 epno |= UE_DIR_IN;
2600
2601         epno = XHCI_EPNO2EPID(epno);
2602         index = xfer->xroot->udev->controller_slot_id;
2603
2604         if (xfer->xroot->udev->flags.self_suspended == 0) {
2605                 XWRITE4(sc, door, XHCI_DOORBELL(index),
2606                     epno | XHCI_DB_SID_SET(/*xfer->stream_id*/ 0));
2607         }
2608 }
2609
2610 static void
2611 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2612 {
2613         struct xhci_endpoint_ext *pepext;
2614
2615         if (xfer->flags_int.bandwidth_reclaimed) {
2616                 xfer->flags_int.bandwidth_reclaimed = 0;
2617
2618                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2619                     xfer->endpoint->edesc);
2620
2621                 pepext->trb_used--;
2622
2623                 pepext->xfer[xfer->qh_pos] = NULL;
2624
2625                 if (error && pepext->trb_running != 0) {
2626                         pepext->trb_halted = 1;
2627                         pepext->trb_running = 0;
2628                 }
2629         }
2630 }
2631
2632 static usb_error_t
2633 xhci_transfer_insert(struct usb_xfer *xfer)
2634 {
2635         struct xhci_td *td_first;
2636         struct xhci_td *td_last;
2637         struct xhci_trb *trb_link;
2638         struct xhci_endpoint_ext *pepext;
2639         uint64_t addr;
2640         uint8_t i;
2641         uint8_t inext;
2642         uint8_t trb_limit;
2643
2644         DPRINTFN(8, "\n");
2645
2646         /* check if already inserted */
2647         if (xfer->flags_int.bandwidth_reclaimed) {
2648                 DPRINTFN(8, "Already in schedule\n");
2649                 return (0);
2650         }
2651
2652         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2653             xfer->endpoint->edesc);
2654
2655         td_first = xfer->td_transfer_first;
2656         td_last = xfer->td_transfer_last;
2657         addr = pepext->physaddr;
2658
2659         switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2660         case UE_CONTROL:
2661         case UE_INTERRUPT:
2662                 /* single buffered */
2663                 trb_limit = 1;
2664                 break;
2665         default:
2666                 /* multi buffered */
2667                 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2668                 break;
2669         }
2670
2671         if (pepext->trb_used >= trb_limit) {
2672                 DPRINTFN(8, "Too many TDs queued.\n");
2673                 return (USB_ERR_NOMEM);
2674         }
2675
2676         /* check for stopped condition, after putting transfer on interrupt queue */
2677         if (pepext->trb_running == 0) {
2678                 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2679
2680                 DPRINTFN(8, "Not running\n");
2681
2682                 /* start configuration */
2683                 (void)usb_proc_msignal(&sc->sc_config_proc,
2684                     &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2685                 return (0);
2686         }
2687
2688         pepext->trb_used++;
2689
2690         /* get current TRB index */
2691         i = pepext->trb_index;
2692
2693         /* get next TRB index */
2694         inext = (i + 1);
2695
2696         /* the last entry of the ring is a hardcoded link TRB */
2697         if (inext >= (XHCI_MAX_TRANSFERS - 1))
2698                 inext = 0;
2699
2700         /* compute terminating return address */
2701         addr += inext * sizeof(struct xhci_trb);
2702
2703         /* compute link TRB pointer */
2704         trb_link = td_last->td_trb + td_last->ntrb;
2705
2706         /* update next pointer of last link TRB */
2707         trb_link->qwTrb0 = htole64(addr);
2708         trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2709         trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2710             XHCI_TRB_3_CYCLE_BIT |
2711             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2712
2713 #ifdef USB_DEBUG
2714         xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2715 #endif
2716         usb_pc_cpu_flush(td_last->page_cache);
2717
2718         /* write ahead chain end marker */
2719
2720         pepext->trb[inext].qwTrb0 = 0;
2721         pepext->trb[inext].dwTrb2 = 0;
2722         pepext->trb[inext].dwTrb3 = 0;
2723
2724         /* update next pointer of link TRB */
2725
2726         pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2727         pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2728
2729 #ifdef USB_DEBUG
2730         xhci_dump_trb(&pepext->trb[i]);
2731 #endif
2732         usb_pc_cpu_flush(pepext->page_cache);
2733
2734         /* toggle cycle bit which activates the transfer chain */
2735
2736         pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2737             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2738
2739         usb_pc_cpu_flush(pepext->page_cache);
2740
2741         DPRINTF("qh_pos = %u\n", i);
2742
2743         pepext->xfer[i] = xfer;
2744
2745         xfer->qh_pos = i;
2746
2747         xfer->flags_int.bandwidth_reclaimed = 1;
2748
2749         pepext->trb_index = inext;
2750
2751         xhci_endpoint_doorbell(xfer);
2752
2753         return (0);
2754 }
2755
2756 static void
2757 xhci_root_intr(struct xhci_softc *sc)
2758 {
2759         uint16_t i;
2760
2761         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2762
2763         /* clear any old interrupt data */
2764         memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2765
2766         for (i = 1; i <= sc->sc_noport; i++) {
2767                 /* pick out CHANGE bits from the status register */
2768                 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
2769                     XHCI_PS_CSC | XHCI_PS_PEC |
2770                     XHCI_PS_OCC | XHCI_PS_WRC |
2771                     XHCI_PS_PRC | XHCI_PS_PLC |
2772                     XHCI_PS_CEC)) {
2773                         sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2774                         DPRINTF("port %d changed\n", i);
2775                 }
2776         }
2777         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2778             sizeof(sc->sc_hub_idata));
2779 }
2780
2781 /*------------------------------------------------------------------------*
2782  *      xhci_device_done - XHCI done handler
2783  *
2784  * NOTE: This function can be called two times in a row on
2785  * the same USB transfer. From close and from interrupt.
2786  *------------------------------------------------------------------------*/
2787 static void
2788 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
2789 {
2790         DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2791             xfer, xfer->endpoint, error);
2792
2793         /* remove transfer from HW queue */
2794         xhci_transfer_remove(xfer, error);
2795
2796         /* dequeue transfer and start next transfer */
2797         usbd_transfer_done(xfer, error);
2798 }
2799
2800 /*------------------------------------------------------------------------*
2801  * XHCI data transfer support (generic type)
2802  *------------------------------------------------------------------------*/
2803 static void
2804 xhci_device_generic_open(struct usb_xfer *xfer)
2805 {
2806         if (xfer->flags_int.isochronous_xfr) {
2807                 switch (xfer->xroot->udev->speed) {
2808                 case USB_SPEED_FULL:
2809                         break;
2810                 default:
2811                         usb_hs_bandwidth_alloc(xfer);
2812                         break;
2813                 }
2814         }
2815 }
2816
2817 static void
2818 xhci_device_generic_close(struct usb_xfer *xfer)
2819 {
2820         DPRINTF("\n");
2821
2822         xhci_device_done(xfer, USB_ERR_CANCELLED);
2823
2824         if (xfer->flags_int.isochronous_xfr) {
2825                 switch (xfer->xroot->udev->speed) {
2826                 case USB_SPEED_FULL:
2827                         break;
2828                 default:
2829                         usb_hs_bandwidth_free(xfer);
2830                         break;
2831                 }
2832         }
2833 }
2834
2835 static void
2836 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
2837     struct usb_xfer *enter_xfer)
2838 {
2839         struct usb_xfer *xfer;
2840
2841         /* check if there is a current transfer */
2842         xfer = ep->endpoint_q.curr;
2843         if (xfer == NULL)
2844                 return;
2845
2846         /*
2847          * Check if the current transfer is started and then pickup
2848          * the next one, if any. Else wait for next start event due to
2849          * block on failure feature.
2850          */
2851         if (!xfer->flags_int.bandwidth_reclaimed)
2852                 return;
2853
2854         xfer = TAILQ_FIRST(&ep->endpoint_q.head);
2855         if (xfer == NULL) {
2856                 /*
2857                  * In case of enter we have to consider that the
2858                  * transfer is queued by the USB core after the enter
2859                  * method is called.
2860                  */
2861                 xfer = enter_xfer;
2862
2863                 if (xfer == NULL)
2864                         return;
2865         }
2866
2867         /* try to multi buffer */
2868         xhci_transfer_insert(xfer);
2869 }
2870
2871 static void
2872 xhci_device_generic_enter(struct usb_xfer *xfer)
2873 {
2874         DPRINTF("\n");
2875
2876         /* setup TD's and QH */
2877         xhci_setup_generic_chain(xfer);
2878
2879         xhci_device_generic_multi_enter(xfer->endpoint, xfer);
2880 }
2881
2882 static void
2883 xhci_device_generic_start(struct usb_xfer *xfer)
2884 {
2885         DPRINTF("\n");
2886
2887         /* try to insert xfer on HW queue */
2888         xhci_transfer_insert(xfer);
2889
2890         /* try to multi buffer */
2891         xhci_device_generic_multi_enter(xfer->endpoint, NULL);
2892
2893         /* add transfer last on interrupt queue */
2894         usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
2895
2896         /* start timeout, if any */
2897         if (xfer->timeout != 0)
2898                 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
2899 }
2900
2901 struct usb_pipe_methods xhci_device_generic_methods =
2902 {
2903         .open = xhci_device_generic_open,
2904         .close = xhci_device_generic_close,
2905         .enter = xhci_device_generic_enter,
2906         .start = xhci_device_generic_start,
2907 };
2908
2909 /*------------------------------------------------------------------------*
2910  * xhci root HUB support
2911  *------------------------------------------------------------------------*
2912  * Simulate a hardware HUB by handling all the necessary requests.
2913  *------------------------------------------------------------------------*/
2914
2915 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
2916
2917 static const
2918 struct usb_device_descriptor xhci_devd =
2919 {
2920         .bLength = sizeof(xhci_devd),
2921         .bDescriptorType = UDESC_DEVICE,        /* type */
2922         HSETW(.bcdUSB, 0x0300),                 /* USB version */
2923         .bDeviceClass = UDCLASS_HUB,            /* class */
2924         .bDeviceSubClass = UDSUBCLASS_HUB,      /* subclass */
2925         .bDeviceProtocol = UDPROTO_SSHUB,       /* protocol */
2926         .bMaxPacketSize = 9,                    /* max packet size */
2927         HSETW(.idVendor, 0x0000),               /* vendor */
2928         HSETW(.idProduct, 0x0000),              /* product */
2929         HSETW(.bcdDevice, 0x0100),              /* device version */
2930         .iManufacturer = 1,
2931         .iProduct = 2,
2932         .iSerialNumber = 0,
2933         .bNumConfigurations = 1,                /* # of configurations */
2934 };
2935
2936 static const
2937 struct xhci_bos_desc xhci_bosd = {
2938         .bosd = {
2939                 .bLength = sizeof(xhci_bosd.bosd),
2940                 .bDescriptorType = UDESC_BOS,
2941                 HSETW(.wTotalLength, sizeof(xhci_bosd)),
2942                 .bNumDeviceCaps = 3,
2943         },
2944         .usb2extd = {
2945                 .bLength = sizeof(xhci_bosd.usb2extd),
2946                 .bDescriptorType = 1,
2947                 .bDevCapabilityType = 2,
2948                 .bmAttributes[0] = 2,
2949         },
2950         .usbdcd = {
2951                 .bLength = sizeof(xhci_bosd.usbdcd),
2952                 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
2953                 .bDevCapabilityType = 3,
2954                 .bmAttributes = 0, /* XXX */
2955                 HSETW(.wSpeedsSupported, 0x000C),
2956                 .bFunctionalitySupport = 8,
2957                 .bU1DevExitLat = 255,   /* dummy - not used */
2958                 .wU2DevExitLat = { 0x00, 0x08 },
2959         },
2960         .cidd = {
2961                 .bLength = sizeof(xhci_bosd.cidd),
2962                 .bDescriptorType = 1,
2963                 .bDevCapabilityType = 4,
2964                 .bReserved = 0,
2965                 .bContainerID = 0, /* XXX */
2966         },
2967 };
2968
2969 static const
2970 struct xhci_config_desc xhci_confd = {
2971         .confd = {
2972                 .bLength = sizeof(xhci_confd.confd),
2973                 .bDescriptorType = UDESC_CONFIG,
2974                 .wTotalLength[0] = sizeof(xhci_confd),
2975                 .bNumInterface = 1,
2976                 .bConfigurationValue = 1,
2977                 .iConfiguration = 0,
2978                 .bmAttributes = UC_SELF_POWERED,
2979                 .bMaxPower = 0          /* max power */
2980         },
2981         .ifcd = {
2982                 .bLength = sizeof(xhci_confd.ifcd),
2983                 .bDescriptorType = UDESC_INTERFACE,
2984                 .bNumEndpoints = 1,
2985                 .bInterfaceClass = UICLASS_HUB,
2986                 .bInterfaceSubClass = UISUBCLASS_HUB,
2987                 .bInterfaceProtocol = 0,
2988         },
2989         .endpd = {
2990                 .bLength = sizeof(xhci_confd.endpd),
2991                 .bDescriptorType = UDESC_ENDPOINT,
2992                 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
2993                 .bmAttributes = UE_INTERRUPT,
2994                 .wMaxPacketSize[0] = 2,         /* max 15 ports */
2995                 .bInterval = 255,
2996         },
2997         .endpcd = {
2998                 .bLength = sizeof(xhci_confd.endpcd),
2999                 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3000                 .bMaxBurst = 0,
3001                 .bmAttributes = 0,
3002         },
3003 };
3004
3005 static const
3006 struct usb_hub_ss_descriptor xhci_hubd = {
3007         .bLength = sizeof(xhci_hubd),
3008         .bDescriptorType = UDESC_SS_HUB,
3009 };
3010
3011 static usb_error_t
3012 xhci_roothub_exec(struct usb_device *udev,
3013     struct usb_device_request *req, const void **pptr, uint16_t *plength)
3014 {
3015         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3016         const char *str_ptr;
3017         const void *ptr;
3018         uint32_t port;
3019         uint32_t v;
3020         uint16_t len;
3021         uint16_t i;
3022         uint16_t value;
3023         uint16_t index;
3024         uint8_t j;
3025         usb_error_t err;
3026
3027         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3028
3029         /* buffer reset */
3030         ptr = (const void *)&sc->sc_hub_desc;
3031         len = 0;
3032         err = 0;
3033
3034         value = UGETW(req->wValue);
3035         index = UGETW(req->wIndex);
3036
3037         DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3038             "wValue=0x%04x wIndex=0x%04x\n",
3039             req->bmRequestType, req->bRequest,
3040             UGETW(req->wLength), value, index);
3041
3042 #define C(x,y) ((x) | ((y) << 8))
3043         switch (C(req->bRequest, req->bmRequestType)) {
3044         case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3045         case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3046         case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3047                 /*
3048                  * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3049                  * for the integrated root hub.
3050                  */
3051                 break;
3052         case C(UR_GET_CONFIG, UT_READ_DEVICE):
3053                 len = 1;
3054                 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3055                 break;
3056         case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3057                 switch (value >> 8) {
3058                 case UDESC_DEVICE:
3059                         if ((value & 0xff) != 0) {
3060                                 err = USB_ERR_IOERROR;
3061                                 goto done;
3062                         }
3063                         len = sizeof(xhci_devd);
3064                         ptr = (const void *)&xhci_devd;
3065                         break;
3066
3067                 case UDESC_BOS:
3068                         if ((value & 0xff) != 0) {
3069                                 err = USB_ERR_IOERROR;
3070                                 goto done;
3071                         }
3072                         len = sizeof(xhci_bosd);
3073                         ptr = (const void *)&xhci_bosd;
3074                         break;
3075
3076                 case UDESC_CONFIG:
3077                         if ((value & 0xff) != 0) {
3078                                 err = USB_ERR_IOERROR;
3079                                 goto done;
3080                         }
3081                         len = sizeof(xhci_confd);
3082                         ptr = (const void *)&xhci_confd;
3083                         break;
3084
3085                 case UDESC_STRING:
3086                         switch (value & 0xff) {
3087                         case 0: /* Language table */
3088                                 str_ptr = "\001";
3089                                 break;
3090
3091                         case 1: /* Vendor */
3092                                 str_ptr = sc->sc_vendor;
3093                                 break;
3094
3095                         case 2: /* Product */
3096                                 str_ptr = "XHCI root HUB";
3097                                 break;
3098
3099                         default:
3100                                 str_ptr = "";
3101                                 break;
3102                         }
3103
3104                         len = usb_make_str_desc(
3105                             sc->sc_hub_desc.temp,
3106                             sizeof(sc->sc_hub_desc.temp),
3107                             str_ptr);
3108                         break;
3109
3110                 default:
3111                         err = USB_ERR_IOERROR;
3112                         goto done;
3113                 }
3114                 break;
3115         case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3116                 len = 1;
3117                 sc->sc_hub_desc.temp[0] = 0;
3118                 break;
3119         case C(UR_GET_STATUS, UT_READ_DEVICE):
3120                 len = 2;
3121                 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3122                 break;
3123         case C(UR_GET_STATUS, UT_READ_INTERFACE):
3124         case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3125                 len = 2;
3126                 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3127                 break;
3128         case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3129                 if (value >= XHCI_MAX_DEVICES) {
3130                         err = USB_ERR_IOERROR;
3131                         goto done;
3132                 }
3133                 break;
3134         case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3135                 if (value != 0 && value != 1) {
3136                         err = USB_ERR_IOERROR;
3137                         goto done;
3138                 }
3139                 sc->sc_conf = value;
3140                 break;
3141         case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3142                 break;
3143         case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3144         case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3145         case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3146                 err = USB_ERR_IOERROR;
3147                 goto done;
3148         case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3149                 break;
3150         case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3151                 break;
3152                 /* Hub requests */
3153         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3154                 break;
3155         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3156                 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3157
3158                 if ((index < 1) ||
3159                     (index > sc->sc_noport)) {
3160                         err = USB_ERR_IOERROR;
3161                         goto done;
3162                 }
3163                 port = XHCI_PORTSC(index);
3164
3165                 v = XREAD4(sc, oper, port);
3166                 i = XHCI_PS_PLS_GET(v);
3167                 v &= ~XHCI_PS_CLEAR;
3168
3169                 switch (value) {
3170                 case UHF_C_BH_PORT_RESET:
3171                         XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3172                         break;
3173                 case UHF_C_PORT_CONFIG_ERROR:
3174                         XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3175                         break;
3176                 case UHF_C_PORT_SUSPEND:
3177                 case UHF_C_PORT_LINK_STATE:
3178                         XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3179                         break;
3180                 case UHF_C_PORT_CONNECTION:
3181                         XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3182                         break;
3183                 case UHF_C_PORT_ENABLE:
3184                         XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3185                         break;
3186                 case UHF_C_PORT_OVER_CURRENT:
3187                         XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3188                         break;
3189                 case UHF_C_PORT_RESET:
3190                         XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3191                         break;
3192                 case UHF_PORT_ENABLE:
3193                         XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3194                         break;
3195                 case UHF_PORT_POWER:
3196                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3197                         break;
3198                 case UHF_PORT_INDICATOR:
3199                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3200                         break;
3201                 case UHF_PORT_SUSPEND:
3202
3203                         /* U3 -> U15 */
3204                         if (i == 3) {
3205                                 XWRITE4(sc, oper, port, v |
3206                                     XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3207                         }
3208
3209                         /* wait 20ms for resume sequence to complete */
3210                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3211
3212                         /* U0 */
3213                         XWRITE4(sc, oper, port, v |
3214                             XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3215                         break;
3216                 default:
3217                         err = USB_ERR_IOERROR;
3218                         goto done;
3219                 }
3220                 break;
3221
3222         case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3223                 if ((value & 0xff) != 0) {
3224                         err = USB_ERR_IOERROR;
3225                         goto done;
3226                 }
3227
3228                 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3229
3230                 sc->sc_hub_desc.hubd = xhci_hubd;
3231
3232                 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3233
3234                 if (XHCI_HCS0_PPC(v))
3235                         i = UHD_PWR_INDIVIDUAL;
3236                 else
3237                         i = UHD_PWR_GANGED;
3238
3239                 if (XHCI_HCS0_PIND(v))
3240                         i |= UHD_PORT_IND;
3241
3242                 i |= UHD_OC_INDIVIDUAL;
3243
3244                 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3245
3246                 /* see XHCI section 5.4.9: */
3247                 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3248
3249                 for (j = 1; j <= sc->sc_noport; j++) {
3250
3251                         v = XREAD4(sc, oper, XHCI_PORTSC(j));
3252                         if (v & XHCI_PS_DR) {
3253                                 sc->sc_hub_desc.hubd.
3254                                     DeviceRemovable[j / 8] |= 1U << (j % 8);
3255                         }
3256                 }
3257                 len = sc->sc_hub_desc.hubd.bLength;
3258                 break;
3259
3260         case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3261                 len = 16;
3262                 memset(sc->sc_hub_desc.temp, 0, 16);
3263                 break;
3264
3265         case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3266                 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3267
3268                 if ((index < 1) ||
3269                     (index > sc->sc_noport)) {
3270                         err = USB_ERR_IOERROR;
3271                         goto done;
3272                 }
3273
3274                 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3275
3276                 DPRINTFN(9, "port status=0x%08x\n", v);
3277
3278                 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3279
3280                 switch (XHCI_PS_SPEED_GET(v)) {
3281                 case 3:
3282                         i |= UPS_HIGH_SPEED;
3283                         break;
3284                 case 2:
3285                         i |= UPS_LOW_SPEED;
3286                         break;
3287                 case 1:
3288                         /* FULL speed */
3289                         break;
3290                 default:
3291                         i |= UPS_OTHER_SPEED;
3292                         break;
3293                 }
3294
3295                 if (v & XHCI_PS_CCS)
3296                         i |= UPS_CURRENT_CONNECT_STATUS;
3297                 if (v & XHCI_PS_PED)
3298                         i |= UPS_PORT_ENABLED;
3299                 if (v & XHCI_PS_OCA)
3300                         i |= UPS_OVERCURRENT_INDICATOR;
3301                 if (v & XHCI_PS_PR)
3302                         i |= UPS_RESET;
3303                 if (v & XHCI_PS_PP) {
3304                         /*
3305                          * The USB 3.0 RH is using the
3306                          * USB 2.0's power bit
3307                          */
3308                         i |= UPS_PORT_POWER;
3309                 }
3310                 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3311
3312                 i = 0;
3313                 if (v & XHCI_PS_CSC)
3314                         i |= UPS_C_CONNECT_STATUS;
3315                 if (v & XHCI_PS_PEC)
3316                         i |= UPS_C_PORT_ENABLED;
3317                 if (v & XHCI_PS_OCC)
3318                         i |= UPS_C_OVERCURRENT_INDICATOR;
3319                 if (v & XHCI_PS_WRC)
3320                         i |= UPS_C_BH_PORT_RESET;
3321                 if (v & XHCI_PS_PRC)
3322                         i |= UPS_C_PORT_RESET;
3323                 if (v & XHCI_PS_PLC)
3324                         i |= UPS_C_PORT_LINK_STATE;
3325                 if (v & XHCI_PS_CEC)
3326                         i |= UPS_C_PORT_CONFIG_ERROR;
3327
3328                 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3329                 len = sizeof(sc->sc_hub_desc.ps);
3330                 break;
3331
3332         case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3333                 err = USB_ERR_IOERROR;
3334                 goto done;
3335
3336         case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3337                 break;
3338
3339         case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3340
3341                 i = index >> 8;
3342                 index &= 0x00FF;
3343
3344                 if ((index < 1) ||
3345                     (index > sc->sc_noport)) {
3346                         err = USB_ERR_IOERROR;
3347                         goto done;
3348                 }
3349
3350                 port = XHCI_PORTSC(index);
3351                 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3352
3353                 switch (value) {
3354                 case UHF_PORT_U1_TIMEOUT:
3355                         if (XHCI_PS_SPEED_GET(v) != 4) {
3356                                 err = USB_ERR_IOERROR;
3357                                 goto done;
3358                         }
3359                         port = XHCI_PORTPMSC(index);
3360                         v = XREAD4(sc, oper, port);
3361                         v &= ~XHCI_PM3_U1TO_SET(0xFF);
3362                         v |= XHCI_PM3_U1TO_SET(i);
3363                         XWRITE4(sc, oper, port, v);
3364                         break;
3365                 case UHF_PORT_U2_TIMEOUT:
3366                         if (XHCI_PS_SPEED_GET(v) != 4) {
3367                                 err = USB_ERR_IOERROR;
3368                                 goto done;
3369                         }
3370                         port = XHCI_PORTPMSC(index);
3371                         v = XREAD4(sc, oper, port);
3372                         v &= ~XHCI_PM3_U2TO_SET(0xFF);
3373                         v |= XHCI_PM3_U2TO_SET(i);
3374                         XWRITE4(sc, oper, port, v);
3375                         break;
3376                 case UHF_BH_PORT_RESET:
3377                         XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3378                         break;
3379                 case UHF_PORT_LINK_STATE:
3380                         XWRITE4(sc, oper, port, v |
3381                             XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3382                         /* 4ms settle time */
3383                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3384                         break;
3385                 case UHF_PORT_ENABLE:
3386                         DPRINTFN(3, "set port enable %d\n", index);
3387                         break;
3388                 case UHF_PORT_SUSPEND:
3389                         DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3390                         j = XHCI_PS_SPEED_GET(v);
3391                         if ((j < 1) || (j > 3)) {
3392                                 /* non-supported speed */
3393                                 err = USB_ERR_IOERROR;
3394                                 goto done;
3395                         }
3396                         XWRITE4(sc, oper, port, v |
3397                             XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3398                         break;
3399                 case UHF_PORT_RESET:
3400                         DPRINTFN(6, "reset port %d\n", index);
3401                         XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3402                         break;
3403                 case UHF_PORT_POWER:
3404                         DPRINTFN(3, "set port power %d\n", index);
3405                         XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3406                         break;
3407                 case UHF_PORT_TEST:
3408                         DPRINTFN(3, "set port test %d\n", index);
3409                         break;
3410                 case UHF_PORT_INDICATOR:
3411                         DPRINTFN(3, "set port indicator %d\n", index);
3412
3413                         v &= ~XHCI_PS_PIC_SET(3);
3414                         v |= XHCI_PS_PIC_SET(1);
3415
3416                         XWRITE4(sc, oper, port, v);
3417                         break;
3418                 default:
3419                         err = USB_ERR_IOERROR;
3420                         goto done;
3421                 }
3422                 break;
3423
3424         case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3425         case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3426         case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3427         case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3428                 break;
3429         default:
3430                 err = USB_ERR_IOERROR;
3431                 goto done;
3432         }
3433 done:
3434         *plength = len;
3435         *pptr = ptr;
3436         return (err);
3437 }
3438
3439 static void
3440 xhci_xfer_setup(struct usb_setup_params *parm)
3441 {
3442         struct usb_page_search page_info;
3443         struct usb_page_cache *pc;
3444         struct xhci_softc *sc;
3445         struct usb_xfer *xfer;
3446         void *last_obj;
3447         uint32_t ntd;
3448         uint32_t n;
3449
3450         sc = XHCI_BUS2SC(parm->udev->bus);
3451         xfer = parm->curr_xfer;
3452
3453         /*
3454          * The proof for the "ntd" formula is illustrated like this:
3455          *
3456          * +------------------------------------+
3457          * |                                    |
3458          * |         |remainder ->              |
3459          * |   +-----+---+                      |
3460          * |   | xxx | x | frm 0                |
3461          * |   +-----+---++                     |
3462          * |   | xxx | xx | frm 1               |
3463          * |   +-----+----+                     |
3464          * |            ...                     |
3465          * +------------------------------------+
3466          *
3467          * "xxx" means a completely full USB transfer descriptor
3468          *
3469          * "x" and "xx" means a short USB packet
3470          *
3471          * For the remainder of an USB transfer modulo
3472          * "max_data_length" we need two USB transfer descriptors.
3473          * One to transfer the remaining data and one to finalise with
3474          * a zero length packet in case the "force_short_xfer" flag is
3475          * set. We only need two USB transfer descriptors in the case
3476          * where the transfer length of the first one is a factor of
3477          * "max_frame_size". The rest of the needed USB transfer
3478          * descriptors is given by the buffer size divided by the
3479          * maximum data payload.
3480          */
3481         parm->hc_max_packet_size = 0x400;
3482         parm->hc_max_packet_count = 16 * 3;
3483         parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3484
3485         xfer->flags_int.bdma_enable = 1;
3486
3487         usbd_transfer_setup_sub(parm);
3488
3489         if (xfer->flags_int.isochronous_xfr) {
3490                 ntd = ((1 * xfer->nframes)
3491                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3492         } else if (xfer->flags_int.control_xfr) {
3493                 ntd = ((2 * xfer->nframes) + 1  /* STATUS */
3494                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3495         } else {
3496                 ntd = ((2 * xfer->nframes)
3497                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3498         }
3499
3500 alloc_dma_set:
3501
3502         if (parm->err)
3503                 return;
3504
3505         /*
3506          * Allocate queue heads and transfer descriptors
3507          */
3508         last_obj = NULL;
3509
3510         if (usbd_transfer_setup_sub_malloc(
3511             parm, &pc, sizeof(struct xhci_td),
3512             XHCI_TD_ALIGN, ntd)) {
3513                 parm->err = USB_ERR_NOMEM;
3514                 return;
3515         }
3516         if (parm->buf) {
3517                 for (n = 0; n != ntd; n++) {
3518                         struct xhci_td *td;
3519
3520                         usbd_get_page(pc + n, 0, &page_info);
3521
3522                         td = page_info.buffer;
3523
3524                         /* init TD */
3525                         td->td_self = page_info.physaddr;
3526                         td->obj_next = last_obj;
3527                         td->page_cache = pc + n;
3528
3529                         last_obj = td;
3530
3531                         usb_pc_cpu_flush(pc + n);
3532                 }
3533         }
3534         xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3535
3536         if (!xfer->flags_int.curr_dma_set) {
3537                 xfer->flags_int.curr_dma_set = 1;
3538                 goto alloc_dma_set;
3539         }
3540 }
3541
3542 static usb_error_t
3543 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3544 {
3545         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3546         struct usb_page_search buf_inp;
3547         struct usb_device *udev;
3548         struct xhci_endpoint_ext *pepext;
3549         struct usb_endpoint_descriptor *edesc;
3550         struct usb_page_cache *pcinp;
3551         usb_error_t err;
3552         uint8_t index;
3553         uint8_t epno;
3554
3555         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3556             xfer->endpoint->edesc);
3557
3558         udev = xfer->xroot->udev;
3559         index = udev->controller_slot_id;
3560
3561         pcinp = &sc->sc_hw.devs[index].input_pc;
3562
3563         usbd_get_page(pcinp, 0, &buf_inp);
3564
3565         edesc = xfer->endpoint->edesc;
3566
3567         epno = edesc->bEndpointAddress;
3568
3569         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3570                 epno |= UE_DIR_IN;
3571
3572         epno = XHCI_EPNO2EPID(epno);
3573
3574         if (epno == 0)
3575                 return (USB_ERR_NO_PIPE);               /* invalid */
3576
3577         XHCI_CMD_LOCK(sc);
3578
3579         /* configure endpoint */
3580
3581         err = xhci_configure_endpoint_by_xfer(xfer);
3582
3583         if (err != 0) {
3584                 XHCI_CMD_UNLOCK(sc);
3585                 return (err);
3586         }
3587
3588         /*
3589          * Get the endpoint into the stopped state according to the
3590          * endpoint context state diagram in the XHCI specification:
3591          */
3592
3593         err = xhci_cmd_stop_ep(sc, 0, epno, index);
3594
3595         if (err != 0)
3596                 DPRINTF("Could not stop endpoint %u\n", epno);
3597
3598         err = xhci_cmd_reset_ep(sc, 0, epno, index);
3599
3600         if (err != 0)
3601                 DPRINTF("Could not reset endpoint %u\n", epno);
3602
3603         err = xhci_cmd_set_tr_dequeue_ptr(sc, pepext->physaddr |
3604             XHCI_EPCTX_2_DCS_SET(1), 0, epno, index);
3605
3606         if (err != 0)
3607                 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3608
3609         /*
3610          * Get the endpoint into the running state according to the
3611          * endpoint context state diagram in the XHCI specification:
3612          */
3613
3614         xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3615
3616         err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3617
3618         if (err != 0)
3619                 DPRINTF("Could not configure endpoint %u\n", epno);
3620
3621         err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3622
3623         if (err != 0)
3624                 DPRINTF("Could not configure endpoint %u\n", epno);
3625
3626         XHCI_CMD_UNLOCK(sc);
3627
3628         return (0);
3629 }
3630
3631 static void
3632 xhci_xfer_unsetup(struct usb_xfer *xfer)
3633 {
3634         return;
3635 }
3636
3637 static void
3638 xhci_start_dma_delay(struct usb_xfer *xfer)
3639 {
3640         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3641
3642         /* put transfer on interrupt queue (again) */
3643         usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3644
3645         (void)usb_proc_msignal(&sc->sc_config_proc,
3646             &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3647 }
3648
3649 static void
3650 xhci_configure_msg(struct usb_proc_msg *pm)
3651 {
3652         struct xhci_softc *sc;
3653         struct xhci_endpoint_ext *pepext;
3654         struct usb_xfer *xfer;
3655
3656         sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3657
3658 restart:
3659         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3660
3661                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3662                     xfer->endpoint->edesc);
3663
3664                 if ((pepext->trb_halted != 0) ||
3665                     (pepext->trb_running == 0)) {
3666
3667                         uint8_t i;
3668
3669                         /* clear halted and running */
3670                         pepext->trb_halted = 0;
3671                         pepext->trb_running = 0;
3672
3673                         /* nuke remaining buffered transfers */
3674
3675                         for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
3676                                 /*
3677                                  * NOTE: We need to use the timeout
3678                                  * error code here else existing
3679                                  * isochronous clients can get
3680                                  * confused:
3681                                  */
3682                                 if (pepext->xfer[i] != NULL) {
3683                                         xhci_device_done(pepext->xfer[i],
3684                                             USB_ERR_TIMEOUT);
3685                                 }
3686                         }
3687
3688                         /*
3689                          * NOTE: The USB transfer cannot vanish in
3690                          * this state!
3691                          */
3692
3693                         USB_BUS_UNLOCK(&sc->sc_bus);
3694
3695                         xhci_configure_reset_endpoint(xfer);
3696
3697                         USB_BUS_LOCK(&sc->sc_bus);
3698
3699                         /* check if halted is still cleared */
3700                         if (pepext->trb_halted == 0) {
3701                                 pepext->trb_running = 1;
3702                                 pepext->trb_index = 0;
3703                         }
3704                         goto restart;
3705                 }
3706
3707                 if (xfer->flags_int.did_dma_delay) {
3708
3709                         /* remove transfer from interrupt queue (again) */
3710                         usbd_transfer_dequeue(xfer);
3711
3712                         /* we are finally done */
3713                         usb_dma_delay_done_cb(xfer);
3714
3715                         /* queue changed - restart */
3716                         goto restart;
3717                 }
3718         }
3719
3720         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3721
3722                 /* try to insert xfer on HW queue */
3723                 xhci_transfer_insert(xfer);
3724
3725                 /* try to multi buffer */
3726                 xhci_device_generic_multi_enter(xfer->endpoint, NULL);
3727         }
3728 }
3729
3730 static void
3731 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3732     struct usb_endpoint *ep)
3733 {
3734         struct xhci_endpoint_ext *pepext;
3735
3736         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3737             ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
3738
3739         if (udev->flags.usb_mode != USB_MODE_HOST) {
3740                 /* not supported */
3741                 return;
3742         }
3743         if (udev->parent_hub == NULL) {
3744                 /* root HUB has special endpoint handling */
3745                 return;
3746         }
3747
3748         ep->methods = &xhci_device_generic_methods;
3749
3750         pepext = xhci_get_endpoint_ext(udev, edesc);
3751
3752         USB_BUS_LOCK(udev->bus);
3753         pepext->trb_halted = 1;
3754         pepext->trb_running = 0;
3755         USB_BUS_UNLOCK(udev->bus);
3756 }
3757
3758 static void
3759 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
3760 {
3761
3762 }
3763
3764 static void
3765 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3766 {
3767         struct xhci_endpoint_ext *pepext;
3768
3769         DPRINTF("\n");
3770
3771         if (udev->flags.usb_mode != USB_MODE_HOST) {
3772                 /* not supported */
3773                 return;
3774         }
3775         if (udev->parent_hub == NULL) {
3776                 /* root HUB has special endpoint handling */
3777                 return;
3778         }
3779
3780         pepext = xhci_get_endpoint_ext(udev, ep->edesc);
3781
3782         USB_BUS_LOCK(udev->bus);
3783         pepext->trb_halted = 1;
3784         pepext->trb_running = 0;
3785         USB_BUS_UNLOCK(udev->bus);
3786 }
3787
3788 static usb_error_t
3789 xhci_device_init(struct usb_device *udev)
3790 {
3791         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3792         usb_error_t err;
3793         uint8_t temp;
3794
3795         /* no init for root HUB */
3796         if (udev->parent_hub == NULL)
3797                 return (0);
3798
3799         XHCI_CMD_LOCK(sc);
3800
3801         /* set invalid default */
3802
3803         udev->controller_slot_id = sc->sc_noslot + 1;
3804
3805         /* try to get a new slot ID from the XHCI */
3806
3807         err = xhci_cmd_enable_slot(sc, &temp);
3808
3809         if (err) {
3810                 XHCI_CMD_UNLOCK(sc);
3811                 return (err);
3812         }
3813
3814         if (temp > sc->sc_noslot) {
3815                 XHCI_CMD_UNLOCK(sc);
3816                 return (USB_ERR_BAD_ADDRESS);
3817         }
3818
3819         if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
3820                 DPRINTF("slot %u already allocated.\n", temp);
3821                 XHCI_CMD_UNLOCK(sc);
3822                 return (USB_ERR_BAD_ADDRESS);
3823         }
3824
3825         /* store slot ID for later reference */
3826
3827         udev->controller_slot_id = temp;
3828
3829         /* reset data structure */
3830
3831         memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
3832
3833         /* set mark slot allocated */
3834
3835         sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
3836
3837         err = xhci_alloc_device_ext(udev);
3838
3839         XHCI_CMD_UNLOCK(sc);
3840
3841         /* get device into default state */
3842
3843         if (err == 0)
3844                 err = xhci_set_address(udev, NULL, 0);
3845
3846         return (err);
3847 }
3848
3849 static void
3850 xhci_device_uninit(struct usb_device *udev)
3851 {
3852         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3853         uint8_t index;
3854
3855         /* no init for root HUB */
3856         if (udev->parent_hub == NULL)
3857                 return;
3858
3859         XHCI_CMD_LOCK(sc);
3860
3861         index = udev->controller_slot_id;
3862
3863         if (index <= sc->sc_noslot) {
3864                 xhci_cmd_disable_slot(sc, index);
3865                 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
3866
3867                 /* free device extension */
3868                 xhci_free_device_ext(udev);
3869         }
3870
3871         XHCI_CMD_UNLOCK(sc);
3872 }
3873
3874 static void
3875 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
3876 {
3877         /*
3878          * Wait until the hardware has finished any possible use of
3879          * the transfer descriptor(s)
3880          */
3881         *pus = 2048;                    /* microseconds */
3882 }
3883
3884 static void
3885 xhci_device_resume(struct usb_device *udev)
3886 {
3887         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3888         uint8_t index;
3889         uint8_t n;
3890         uint8_t p;
3891
3892         DPRINTF("\n");
3893
3894         /* check for root HUB */
3895         if (udev->parent_hub == NULL)
3896                 return;
3897
3898         index = udev->controller_slot_id;
3899
3900         XHCI_CMD_LOCK(sc);
3901
3902         /* blindly resume all endpoints */
3903
3904         USB_BUS_LOCK(udev->bus);
3905
3906         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
3907                 for (p = 0; p != 1 /*XHCI_MAX_STREAMS*/; p++) {
3908                         XWRITE4(sc, door, XHCI_DOORBELL(index),
3909                             n | XHCI_DB_SID_SET(p));
3910                 }
3911         }
3912
3913         USB_BUS_UNLOCK(udev->bus);
3914
3915         XHCI_CMD_UNLOCK(sc);
3916 }
3917
3918 static void
3919 xhci_device_suspend(struct usb_device *udev)
3920 {
3921         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3922         uint8_t index;
3923         uint8_t n;
3924         usb_error_t err;
3925
3926         DPRINTF("\n");
3927
3928         /* check for root HUB */
3929         if (udev->parent_hub == NULL)
3930                 return;
3931
3932         index = udev->controller_slot_id;
3933
3934         XHCI_CMD_LOCK(sc);
3935
3936         /* blindly suspend all endpoints */
3937
3938         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
3939                 err = xhci_cmd_stop_ep(sc, 1, n, index);
3940                 if (err != 0) {
3941                         DPRINTF("Failed to suspend endpoint "
3942                             "%u on slot %u (ignored).\n", n, index);
3943                 }
3944         }
3945
3946         XHCI_CMD_UNLOCK(sc);
3947 }
3948
3949 static void
3950 xhci_set_hw_power(struct usb_bus *bus)
3951 {
3952         DPRINTF("\n");
3953 }
3954
3955 static void
3956 xhci_device_state_change(struct usb_device *udev)
3957 {
3958         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3959         struct usb_page_search buf_inp;
3960         usb_error_t err;
3961         uint8_t index;
3962
3963         /* check for root HUB */
3964         if (udev->parent_hub == NULL)
3965                 return;
3966
3967         index = udev->controller_slot_id;
3968
3969         DPRINTF("\n");
3970
3971         if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
3972                 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
3973                     &sc->sc_hw.devs[index].tt);
3974                 if (err != 0)
3975                         sc->sc_hw.devs[index].nports = 0;
3976         }
3977
3978         XHCI_CMD_LOCK(sc);
3979
3980         switch (usb_get_device_state(udev)) {
3981         case USB_STATE_POWERED:
3982                 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
3983                         break;
3984
3985                 /* set default state */
3986                 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
3987
3988                 /* reset number of contexts */
3989                 sc->sc_hw.devs[index].context_num = 0;
3990
3991                 err = xhci_cmd_reset_dev(sc, index);
3992
3993                 if (err != 0) {
3994                         DPRINTF("Device reset failed "
3995                             "for slot %u.\n", index);
3996                 }
3997                 break;
3998
3999         case USB_STATE_ADDRESSED:
4000                 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4001                         break;
4002
4003                 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4004
4005                 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4006
4007                 if (err) {
4008                         DPRINTF("Failed to deconfigure "
4009                             "slot %u.\n", index);
4010                 }
4011                 break;
4012
4013         case USB_STATE_CONFIGURED:
4014                 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4015                         break;
4016
4017                 /* set configured state */
4018                 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4019
4020                 /* reset number of contexts */
4021                 sc->sc_hw.devs[index].context_num = 0;
4022
4023                 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4024
4025                 xhci_configure_mask(udev, 3, 0);
4026
4027                 err = xhci_configure_device(udev);
4028                 if (err != 0) {
4029                         DPRINTF("Could not configure device "
4030                             "at slot %u.\n", index);
4031                 }
4032
4033                 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4034                 if (err != 0) {
4035                         DPRINTF("Could not evaluate device "
4036                             "context at slot %u.\n", index);
4037                 }
4038                 break;
4039
4040         default:
4041                 break;
4042         }
4043         XHCI_CMD_UNLOCK(sc);
4044 }
4045
4046 struct usb_bus_methods xhci_bus_methods = {
4047         .endpoint_init = xhci_ep_init,
4048         .endpoint_uninit = xhci_ep_uninit,
4049         .xfer_setup = xhci_xfer_setup,
4050         .xfer_unsetup = xhci_xfer_unsetup,
4051         .get_dma_delay = xhci_get_dma_delay,
4052         .device_init = xhci_device_init,
4053         .device_uninit = xhci_device_uninit,
4054         .device_resume = xhci_device_resume,
4055         .device_suspend = xhci_device_suspend,
4056         .set_hw_power = xhci_set_hw_power,
4057         .roothub_exec = xhci_roothub_exec,
4058         .xfer_poll = xhci_do_poll,
4059         .start_dma_delay = xhci_start_dma_delay,
4060         .set_address = xhci_set_address,
4061         .clear_stall = xhci_ep_clear_stall,
4062         .device_state_change = xhci_device_state_change,
4063         .set_hw_power_sleep = xhci_set_hw_power_sleep,
4064 };