2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
29 * The XHCI 1.0 spec can be found at
30 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
31 * and the USB 3.0 spec at
32 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
36 * A few words about the design implementation: This driver emulates
37 * the concept about TDs which is found in EHCI specification. This
38 * way we avoid too much diveration among USB drivers.
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
44 #include <sys/stdint.h>
45 #include <sys/stddef.h>
46 #include <sys/param.h>
47 #include <sys/queue.h>
48 #include <sys/types.h>
49 #include <sys/systm.h>
50 #include <sys/kernel.h>
52 #include <sys/module.h>
54 #include <sys/mutex.h>
55 #include <sys/condvar.h>
56 #include <sys/sysctl.h>
58 #include <sys/unistd.h>
59 #include <sys/callout.h>
60 #include <sys/malloc.h>
63 #include <dev/usb/usb.h>
64 #include <dev/usb/usbdi.h>
66 #define USB_DEBUG_VAR xhcidebug
68 #include <dev/usb/usb_core.h>
69 #include <dev/usb/usb_debug.h>
70 #include <dev/usb/usb_busdma.h>
71 #include <dev/usb/usb_process.h>
72 #include <dev/usb/usb_transfer.h>
73 #include <dev/usb/usb_device.h>
74 #include <dev/usb/usb_hub.h>
75 #include <dev/usb/usb_util.h>
77 #include <dev/usb/usb_controller.h>
78 #include <dev/usb/usb_bus.h>
79 #include <dev/usb/controller/xhci.h>
80 #include <dev/usb/controller/xhcireg.h>
82 #define XHCI_BUS2SC(bus) \
83 ((struct xhci_softc *)(((uint8_t *)(bus)) - \
84 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
90 SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
91 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
92 &xhcidebug, 0, "Debug level");
93 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
94 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN,
95 &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller");
96 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
101 #define XHCI_INTR_ENDPT 1
103 struct xhci_std_temp {
104 struct xhci_softc *sc;
105 struct usb_page_cache *pc;
107 struct xhci_td *td_next;
110 uint32_t max_packet_size;
122 uint8_t do_isoc_sync;
125 static void xhci_do_poll(struct usb_bus *);
126 static void xhci_device_done(struct usb_xfer *, usb_error_t);
127 static void xhci_root_intr(struct xhci_softc *);
128 static void xhci_free_device_ext(struct usb_device *);
129 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
130 struct usb_endpoint_descriptor *);
131 static usb_proc_callback_t xhci_configure_msg;
132 static usb_error_t xhci_configure_device(struct usb_device *);
133 static usb_error_t xhci_configure_endpoint(struct usb_device *,
134 struct usb_endpoint_descriptor *, uint64_t, uint16_t,
135 uint8_t, uint8_t, uint8_t, uint16_t, uint16_t);
136 static usb_error_t xhci_configure_mask(struct usb_device *,
138 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
140 static void xhci_endpoint_doorbell(struct usb_xfer *);
141 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
142 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
143 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
145 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
148 extern struct usb_bus_methods xhci_bus_methods;
152 xhci_dump_trb(struct xhci_trb *trb)
154 DPRINTFN(5, "trb = %p\n", trb);
155 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
156 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
157 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
161 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
163 DPRINTFN(5, "pep = %p\n", pep);
164 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
165 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
166 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
167 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
168 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
169 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
170 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
174 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
176 DPRINTFN(5, "psl = %p\n", psl);
177 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
178 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
179 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
180 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
185 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
187 struct xhci_softc *sc = XHCI_BUS2SC(bus);
190 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
191 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
193 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
194 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
196 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) {
197 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
198 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
203 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
205 if (sc->sc_ctx_is_64_byte) {
207 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
208 /* all contexts are initially 32-bytes */
209 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
210 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
216 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
218 if (sc->sc_ctx_is_64_byte) {
220 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
221 /* all contexts are initially 32-bytes */
222 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
223 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
225 return (le32toh(*ptr));
229 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
231 if (sc->sc_ctx_is_64_byte) {
233 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
234 /* all contexts are initially 32-bytes */
235 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
236 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
243 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
245 if (sc->sc_ctx_is_64_byte) {
247 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
248 /* all contexts are initially 32-bytes */
249 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
250 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
252 return (le64toh(*ptr));
257 xhci_reset_command_queue_locked(struct xhci_softc *sc)
259 struct usb_page_search buf_res;
260 struct xhci_hw_root *phwr;
266 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
267 if (temp & XHCI_CRCR_LO_CRR) {
268 DPRINTF("Command ring running\n");
269 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
272 * Try to abort the last command as per section
273 * 4.6.1.2 "Aborting a Command" of the XHCI
277 /* stop and cancel */
278 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
279 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
281 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
282 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
285 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
287 /* check if command ring is still running */
288 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
289 if (temp & XHCI_CRCR_LO_CRR) {
290 DPRINTF("Comand ring still running\n");
291 return (USB_ERR_IOERROR);
295 /* reset command ring */
296 sc->sc_command_ccs = 1;
297 sc->sc_command_idx = 0;
299 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
301 /* setup command ring control base address */
302 addr = buf_res.physaddr;
303 phwr = buf_res.buffer;
304 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
306 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
308 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
309 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
311 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
313 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
314 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
320 xhci_start_controller(struct xhci_softc *sc)
322 struct usb_page_search buf_res;
323 struct xhci_hw_root *phwr;
324 struct xhci_dev_ctx_addr *pdctxa;
332 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
333 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
334 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
336 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
337 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
338 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
340 sc->sc_event_ccs = 1;
341 sc->sc_event_idx = 0;
342 sc->sc_command_ccs = 1;
343 sc->sc_command_idx = 0;
345 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
347 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
349 DPRINTF("HCS0 = 0x%08x\n", temp);
351 if (XHCI_HCS0_CSZ(temp)) {
352 sc->sc_ctx_is_64_byte = 1;
353 device_printf(sc->sc_bus.parent, "64 byte context size.\n");
355 sc->sc_ctx_is_64_byte = 0;
356 device_printf(sc->sc_bus.parent, "32 byte context size.\n");
359 /* Reset controller */
360 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
362 for (i = 0; i != 100; i++) {
363 usb_pause_mtx(NULL, hz / 100);
364 temp = XREAD4(sc, oper, XHCI_USBCMD) &
365 (XHCI_CMD_HCRST | XHCI_STS_CNR);
371 device_printf(sc->sc_bus.parent, "Controller "
373 return (USB_ERR_IOERROR);
376 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
377 device_printf(sc->sc_bus.parent, "Controller does "
378 "not support 4K page size.\n");
379 return (USB_ERR_IOERROR);
382 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
384 i = XHCI_HCS1_N_PORTS(temp);
387 device_printf(sc->sc_bus.parent, "Invalid number "
388 "of ports: %u\n", i);
389 return (USB_ERR_IOERROR);
393 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
395 if (sc->sc_noslot > XHCI_MAX_DEVICES)
396 sc->sc_noslot = XHCI_MAX_DEVICES;
398 /* setup number of device slots */
400 DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
401 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
403 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
405 DPRINTF("Max slots: %u\n", sc->sc_noslot);
407 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
409 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
411 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
412 device_printf(sc->sc_bus.parent, "XHCI request "
413 "too many scratchpads\n");
414 return (USB_ERR_NOMEM);
417 DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
419 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
421 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
422 XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
424 temp = XREAD4(sc, oper, XHCI_USBSTS);
426 /* clear interrupts */
427 XWRITE4(sc, oper, XHCI_USBSTS, temp);
428 /* disable all device notifications */
429 XWRITE4(sc, oper, XHCI_DNCTRL, 0);
431 /* setup device context base address */
432 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
433 pdctxa = buf_res.buffer;
434 memset(pdctxa, 0, sizeof(*pdctxa));
436 addr = buf_res.physaddr;
437 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
439 /* slot 0 points to the table of scratchpad pointers */
440 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
442 for (i = 0; i != sc->sc_noscratch; i++) {
443 struct usb_page_search buf_scp;
444 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
445 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
448 addr = buf_res.physaddr;
450 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
451 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
452 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
453 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
455 /* Setup event table size */
457 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
459 DPRINTF("HCS2=0x%08x\n", temp);
461 temp = XHCI_HCS2_ERST_MAX(temp);
463 if (temp > XHCI_MAX_RSEG)
464 temp = XHCI_MAX_RSEG;
466 sc->sc_erst_max = temp;
468 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
469 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp);
471 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp));
473 /* Setup interrupt rate */
474 XWRITE4(sc, runt, XHCI_IMOD(0), XHCI_IMOD_DEFAULT);
476 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
478 phwr = buf_res.buffer;
479 addr = buf_res.physaddr;
480 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
482 /* reset hardware root structure */
483 memset(phwr, 0, sizeof(*phwr));
485 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
486 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
488 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
490 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
491 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
493 addr = (uint64_t)buf_res.physaddr;
495 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
497 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
498 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
500 /* Setup interrupter registers */
502 temp = XREAD4(sc, runt, XHCI_IMAN(0));
503 temp |= XHCI_IMAN_INTR_ENA;
504 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
506 /* setup command ring control base address */
507 addr = buf_res.physaddr;
508 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
510 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
512 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
513 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
515 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
517 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
520 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
521 XHCI_CMD_INTE | XHCI_CMD_HSEE);
523 for (i = 0; i != 100; i++) {
524 usb_pause_mtx(NULL, hz / 100);
525 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
530 XWRITE4(sc, oper, XHCI_USBCMD, 0);
531 device_printf(sc->sc_bus.parent, "Run timeout.\n");
532 return (USB_ERR_IOERROR);
535 /* catch any lost interrupts */
536 xhci_do_poll(&sc->sc_bus);
538 if (sc->sc_port_route != NULL) {
539 /* Route all ports to the XHCI by default */
540 sc->sc_port_route(sc->sc_bus.parent,
541 ~xhciroute, xhciroute);
547 xhci_halt_controller(struct xhci_softc *sc)
555 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
556 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
557 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
559 /* Halt controller */
560 XWRITE4(sc, oper, XHCI_USBCMD, 0);
562 for (i = 0; i != 100; i++) {
563 usb_pause_mtx(NULL, hz / 100);
564 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
570 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
571 return (USB_ERR_IOERROR);
577 xhci_init(struct xhci_softc *sc, device_t self)
579 /* initialise some bus fields */
580 sc->sc_bus.parent = self;
582 /* set the bus revision */
583 sc->sc_bus.usbrev = USB_REV_3_0;
585 /* set up the bus struct */
586 sc->sc_bus.methods = &xhci_bus_methods;
588 /* setup devices array */
589 sc->sc_bus.devices = sc->sc_devices;
590 sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
592 /* setup command queue mutex and condition varible */
593 cv_init(&sc->sc_cmd_cv, "CMDQ");
594 sx_init(&sc->sc_cmd_sx, "CMDQ lock");
596 /* get all DMA memory */
597 if (usb_bus_mem_alloc_all(&sc->sc_bus,
598 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
602 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
603 sc->sc_config_msg[0].bus = &sc->sc_bus;
604 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
605 sc->sc_config_msg[1].bus = &sc->sc_bus;
607 if (usb_proc_create(&sc->sc_config_proc,
608 &sc->sc_bus.bus_mtx, device_get_nameunit(self), USB_PRI_MED)) {
609 printf("WARNING: Creation of XHCI configure "
610 "callback process failed.\n");
616 xhci_uninit(struct xhci_softc *sc)
618 usb_proc_free(&sc->sc_config_proc);
620 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
622 cv_destroy(&sc->sc_cmd_cv);
623 sx_destroy(&sc->sc_cmd_sx);
627 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
629 struct xhci_softc *sc = XHCI_BUS2SC(bus);
632 case USB_HW_POWER_SUSPEND:
633 DPRINTF("Stopping the XHCI\n");
634 xhci_halt_controller(sc);
636 case USB_HW_POWER_SHUTDOWN:
637 DPRINTF("Stopping the XHCI\n");
638 xhci_halt_controller(sc);
640 case USB_HW_POWER_RESUME:
641 DPRINTF("Starting the XHCI\n");
642 xhci_start_controller(sc);
650 xhci_generic_done_sub(struct usb_xfer *xfer)
653 struct xhci_td *td_alt_next;
657 td = xfer->td_transfer_cache;
658 td_alt_next = td->alt_next;
660 if (xfer->aframes != xfer->nframes)
661 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
665 usb_pc_cpu_invalidate(td->page_cache);
670 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
671 xfer, (unsigned int)xfer->aframes,
672 (unsigned int)xfer->nframes,
673 (unsigned int)len, (unsigned int)td->len,
674 (unsigned int)status);
677 * Verify the status length and
678 * add the length to "frlengths[]":
681 /* should not happen */
682 DPRINTF("Invalid status length, "
683 "0x%04x/0x%04x bytes\n", len, td->len);
684 status = XHCI_TRB_ERROR_LENGTH;
685 } else if (xfer->aframes != xfer->nframes) {
686 xfer->frlengths[xfer->aframes] += td->len - len;
688 /* Check for last transfer */
689 if (((void *)td) == xfer->td_transfer_last) {
693 /* Check for transfer error */
694 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
695 status != XHCI_TRB_ERROR_SUCCESS) {
696 /* the transfer is finished */
700 /* Check for short transfer */
702 if (xfer->flags_int.short_frames_ok ||
703 xfer->flags_int.isochronous_xfr ||
704 xfer->flags_int.control_xfr) {
705 /* follow alt next */
708 /* the transfer is finished */
715 if (td->alt_next != td_alt_next) {
716 /* this USB frame is complete */
721 /* update transfer cache */
723 xfer->td_transfer_cache = td;
725 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
726 (status != XHCI_TRB_ERROR_SHORT_PKT &&
727 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
728 USB_ERR_NORMAL_COMPLETION);
732 xhci_generic_done(struct usb_xfer *xfer)
736 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
737 xfer, xfer->endpoint);
741 xfer->td_transfer_cache = xfer->td_transfer_first;
743 if (xfer->flags_int.control_xfr) {
745 if (xfer->flags_int.control_hdr)
746 err = xhci_generic_done_sub(xfer);
750 if (xfer->td_transfer_cache == NULL)
754 while (xfer->aframes != xfer->nframes) {
756 err = xhci_generic_done_sub(xfer);
759 if (xfer->td_transfer_cache == NULL)
763 if (xfer->flags_int.control_xfr &&
764 !xfer->flags_int.control_act)
765 err = xhci_generic_done_sub(xfer);
767 /* transfer is complete */
768 xhci_device_done(xfer, err);
772 xhci_activate_transfer(struct usb_xfer *xfer)
776 td = xfer->td_transfer_cache;
778 usb_pc_cpu_invalidate(td->page_cache);
780 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
782 /* activate the transfer */
784 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
785 usb_pc_cpu_flush(td->page_cache);
787 xhci_endpoint_doorbell(xfer);
792 xhci_skip_transfer(struct usb_xfer *xfer)
795 struct xhci_td *td_last;
797 td = xfer->td_transfer_cache;
798 td_last = xfer->td_transfer_last;
802 usb_pc_cpu_invalidate(td->page_cache);
804 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
806 usb_pc_cpu_invalidate(td_last->page_cache);
808 /* copy LINK TRB to current waiting location */
810 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
811 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
812 usb_pc_cpu_flush(td->page_cache);
814 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
815 usb_pc_cpu_flush(td->page_cache);
817 xhci_endpoint_doorbell(xfer);
821 /*------------------------------------------------------------------------*
822 * xhci_check_transfer
823 *------------------------------------------------------------------------*/
825 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
838 td_event = le64toh(trb->qwTrb0);
839 temp = le32toh(trb->dwTrb2);
841 remainder = XHCI_TRB_2_REM_GET(temp);
842 status = XHCI_TRB_2_ERROR_GET(temp);
844 temp = le32toh(trb->dwTrb3);
845 epno = XHCI_TRB_3_EP_GET(temp);
846 index = XHCI_TRB_3_SLOT_GET(temp);
848 /* check if error means halted */
849 halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
850 status != XHCI_TRB_ERROR_SUCCESS);
852 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n",
853 index, epno, remainder, status);
855 if (index > sc->sc_noslot) {
856 DPRINTF("Invalid slot.\n");
860 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
861 DPRINTF("Invalid endpoint.\n");
865 /* try to find the USB transfer that generated the event */
866 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
867 struct usb_xfer *xfer;
869 struct xhci_endpoint_ext *pepext;
871 pepext = &sc->sc_hw.devs[index].endp[epno];
873 xfer = pepext->xfer[i];
877 td = xfer->td_transfer_cache;
879 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
881 (long long)td->td_self,
882 (long long)td->td_self + sizeof(td->td_trb));
885 * NOTE: Some XHCI implementations might not trigger
886 * an event on the last LINK TRB so we need to
887 * consider both the last and second last event
888 * address as conditions for a successful transfer.
890 * NOTE: We assume that the XHCI will only trigger one
891 * event per chain of TRBs.
894 offset = td_event - td->td_self;
897 offset < (int64_t)sizeof(td->td_trb)) {
899 usb_pc_cpu_invalidate(td->page_cache);
901 /* compute rest of remainder, if any */
902 for (i = (offset / 16) + 1; i < td->ntrb; i++) {
903 temp = le32toh(td->td_trb[i].dwTrb2);
904 remainder += XHCI_TRB_2_BYTES_GET(temp);
907 DPRINTFN(5, "New remainder: %u\n", remainder);
909 /* clear isochronous transfer errors */
910 if (xfer->flags_int.isochronous_xfr) {
913 status = XHCI_TRB_ERROR_SUCCESS;
918 /* "td->remainder" is verified later */
919 td->remainder = remainder;
922 usb_pc_cpu_flush(td->page_cache);
925 * 1) Last transfer descriptor makes the
928 if (((void *)td) == xfer->td_transfer_last) {
929 DPRINTF("TD is last\n");
930 xhci_generic_done(xfer);
935 * 2) Any kind of error makes the transfer
939 DPRINTF("TD has I/O error\n");
940 xhci_generic_done(xfer);
945 * 3) If there is no alternate next transfer,
946 * a short packet also makes the transfer done
948 if (td->remainder > 0) {
949 if (td->alt_next == NULL) {
951 "short TD has no alternate next\n");
952 xhci_generic_done(xfer);
955 DPRINTF("TD has short pkt\n");
956 if (xfer->flags_int.short_frames_ok ||
957 xfer->flags_int.isochronous_xfr ||
958 xfer->flags_int.control_xfr) {
959 /* follow the alt next */
960 xfer->td_transfer_cache = td->alt_next;
961 xhci_activate_transfer(xfer);
964 xhci_skip_transfer(xfer);
965 xhci_generic_done(xfer);
970 * 4) Transfer complete - go to next TD
972 DPRINTF("Following next TD\n");
973 xfer->td_transfer_cache = td->obj_next;
974 xhci_activate_transfer(xfer);
975 break; /* there should only be one match */
981 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
983 if (sc->sc_cmd_addr == trb->qwTrb0) {
984 DPRINTF("Received command event\n");
985 sc->sc_cmd_result[0] = trb->dwTrb2;
986 sc->sc_cmd_result[1] = trb->dwTrb3;
987 cv_signal(&sc->sc_cmd_cv);
988 return (1); /* command match */
994 xhci_interrupt_poll(struct xhci_softc *sc)
996 struct usb_page_search buf_res;
997 struct xhci_hw_root *phwr;
1007 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1009 phwr = buf_res.buffer;
1011 /* Receive any events */
1013 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1015 i = sc->sc_event_idx;
1016 j = sc->sc_event_ccs;
1021 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1023 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1028 event = XHCI_TRB_3_TYPE_GET(temp);
1030 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1031 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1032 (long)le32toh(phwr->hwr_events[i].dwTrb2),
1033 (long)le32toh(phwr->hwr_events[i].dwTrb3));
1036 case XHCI_TRB_EVENT_TRANSFER:
1037 xhci_check_transfer(sc, &phwr->hwr_events[i]);
1039 case XHCI_TRB_EVENT_CMD_COMPLETE:
1040 retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1043 DPRINTF("Unhandled event = %u\n", event);
1049 if (i == XHCI_MAX_EVENTS) {
1053 /* check for timeout */
1059 sc->sc_event_idx = i;
1060 sc->sc_event_ccs = j;
1063 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1064 * latched. That means to activate the register we need to
1065 * write both the low and high double word of the 64-bit
1069 addr = (uint32_t)buf_res.physaddr;
1070 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1072 /* try to clear busy bit */
1073 addr |= XHCI_ERDP_LO_BUSY;
1075 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1076 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1082 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1083 uint16_t timeout_ms)
1085 struct usb_page_search buf_res;
1086 struct xhci_hw_root *phwr;
1091 uint8_t timeout = 0;
1094 XHCI_CMD_ASSERT_LOCKED(sc);
1096 /* get hardware root structure */
1098 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1100 phwr = buf_res.buffer;
1104 USB_BUS_LOCK(&sc->sc_bus);
1106 i = sc->sc_command_idx;
1107 j = sc->sc_command_ccs;
1109 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1110 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1111 (long long)le64toh(trb->qwTrb0),
1112 (long)le32toh(trb->dwTrb2),
1113 (long)le32toh(trb->dwTrb3));
1115 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1116 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1118 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1123 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1125 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1127 temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1129 phwr->hwr_commands[i].dwTrb3 = temp;
1131 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1133 addr = buf_res.physaddr;
1134 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1136 sc->sc_cmd_addr = htole64(addr);
1140 if (i == (XHCI_MAX_COMMANDS - 1)) {
1143 temp = htole32(XHCI_TRB_3_TC_BIT |
1144 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1145 XHCI_TRB_3_CYCLE_BIT);
1147 temp = htole32(XHCI_TRB_3_TC_BIT |
1148 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1151 phwr->hwr_commands[i].dwTrb3 = temp;
1153 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1159 sc->sc_command_idx = i;
1160 sc->sc_command_ccs = j;
1162 XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1164 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1165 USB_MS_TO_TICKS(timeout_ms));
1168 * In some error cases event interrupts are not generated.
1169 * Poll one time to see if the command has completed.
1171 if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1172 DPRINTF("Command was completed when polling\n");
1176 DPRINTF("Command timeout!\n");
1178 * After some weeks of continuous operation, it has
1179 * been observed that the ASMedia Technology, ASM1042
1180 * SuperSpeed USB Host Controller can suddenly stop
1181 * accepting commands via the command queue. Try to
1182 * first reset the command queue. If that fails do a
1183 * host controller reset.
1186 xhci_reset_command_queue_locked(sc) == 0) {
1190 DPRINTF("Controller reset!\n");
1191 usb_bus_reset_async_locked(&sc->sc_bus);
1193 err = USB_ERR_TIMEOUT;
1197 temp = le32toh(sc->sc_cmd_result[0]);
1198 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1199 err = USB_ERR_IOERROR;
1201 trb->dwTrb2 = sc->sc_cmd_result[0];
1202 trb->dwTrb3 = sc->sc_cmd_result[1];
1205 USB_BUS_UNLOCK(&sc->sc_bus);
1212 xhci_cmd_nop(struct xhci_softc *sc)
1214 struct xhci_trb trb;
1221 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1223 trb.dwTrb3 = htole32(temp);
1225 return (xhci_do_command(sc, &trb, 100 /* ms */));
1230 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1232 struct xhci_trb trb;
1240 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1242 err = xhci_do_command(sc, &trb, 100 /* ms */);
1246 temp = le32toh(trb.dwTrb3);
1248 *pslot = XHCI_TRB_3_SLOT_GET(temp);
1255 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1257 struct xhci_trb trb;
1264 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1265 XHCI_TRB_3_SLOT_SET(slot_id);
1267 trb.dwTrb3 = htole32(temp);
1269 return (xhci_do_command(sc, &trb, 100 /* ms */));
1273 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1274 uint8_t bsr, uint8_t slot_id)
1276 struct xhci_trb trb;
1281 trb.qwTrb0 = htole64(input_ctx);
1283 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1284 XHCI_TRB_3_SLOT_SET(slot_id);
1287 temp |= XHCI_TRB_3_BSR_BIT;
1289 trb.dwTrb3 = htole32(temp);
1291 return (xhci_do_command(sc, &trb, 500 /* ms */));
1295 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1297 struct usb_page_search buf_inp;
1298 struct usb_page_search buf_dev;
1299 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1300 struct xhci_hw_dev *hdev;
1301 struct xhci_dev_ctx *pdev;
1302 struct xhci_endpoint_ext *pepext;
1308 /* the root HUB case is not handled here */
1309 if (udev->parent_hub == NULL)
1310 return (USB_ERR_INVAL);
1312 index = udev->controller_slot_id;
1314 hdev = &sc->sc_hw.devs[index];
1321 switch (hdev->state) {
1322 case XHCI_ST_DEFAULT:
1323 case XHCI_ST_ENABLED:
1325 hdev->state = XHCI_ST_ENABLED;
1327 /* set configure mask to slot and EP0 */
1328 xhci_configure_mask(udev, 3, 0);
1330 /* configure input slot context structure */
1331 err = xhci_configure_device(udev);
1334 DPRINTF("Could not configure device\n");
1338 /* configure input endpoint context structure */
1339 switch (udev->speed) {
1341 case USB_SPEED_FULL:
1344 case USB_SPEED_HIGH:
1352 pepext = xhci_get_endpoint_ext(udev,
1353 &udev->ctrl_ep_desc);
1354 err = xhci_configure_endpoint(udev,
1355 &udev->ctrl_ep_desc, pepext->physaddr,
1356 0, 1, 1, 0, mps, mps);
1359 DPRINTF("Could not configure default endpoint\n");
1363 /* execute set address command */
1364 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1366 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1367 (address == 0), index);
1370 temp = le32toh(sc->sc_cmd_result[0]);
1371 if (address == 0 && sc->sc_port_route != NULL &&
1372 XHCI_TRB_2_ERROR_GET(temp) ==
1373 XHCI_TRB_ERROR_PARAMETER) {
1374 /* LynxPoint XHCI - ports are not switchable */
1375 /* Un-route all ports from the XHCI */
1376 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1378 DPRINTF("Could not set address "
1379 "for slot %u.\n", index);
1384 /* update device address to new value */
1386 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1387 pdev = buf_dev.buffer;
1388 usb_pc_cpu_invalidate(&hdev->device_pc);
1390 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1391 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1393 /* update device state to new value */
1396 hdev->state = XHCI_ST_ADDRESSED;
1398 hdev->state = XHCI_ST_DEFAULT;
1402 DPRINTF("Wrong state for set address.\n");
1403 err = USB_ERR_IOERROR;
1406 XHCI_CMD_UNLOCK(sc);
1415 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1416 uint8_t deconfigure, uint8_t slot_id)
1418 struct xhci_trb trb;
1423 trb.qwTrb0 = htole64(input_ctx);
1425 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1426 XHCI_TRB_3_SLOT_SET(slot_id);
1429 temp |= XHCI_TRB_3_DCEP_BIT;
1431 trb.dwTrb3 = htole32(temp);
1433 return (xhci_do_command(sc, &trb, 100 /* ms */));
1437 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1440 struct xhci_trb trb;
1445 trb.qwTrb0 = htole64(input_ctx);
1447 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1448 XHCI_TRB_3_SLOT_SET(slot_id);
1449 trb.dwTrb3 = htole32(temp);
1451 return (xhci_do_command(sc, &trb, 100 /* ms */));
1455 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1456 uint8_t ep_id, uint8_t slot_id)
1458 struct xhci_trb trb;
1465 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1466 XHCI_TRB_3_SLOT_SET(slot_id) |
1467 XHCI_TRB_3_EP_SET(ep_id);
1470 temp |= XHCI_TRB_3_PRSV_BIT;
1472 trb.dwTrb3 = htole32(temp);
1474 return (xhci_do_command(sc, &trb, 100 /* ms */));
1478 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1479 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1481 struct xhci_trb trb;
1486 trb.qwTrb0 = htole64(dequeue_ptr);
1488 temp = XHCI_TRB_2_STREAM_SET(stream_id);
1489 trb.dwTrb2 = htole32(temp);
1491 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1492 XHCI_TRB_3_SLOT_SET(slot_id) |
1493 XHCI_TRB_3_EP_SET(ep_id);
1494 trb.dwTrb3 = htole32(temp);
1496 return (xhci_do_command(sc, &trb, 100 /* ms */));
1500 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1501 uint8_t ep_id, uint8_t slot_id)
1503 struct xhci_trb trb;
1510 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1511 XHCI_TRB_3_SLOT_SET(slot_id) |
1512 XHCI_TRB_3_EP_SET(ep_id);
1515 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1517 trb.dwTrb3 = htole32(temp);
1519 return (xhci_do_command(sc, &trb, 100 /* ms */));
1523 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1525 struct xhci_trb trb;
1532 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1533 XHCI_TRB_3_SLOT_SET(slot_id);
1535 trb.dwTrb3 = htole32(temp);
1537 return (xhci_do_command(sc, &trb, 100 /* ms */));
1540 /*------------------------------------------------------------------------*
1541 * xhci_interrupt - XHCI interrupt handler
1542 *------------------------------------------------------------------------*/
1544 xhci_interrupt(struct xhci_softc *sc)
1548 USB_BUS_LOCK(&sc->sc_bus);
1550 status = XREAD4(sc, oper, XHCI_USBSTS);
1554 /* acknowledge interrupts */
1556 XWRITE4(sc, oper, XHCI_USBSTS, status);
1558 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1560 if (status & XHCI_STS_EINT) {
1561 /* check for event(s) */
1562 xhci_interrupt_poll(sc);
1565 if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1566 XHCI_STS_HSE | XHCI_STS_HCE)) {
1568 if (status & XHCI_STS_PCD) {
1572 if (status & XHCI_STS_HCH) {
1573 printf("%s: host controller halted\n",
1577 if (status & XHCI_STS_HSE) {
1578 printf("%s: host system error\n",
1582 if (status & XHCI_STS_HCE) {
1583 printf("%s: host controller error\n",
1588 USB_BUS_UNLOCK(&sc->sc_bus);
1591 /*------------------------------------------------------------------------*
1592 * xhci_timeout - XHCI timeout handler
1593 *------------------------------------------------------------------------*/
1595 xhci_timeout(void *arg)
1597 struct usb_xfer *xfer = arg;
1599 DPRINTF("xfer=%p\n", xfer);
1601 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1603 /* transfer is transferred */
1604 xhci_device_done(xfer, USB_ERR_TIMEOUT);
1608 xhci_do_poll(struct usb_bus *bus)
1610 struct xhci_softc *sc = XHCI_BUS2SC(bus);
1612 USB_BUS_LOCK(&sc->sc_bus);
1613 xhci_interrupt_poll(sc);
1614 USB_BUS_UNLOCK(&sc->sc_bus);
1618 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1620 struct usb_page_search buf_res;
1622 struct xhci_td *td_next;
1623 struct xhci_td *td_alt_next;
1624 struct xhci_td *td_first;
1625 uint32_t buf_offset;
1630 uint8_t shortpkt_old;
1636 shortpkt_old = temp->shortpkt;
1637 len_old = temp->len;
1644 td_next = td_first = temp->td_next;
1648 if (temp->len == 0) {
1653 /* send a Zero Length Packet, ZLP, last */
1660 average = temp->average;
1662 if (temp->len < average) {
1663 if (temp->len % temp->max_packet_size) {
1666 average = temp->len;
1670 if (td_next == NULL)
1671 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1676 td_next = td->obj_next;
1678 /* check if we are pre-computing */
1682 /* update remaining length */
1684 temp->len -= average;
1688 /* fill out current TD */
1694 /* update remaining length */
1696 temp->len -= average;
1698 /* reset TRB index */
1702 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1703 /* immediate data */
1708 td->td_trb[0].qwTrb0 = 0;
1710 usbd_copy_out(temp->pc, temp->offset + buf_offset,
1711 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1714 dword = XHCI_TRB_2_BYTES_SET(8) |
1715 XHCI_TRB_2_TDSZ_SET(0) |
1716 XHCI_TRB_2_IRQ_SET(0);
1718 td->td_trb[0].dwTrb2 = htole32(dword);
1720 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1721 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1724 if (td->td_trb[0].qwTrb0 &
1725 htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1726 if (td->td_trb[0].qwTrb0 & htole64(1))
1727 dword |= XHCI_TRB_3_TRT_IN;
1729 dword |= XHCI_TRB_3_TRT_OUT;
1732 td->td_trb[0].dwTrb3 = htole32(dword);
1734 xhci_dump_trb(&td->td_trb[x]);
1742 /* fill out buffer pointers */
1745 memset(&buf_res, 0, sizeof(buf_res));
1747 usbd_get_page(temp->pc, temp->offset +
1748 buf_offset, &buf_res);
1750 /* get length to end of page */
1751 if (buf_res.length > average)
1752 buf_res.length = average;
1754 /* check for maximum length */
1755 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1756 buf_res.length = XHCI_TD_PAGE_SIZE;
1758 npkt_off += buf_res.length;
1762 npkt = (len_old - npkt_off + temp->max_packet_size - 1) /
1763 temp->max_packet_size;
1770 /* fill out TRB's */
1771 td->td_trb[x].qwTrb0 =
1772 htole64((uint64_t)buf_res.physaddr);
1775 XHCI_TRB_2_BYTES_SET(buf_res.length) |
1776 XHCI_TRB_2_TDSZ_SET(npkt) |
1777 XHCI_TRB_2_IRQ_SET(0);
1779 td->td_trb[x].dwTrb2 = htole32(dword);
1781 switch (temp->trb_type) {
1782 case XHCI_TRB_TYPE_ISOCH:
1783 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1784 XHCI_TRB_3_TBC_SET(temp->tbc) |
1785 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1786 if (td != td_first) {
1787 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1788 } else if (temp->do_isoc_sync != 0) {
1789 temp->do_isoc_sync = 0;
1790 /* wait until "isoc_frame" */
1791 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1792 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1794 /* start data transfer at next interval */
1795 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1796 XHCI_TRB_3_ISO_SIA_BIT;
1798 if (temp->direction == UE_DIR_IN)
1799 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1801 case XHCI_TRB_TYPE_DATA_STAGE:
1802 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1803 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) |
1804 XHCI_TRB_3_TBC_SET(temp->tbc) |
1805 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1806 if (temp->direction == UE_DIR_IN)
1807 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1809 case XHCI_TRB_TYPE_STATUS_STAGE:
1810 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1811 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) |
1812 XHCI_TRB_3_TBC_SET(temp->tbc) |
1813 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1814 if (temp->direction == UE_DIR_IN)
1815 dword |= XHCI_TRB_3_DIR_IN;
1817 default: /* XHCI_TRB_TYPE_NORMAL */
1818 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1819 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) |
1820 XHCI_TRB_3_TBC_SET(temp->tbc) |
1821 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1822 if (temp->direction == UE_DIR_IN)
1823 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1826 td->td_trb[x].dwTrb3 = htole32(dword);
1828 average -= buf_res.length;
1829 buf_offset += buf_res.length;
1831 xhci_dump_trb(&td->td_trb[x]);
1835 } while (average != 0);
1837 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1839 /* store number of data TRB's */
1843 DPRINTF("NTRB=%u\n", x);
1845 /* fill out link TRB */
1847 if (td_next != NULL) {
1848 /* link the current TD with the next one */
1849 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1850 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1852 /* this field will get updated later */
1853 DPRINTF("NOLINK\n");
1856 dword = XHCI_TRB_2_IRQ_SET(0);
1858 td->td_trb[x].dwTrb2 = htole32(dword);
1860 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1861 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT;
1863 td->td_trb[x].dwTrb3 = htole32(dword);
1865 td->alt_next = td_alt_next;
1867 xhci_dump_trb(&td->td_trb[x]);
1869 usb_pc_cpu_flush(td->page_cache);
1875 /* setup alt next pointer, if any */
1876 if (temp->last_frame) {
1879 /* we use this field internally */
1880 td_alt_next = td_next;
1884 temp->shortpkt = shortpkt_old;
1885 temp->len = len_old;
1890 * Remove cycle bit from the first TRB if we are
1893 if (temp->step_td != 0) {
1894 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1895 usb_pc_cpu_flush(td_first->page_cache);
1898 /* clear TD SIZE to zero, hence this is the last TRB */
1899 /* remove chain bit because this is the last TRB in the chain */
1900 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1901 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1903 usb_pc_cpu_flush(td->page_cache);
1906 temp->td_next = td_next;
1910 xhci_setup_generic_chain(struct usb_xfer *xfer)
1912 struct xhci_std_temp temp;
1918 temp.do_isoc_sync = 0;
1922 temp.average = xfer->max_hc_frame_size;
1923 temp.max_packet_size = xfer->max_packet_size;
1924 temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
1926 temp.last_frame = 0;
1928 temp.multishort = xfer->flags_int.isochronous_xfr ||
1929 xfer->flags_int.control_xfr ||
1930 xfer->flags_int.short_frames_ok;
1932 /* toggle the DMA set we are using */
1933 xfer->flags_int.curr_dma_set ^= 1;
1935 /* get next DMA set */
1936 td = xfer->td_start[xfer->flags_int.curr_dma_set];
1941 xfer->td_transfer_first = td;
1942 xfer->td_transfer_cache = td;
1944 if (xfer->flags_int.isochronous_xfr) {
1947 /* compute multiplier for ISOCHRONOUS transfers */
1948 mult = xfer->endpoint->ecomp ?
1949 (xfer->endpoint->ecomp->bmAttributes & 3) : 0;
1950 /* check for USB 2.0 multiplier */
1952 mult = (xfer->endpoint->edesc->
1953 wMaxPacketSize[1] >> 3) & 3;
1961 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
1963 DPRINTF("MFINDEX=0x%08x\n", x);
1965 switch (usbd_get_speed(xfer->xroot->udev)) {
1966 case USB_SPEED_FULL:
1968 temp.isoc_delta = 8; /* 1ms */
1969 x += temp.isoc_delta - 1;
1970 x &= ~(temp.isoc_delta - 1);
1973 shift = usbd_xfer_get_fps_shift(xfer);
1974 temp.isoc_delta = 1U << shift;
1975 x += temp.isoc_delta - 1;
1976 x &= ~(temp.isoc_delta - 1);
1977 /* simple frame load balancing */
1978 x += xfer->endpoint->usb_uframe;
1982 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
1984 if ((xfer->endpoint->is_synced == 0) ||
1985 (y < (xfer->nframes << shift)) ||
1986 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
1988 * If there is data underflow or the pipe
1989 * queue is empty we schedule the transfer a
1990 * few frames ahead of the current frame
1991 * position. Else two isochronous transfers
1994 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
1995 xfer->endpoint->is_synced = 1;
1996 temp.do_isoc_sync = 1;
1998 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2001 /* compute isochronous completion time */
2003 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2005 xfer->isoc_time_complete =
2006 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2007 (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2010 temp.isoc_frame = xfer->endpoint->isoc_next;
2011 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2013 xfer->endpoint->isoc_next += xfer->nframes << shift;
2015 } else if (xfer->flags_int.control_xfr) {
2017 /* check if we should prepend a setup message */
2019 if (xfer->flags_int.control_hdr) {
2021 temp.len = xfer->frlengths[0];
2022 temp.pc = xfer->frbuffers + 0;
2023 temp.shortpkt = temp.len ? 1 : 0;
2024 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2027 /* check for last frame */
2028 if (xfer->nframes == 1) {
2029 /* no STATUS stage yet, SETUP is last */
2030 if (xfer->flags_int.control_act)
2031 temp.last_frame = 1;
2034 xhci_setup_generic_chain_sub(&temp);
2038 temp.isoc_delta = 0;
2039 temp.isoc_frame = 0;
2040 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE;
2044 temp.isoc_delta = 0;
2045 temp.isoc_frame = 0;
2046 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2049 if (x != xfer->nframes) {
2050 /* setup page_cache pointer */
2051 temp.pc = xfer->frbuffers + x;
2052 /* set endpoint direction */
2053 temp.direction = UE_GET_DIR(xfer->endpointno);
2056 while (x != xfer->nframes) {
2058 /* DATA0 / DATA1 message */
2060 temp.len = xfer->frlengths[x];
2061 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2062 x != 0 && temp.multishort == 0);
2066 if (x == xfer->nframes) {
2067 if (xfer->flags_int.control_xfr) {
2068 /* no STATUS stage yet, DATA is last */
2069 if (xfer->flags_int.control_act)
2070 temp.last_frame = 1;
2072 temp.last_frame = 1;
2075 if (temp.len == 0) {
2077 /* make sure that we send an USB packet */
2082 temp.tlbpc = mult - 1;
2084 } else if (xfer->flags_int.isochronous_xfr) {
2089 * Isochronous transfers don't have short
2090 * packet termination:
2095 /* isochronous transfers have a transfer limit */
2097 if (temp.len > xfer->max_frame_size)
2098 temp.len = xfer->max_frame_size;
2100 /* compute TD packet count */
2101 tdpc = (temp.len + xfer->max_packet_size - 1) /
2102 xfer->max_packet_size;
2104 temp.tbc = ((tdpc + mult - 1) / mult) - 1;
2105 temp.tlbpc = (tdpc % mult);
2107 if (temp.tlbpc == 0)
2108 temp.tlbpc = mult - 1;
2113 /* regular data transfer */
2115 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2118 xhci_setup_generic_chain_sub(&temp);
2120 if (xfer->flags_int.isochronous_xfr) {
2121 temp.offset += xfer->frlengths[x - 1];
2122 temp.isoc_frame += temp.isoc_delta;
2124 /* get next Page Cache pointer */
2125 temp.pc = xfer->frbuffers + x;
2129 /* check if we should append a status stage */
2131 if (xfer->flags_int.control_xfr &&
2132 !xfer->flags_int.control_act) {
2135 * Send a DATA1 message and invert the current
2136 * endpoint direction.
2138 temp.step_td = (xfer->nframes != 0);
2139 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2143 temp.last_frame = 1;
2144 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2146 xhci_setup_generic_chain_sub(&temp);
2151 /* must have at least one frame! */
2153 xfer->td_transfer_last = td;
2155 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2159 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2161 struct usb_page_search buf_res;
2162 struct xhci_dev_ctx_addr *pdctxa;
2164 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2166 pdctxa = buf_res.buffer;
2168 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2170 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2172 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2176 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2178 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2179 struct usb_page_search buf_inp;
2180 struct xhci_input_dev_ctx *pinp;
2185 index = udev->controller_slot_id;
2187 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2189 pinp = buf_inp.buffer;
2192 mask &= XHCI_INCTX_NON_CTRL_MASK;
2193 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2194 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2196 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0);
2197 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2199 /* find most significant set bit */
2200 for (x = 31; x != 1; x--) {
2201 if (mask & (1 << x))
2208 /* figure out maximum */
2209 if (x > sc->sc_hw.devs[index].context_num) {
2210 sc->sc_hw.devs[index].context_num = x;
2211 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2212 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2213 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2214 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2221 xhci_configure_endpoint(struct usb_device *udev,
2222 struct usb_endpoint_descriptor *edesc, uint64_t ring_addr,
2223 uint16_t interval, uint8_t max_packet_count, uint8_t mult,
2224 uint8_t fps_shift, uint16_t max_packet_size, uint16_t max_frame_size)
2226 struct usb_page_search buf_inp;
2227 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2228 struct xhci_input_dev_ctx *pinp;
2234 index = udev->controller_slot_id;
2236 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2238 pinp = buf_inp.buffer;
2240 epno = edesc->bEndpointAddress;
2241 type = edesc->bmAttributes & UE_XFERTYPE;
2243 if (type == UE_CONTROL)
2246 epno = XHCI_EPNO2EPID(epno);
2249 return (USB_ERR_NO_PIPE); /* invalid */
2251 if (max_packet_count == 0)
2252 return (USB_ERR_BAD_BUFSIZE);
2257 return (USB_ERR_BAD_BUFSIZE);
2259 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2260 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2261 XHCI_EPCTX_0_LSA_SET(0);
2263 switch (udev->speed) {
2264 case USB_SPEED_FULL:
2277 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2279 case UE_ISOCHRONOUS:
2280 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2282 switch (udev->speed) {
2283 case USB_SPEED_SUPER:
2286 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2287 max_packet_count /= mult;
2297 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2300 XHCI_EPCTX_1_HID_SET(0) |
2301 XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2302 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2304 if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) {
2305 if (type != UE_ISOCHRONOUS)
2306 temp |= XHCI_EPCTX_1_CERR_SET(3);
2311 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2313 case UE_ISOCHRONOUS:
2314 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2317 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2320 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2324 /* check for IN direction */
2326 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2328 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2330 ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2332 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2334 switch (edesc->bmAttributes & UE_XFERTYPE) {
2336 case UE_ISOCHRONOUS:
2337 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2338 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2342 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2345 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2349 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2352 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2354 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2356 return (0); /* success */
2360 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2362 struct xhci_endpoint_ext *pepext;
2363 struct usb_endpoint_ss_comp_descriptor *ecomp;
2365 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2366 xfer->endpoint->edesc);
2368 ecomp = xfer->endpoint->ecomp;
2370 pepext->trb[0].dwTrb3 = 0; /* halt any transfers */
2371 usb_pc_cpu_flush(pepext->page_cache);
2373 return (xhci_configure_endpoint(xfer->xroot->udev,
2374 xfer->endpoint->edesc, pepext->physaddr,
2375 xfer->interval, xfer->max_packet_count,
2376 (ecomp != NULL) ? (ecomp->bmAttributes & 3) + 1 : 1,
2377 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2378 xfer->max_frame_size));
2382 xhci_configure_device(struct usb_device *udev)
2384 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2385 struct usb_page_search buf_inp;
2386 struct usb_page_cache *pcinp;
2387 struct xhci_input_dev_ctx *pinp;
2388 struct usb_device *hubdev;
2396 index = udev->controller_slot_id;
2398 DPRINTF("index=%u\n", index);
2400 pcinp = &sc->sc_hw.devs[index].input_pc;
2402 usbd_get_page(pcinp, 0, &buf_inp);
2404 pinp = buf_inp.buffer;
2409 /* figure out route string and root HUB port number */
2411 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2413 if (hubdev->parent_hub == NULL)
2416 depth = hubdev->parent_hub->depth;
2419 * NOTE: HS/FS/LS devices and the SS root HUB can have
2420 * more than 15 ports
2423 rh_port = hubdev->port_no;
2432 route |= rh_port << (4 * (depth - 1));
2435 DPRINTF("Route=0x%08x\n", route);
2437 temp = XHCI_SCTX_0_ROUTE_SET(route) |
2438 XHCI_SCTX_0_CTX_NUM_SET(
2439 sc->sc_hw.devs[index].context_num + 1);
2441 switch (udev->speed) {
2443 temp |= XHCI_SCTX_0_SPEED_SET(2);
2444 if (udev->parent_hs_hub != NULL &&
2445 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2447 DPRINTF("Device inherits MTT\n");
2448 temp |= XHCI_SCTX_0_MTT_SET(1);
2451 case USB_SPEED_HIGH:
2452 temp |= XHCI_SCTX_0_SPEED_SET(3);
2453 if (sc->sc_hw.devs[index].nports != 0 &&
2454 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2455 DPRINTF("HUB supports MTT\n");
2456 temp |= XHCI_SCTX_0_MTT_SET(1);
2459 case USB_SPEED_FULL:
2460 temp |= XHCI_SCTX_0_SPEED_SET(1);
2461 if (udev->parent_hs_hub != NULL &&
2462 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2464 DPRINTF("Device inherits MTT\n");
2465 temp |= XHCI_SCTX_0_MTT_SET(1);
2469 temp |= XHCI_SCTX_0_SPEED_SET(4);
2473 is_hub = sc->sc_hw.devs[index].nports != 0 &&
2474 (udev->speed == USB_SPEED_SUPER ||
2475 udev->speed == USB_SPEED_HIGH);
2478 temp |= XHCI_SCTX_0_HUB_SET(1);
2480 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2482 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2485 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2486 sc->sc_hw.devs[index].nports);
2489 switch (udev->speed) {
2490 case USB_SPEED_SUPER:
2491 switch (sc->sc_hw.devs[index].state) {
2492 case XHCI_ST_ADDRESSED:
2493 case XHCI_ST_CONFIGURED:
2494 /* enable power save */
2495 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2498 /* disable power save */
2506 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2508 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2511 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2512 sc->sc_hw.devs[index].tt);
2515 hubdev = udev->parent_hs_hub;
2517 /* check if we should activate the transaction translator */
2518 switch (udev->speed) {
2519 case USB_SPEED_FULL:
2521 if (hubdev != NULL) {
2522 temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2523 hubdev->controller_slot_id);
2524 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2532 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2534 temp = XHCI_SCTX_3_DEV_ADDR_SET(udev->address) |
2535 XHCI_SCTX_3_SLOT_STATE_SET(0);
2537 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2540 xhci_dump_device(sc, &pinp->ctx_slot);
2542 usb_pc_cpu_flush(pcinp);
2544 return (0); /* success */
2548 xhci_alloc_device_ext(struct usb_device *udev)
2550 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2551 struct usb_page_search buf_dev;
2552 struct usb_page_search buf_ep;
2553 struct xhci_trb *trb;
2554 struct usb_page_cache *pc;
2555 struct usb_page *pg;
2560 index = udev->controller_slot_id;
2562 pc = &sc->sc_hw.devs[index].device_pc;
2563 pg = &sc->sc_hw.devs[index].device_pg;
2565 /* need to initialize the page cache */
2566 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2568 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2569 (2 * sizeof(struct xhci_dev_ctx)) :
2570 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2573 usbd_get_page(pc, 0, &buf_dev);
2575 pc = &sc->sc_hw.devs[index].input_pc;
2576 pg = &sc->sc_hw.devs[index].input_pg;
2578 /* need to initialize the page cache */
2579 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2581 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2582 (2 * sizeof(struct xhci_input_dev_ctx)) :
2583 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2587 pc = &sc->sc_hw.devs[index].endpoint_pc;
2588 pg = &sc->sc_hw.devs[index].endpoint_pg;
2590 /* need to initialize the page cache */
2591 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2593 if (usb_pc_alloc_mem(pc, pg,
2594 sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) {
2598 /* initialise all endpoint LINK TRBs */
2600 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2602 /* lookup endpoint TRB ring */
2603 usbd_get_page(pc, (uintptr_t)&
2604 ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep);
2606 /* get TRB pointer */
2607 trb = buf_ep.buffer;
2608 trb += XHCI_MAX_TRANSFERS - 1;
2610 /* get TRB start address */
2611 addr = buf_ep.physaddr;
2613 /* create LINK TRB */
2614 trb->qwTrb0 = htole64(addr);
2615 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2616 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2617 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2620 usb_pc_cpu_flush(pc);
2622 xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2627 xhci_free_device_ext(udev);
2629 return (USB_ERR_NOMEM);
2633 xhci_free_device_ext(struct usb_device *udev)
2635 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2638 index = udev->controller_slot_id;
2639 xhci_set_slot_pointer(sc, index, 0);
2641 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2642 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2643 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc);
2646 static struct xhci_endpoint_ext *
2647 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2649 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2650 struct xhci_endpoint_ext *pepext;
2651 struct usb_page_cache *pc;
2652 struct usb_page_search buf_ep;
2656 epno = edesc->bEndpointAddress;
2657 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2660 epno = XHCI_EPNO2EPID(epno);
2662 index = udev->controller_slot_id;
2664 pc = &sc->sc_hw.devs[index].endpoint_pc;
2666 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->trb[epno][0], &buf_ep);
2668 pepext = &sc->sc_hw.devs[index].endp[epno];
2669 pepext->page_cache = pc;
2670 pepext->trb = buf_ep.buffer;
2671 pepext->physaddr = buf_ep.physaddr;
2677 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2679 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2683 epno = xfer->endpointno;
2684 if (xfer->flags_int.control_xfr)
2687 epno = XHCI_EPNO2EPID(epno);
2688 index = xfer->xroot->udev->controller_slot_id;
2690 if (xfer->xroot->udev->flags.self_suspended == 0) {
2691 XWRITE4(sc, door, XHCI_DOORBELL(index),
2692 epno | XHCI_DB_SID_SET(/*xfer->stream_id*/ 0));
2697 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2699 struct xhci_endpoint_ext *pepext;
2701 if (xfer->flags_int.bandwidth_reclaimed) {
2702 xfer->flags_int.bandwidth_reclaimed = 0;
2704 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2705 xfer->endpoint->edesc);
2709 pepext->xfer[xfer->qh_pos] = NULL;
2711 if (error && pepext->trb_running != 0) {
2712 pepext->trb_halted = 1;
2713 pepext->trb_running = 0;
2719 xhci_transfer_insert(struct usb_xfer *xfer)
2721 struct xhci_td *td_first;
2722 struct xhci_td *td_last;
2723 struct xhci_trb *trb_link;
2724 struct xhci_endpoint_ext *pepext;
2732 /* check if already inserted */
2733 if (xfer->flags_int.bandwidth_reclaimed) {
2734 DPRINTFN(8, "Already in schedule\n");
2738 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2739 xfer->endpoint->edesc);
2741 td_first = xfer->td_transfer_first;
2742 td_last = xfer->td_transfer_last;
2743 addr = pepext->physaddr;
2745 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2748 /* single buffered */
2752 /* multi buffered */
2753 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2757 if (pepext->trb_used >= trb_limit) {
2758 DPRINTFN(8, "Too many TDs queued.\n");
2759 return (USB_ERR_NOMEM);
2762 /* check for stopped condition, after putting transfer on interrupt queue */
2763 if (pepext->trb_running == 0) {
2764 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2766 DPRINTFN(8, "Not running\n");
2768 /* start configuration */
2769 (void)usb_proc_msignal(&sc->sc_config_proc,
2770 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2776 /* get current TRB index */
2777 i = pepext->trb_index;
2779 /* get next TRB index */
2782 /* the last entry of the ring is a hardcoded link TRB */
2783 if (inext >= (XHCI_MAX_TRANSFERS - 1))
2786 /* compute terminating return address */
2787 addr += inext * sizeof(struct xhci_trb);
2789 /* compute link TRB pointer */
2790 trb_link = td_last->td_trb + td_last->ntrb;
2792 /* update next pointer of last link TRB */
2793 trb_link->qwTrb0 = htole64(addr);
2794 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2795 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2796 XHCI_TRB_3_CYCLE_BIT |
2797 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2800 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2802 usb_pc_cpu_flush(td_last->page_cache);
2804 /* write ahead chain end marker */
2806 pepext->trb[inext].qwTrb0 = 0;
2807 pepext->trb[inext].dwTrb2 = 0;
2808 pepext->trb[inext].dwTrb3 = 0;
2810 /* update next pointer of link TRB */
2812 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2813 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2816 xhci_dump_trb(&pepext->trb[i]);
2818 usb_pc_cpu_flush(pepext->page_cache);
2820 /* toggle cycle bit which activates the transfer chain */
2822 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2823 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2825 usb_pc_cpu_flush(pepext->page_cache);
2827 DPRINTF("qh_pos = %u\n", i);
2829 pepext->xfer[i] = xfer;
2833 xfer->flags_int.bandwidth_reclaimed = 1;
2835 pepext->trb_index = inext;
2837 xhci_endpoint_doorbell(xfer);
2843 xhci_root_intr(struct xhci_softc *sc)
2847 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2849 /* clear any old interrupt data */
2850 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2852 for (i = 1; i <= sc->sc_noport; i++) {
2853 /* pick out CHANGE bits from the status register */
2854 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
2855 XHCI_PS_CSC | XHCI_PS_PEC |
2856 XHCI_PS_OCC | XHCI_PS_WRC |
2857 XHCI_PS_PRC | XHCI_PS_PLC |
2859 sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2860 DPRINTF("port %d changed\n", i);
2863 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2864 sizeof(sc->sc_hub_idata));
2867 /*------------------------------------------------------------------------*
2868 * xhci_device_done - XHCI done handler
2870 * NOTE: This function can be called two times in a row on
2871 * the same USB transfer. From close and from interrupt.
2872 *------------------------------------------------------------------------*/
2874 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
2876 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2877 xfer, xfer->endpoint, error);
2879 /* remove transfer from HW queue */
2880 xhci_transfer_remove(xfer, error);
2882 /* dequeue transfer and start next transfer */
2883 usbd_transfer_done(xfer, error);
2886 /*------------------------------------------------------------------------*
2887 * XHCI data transfer support (generic type)
2888 *------------------------------------------------------------------------*/
2890 xhci_device_generic_open(struct usb_xfer *xfer)
2892 if (xfer->flags_int.isochronous_xfr) {
2893 switch (xfer->xroot->udev->speed) {
2894 case USB_SPEED_FULL:
2897 usb_hs_bandwidth_alloc(xfer);
2904 xhci_device_generic_close(struct usb_xfer *xfer)
2908 xhci_device_done(xfer, USB_ERR_CANCELLED);
2910 if (xfer->flags_int.isochronous_xfr) {
2911 switch (xfer->xroot->udev->speed) {
2912 case USB_SPEED_FULL:
2915 usb_hs_bandwidth_free(xfer);
2922 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
2923 struct usb_xfer *enter_xfer)
2925 struct usb_xfer *xfer;
2927 /* check if there is a current transfer */
2928 xfer = ep->endpoint_q.curr;
2933 * Check if the current transfer is started and then pickup
2934 * the next one, if any. Else wait for next start event due to
2935 * block on failure feature.
2937 if (!xfer->flags_int.bandwidth_reclaimed)
2940 xfer = TAILQ_FIRST(&ep->endpoint_q.head);
2943 * In case of enter we have to consider that the
2944 * transfer is queued by the USB core after the enter
2953 /* try to multi buffer */
2954 xhci_transfer_insert(xfer);
2958 xhci_device_generic_enter(struct usb_xfer *xfer)
2962 /* setup TD's and QH */
2963 xhci_setup_generic_chain(xfer);
2965 xhci_device_generic_multi_enter(xfer->endpoint, xfer);
2969 xhci_device_generic_start(struct usb_xfer *xfer)
2973 /* try to insert xfer on HW queue */
2974 xhci_transfer_insert(xfer);
2976 /* try to multi buffer */
2977 xhci_device_generic_multi_enter(xfer->endpoint, NULL);
2979 /* add transfer last on interrupt queue */
2980 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
2982 /* start timeout, if any */
2983 if (xfer->timeout != 0)
2984 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
2987 struct usb_pipe_methods xhci_device_generic_methods =
2989 .open = xhci_device_generic_open,
2990 .close = xhci_device_generic_close,
2991 .enter = xhci_device_generic_enter,
2992 .start = xhci_device_generic_start,
2995 /*------------------------------------------------------------------------*
2996 * xhci root HUB support
2997 *------------------------------------------------------------------------*
2998 * Simulate a hardware HUB by handling all the necessary requests.
2999 *------------------------------------------------------------------------*/
3001 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3004 struct usb_device_descriptor xhci_devd =
3006 .bLength = sizeof(xhci_devd),
3007 .bDescriptorType = UDESC_DEVICE, /* type */
3008 HSETW(.bcdUSB, 0x0300), /* USB version */
3009 .bDeviceClass = UDCLASS_HUB, /* class */
3010 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */
3011 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */
3012 .bMaxPacketSize = 9, /* max packet size */
3013 HSETW(.idVendor, 0x0000), /* vendor */
3014 HSETW(.idProduct, 0x0000), /* product */
3015 HSETW(.bcdDevice, 0x0100), /* device version */
3019 .bNumConfigurations = 1, /* # of configurations */
3023 struct xhci_bos_desc xhci_bosd = {
3025 .bLength = sizeof(xhci_bosd.bosd),
3026 .bDescriptorType = UDESC_BOS,
3027 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3028 .bNumDeviceCaps = 3,
3031 .bLength = sizeof(xhci_bosd.usb2extd),
3032 .bDescriptorType = 1,
3033 .bDevCapabilityType = 2,
3034 .bmAttributes[0] = 2,
3037 .bLength = sizeof(xhci_bosd.usbdcd),
3038 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3039 .bDevCapabilityType = 3,
3040 .bmAttributes = 0, /* XXX */
3041 HSETW(.wSpeedsSupported, 0x000C),
3042 .bFunctionalitySupport = 8,
3043 .bU1DevExitLat = 255, /* dummy - not used */
3044 .wU2DevExitLat = { 0x00, 0x08 },
3047 .bLength = sizeof(xhci_bosd.cidd),
3048 .bDescriptorType = 1,
3049 .bDevCapabilityType = 4,
3051 .bContainerID = 0, /* XXX */
3056 struct xhci_config_desc xhci_confd = {
3058 .bLength = sizeof(xhci_confd.confd),
3059 .bDescriptorType = UDESC_CONFIG,
3060 .wTotalLength[0] = sizeof(xhci_confd),
3062 .bConfigurationValue = 1,
3063 .iConfiguration = 0,
3064 .bmAttributes = UC_SELF_POWERED,
3065 .bMaxPower = 0 /* max power */
3068 .bLength = sizeof(xhci_confd.ifcd),
3069 .bDescriptorType = UDESC_INTERFACE,
3071 .bInterfaceClass = UICLASS_HUB,
3072 .bInterfaceSubClass = UISUBCLASS_HUB,
3073 .bInterfaceProtocol = 0,
3076 .bLength = sizeof(xhci_confd.endpd),
3077 .bDescriptorType = UDESC_ENDPOINT,
3078 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3079 .bmAttributes = UE_INTERRUPT,
3080 .wMaxPacketSize[0] = 2, /* max 15 ports */
3084 .bLength = sizeof(xhci_confd.endpcd),
3085 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3092 struct usb_hub_ss_descriptor xhci_hubd = {
3093 .bLength = sizeof(xhci_hubd),
3094 .bDescriptorType = UDESC_SS_HUB,
3098 xhci_roothub_exec(struct usb_device *udev,
3099 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3101 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3102 const char *str_ptr;
3113 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3116 ptr = (const void *)&sc->sc_hub_desc;
3120 value = UGETW(req->wValue);
3121 index = UGETW(req->wIndex);
3123 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3124 "wValue=0x%04x wIndex=0x%04x\n",
3125 req->bmRequestType, req->bRequest,
3126 UGETW(req->wLength), value, index);
3128 #define C(x,y) ((x) | ((y) << 8))
3129 switch (C(req->bRequest, req->bmRequestType)) {
3130 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3131 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3132 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3134 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3135 * for the integrated root hub.
3138 case C(UR_GET_CONFIG, UT_READ_DEVICE):
3140 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3142 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3143 switch (value >> 8) {
3145 if ((value & 0xff) != 0) {
3146 err = USB_ERR_IOERROR;
3149 len = sizeof(xhci_devd);
3150 ptr = (const void *)&xhci_devd;
3154 if ((value & 0xff) != 0) {
3155 err = USB_ERR_IOERROR;
3158 len = sizeof(xhci_bosd);
3159 ptr = (const void *)&xhci_bosd;
3163 if ((value & 0xff) != 0) {
3164 err = USB_ERR_IOERROR;
3167 len = sizeof(xhci_confd);
3168 ptr = (const void *)&xhci_confd;
3172 switch (value & 0xff) {
3173 case 0: /* Language table */
3177 case 1: /* Vendor */
3178 str_ptr = sc->sc_vendor;
3181 case 2: /* Product */
3182 str_ptr = "XHCI root HUB";
3190 len = usb_make_str_desc(
3191 sc->sc_hub_desc.temp,
3192 sizeof(sc->sc_hub_desc.temp),
3197 err = USB_ERR_IOERROR;
3201 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3203 sc->sc_hub_desc.temp[0] = 0;
3205 case C(UR_GET_STATUS, UT_READ_DEVICE):
3207 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3209 case C(UR_GET_STATUS, UT_READ_INTERFACE):
3210 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3212 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3214 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3215 if (value >= XHCI_MAX_DEVICES) {
3216 err = USB_ERR_IOERROR;
3220 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3221 if (value != 0 && value != 1) {
3222 err = USB_ERR_IOERROR;
3225 sc->sc_conf = value;
3227 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3229 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3230 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3231 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3232 err = USB_ERR_IOERROR;
3234 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3236 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3239 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3241 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3242 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3245 (index > sc->sc_noport)) {
3246 err = USB_ERR_IOERROR;
3249 port = XHCI_PORTSC(index);
3251 v = XREAD4(sc, oper, port);
3252 i = XHCI_PS_PLS_GET(v);
3253 v &= ~XHCI_PS_CLEAR;
3256 case UHF_C_BH_PORT_RESET:
3257 XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3259 case UHF_C_PORT_CONFIG_ERROR:
3260 XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3262 case UHF_C_PORT_SUSPEND:
3263 case UHF_C_PORT_LINK_STATE:
3264 XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3266 case UHF_C_PORT_CONNECTION:
3267 XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3269 case UHF_C_PORT_ENABLE:
3270 XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3272 case UHF_C_PORT_OVER_CURRENT:
3273 XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3275 case UHF_C_PORT_RESET:
3276 XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3278 case UHF_PORT_ENABLE:
3279 XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3281 case UHF_PORT_POWER:
3282 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3284 case UHF_PORT_INDICATOR:
3285 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3287 case UHF_PORT_SUSPEND:
3291 XWRITE4(sc, oper, port, v |
3292 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3295 /* wait 20ms for resume sequence to complete */
3296 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3299 XWRITE4(sc, oper, port, v |
3300 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3303 err = USB_ERR_IOERROR;
3308 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3309 if ((value & 0xff) != 0) {
3310 err = USB_ERR_IOERROR;
3314 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3316 sc->sc_hub_desc.hubd = xhci_hubd;
3318 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3320 if (XHCI_HCS0_PPC(v))
3321 i = UHD_PWR_INDIVIDUAL;
3325 if (XHCI_HCS0_PIND(v))
3328 i |= UHD_OC_INDIVIDUAL;
3330 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3332 /* see XHCI section 5.4.9: */
3333 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3335 for (j = 1; j <= sc->sc_noport; j++) {
3337 v = XREAD4(sc, oper, XHCI_PORTSC(j));
3338 if (v & XHCI_PS_DR) {
3339 sc->sc_hub_desc.hubd.
3340 DeviceRemovable[j / 8] |= 1U << (j % 8);
3343 len = sc->sc_hub_desc.hubd.bLength;
3346 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3348 memset(sc->sc_hub_desc.temp, 0, 16);
3351 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3352 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3355 (index > sc->sc_noport)) {
3356 err = USB_ERR_IOERROR;
3360 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3362 DPRINTFN(9, "port status=0x%08x\n", v);
3364 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3366 switch (XHCI_PS_SPEED_GET(v)) {
3368 i |= UPS_HIGH_SPEED;
3377 i |= UPS_OTHER_SPEED;
3381 if (v & XHCI_PS_CCS)
3382 i |= UPS_CURRENT_CONNECT_STATUS;
3383 if (v & XHCI_PS_PED)
3384 i |= UPS_PORT_ENABLED;
3385 if (v & XHCI_PS_OCA)
3386 i |= UPS_OVERCURRENT_INDICATOR;
3389 if (v & XHCI_PS_PP) {
3391 * The USB 3.0 RH is using the
3392 * USB 2.0's power bit
3394 i |= UPS_PORT_POWER;
3396 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3399 if (v & XHCI_PS_CSC)
3400 i |= UPS_C_CONNECT_STATUS;
3401 if (v & XHCI_PS_PEC)
3402 i |= UPS_C_PORT_ENABLED;
3403 if (v & XHCI_PS_OCC)
3404 i |= UPS_C_OVERCURRENT_INDICATOR;
3405 if (v & XHCI_PS_WRC)
3406 i |= UPS_C_BH_PORT_RESET;
3407 if (v & XHCI_PS_PRC)
3408 i |= UPS_C_PORT_RESET;
3409 if (v & XHCI_PS_PLC)
3410 i |= UPS_C_PORT_LINK_STATE;
3411 if (v & XHCI_PS_CEC)
3412 i |= UPS_C_PORT_CONFIG_ERROR;
3414 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3415 len = sizeof(sc->sc_hub_desc.ps);
3418 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3419 err = USB_ERR_IOERROR;
3422 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3425 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3431 (index > sc->sc_noport)) {
3432 err = USB_ERR_IOERROR;
3436 port = XHCI_PORTSC(index);
3437 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3440 case UHF_PORT_U1_TIMEOUT:
3441 if (XHCI_PS_SPEED_GET(v) != 4) {
3442 err = USB_ERR_IOERROR;
3445 port = XHCI_PORTPMSC(index);
3446 v = XREAD4(sc, oper, port);
3447 v &= ~XHCI_PM3_U1TO_SET(0xFF);
3448 v |= XHCI_PM3_U1TO_SET(i);
3449 XWRITE4(sc, oper, port, v);
3451 case UHF_PORT_U2_TIMEOUT:
3452 if (XHCI_PS_SPEED_GET(v) != 4) {
3453 err = USB_ERR_IOERROR;
3456 port = XHCI_PORTPMSC(index);
3457 v = XREAD4(sc, oper, port);
3458 v &= ~XHCI_PM3_U2TO_SET(0xFF);
3459 v |= XHCI_PM3_U2TO_SET(i);
3460 XWRITE4(sc, oper, port, v);
3462 case UHF_BH_PORT_RESET:
3463 XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3465 case UHF_PORT_LINK_STATE:
3466 XWRITE4(sc, oper, port, v |
3467 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3468 /* 4ms settle time */
3469 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3471 case UHF_PORT_ENABLE:
3472 DPRINTFN(3, "set port enable %d\n", index);
3474 case UHF_PORT_SUSPEND:
3475 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3476 j = XHCI_PS_SPEED_GET(v);
3477 if ((j < 1) || (j > 3)) {
3478 /* non-supported speed */
3479 err = USB_ERR_IOERROR;
3482 XWRITE4(sc, oper, port, v |
3483 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3485 case UHF_PORT_RESET:
3486 DPRINTFN(6, "reset port %d\n", index);
3487 XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3489 case UHF_PORT_POWER:
3490 DPRINTFN(3, "set port power %d\n", index);
3491 XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3494 DPRINTFN(3, "set port test %d\n", index);
3496 case UHF_PORT_INDICATOR:
3497 DPRINTFN(3, "set port indicator %d\n", index);
3499 v &= ~XHCI_PS_PIC_SET(3);
3500 v |= XHCI_PS_PIC_SET(1);
3502 XWRITE4(sc, oper, port, v);
3505 err = USB_ERR_IOERROR;
3510 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3511 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3512 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3513 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3516 err = USB_ERR_IOERROR;
3526 xhci_xfer_setup(struct usb_setup_params *parm)
3528 struct usb_page_search page_info;
3529 struct usb_page_cache *pc;
3530 struct xhci_softc *sc;
3531 struct usb_xfer *xfer;
3536 sc = XHCI_BUS2SC(parm->udev->bus);
3537 xfer = parm->curr_xfer;
3540 * The proof for the "ntd" formula is illustrated like this:
3542 * +------------------------------------+
3546 * | | xxx | x | frm 0 |
3548 * | | xxx | xx | frm 1 |
3551 * +------------------------------------+
3553 * "xxx" means a completely full USB transfer descriptor
3555 * "x" and "xx" means a short USB packet
3557 * For the remainder of an USB transfer modulo
3558 * "max_data_length" we need two USB transfer descriptors.
3559 * One to transfer the remaining data and one to finalise with
3560 * a zero length packet in case the "force_short_xfer" flag is
3561 * set. We only need two USB transfer descriptors in the case
3562 * where the transfer length of the first one is a factor of
3563 * "max_frame_size". The rest of the needed USB transfer
3564 * descriptors is given by the buffer size divided by the
3565 * maximum data payload.
3567 parm->hc_max_packet_size = 0x400;
3568 parm->hc_max_packet_count = 16 * 3;
3569 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3571 xfer->flags_int.bdma_enable = 1;
3573 usbd_transfer_setup_sub(parm);
3575 if (xfer->flags_int.isochronous_xfr) {
3576 ntd = ((1 * xfer->nframes)
3577 + (xfer->max_data_length / xfer->max_hc_frame_size));
3578 } else if (xfer->flags_int.control_xfr) {
3579 ntd = ((2 * xfer->nframes) + 1 /* STATUS */
3580 + (xfer->max_data_length / xfer->max_hc_frame_size));
3582 ntd = ((2 * xfer->nframes)
3583 + (xfer->max_data_length / xfer->max_hc_frame_size));
3592 * Allocate queue heads and transfer descriptors
3596 if (usbd_transfer_setup_sub_malloc(
3597 parm, &pc, sizeof(struct xhci_td),
3598 XHCI_TD_ALIGN, ntd)) {
3599 parm->err = USB_ERR_NOMEM;
3603 for (n = 0; n != ntd; n++) {
3606 usbd_get_page(pc + n, 0, &page_info);
3608 td = page_info.buffer;
3611 td->td_self = page_info.physaddr;
3612 td->obj_next = last_obj;
3613 td->page_cache = pc + n;
3617 usb_pc_cpu_flush(pc + n);
3620 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3622 if (!xfer->flags_int.curr_dma_set) {
3623 xfer->flags_int.curr_dma_set = 1;
3629 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3631 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3632 struct usb_page_search buf_inp;
3633 struct usb_device *udev;
3634 struct xhci_endpoint_ext *pepext;
3635 struct usb_endpoint_descriptor *edesc;
3636 struct usb_page_cache *pcinp;
3641 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3642 xfer->endpoint->edesc);
3644 udev = xfer->xroot->udev;
3645 index = udev->controller_slot_id;
3647 pcinp = &sc->sc_hw.devs[index].input_pc;
3649 usbd_get_page(pcinp, 0, &buf_inp);
3651 edesc = xfer->endpoint->edesc;
3653 epno = edesc->bEndpointAddress;
3655 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3658 epno = XHCI_EPNO2EPID(epno);
3661 return (USB_ERR_NO_PIPE); /* invalid */
3665 /* configure endpoint */
3667 err = xhci_configure_endpoint_by_xfer(xfer);
3670 XHCI_CMD_UNLOCK(sc);
3675 * Get the endpoint into the stopped state according to the
3676 * endpoint context state diagram in the XHCI specification:
3679 err = xhci_cmd_stop_ep(sc, 0, epno, index);
3682 DPRINTF("Could not stop endpoint %u\n", epno);
3684 err = xhci_cmd_reset_ep(sc, 0, epno, index);
3687 DPRINTF("Could not reset endpoint %u\n", epno);
3689 err = xhci_cmd_set_tr_dequeue_ptr(sc, pepext->physaddr |
3690 XHCI_EPCTX_2_DCS_SET(1), 0, epno, index);
3693 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3696 * Get the endpoint into the running state according to the
3697 * endpoint context state diagram in the XHCI specification:
3700 xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3702 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3705 DPRINTF("Could not configure endpoint %u\n", epno);
3707 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3710 DPRINTF("Could not configure endpoint %u\n", epno);
3712 XHCI_CMD_UNLOCK(sc);
3718 xhci_xfer_unsetup(struct usb_xfer *xfer)
3724 xhci_start_dma_delay(struct usb_xfer *xfer)
3726 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3728 /* put transfer on interrupt queue (again) */
3729 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3731 (void)usb_proc_msignal(&sc->sc_config_proc,
3732 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3736 xhci_configure_msg(struct usb_proc_msg *pm)
3738 struct xhci_softc *sc;
3739 struct xhci_endpoint_ext *pepext;
3740 struct usb_xfer *xfer;
3742 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3745 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3747 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3748 xfer->endpoint->edesc);
3750 if ((pepext->trb_halted != 0) ||
3751 (pepext->trb_running == 0)) {
3755 /* clear halted and running */
3756 pepext->trb_halted = 0;
3757 pepext->trb_running = 0;
3759 /* nuke remaining buffered transfers */
3761 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
3763 * NOTE: We need to use the timeout
3764 * error code here else existing
3765 * isochronous clients can get
3768 if (pepext->xfer[i] != NULL) {
3769 xhci_device_done(pepext->xfer[i],
3775 * NOTE: The USB transfer cannot vanish in
3779 USB_BUS_UNLOCK(&sc->sc_bus);
3781 xhci_configure_reset_endpoint(xfer);
3783 USB_BUS_LOCK(&sc->sc_bus);
3785 /* check if halted is still cleared */
3786 if (pepext->trb_halted == 0) {
3787 pepext->trb_running = 1;
3788 pepext->trb_index = 0;
3793 if (xfer->flags_int.did_dma_delay) {
3795 /* remove transfer from interrupt queue (again) */
3796 usbd_transfer_dequeue(xfer);
3798 /* we are finally done */
3799 usb_dma_delay_done_cb(xfer);
3801 /* queue changed - restart */
3806 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3808 /* try to insert xfer on HW queue */
3809 xhci_transfer_insert(xfer);
3811 /* try to multi buffer */
3812 xhci_device_generic_multi_enter(xfer->endpoint, NULL);
3817 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3818 struct usb_endpoint *ep)
3820 struct xhci_endpoint_ext *pepext;
3822 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3823 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
3825 if (udev->flags.usb_mode != USB_MODE_HOST) {
3829 if (udev->parent_hub == NULL) {
3830 /* root HUB has special endpoint handling */
3834 ep->methods = &xhci_device_generic_methods;
3836 pepext = xhci_get_endpoint_ext(udev, edesc);
3838 USB_BUS_LOCK(udev->bus);
3839 pepext->trb_halted = 1;
3840 pepext->trb_running = 0;
3841 USB_BUS_UNLOCK(udev->bus);
3845 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
3851 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3853 struct xhci_endpoint_ext *pepext;
3857 if (udev->flags.usb_mode != USB_MODE_HOST) {
3861 if (udev->parent_hub == NULL) {
3862 /* root HUB has special endpoint handling */
3866 pepext = xhci_get_endpoint_ext(udev, ep->edesc);
3868 USB_BUS_LOCK(udev->bus);
3869 pepext->trb_halted = 1;
3870 pepext->trb_running = 0;
3871 USB_BUS_UNLOCK(udev->bus);
3875 xhci_device_init(struct usb_device *udev)
3877 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3881 /* no init for root HUB */
3882 if (udev->parent_hub == NULL)
3887 /* set invalid default */
3889 udev->controller_slot_id = sc->sc_noslot + 1;
3891 /* try to get a new slot ID from the XHCI */
3893 err = xhci_cmd_enable_slot(sc, &temp);
3896 XHCI_CMD_UNLOCK(sc);
3900 if (temp > sc->sc_noslot) {
3901 XHCI_CMD_UNLOCK(sc);
3902 return (USB_ERR_BAD_ADDRESS);
3905 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
3906 DPRINTF("slot %u already allocated.\n", temp);
3907 XHCI_CMD_UNLOCK(sc);
3908 return (USB_ERR_BAD_ADDRESS);
3911 /* store slot ID for later reference */
3913 udev->controller_slot_id = temp;
3915 /* reset data structure */
3917 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
3919 /* set mark slot allocated */
3921 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
3923 err = xhci_alloc_device_ext(udev);
3925 XHCI_CMD_UNLOCK(sc);
3927 /* get device into default state */
3930 err = xhci_set_address(udev, NULL, 0);
3936 xhci_device_uninit(struct usb_device *udev)
3938 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3941 /* no init for root HUB */
3942 if (udev->parent_hub == NULL)
3947 index = udev->controller_slot_id;
3949 if (index <= sc->sc_noslot) {
3950 xhci_cmd_disable_slot(sc, index);
3951 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
3953 /* free device extension */
3954 xhci_free_device_ext(udev);
3957 XHCI_CMD_UNLOCK(sc);
3961 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
3964 * Wait until the hardware has finished any possible use of
3965 * the transfer descriptor(s)
3967 *pus = 2048; /* microseconds */
3971 xhci_device_resume(struct usb_device *udev)
3973 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3980 /* check for root HUB */
3981 if (udev->parent_hub == NULL)
3984 index = udev->controller_slot_id;
3988 /* blindly resume all endpoints */
3990 USB_BUS_LOCK(udev->bus);
3992 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
3993 for (p = 0; p != 1 /*XHCI_MAX_STREAMS*/; p++) {
3994 XWRITE4(sc, door, XHCI_DOORBELL(index),
3995 n | XHCI_DB_SID_SET(p));
3999 USB_BUS_UNLOCK(udev->bus);
4001 XHCI_CMD_UNLOCK(sc);
4005 xhci_device_suspend(struct usb_device *udev)
4007 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4014 /* check for root HUB */
4015 if (udev->parent_hub == NULL)
4018 index = udev->controller_slot_id;
4022 /* blindly suspend all endpoints */
4024 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4025 err = xhci_cmd_stop_ep(sc, 1, n, index);
4027 DPRINTF("Failed to suspend endpoint "
4028 "%u on slot %u (ignored).\n", n, index);
4032 XHCI_CMD_UNLOCK(sc);
4036 xhci_set_hw_power(struct usb_bus *bus)
4042 xhci_device_state_change(struct usb_device *udev)
4044 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4045 struct usb_page_search buf_inp;
4049 /* check for root HUB */
4050 if (udev->parent_hub == NULL)
4053 index = udev->controller_slot_id;
4057 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4058 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4059 &sc->sc_hw.devs[index].tt);
4061 sc->sc_hw.devs[index].nports = 0;
4066 switch (usb_get_device_state(udev)) {
4067 case USB_STATE_POWERED:
4068 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4071 /* set default state */
4072 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4074 /* reset number of contexts */
4075 sc->sc_hw.devs[index].context_num = 0;
4077 err = xhci_cmd_reset_dev(sc, index);
4080 DPRINTF("Device reset failed "
4081 "for slot %u.\n", index);
4085 case USB_STATE_ADDRESSED:
4086 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4089 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4091 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4094 DPRINTF("Failed to deconfigure "
4095 "slot %u.\n", index);
4099 case USB_STATE_CONFIGURED:
4100 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4103 /* set configured state */
4104 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4106 /* reset number of contexts */
4107 sc->sc_hw.devs[index].context_num = 0;
4109 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4111 xhci_configure_mask(udev, 3, 0);
4113 err = xhci_configure_device(udev);
4115 DPRINTF("Could not configure device "
4116 "at slot %u.\n", index);
4119 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4121 DPRINTF("Could not evaluate device "
4122 "context at slot %u.\n", index);
4129 XHCI_CMD_UNLOCK(sc);
4132 struct usb_bus_methods xhci_bus_methods = {
4133 .endpoint_init = xhci_ep_init,
4134 .endpoint_uninit = xhci_ep_uninit,
4135 .xfer_setup = xhci_xfer_setup,
4136 .xfer_unsetup = xhci_xfer_unsetup,
4137 .get_dma_delay = xhci_get_dma_delay,
4138 .device_init = xhci_device_init,
4139 .device_uninit = xhci_device_uninit,
4140 .device_resume = xhci_device_resume,
4141 .device_suspend = xhci_device_suspend,
4142 .set_hw_power = xhci_set_hw_power,
4143 .roothub_exec = xhci_roothub_exec,
4144 .xfer_poll = xhci_do_poll,
4145 .start_dma_delay = xhci_start_dma_delay,
4146 .set_address = xhci_set_address,
4147 .clear_stall = xhci_ep_clear_stall,
4148 .device_state_change = xhci_device_state_change,
4149 .set_hw_power_sleep = xhci_set_hw_power_sleep,