sys/dev/usb/controller/xhci.c

   1 /*-
   2  * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  */
  25
  26 /*
  27  * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
  28  *
  29  * The XHCI 1.0 spec can be found at
  30  * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
  31  * and the USB 3.0 spec at
  32  * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
  33  */
  34
  35 /*
  36  * A few words about the design implementation: This driver emulates
  37  * the concept about TDs which is found in EHCI specification. This
  38  * way we avoid too much diveration among USB drivers.
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include <sys/stdint.h>
  45 #include <sys/stddef.h>
  46 #include <sys/param.h>
  47 #include <sys/queue.h>
  48 #include <sys/types.h>
  49 #include <sys/systm.h>
  50 #include <sys/kernel.h>
  51 #include <sys/bus.h>
  52 #include <sys/module.h>
  53 #include <sys/lock.h>
  54 #include <sys/mutex.h>
  55 #include <sys/condvar.h>
  56 #include <sys/sysctl.h>
  57 #include <sys/sx.h>
  58 #include <sys/unistd.h>
  59 #include <sys/callout.h>
  60 #include <sys/malloc.h>
  61 #include <sys/priv.h>
  62
  63 #include <dev/usb/usb.h>
  64 #include <dev/usb/usbdi.h>
  65
  66 #define USB_DEBUG_VAR xhcidebug
  67
  68 #include <dev/usb/usb_core.h>
  69 #include <dev/usb/usb_debug.h>
  70 #include <dev/usb/usb_busdma.h>
  71 #include <dev/usb/usb_process.h>
  72 #include <dev/usb/usb_transfer.h>
  73 #include <dev/usb/usb_device.h>
  74 #include <dev/usb/usb_hub.h>
  75 #include <dev/usb/usb_util.h>
  76
  77 #include <dev/usb/usb_controller.h>
  78 #include <dev/usb/usb_bus.h>
  79 #include <dev/usb/controller/xhci.h>
  80 #include <dev/usb/controller/xhcireg.h>
  81
  82 #define XHCI_BUS2SC(bus) \
  83    ((struct xhci_softc *)(((uint8_t *)(bus)) - \
  84     ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
  85
  86 #ifdef USB_DEBUG
  87 static int xhcidebug;
  88 static int xhciroute;
  89 static int xhcipolling;
  90
  91 SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
  92 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
  93     &xhcidebug, 0, "Debug level");
  94 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
  95 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN,
  96     &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller");
  97 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
  98 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RW | CTLFLAG_TUN,
  99     &xhcipolling, 0, "Set to enable software interrupt polling for XHCI controller");
 100 TUNABLE_INT("hw.usb.xhci.use_polling", &xhcipolling);
 101 #else
 102 #define xhciroute 0
 103 #endif
 104
 105 #define XHCI_INTR_ENDPT 1
 106
 107 struct xhci_std_temp {
 108         struct xhci_softc       *sc;
 109         struct usb_page_cache   *pc;
 110         struct xhci_td          *td;
 111         struct xhci_td          *td_next;
 112         uint32_t                len;
 113         uint32_t                offset;
 114         uint32_t                max_packet_size;
 115         uint32_t                average;
 116         uint16_t                isoc_delta;
 117         uint16_t                isoc_frame;
 118         uint8_t                 shortpkt;
 119         uint8_t                 multishort;
 120         uint8_t                 last_frame;
 121         uint8_t                 trb_type;
 122         uint8_t                 direction;
 123         uint8_t                 tbc;
 124         uint8_t                 tlbpc;
 125         uint8_t                 step_td;
 126         uint8_t                 do_isoc_sync;
 127 };
 128
 129 static void     xhci_do_poll(struct usb_bus *);
 130 static void     xhci_device_done(struct usb_xfer *, usb_error_t);
 131 static void     xhci_root_intr(struct xhci_softc *);
 132 static void     xhci_free_device_ext(struct usb_device *);
 133 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
 134                     struct usb_endpoint_descriptor *);
 135 static usb_proc_callback_t xhci_configure_msg;
 136 static usb_error_t xhci_configure_device(struct usb_device *);
 137 static usb_error_t xhci_configure_endpoint(struct usb_device *,
 138                     struct usb_endpoint_descriptor *, uint64_t, uint16_t,
 139                     uint8_t, uint8_t, uint8_t, uint16_t, uint16_t);
 140 static usb_error_t xhci_configure_mask(struct usb_device *,
 141                     uint32_t, uint8_t);
 142 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
 143                     uint64_t, uint8_t);
 144 static void xhci_endpoint_doorbell(struct usb_xfer *);
 145 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
 146 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
 147 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
 148 #ifdef USB_DEBUG
 149 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
 150 #endif
 151
 152 extern struct usb_bus_methods xhci_bus_methods;
 153
 154 #ifdef USB_DEBUG
 155 static void
 156 xhci_dump_trb(struct xhci_trb *trb)
 157 {
 158         DPRINTFN(5, "trb = %p\n", trb);
 159         DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
 160         DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
 161         DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
 162 }
 163
 164 static void
 165 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
 166 {
 167         DPRINTFN(5, "pep = %p\n", pep);
 168         DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
 169         DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
 170         DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
 171         DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
 172         DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
 173         DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
 174         DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
 175 }
 176
 177 static void
 178 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
 179 {
 180         DPRINTFN(5, "psl = %p\n", psl);
 181         DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
 182         DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
 183         DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
 184         DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
 185 }
 186 #endif
 187
 188 uint8_t
 189 xhci_use_polling(void)
 190 {
 191 #ifdef USB_DEBUG
 192         return (xhcipolling != 0);
 193 #else
 194         return (0);
 195 #endif
 196 }
 197
 198 static void
 199 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
 200 {
 201         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 202         uint8_t i;
 203
 204         cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
 205            sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
 206
 207         cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
 208            sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
 209
 210         for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) {
 211                 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
 212                     XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
 213         }
 214 }
 215
 216 static void
 217 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
 218 {
 219         if (sc->sc_ctx_is_64_byte) {
 220                 uint32_t offset;
 221                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 222                 /* all contexts are initially 32-bytes */
 223                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 224                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 225         }
 226         *ptr = htole32(val);
 227 }
 228
 229 static uint32_t
 230 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
 231 {
 232         if (sc->sc_ctx_is_64_byte) {
 233                 uint32_t offset;
 234                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 235                 /* all contexts are initially 32-bytes */
 236                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 237                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 238         }
 239         return (le32toh(*ptr));
 240 }
 241
 242 static void
 243 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
 244 {
 245         if (sc->sc_ctx_is_64_byte) {
 246                 uint32_t offset;
 247                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 248                 /* all contexts are initially 32-bytes */
 249                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 250                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 251         }
 252         *ptr = htole64(val);
 253 }
 254
 255 #ifdef USB_DEBUG
 256 static uint64_t
 257 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
 258 {
 259         if (sc->sc_ctx_is_64_byte) {
 260                 uint32_t offset;
 261                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 262                 /* all contexts are initially 32-bytes */
 263                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 264                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 265         }
 266         return (le64toh(*ptr));
 267 }
 268 #endif
 269
 270 static int
 271 xhci_reset_command_queue_locked(struct xhci_softc *sc)
 272 {
 273         struct usb_page_search buf_res;
 274         struct xhci_hw_root *phwr;
 275         uint64_t addr;
 276         uint32_t temp;
 277
 278         DPRINTF("\n");
 279
 280         temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 281         if (temp & XHCI_CRCR_LO_CRR) {
 282                 DPRINTF("Command ring running\n");
 283                 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
 284
 285                 /*
 286                  * Try to abort the last command as per section
 287                  * 4.6.1.2 "Aborting a Command" of the XHCI
 288                  * specification:
 289                  */
 290
 291                 /* stop and cancel */
 292                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
 293                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 294
 295                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
 296                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 297
 298                 /* wait 250ms */
 299                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
 300
 301                 /* check if command ring is still running */
 302                 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 303                 if (temp & XHCI_CRCR_LO_CRR) {
 304                         DPRINTF("Comand ring still running\n");
 305                         return (USB_ERR_IOERROR);
 306                 }
 307         }
 308
 309         /* reset command ring */
 310         sc->sc_command_ccs = 1;
 311         sc->sc_command_idx = 0;
 312
 313         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 314
 315         /* setup command ring control base address */
 316         addr = buf_res.physaddr;
 317         phwr = buf_res.buffer;
 318         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 319
 320         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 321
 322         memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
 323         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 324
 325         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
 326
 327         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 328         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 329
 330         return (0);
 331 }
 332
 333 usb_error_t
 334 xhci_start_controller(struct xhci_softc *sc)
 335 {
 336         struct usb_page_search buf_res;
 337         struct xhci_hw_root *phwr;
 338         struct xhci_dev_ctx_addr *pdctxa;
 339         uint64_t addr;
 340         uint32_t temp;
 341         uint16_t i;
 342
 343         DPRINTF("\n");
 344
 345         sc->sc_capa_off = 0;
 346         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 347         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
 348         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 349
 350         DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
 351         DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
 352         DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
 353
 354         sc->sc_event_ccs = 1;
 355         sc->sc_event_idx = 0;
 356         sc->sc_command_ccs = 1;
 357         sc->sc_command_idx = 0;
 358
 359         DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
 360
 361         temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
 362
 363         DPRINTF("HCS0 = 0x%08x\n", temp);
 364
 365         if (XHCI_HCS0_CSZ(temp)) {
 366                 sc->sc_ctx_is_64_byte = 1;
 367                 device_printf(sc->sc_bus.parent, "64 byte context size.\n");
 368         } else {
 369                 sc->sc_ctx_is_64_byte = 0;
 370                 device_printf(sc->sc_bus.parent, "32 byte context size.\n");
 371         }
 372
 373         /* Reset controller */
 374         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
 375
 376         for (i = 0; i != 100; i++) {
 377                 usb_pause_mtx(NULL, hz / 100);
 378                 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
 379                     (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
 380                 if (!temp)
 381                         break;
 382         }
 383
 384         if (temp) {
 385                 device_printf(sc->sc_bus.parent, "Controller "
 386                     "reset timeout.\n");
 387                 return (USB_ERR_IOERROR);
 388         }
 389
 390         if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
 391                 device_printf(sc->sc_bus.parent, "Controller does "
 392                     "not support 4K page size.\n");
 393                 return (USB_ERR_IOERROR);
 394         }
 395
 396         temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
 397
 398         i = XHCI_HCS1_N_PORTS(temp);
 399
 400         if (i == 0) {
 401                 device_printf(sc->sc_bus.parent, "Invalid number "
 402                     "of ports: %u\n", i);
 403                 return (USB_ERR_IOERROR);
 404         }
 405
 406         sc->sc_noport = i;
 407         sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
 408
 409         if (sc->sc_noslot > XHCI_MAX_DEVICES)
 410                 sc->sc_noslot = XHCI_MAX_DEVICES;
 411
 412         /* setup number of device slots */
 413
 414         DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
 415             XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
 416
 417         XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
 418
 419         DPRINTF("Max slots: %u\n", sc->sc_noslot);
 420
 421         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 422
 423         sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
 424
 425         if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
 426                 device_printf(sc->sc_bus.parent, "XHCI request "
 427                     "too many scratchpads\n");
 428                 return (USB_ERR_NOMEM);
 429         }
 430
 431         DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
 432
 433         temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
 434
 435         sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
 436             XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
 437
 438         temp = XREAD4(sc, oper, XHCI_USBSTS);
 439
 440         /* clear interrupts */
 441         XWRITE4(sc, oper, XHCI_USBSTS, temp);
 442         /* disable all device notifications */
 443         XWRITE4(sc, oper, XHCI_DNCTRL, 0);
 444
 445         /* setup device context base address */
 446         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
 447         pdctxa = buf_res.buffer;
 448         memset(pdctxa, 0, sizeof(*pdctxa));
 449
 450         addr = buf_res.physaddr;
 451         addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
 452
 453         /* slot 0 points to the table of scratchpad pointers */
 454         pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
 455
 456         for (i = 0; i != sc->sc_noscratch; i++) {
 457                 struct usb_page_search buf_scp;
 458                 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
 459                 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
 460         }
 461
 462         addr = buf_res.physaddr;
 463
 464         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 465         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 466         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 467         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 468
 469         /* Setup event table size */
 470
 471         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 472
 473         DPRINTF("HCS2=0x%08x\n", temp);
 474
 475         temp = XHCI_HCS2_ERST_MAX(temp);
 476         temp = 1U << temp;
 477         if (temp > XHCI_MAX_RSEG)
 478                 temp = XHCI_MAX_RSEG;
 479
 480         sc->sc_erst_max = temp;
 481
 482         DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
 483             XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp);
 484
 485         XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp));
 486
 487         /* Check if we should use the default IMOD value */
 488         if (sc->sc_imod_default == 0)
 489                 sc->sc_imod_default = XHCI_IMOD_DEFAULT;
 490
 491         /* Setup interrupt rate */
 492         XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default);
 493
 494         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 495
 496         phwr = buf_res.buffer;
 497         addr = buf_res.physaddr;
 498         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
 499
 500         /* reset hardware root structure */
 501         memset(phwr, 0, sizeof(*phwr));
 502
 503         phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
 504         phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
 505
 506         DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
 507
 508         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
 509         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
 510
 511         addr = buf_res.physaddr;
 512
 513         DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
 514
 515         XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
 516         XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
 517
 518         /* Setup interrupter registers */
 519
 520         temp = XREAD4(sc, runt, XHCI_IMAN(0));
 521         temp |= XHCI_IMAN_INTR_ENA;
 522         XWRITE4(sc, runt, XHCI_IMAN(0), temp);
 523
 524         /* setup command ring control base address */
 525         addr = buf_res.physaddr;
 526         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 527
 528         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 529
 530         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 531         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 532
 533         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 534
 535         usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 536
 537         /* Go! */
 538         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
 539             XHCI_CMD_INTE | XHCI_CMD_HSEE);
 540
 541         for (i = 0; i != 100; i++) {
 542                 usb_pause_mtx(NULL, hz / 100);
 543                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 544                 if (!temp)
 545                         break;
 546         }
 547         if (temp) {
 548                 XWRITE4(sc, oper, XHCI_USBCMD, 0);
 549                 device_printf(sc->sc_bus.parent, "Run timeout.\n");
 550                 return (USB_ERR_IOERROR);
 551         }
 552
 553         /* catch any lost interrupts */
 554         xhci_do_poll(&sc->sc_bus);
 555
 556         if (sc->sc_port_route != NULL) {
 557                 /* Route all ports to the XHCI by default */
 558                 sc->sc_port_route(sc->sc_bus.parent,
 559                     ~xhciroute, xhciroute);
 560         }
 561         return (0);
 562 }
 563
 564 usb_error_t
 565 xhci_halt_controller(struct xhci_softc *sc)
 566 {
 567         uint32_t temp;
 568         uint16_t i;
 569
 570         DPRINTF("\n");
 571
 572         sc->sc_capa_off = 0;
 573         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 574         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
 575         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 576
 577         /* Halt controller */
 578         XWRITE4(sc, oper, XHCI_USBCMD, 0);
 579
 580         for (i = 0; i != 100; i++) {
 581                 usb_pause_mtx(NULL, hz / 100);
 582                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 583                 if (temp)
 584                         break;
 585         }
 586
 587         if (!temp) {
 588                 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
 589                 return (USB_ERR_IOERROR);
 590         }
 591         return (0);
 592 }
 593
 594 usb_error_t
 595 xhci_init(struct xhci_softc *sc, device_t self)
 596 {
 597         /* initialise some bus fields */
 598         sc->sc_bus.parent = self;
 599
 600         /* set the bus revision */
 601         sc->sc_bus.usbrev = USB_REV_3_0;
 602
 603         /* set up the bus struct */
 604         sc->sc_bus.methods = &xhci_bus_methods;
 605
 606         /* setup devices array */
 607         sc->sc_bus.devices = sc->sc_devices;
 608         sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
 609
 610         /* set default cycle state in case of early interrupts */
 611         sc->sc_event_ccs = 1;
 612         sc->sc_command_ccs = 1;
 613
 614         /* setup command queue mutex and condition varible */
 615         cv_init(&sc->sc_cmd_cv, "CMDQ");
 616         sx_init(&sc->sc_cmd_sx, "CMDQ lock");
 617
 618         /* get all DMA memory */
 619         if (usb_bus_mem_alloc_all(&sc->sc_bus,
 620             USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
 621                 return (ENOMEM);
 622         }
 623
 624         sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
 625         sc->sc_config_msg[0].bus = &sc->sc_bus;
 626         sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
 627         sc->sc_config_msg[1].bus = &sc->sc_bus;
 628
 629         if (usb_proc_create(&sc->sc_config_proc,
 630             &sc->sc_bus.bus_mtx, device_get_nameunit(self), USB_PRI_MED)) {
 631                 printf("WARNING: Creation of XHCI configure "
 632                     "callback process failed.\n");
 633         }
 634         return (0);
 635 }
 636
 637 void
 638 xhci_uninit(struct xhci_softc *sc)
 639 {
 640         usb_proc_free(&sc->sc_config_proc);
 641
 642         usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 643
 644         cv_destroy(&sc->sc_cmd_cv);
 645         sx_destroy(&sc->sc_cmd_sx);
 646 }
 647
 648 static void
 649 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
 650 {
 651         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 652
 653         switch (state) {
 654         case USB_HW_POWER_SUSPEND:
 655                 DPRINTF("Stopping the XHCI\n");
 656                 xhci_halt_controller(sc);
 657                 break;
 658         case USB_HW_POWER_SHUTDOWN:
 659                 DPRINTF("Stopping the XHCI\n");
 660                 xhci_halt_controller(sc);
 661                 break;
 662         case USB_HW_POWER_RESUME:
 663                 DPRINTF("Starting the XHCI\n");
 664                 xhci_start_controller(sc);
 665                 break;
 666         default:
 667                 break;
 668         }
 669 }
 670
 671 static usb_error_t
 672 xhci_generic_done_sub(struct usb_xfer *xfer)
 673 {
 674         struct xhci_td *td;
 675         struct xhci_td *td_alt_next;
 676         uint32_t len;
 677         uint8_t status;
 678
 679         td = xfer->td_transfer_cache;
 680         td_alt_next = td->alt_next;
 681
 682         if (xfer->aframes != xfer->nframes)
 683                 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
 684
 685         while (1) {
 686
 687                 usb_pc_cpu_invalidate(td->page_cache);
 688
 689                 status = td->status;
 690                 len = td->remainder;
 691
 692                 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
 693                     xfer, (unsigned int)xfer->aframes,
 694                     (unsigned int)xfer->nframes,
 695                     (unsigned int)len, (unsigned int)td->len,
 696                     (unsigned int)status);
 697
 698                 /*
 699                  * Verify the status length and
 700                  * add the length to "frlengths[]":
 701                  */
 702                 if (len > td->len) {
 703                         /* should not happen */
 704                         DPRINTF("Invalid status length, "
 705                             "0x%04x/0x%04x bytes\n", len, td->len);
 706                         status = XHCI_TRB_ERROR_LENGTH;
 707                 } else if (xfer->aframes != xfer->nframes) {
 708                         xfer->frlengths[xfer->aframes] += td->len - len;
 709                 }
 710                 /* Check for last transfer */
 711                 if (((void *)td) == xfer->td_transfer_last) {
 712                         td = NULL;
 713                         break;
 714                 }
 715                 /* Check for transfer error */
 716                 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
 717                     status != XHCI_TRB_ERROR_SUCCESS) {
 718                         /* the transfer is finished */
 719                         td = NULL;
 720                         break;
 721                 }
 722                 /* Check for short transfer */
 723                 if (len > 0) {
 724                         if (xfer->flags_int.short_frames_ok ||
 725                             xfer->flags_int.isochronous_xfr ||
 726                             xfer->flags_int.control_xfr) {
 727                                 /* follow alt next */
 728                                 td = td->alt_next;
 729                         } else {
 730                                 /* the transfer is finished */
 731                                 td = NULL;
 732                         }
 733                         break;
 734                 }
 735                 td = td->obj_next;
 736
 737                 if (td->alt_next != td_alt_next) {
 738                         /* this USB frame is complete */
 739                         break;
 740                 }
 741         }
 742
 743         /* update transfer cache */
 744
 745         xfer->td_transfer_cache = td;
 746
 747         return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
 748             (status != XHCI_TRB_ERROR_SHORT_PKT &&
 749             status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
 750             USB_ERR_NORMAL_COMPLETION);
 751 }
 752
 753 static void
 754 xhci_generic_done(struct usb_xfer *xfer)
 755 {
 756         usb_error_t err = 0;
 757
 758         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
 759             xfer, xfer->endpoint);
 760
 761         /* reset scanner */
 762
 763         xfer->td_transfer_cache = xfer->td_transfer_first;
 764
 765         if (xfer->flags_int.control_xfr) {
 766
 767                 if (xfer->flags_int.control_hdr)
 768                         err = xhci_generic_done_sub(xfer);
 769
 770                 xfer->aframes = 1;
 771
 772                 if (xfer->td_transfer_cache == NULL)
 773                         goto done;
 774         }
 775
 776         while (xfer->aframes != xfer->nframes) {
 777
 778                 err = xhci_generic_done_sub(xfer);
 779                 xfer->aframes++;
 780
 781                 if (xfer->td_transfer_cache == NULL)
 782                         goto done;
 783         }
 784
 785         if (xfer->flags_int.control_xfr &&
 786             !xfer->flags_int.control_act)
 787                 err = xhci_generic_done_sub(xfer);
 788 done:
 789         /* transfer is complete */
 790         xhci_device_done(xfer, err);
 791 }
 792
 793 static void
 794 xhci_activate_transfer(struct usb_xfer *xfer)
 795 {
 796         struct xhci_td *td;
 797
 798         td = xfer->td_transfer_cache;
 799
 800         usb_pc_cpu_invalidate(td->page_cache);
 801
 802         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 803
 804                 /* activate the transfer */
 805
 806                 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
 807                 usb_pc_cpu_flush(td->page_cache);
 808
 809                 xhci_endpoint_doorbell(xfer);
 810         }
 811 }
 812
 813 static void
 814 xhci_skip_transfer(struct usb_xfer *xfer)
 815 {
 816         struct xhci_td *td;
 817         struct xhci_td *td_last;
 818
 819         td = xfer->td_transfer_cache;
 820         td_last = xfer->td_transfer_last;
 821
 822         td = td->alt_next;
 823
 824         usb_pc_cpu_invalidate(td->page_cache);
 825
 826         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 827
 828                 usb_pc_cpu_invalidate(td_last->page_cache);
 829
 830                 /* copy LINK TRB to current waiting location */
 831
 832                 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
 833                 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
 834                 usb_pc_cpu_flush(td->page_cache);
 835
 836                 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
 837                 usb_pc_cpu_flush(td->page_cache);
 838
 839                 xhci_endpoint_doorbell(xfer);
 840         }
 841 }
 842
 843 /*------------------------------------------------------------------------*
 844  *      xhci_check_transfer
 845  *------------------------------------------------------------------------*/
 846 static void
 847 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
 848 {
 849         int64_t offset;
 850         uint64_t td_event;
 851         uint32_t temp;
 852         uint32_t remainder;
 853         uint8_t status;
 854         uint8_t halted;
 855         uint8_t epno;
 856         uint8_t index;
 857         uint8_t i;
 858
 859         /* decode TRB */
 860         td_event = le64toh(trb->qwTrb0);
 861         temp = le32toh(trb->dwTrb2);
 862
 863         remainder = XHCI_TRB_2_REM_GET(temp);
 864         status = XHCI_TRB_2_ERROR_GET(temp);
 865
 866         temp = le32toh(trb->dwTrb3);
 867         epno = XHCI_TRB_3_EP_GET(temp);
 868         index = XHCI_TRB_3_SLOT_GET(temp);
 869
 870         /* check if error means halted */
 871         halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
 872             status != XHCI_TRB_ERROR_SUCCESS);
 873
 874         DPRINTF("slot=%u epno=%u remainder=%u status=%u\n",
 875             index, epno, remainder, status);
 876
 877         if (index > sc->sc_noslot) {
 878                 DPRINTF("Invalid slot.\n");
 879                 return;
 880         }
 881
 882         if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
 883                 DPRINTF("Invalid endpoint.\n");
 884                 return;
 885         }
 886
 887         /* try to find the USB transfer that generated the event */
 888         for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
 889                 struct usb_xfer *xfer;
 890                 struct xhci_td *td;
 891                 struct xhci_endpoint_ext *pepext;
 892
 893                 pepext = &sc->sc_hw.devs[index].endp[epno];
 894
 895                 xfer = pepext->xfer[i];
 896                 if (xfer == NULL)
 897                         continue;
 898
 899                 td = xfer->td_transfer_cache;
 900
 901                 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
 902                         (long long)td_event,
 903                         (long long)td->td_self,
 904                         (long long)td->td_self + sizeof(td->td_trb));
 905
 906                 /*
 907                  * NOTE: Some XHCI implementations might not trigger
 908                  * an event on the last LINK TRB so we need to
 909                  * consider both the last and second last event
 910                  * address as conditions for a successful transfer.
 911                  *
 912                  * NOTE: We assume that the XHCI will only trigger one
 913                  * event per chain of TRBs.
 914                  */
 915
 916                 offset = td_event - td->td_self;
 917
 918                 if (offset >= 0 &&
 919                     offset < (int64_t)sizeof(td->td_trb)) {
 920
 921                         usb_pc_cpu_invalidate(td->page_cache);
 922
 923                         /* compute rest of remainder, if any */
 924                         for (i = (offset / 16) + 1; i < td->ntrb; i++) {
 925                                 temp = le32toh(td->td_trb[i].dwTrb2);
 926                                 remainder += XHCI_TRB_2_BYTES_GET(temp);
 927                         }
 928
 929                         DPRINTFN(5, "New remainder: %u\n", remainder);
 930
 931                         /* clear isochronous transfer errors */
 932                         if (xfer->flags_int.isochronous_xfr) {
 933                                 if (halted) {
 934                                         halted = 0;
 935                                         status = XHCI_TRB_ERROR_SUCCESS;
 936                                         remainder = td->len;
 937                                 }
 938                         }
 939
 940                         /* "td->remainder" is verified later */
 941                         td->remainder = remainder;
 942                         td->status = status;
 943
 944                         usb_pc_cpu_flush(td->page_cache);
 945
 946                         /*
 947                          * 1) Last transfer descriptor makes the
 948                          * transfer done
 949                          */
 950                         if (((void *)td) == xfer->td_transfer_last) {
 951                                 DPRINTF("TD is last\n");
 952                                 xhci_generic_done(xfer);
 953                                 break;
 954                         }
 955
 956                         /*
 957                          * 2) Any kind of error makes the transfer
 958                          * done
 959                          */
 960                         if (halted) {
 961                                 DPRINTF("TD has I/O error\n");
 962                                 xhci_generic_done(xfer);
 963                                 break;
 964                         }
 965
 966                         /*
 967                          * 3) If there is no alternate next transfer,
 968                          * a short packet also makes the transfer done
 969                          */
 970                         if (td->remainder > 0) {
 971                                 if (td->alt_next == NULL) {
 972                                         DPRINTF(
 973                                             "short TD has no alternate next\n");
 974                                         xhci_generic_done(xfer);
 975                                         break;
 976                                 }
 977                                 DPRINTF("TD has short pkt\n");
 978                                 if (xfer->flags_int.short_frames_ok ||
 979                                     xfer->flags_int.isochronous_xfr ||
 980                                     xfer->flags_int.control_xfr) {
 981                                         /* follow the alt next */
 982                                         xfer->td_transfer_cache = td->alt_next;
 983                                         xhci_activate_transfer(xfer);
 984                                         break;
 985                                 }
 986                                 xhci_skip_transfer(xfer);
 987                                 xhci_generic_done(xfer);
 988                                 break;
 989                         }
 990
 991                         /*
 992                          * 4) Transfer complete - go to next TD
 993                          */
 994                         DPRINTF("Following next TD\n");
 995                         xfer->td_transfer_cache = td->obj_next;
 996                         xhci_activate_transfer(xfer);
 997                         break;          /* there should only be one match */
 998                 }
 999         }
1000 }
1001
1002 static int
1003 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
1004 {
1005         if (sc->sc_cmd_addr == trb->qwTrb0) {
1006                 DPRINTF("Received command event\n");
1007                 sc->sc_cmd_result[0] = trb->dwTrb2;
1008                 sc->sc_cmd_result[1] = trb->dwTrb3;
1009                 cv_signal(&sc->sc_cmd_cv);
1010                 return (1);     /* command match */
1011         }
1012         return (0);
1013 }
1014
1015 static int
1016 xhci_interrupt_poll(struct xhci_softc *sc)
1017 {
1018         struct usb_page_search buf_res;
1019         struct xhci_hw_root *phwr;
1020         uint64_t addr;
1021         uint32_t temp;
1022         int retval = 0;
1023         uint16_t i;
1024         uint8_t event;
1025         uint8_t j;
1026         uint8_t k;
1027         uint8_t t;
1028
1029         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1030
1031         phwr = buf_res.buffer;
1032
1033         /* Receive any events */
1034
1035         usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1036
1037         i = sc->sc_event_idx;
1038         j = sc->sc_event_ccs;
1039         t = 2;
1040
1041         while (1) {
1042
1043                 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1044
1045                 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1046
1047                 if (j != k)
1048                         break;
1049
1050                 event = XHCI_TRB_3_TYPE_GET(temp);
1051
1052                 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1053                     i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1054                     (long)le32toh(phwr->hwr_events[i].dwTrb2),
1055                     (long)le32toh(phwr->hwr_events[i].dwTrb3));
1056
1057                 switch (event) {
1058                 case XHCI_TRB_EVENT_TRANSFER:
1059                         xhci_check_transfer(sc, &phwr->hwr_events[i]);
1060                         break;
1061                 case XHCI_TRB_EVENT_CMD_COMPLETE:
1062                         retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1063                         break;
1064                 default:
1065                         DPRINTF("Unhandled event = %u\n", event);
1066                         break;
1067                 }
1068
1069                 i++;
1070
1071                 if (i == XHCI_MAX_EVENTS) {
1072                         i = 0;
1073                         j ^= 1;
1074
1075                         /* check for timeout */
1076                         if (!--t)
1077                                 break;
1078                 }
1079         }
1080
1081         sc->sc_event_idx = i;
1082         sc->sc_event_ccs = j;
1083
1084         /*
1085          * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1086          * latched. That means to activate the register we need to
1087          * write both the low and high double word of the 64-bit
1088          * register.
1089          */
1090
1091         addr = buf_res.physaddr;
1092         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1093
1094         /* try to clear busy bit */
1095         addr |= XHCI_ERDP_LO_BUSY;
1096
1097         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1098         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1099
1100         return (retval);
1101 }
1102
1103 static usb_error_t
1104 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1105     uint16_t timeout_ms)
1106 {
1107         struct usb_page_search buf_res;
1108         struct xhci_hw_root *phwr;
1109         uint64_t addr;
1110         uint32_t temp;
1111         uint8_t i;
1112         uint8_t j;
1113         uint8_t timeout = 0;
1114         int err;
1115
1116         XHCI_CMD_ASSERT_LOCKED(sc);
1117
1118         /* get hardware root structure */
1119
1120         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1121
1122         phwr = buf_res.buffer;
1123
1124         /* Queue command */
1125
1126         USB_BUS_LOCK(&sc->sc_bus);
1127 retry:
1128         i = sc->sc_command_idx;
1129         j = sc->sc_command_ccs;
1130
1131         DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1132             i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1133             (long long)le64toh(trb->qwTrb0),
1134             (long)le32toh(trb->dwTrb2),
1135             (long)le32toh(trb->dwTrb3));
1136
1137         phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1138         phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1139
1140         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1141
1142         temp = trb->dwTrb3;
1143
1144         if (j)
1145                 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1146         else
1147                 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1148
1149         temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1150
1151         phwr->hwr_commands[i].dwTrb3 = temp;
1152
1153         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1154
1155         addr = buf_res.physaddr;
1156         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1157
1158         sc->sc_cmd_addr = htole64(addr);
1159
1160         i++;
1161
1162         if (i == (XHCI_MAX_COMMANDS - 1)) {
1163
1164                 if (j) {
1165                         temp = htole32(XHCI_TRB_3_TC_BIT |
1166                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1167                             XHCI_TRB_3_CYCLE_BIT);
1168                 } else {
1169                         temp = htole32(XHCI_TRB_3_TC_BIT |
1170                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1171                 }
1172
1173                 phwr->hwr_commands[i].dwTrb3 = temp;
1174
1175                 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1176
1177                 i = 0;
1178                 j ^= 1;
1179         }
1180
1181         sc->sc_command_idx = i;
1182         sc->sc_command_ccs = j;
1183
1184         XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1185
1186         err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1187             USB_MS_TO_TICKS(timeout_ms));
1188
1189         /*
1190          * In some error cases event interrupts are not generated.
1191          * Poll one time to see if the command has completed.
1192          */
1193         if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1194                 DPRINTF("Command was completed when polling\n");
1195                 err = 0;
1196         }
1197         if (err != 0) {
1198                 DPRINTF("Command timeout!\n");
1199                 /*
1200                  * After some weeks of continuous operation, it has
1201                  * been observed that the ASMedia Technology, ASM1042
1202                  * SuperSpeed USB Host Controller can suddenly stop
1203                  * accepting commands via the command queue. Try to
1204                  * first reset the command queue. If that fails do a
1205                  * host controller reset.
1206                  */
1207                 if (timeout == 0 &&
1208                     xhci_reset_command_queue_locked(sc) == 0) {
1209                         temp = le32toh(trb->dwTrb3);
1210
1211                         /*
1212                          * Avoid infinite XHCI reset loops if the set
1213                          * address command fails to respond due to a
1214                          * non-enumerating device:
1215                          */
1216                         if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE &&
1217                             (temp & XHCI_TRB_3_BSR_BIT) == 0) {
1218                                 DPRINTF("Set address timeout\n");
1219                         } else {
1220                                 timeout = 1;
1221                                 goto retry;
1222                         }
1223                 } else {
1224                         DPRINTF("Controller reset!\n");
1225                         usb_bus_reset_async_locked(&sc->sc_bus);
1226                 }
1227                 err = USB_ERR_TIMEOUT;
1228                 trb->dwTrb2 = 0;
1229                 trb->dwTrb3 = 0;
1230         } else {
1231                 temp = le32toh(sc->sc_cmd_result[0]);
1232                 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1233                         err = USB_ERR_IOERROR;
1234
1235                 trb->dwTrb2 = sc->sc_cmd_result[0];
1236                 trb->dwTrb3 = sc->sc_cmd_result[1];
1237         }
1238
1239         USB_BUS_UNLOCK(&sc->sc_bus);
1240
1241         return (err);
1242 }
1243
1244 #if 0
1245 static usb_error_t
1246 xhci_cmd_nop(struct xhci_softc *sc)
1247 {
1248         struct xhci_trb trb;
1249         uint32_t temp;
1250
1251         DPRINTF("\n");
1252
1253         trb.qwTrb0 = 0;
1254         trb.dwTrb2 = 0;
1255         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1256
1257         trb.dwTrb3 = htole32(temp);
1258
1259         return (xhci_do_command(sc, &trb, 100 /* ms */));
1260 }
1261 #endif
1262
1263 static usb_error_t
1264 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1265 {
1266         struct xhci_trb trb;
1267         uint32_t temp;
1268         usb_error_t err;
1269
1270         DPRINTF("\n");
1271
1272         trb.qwTrb0 = 0;
1273         trb.dwTrb2 = 0;
1274         trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1275
1276         err = xhci_do_command(sc, &trb, 100 /* ms */);
1277         if (err)
1278                 goto done;
1279
1280         temp = le32toh(trb.dwTrb3);
1281
1282         *pslot = XHCI_TRB_3_SLOT_GET(temp);
1283
1284 done:
1285         return (err);
1286 }
1287
1288 static usb_error_t
1289 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1290 {
1291         struct xhci_trb trb;
1292         uint32_t temp;
1293
1294         DPRINTF("\n");
1295
1296         trb.qwTrb0 = 0;
1297         trb.dwTrb2 = 0;
1298         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1299             XHCI_TRB_3_SLOT_SET(slot_id);
1300
1301         trb.dwTrb3 = htole32(temp);
1302
1303         return (xhci_do_command(sc, &trb, 100 /* ms */));
1304 }
1305
1306 static usb_error_t
1307 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1308     uint8_t bsr, uint8_t slot_id)
1309 {
1310         struct xhci_trb trb;
1311         uint32_t temp;
1312
1313         DPRINTF("\n");
1314
1315         trb.qwTrb0 = htole64(input_ctx);
1316         trb.dwTrb2 = 0;
1317         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1318             XHCI_TRB_3_SLOT_SET(slot_id);
1319
1320         if (bsr)
1321                 temp |= XHCI_TRB_3_BSR_BIT;
1322
1323         trb.dwTrb3 = htole32(temp);
1324
1325         return (xhci_do_command(sc, &trb, 500 /* ms */));
1326 }
1327
1328 static usb_error_t
1329 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1330 {
1331         struct usb_page_search buf_inp;
1332         struct usb_page_search buf_dev;
1333         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1334         struct xhci_hw_dev *hdev;
1335         struct xhci_dev_ctx *pdev;
1336         struct xhci_endpoint_ext *pepext;
1337         uint32_t temp;
1338         uint16_t mps;
1339         usb_error_t err;
1340         uint8_t index;
1341
1342         /* the root HUB case is not handled here */
1343         if (udev->parent_hub == NULL)
1344                 return (USB_ERR_INVAL);
1345
1346         index = udev->controller_slot_id;
1347
1348         hdev =  &sc->sc_hw.devs[index];
1349
1350         if (mtx != NULL)
1351                 mtx_unlock(mtx);
1352
1353         XHCI_CMD_LOCK(sc);
1354
1355         switch (hdev->state) {
1356         case XHCI_ST_DEFAULT:
1357         case XHCI_ST_ENABLED:
1358
1359                 hdev->state = XHCI_ST_ENABLED;
1360
1361                 /* set configure mask to slot and EP0 */
1362                 xhci_configure_mask(udev, 3, 0);
1363
1364                 /* configure input slot context structure */
1365                 err = xhci_configure_device(udev);
1366
1367                 if (err != 0) {
1368                         DPRINTF("Could not configure device\n");
1369                         break;
1370                 }
1371
1372                 /* configure input endpoint context structure */
1373                 switch (udev->speed) {
1374                 case USB_SPEED_LOW:
1375                 case USB_SPEED_FULL:
1376                         mps = 8;
1377                         break;
1378                 case USB_SPEED_HIGH:
1379                         mps = 64;
1380                         break;
1381                 default:
1382                         mps = 512;
1383                         break;
1384                 }
1385
1386                 pepext = xhci_get_endpoint_ext(udev,
1387                     &udev->ctrl_ep_desc);
1388                 err = xhci_configure_endpoint(udev,
1389                     &udev->ctrl_ep_desc, pepext->physaddr,
1390                     0, 1, 1, 0, mps, mps);
1391
1392                 if (err != 0) {
1393                         DPRINTF("Could not configure default endpoint\n");
1394                         break;
1395                 }
1396
1397                 /* execute set address command */
1398                 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1399
1400                 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1401                     (address == 0), index);
1402
1403                 if (err != 0) {
1404                         temp = le32toh(sc->sc_cmd_result[0]);
1405                         if (address == 0 && sc->sc_port_route != NULL &&
1406                             XHCI_TRB_2_ERROR_GET(temp) ==
1407                             XHCI_TRB_ERROR_PARAMETER) {
1408                                 /* LynxPoint XHCI - ports are not switchable */
1409                                 /* Un-route all ports from the XHCI */
1410                                 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1411                         }
1412                         DPRINTF("Could not set address "
1413                             "for slot %u.\n", index);
1414                         if (address != 0)
1415                                 break;
1416                 }
1417
1418                 /* update device address to new value */
1419
1420                 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1421                 pdev = buf_dev.buffer;
1422                 usb_pc_cpu_invalidate(&hdev->device_pc);
1423
1424                 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1425                 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1426
1427                 /* update device state to new value */
1428
1429                 if (address != 0)
1430                         hdev->state = XHCI_ST_ADDRESSED;
1431                 else
1432                         hdev->state = XHCI_ST_DEFAULT;
1433                 break;
1434
1435         default:
1436                 DPRINTF("Wrong state for set address.\n");
1437                 err = USB_ERR_IOERROR;
1438                 break;
1439         }
1440         XHCI_CMD_UNLOCK(sc);
1441
1442         if (mtx != NULL)
1443                 mtx_lock(mtx);
1444
1445         return (err);
1446 }
1447
1448 static usb_error_t
1449 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1450     uint8_t deconfigure, uint8_t slot_id)
1451 {
1452         struct xhci_trb trb;
1453         uint32_t temp;
1454
1455         DPRINTF("\n");
1456
1457         trb.qwTrb0 = htole64(input_ctx);
1458         trb.dwTrb2 = 0;
1459         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1460             XHCI_TRB_3_SLOT_SET(slot_id);
1461
1462         if (deconfigure)
1463                 temp |= XHCI_TRB_3_DCEP_BIT;
1464
1465         trb.dwTrb3 = htole32(temp);
1466
1467         return (xhci_do_command(sc, &trb, 100 /* ms */));
1468 }
1469
1470 static usb_error_t
1471 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1472     uint8_t slot_id)
1473 {
1474         struct xhci_trb trb;
1475         uint32_t temp;
1476
1477         DPRINTF("\n");
1478
1479         trb.qwTrb0 = htole64(input_ctx);
1480         trb.dwTrb2 = 0;
1481         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1482             XHCI_TRB_3_SLOT_SET(slot_id);
1483         trb.dwTrb3 = htole32(temp);
1484
1485         return (xhci_do_command(sc, &trb, 100 /* ms */));
1486 }
1487
1488 static usb_error_t
1489 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1490     uint8_t ep_id, uint8_t slot_id)
1491 {
1492         struct xhci_trb trb;
1493         uint32_t temp;
1494
1495         DPRINTF("\n");
1496
1497         trb.qwTrb0 = 0;
1498         trb.dwTrb2 = 0;
1499         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1500             XHCI_TRB_3_SLOT_SET(slot_id) |
1501             XHCI_TRB_3_EP_SET(ep_id);
1502
1503         if (preserve)
1504                 temp |= XHCI_TRB_3_PRSV_BIT;
1505
1506         trb.dwTrb3 = htole32(temp);
1507
1508         return (xhci_do_command(sc, &trb, 100 /* ms */));
1509 }
1510
1511 static usb_error_t
1512 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1513     uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1514 {
1515         struct xhci_trb trb;
1516         uint32_t temp;
1517
1518         DPRINTF("\n");
1519
1520         trb.qwTrb0 = htole64(dequeue_ptr);
1521
1522         temp = XHCI_TRB_2_STREAM_SET(stream_id);
1523         trb.dwTrb2 = htole32(temp);
1524
1525         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1526             XHCI_TRB_3_SLOT_SET(slot_id) |
1527             XHCI_TRB_3_EP_SET(ep_id);
1528         trb.dwTrb3 = htole32(temp);
1529
1530         return (xhci_do_command(sc, &trb, 100 /* ms */));
1531 }
1532
1533 static usb_error_t
1534 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1535     uint8_t ep_id, uint8_t slot_id)
1536 {
1537         struct xhci_trb trb;
1538         uint32_t temp;
1539
1540         DPRINTF("\n");
1541
1542         trb.qwTrb0 = 0;
1543         trb.dwTrb2 = 0;
1544         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1545             XHCI_TRB_3_SLOT_SET(slot_id) |
1546             XHCI_TRB_3_EP_SET(ep_id);
1547
1548         if (suspend)
1549                 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1550
1551         trb.dwTrb3 = htole32(temp);
1552
1553         return (xhci_do_command(sc, &trb, 100 /* ms */));
1554 }
1555
1556 static usb_error_t
1557 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1558 {
1559         struct xhci_trb trb;
1560         uint32_t temp;
1561
1562         DPRINTF("\n");
1563
1564         trb.qwTrb0 = 0;
1565         trb.dwTrb2 = 0;
1566         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1567             XHCI_TRB_3_SLOT_SET(slot_id);
1568
1569         trb.dwTrb3 = htole32(temp);
1570
1571         return (xhci_do_command(sc, &trb, 100 /* ms */));
1572 }
1573
1574 /*------------------------------------------------------------------------*
1575  *      xhci_interrupt - XHCI interrupt handler
1576  *------------------------------------------------------------------------*/
1577 void
1578 xhci_interrupt(struct xhci_softc *sc)
1579 {
1580         uint32_t status;
1581         uint32_t temp;
1582
1583         USB_BUS_LOCK(&sc->sc_bus);
1584
1585         status = XREAD4(sc, oper, XHCI_USBSTS);
1586
1587         /* acknowledge interrupts, if any */
1588         if (status != 0) {
1589                 XWRITE4(sc, oper, XHCI_USBSTS, status);
1590                 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1591         }
1592
1593         temp = XREAD4(sc, runt, XHCI_IMAN(0));
1594
1595         /* force clearing of pending interrupts */
1596         if (temp & XHCI_IMAN_INTR_PEND)
1597                 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1598
1599         /* check for event(s) */
1600         xhci_interrupt_poll(sc);
1601
1602         if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1603             XHCI_STS_HSE | XHCI_STS_HCE)) {
1604
1605                 if (status & XHCI_STS_PCD) {
1606                         xhci_root_intr(sc);
1607                 }
1608
1609                 if (status & XHCI_STS_HCH) {
1610                         printf("%s: host controller halted\n",
1611                             __FUNCTION__);
1612                 }
1613
1614                 if (status & XHCI_STS_HSE) {
1615                         printf("%s: host system error\n",
1616                             __FUNCTION__);
1617                 }
1618
1619                 if (status & XHCI_STS_HCE) {
1620                         printf("%s: host controller error\n",
1621                            __FUNCTION__);
1622                 }
1623         }
1624         USB_BUS_UNLOCK(&sc->sc_bus);
1625 }
1626
1627 /*------------------------------------------------------------------------*
1628  *      xhci_timeout - XHCI timeout handler
1629  *------------------------------------------------------------------------*/
1630 static void
1631 xhci_timeout(void *arg)
1632 {
1633         struct usb_xfer *xfer = arg;
1634
1635         DPRINTF("xfer=%p\n", xfer);
1636
1637         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1638
1639         /* transfer is transferred */
1640         xhci_device_done(xfer, USB_ERR_TIMEOUT);
1641 }
1642
1643 static void
1644 xhci_do_poll(struct usb_bus *bus)
1645 {
1646         struct xhci_softc *sc = XHCI_BUS2SC(bus);
1647
1648         USB_BUS_LOCK(&sc->sc_bus);
1649         xhci_interrupt_poll(sc);
1650         USB_BUS_UNLOCK(&sc->sc_bus);
1651 }
1652
1653 static void
1654 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1655 {
1656         struct usb_page_search buf_res;
1657         struct xhci_td *td;
1658         struct xhci_td *td_next;
1659         struct xhci_td *td_alt_next;
1660         struct xhci_td *td_first;
1661         uint32_t buf_offset;
1662         uint32_t average;
1663         uint32_t len_old;
1664         uint32_t npkt_off;
1665         uint32_t dword;
1666         uint8_t shortpkt_old;
1667         uint8_t precompute;
1668         uint8_t x;
1669
1670         td_alt_next = NULL;
1671         buf_offset = 0;
1672         shortpkt_old = temp->shortpkt;
1673         len_old = temp->len;
1674         npkt_off = 0;
1675         precompute = 1;
1676
1677 restart:
1678
1679         td = temp->td;
1680         td_next = td_first = temp->td_next;
1681
1682         while (1) {
1683
1684                 if (temp->len == 0) {
1685
1686                         if (temp->shortpkt)
1687                                 break;
1688
1689                         /* send a Zero Length Packet, ZLP, last */
1690
1691                         temp->shortpkt = 1;
1692                         average = 0;
1693
1694                 } else {
1695
1696                         average = temp->average;
1697
1698                         if (temp->len < average) {
1699                                 if (temp->len % temp->max_packet_size) {
1700                                         temp->shortpkt = 1;
1701                                 }
1702                                 average = temp->len;
1703                         }
1704                 }
1705
1706                 if (td_next == NULL)
1707                         panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1708
1709                 /* get next TD */
1710
1711                 td = td_next;
1712                 td_next = td->obj_next;
1713
1714                 /* check if we are pre-computing */
1715
1716                 if (precompute) {
1717
1718                         /* update remaining length */
1719
1720                         temp->len -= average;
1721
1722                         continue;
1723                 }
1724                 /* fill out current TD */
1725
1726                 td->len = average;
1727                 td->remainder = 0;
1728                 td->status = 0;
1729
1730                 /* update remaining length */
1731
1732                 temp->len -= average;
1733
1734                 /* reset TRB index */
1735
1736                 x = 0;
1737
1738                 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1739                         /* immediate data */
1740
1741                         if (average > 8)
1742                                 average = 8;
1743
1744                         td->td_trb[0].qwTrb0 = 0;
1745
1746                         usbd_copy_out(temp->pc, temp->offset + buf_offset,
1747                            (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1748                            average);
1749
1750                         dword = XHCI_TRB_2_BYTES_SET(8) |
1751                             XHCI_TRB_2_TDSZ_SET(0) |
1752                             XHCI_TRB_2_IRQ_SET(0);
1753
1754                         td->td_trb[0].dwTrb2 = htole32(dword);
1755
1756                         dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1757                           XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1758
1759                         /* check wLength */
1760                         if (td->td_trb[0].qwTrb0 &
1761                            htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1762                                 if (td->td_trb[0].qwTrb0 &
1763                                     htole64(XHCI_TRB_0_DIR_IN_MASK))
1764                                         dword |= XHCI_TRB_3_TRT_IN;
1765                                 else
1766                                         dword |= XHCI_TRB_3_TRT_OUT;
1767                         }
1768
1769                         td->td_trb[0].dwTrb3 = htole32(dword);
1770 #ifdef USB_DEBUG
1771                         xhci_dump_trb(&td->td_trb[x]);
1772 #endif
1773                         x++;
1774
1775                 } else do {
1776
1777                         uint32_t npkt;
1778
1779                         /* fill out buffer pointers */
1780
1781                         if (average == 0) {
1782                                 memset(&buf_res, 0, sizeof(buf_res));
1783                         } else {
1784                                 usbd_get_page(temp->pc, temp->offset +
1785                                     buf_offset, &buf_res);
1786
1787                                 /* get length to end of page */
1788                                 if (buf_res.length > average)
1789                                         buf_res.length = average;
1790
1791                                 /* check for maximum length */
1792                                 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1793                                         buf_res.length = XHCI_TD_PAGE_SIZE;
1794
1795                                 npkt_off += buf_res.length;
1796                         }
1797
1798                         /* setup npkt */
1799                         npkt = (len_old - npkt_off + temp->max_packet_size - 1) /
1800                             temp->max_packet_size;
1801
1802                         if (npkt == 0)
1803                                 npkt = 1;
1804                         else if (npkt > 31)
1805                                 npkt = 31;
1806
1807                         /* fill out TRB's */
1808                         td->td_trb[x].qwTrb0 =
1809                             htole64((uint64_t)buf_res.physaddr);
1810
1811                         dword =
1812                           XHCI_TRB_2_BYTES_SET(buf_res.length) |
1813                           XHCI_TRB_2_TDSZ_SET(npkt) |
1814                           XHCI_TRB_2_IRQ_SET(0);
1815
1816                         td->td_trb[x].dwTrb2 = htole32(dword);
1817
1818                         switch (temp->trb_type) {
1819                         case XHCI_TRB_TYPE_ISOCH:
1820                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1821                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1822                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1823                                 if (td != td_first) {
1824                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1825                                 } else if (temp->do_isoc_sync != 0) {
1826                                         temp->do_isoc_sync = 0;
1827                                         /* wait until "isoc_frame" */
1828                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1829                                             XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1830                                 } else {
1831                                         /* start data transfer at next interval */
1832                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1833                                             XHCI_TRB_3_ISO_SIA_BIT;
1834                                 }
1835                                 if (temp->direction == UE_DIR_IN)
1836                                         dword |= XHCI_TRB_3_ISP_BIT;
1837                                 break;
1838                         case XHCI_TRB_TYPE_DATA_STAGE:
1839                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1840                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE);
1841                                 if (temp->direction == UE_DIR_IN)
1842                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1843                                 /*
1844                                  * Section 3.2.9 in the XHCI
1845                                  * specification about control
1846                                  * transfers says that we should use a
1847                                  * normal-TRB if there are more TRBs
1848                                  * extending the data-stage
1849                                  * TRB. Update the "trb_type".
1850                                  */
1851                                 temp->trb_type = XHCI_TRB_TYPE_NORMAL;
1852                                 break;
1853                         case XHCI_TRB_TYPE_STATUS_STAGE:
1854                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1855                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE);
1856                                 if (temp->direction == UE_DIR_IN)
1857                                         dword |= XHCI_TRB_3_DIR_IN;
1858                                 break;
1859                         default:        /* XHCI_TRB_TYPE_NORMAL */
1860                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1861                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1862                                 if (temp->direction == UE_DIR_IN)
1863                                         dword |= XHCI_TRB_3_ISP_BIT;
1864                                 break;
1865                         }
1866                         td->td_trb[x].dwTrb3 = htole32(dword);
1867
1868                         average -= buf_res.length;
1869                         buf_offset += buf_res.length;
1870 #ifdef USB_DEBUG
1871                         xhci_dump_trb(&td->td_trb[x]);
1872 #endif
1873                         x++;
1874
1875                 } while (average != 0);
1876
1877                 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1878
1879                 /* store number of data TRB's */
1880
1881                 td->ntrb = x;
1882
1883                 DPRINTF("NTRB=%u\n", x);
1884
1885                 /* fill out link TRB */
1886
1887                 if (td_next != NULL) {
1888                         /* link the current TD with the next one */
1889                         td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1890                         DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1891                 } else {
1892                         /* this field will get updated later */
1893                         DPRINTF("NOLINK\n");
1894                 }
1895
1896                 dword = XHCI_TRB_2_IRQ_SET(0);
1897
1898                 td->td_trb[x].dwTrb2 = htole32(dword);
1899
1900                 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1901                     XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1902                     /*
1903                      * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1904                      * frame only receives a single short packet event
1905                      * by setting the CHAIN bit in the LINK field. In
1906                      * addition some XHCI controllers have problems
1907                      * sending a ZLP unless the CHAIN-BIT is set in
1908                      * the LINK TRB.
1909                      */
1910                     XHCI_TRB_3_CHAIN_BIT;
1911
1912                 td->td_trb[x].dwTrb3 = htole32(dword);
1913
1914                 td->alt_next = td_alt_next;
1915 #ifdef USB_DEBUG
1916                 xhci_dump_trb(&td->td_trb[x]);
1917 #endif
1918                 usb_pc_cpu_flush(td->page_cache);
1919         }
1920
1921         if (precompute) {
1922                 precompute = 0;
1923
1924                 /* setup alt next pointer, if any */
1925                 if (temp->last_frame) {
1926                         td_alt_next = NULL;
1927                 } else {
1928                         /* we use this field internally */
1929                         td_alt_next = td_next;
1930                 }
1931
1932                 /* restore */
1933                 temp->shortpkt = shortpkt_old;
1934                 temp->len = len_old;
1935                 goto restart;
1936         }
1937
1938         /*
1939          * Remove cycle bit from the first TRB if we are
1940          * stepping them:
1941          */
1942         if (temp->step_td != 0) {
1943                 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1944                 usb_pc_cpu_flush(td_first->page_cache);
1945         }
1946
1947         /* clear TD SIZE to zero, hence this is the last TRB */
1948         /* remove chain bit because this is the last data TRB in the chain */
1949         td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1950         td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1951         /* remove CHAIN-BIT from last LINK TRB */
1952         td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1953
1954         usb_pc_cpu_flush(td->page_cache);
1955
1956         temp->td = td;
1957         temp->td_next = td_next;
1958 }
1959
1960 static void
1961 xhci_setup_generic_chain(struct usb_xfer *xfer)
1962 {
1963         struct xhci_std_temp temp;
1964         struct xhci_td *td;
1965         uint32_t x;
1966         uint32_t y;
1967         uint8_t mult;
1968
1969         temp.do_isoc_sync = 0;
1970         temp.step_td = 0;
1971         temp.tbc = 0;
1972         temp.tlbpc = 0;
1973         temp.average = xfer->max_hc_frame_size;
1974         temp.max_packet_size = xfer->max_packet_size;
1975         temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
1976         temp.pc = NULL;
1977         temp.last_frame = 0;
1978         temp.offset = 0;
1979         temp.multishort = xfer->flags_int.isochronous_xfr ||
1980             xfer->flags_int.control_xfr ||
1981             xfer->flags_int.short_frames_ok;
1982
1983         /* toggle the DMA set we are using */
1984         xfer->flags_int.curr_dma_set ^= 1;
1985
1986         /* get next DMA set */
1987         td = xfer->td_start[xfer->flags_int.curr_dma_set];
1988
1989         temp.td = NULL;
1990         temp.td_next = td;
1991
1992         xfer->td_transfer_first = td;
1993         xfer->td_transfer_cache = td;
1994
1995         if (xfer->flags_int.isochronous_xfr) {
1996                 uint8_t shift;
1997
1998                 /* compute multiplier for ISOCHRONOUS transfers */
1999                 mult = xfer->endpoint->ecomp ?
2000                     (xfer->endpoint->ecomp->bmAttributes & 3) : 0;
2001                 /* check for USB 2.0 multiplier */
2002                 if (mult == 0) {
2003                         mult = (xfer->endpoint->edesc->
2004                             wMaxPacketSize[1] >> 3) & 3;
2005                 }
2006                 /* range check */
2007                 if (mult > 2)
2008                         mult = 3;
2009                 else
2010                         mult++;
2011
2012                 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
2013
2014                 DPRINTF("MFINDEX=0x%08x\n", x);
2015
2016                 switch (usbd_get_speed(xfer->xroot->udev)) {
2017                 case USB_SPEED_FULL:
2018                         shift = 3;
2019                         temp.isoc_delta = 8;    /* 1ms */
2020                         x += temp.isoc_delta - 1;
2021                         x &= ~(temp.isoc_delta - 1);
2022                         break;
2023                 default:
2024                         shift = usbd_xfer_get_fps_shift(xfer);
2025                         temp.isoc_delta = 1U << shift;
2026                         x += temp.isoc_delta - 1;
2027                         x &= ~(temp.isoc_delta - 1);
2028                         /* simple frame load balancing */
2029                         x += xfer->endpoint->usb_uframe;
2030                         break;
2031                 }
2032
2033                 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
2034
2035                 if ((xfer->endpoint->is_synced == 0) ||
2036                     (y < (xfer->nframes << shift)) ||
2037                     (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
2038                         /*
2039                          * If there is data underflow or the pipe
2040                          * queue is empty we schedule the transfer a
2041                          * few frames ahead of the current frame
2042                          * position. Else two isochronous transfers
2043                          * might overlap.
2044                          */
2045                         xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2046                         xfer->endpoint->is_synced = 1;
2047                         temp.do_isoc_sync = 1;
2048
2049                         DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2050                 }
2051
2052                 /* compute isochronous completion time */
2053
2054                 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2055
2056                 xfer->isoc_time_complete =
2057                     usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2058                     (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2059
2060                 x = 0;
2061                 temp.isoc_frame = xfer->endpoint->isoc_next;
2062                 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2063
2064                 xfer->endpoint->isoc_next += xfer->nframes << shift;
2065
2066         } else if (xfer->flags_int.control_xfr) {
2067
2068                 /* check if we should prepend a setup message */
2069
2070                 if (xfer->flags_int.control_hdr) {
2071
2072                         temp.len = xfer->frlengths[0];
2073                         temp.pc = xfer->frbuffers + 0;
2074                         temp.shortpkt = temp.len ? 1 : 0;
2075                         temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2076                         temp.direction = 0;
2077
2078                         /* check for last frame */
2079                         if (xfer->nframes == 1) {
2080                                 /* no STATUS stage yet, SETUP is last */
2081                                 if (xfer->flags_int.control_act)
2082                                         temp.last_frame = 1;
2083                         }
2084
2085                         xhci_setup_generic_chain_sub(&temp);
2086                 }
2087                 x = 1;
2088                 mult = 1;
2089                 temp.isoc_delta = 0;
2090                 temp.isoc_frame = 0;
2091                 temp.trb_type = xfer->flags_int.control_did_data ?
2092                     XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE;
2093         } else {
2094                 x = 0;
2095                 mult = 1;
2096                 temp.isoc_delta = 0;
2097                 temp.isoc_frame = 0;
2098                 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2099         }
2100
2101         if (x != xfer->nframes) {
2102                 /* setup page_cache pointer */
2103                 temp.pc = xfer->frbuffers + x;
2104                 /* set endpoint direction */
2105                 temp.direction = UE_GET_DIR(xfer->endpointno);
2106         }
2107
2108         while (x != xfer->nframes) {
2109
2110                 /* DATA0 / DATA1 message */
2111
2112                 temp.len = xfer->frlengths[x];
2113                 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2114                     x != 0 && temp.multishort == 0);
2115
2116                 x++;
2117
2118                 if (x == xfer->nframes) {
2119                         if (xfer->flags_int.control_xfr) {
2120                                 /* no STATUS stage yet, DATA is last */
2121                                 if (xfer->flags_int.control_act)
2122                                         temp.last_frame = 1;
2123                         } else {
2124                                 temp.last_frame = 1;
2125                         }
2126                 }
2127                 if (temp.len == 0) {
2128
2129                         /* make sure that we send an USB packet */
2130
2131                         temp.shortpkt = 0;
2132
2133                         temp.tbc = 0;
2134                         temp.tlbpc = mult - 1;
2135
2136                 } else if (xfer->flags_int.isochronous_xfr) {
2137
2138                         uint8_t tdpc;
2139
2140                         /*
2141                          * Isochronous transfers don't have short
2142                          * packet termination:
2143                          */
2144
2145                         temp.shortpkt = 1;
2146
2147                         /* isochronous transfers have a transfer limit */
2148
2149                         if (temp.len > xfer->max_frame_size)
2150                                 temp.len = xfer->max_frame_size;
2151
2152                         /* compute TD packet count */
2153                         tdpc = (temp.len + xfer->max_packet_size - 1) /
2154                             xfer->max_packet_size;
2155
2156                         temp.tbc = ((tdpc + mult - 1) / mult) - 1;
2157                         temp.tlbpc = (tdpc % mult);
2158
2159                         if (temp.tlbpc == 0)
2160                                 temp.tlbpc = mult - 1;
2161                         else
2162                                 temp.tlbpc--;
2163                 } else {
2164
2165                         /* regular data transfer */
2166
2167                         temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2168                 }
2169
2170                 xhci_setup_generic_chain_sub(&temp);
2171
2172                 if (xfer->flags_int.isochronous_xfr) {
2173                         temp.offset += xfer->frlengths[x - 1];
2174                         temp.isoc_frame += temp.isoc_delta;
2175                 } else {
2176                         /* get next Page Cache pointer */
2177                         temp.pc = xfer->frbuffers + x;
2178                 }
2179         }
2180
2181         /* check if we should append a status stage */
2182
2183         if (xfer->flags_int.control_xfr &&
2184             !xfer->flags_int.control_act) {
2185
2186                 /*
2187                  * Send a DATA1 message and invert the current
2188                  * endpoint direction.
2189                  */
2190                 temp.step_td = (xfer->nframes != 0);
2191                 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2192                 temp.len = 0;
2193                 temp.pc = NULL;
2194                 temp.shortpkt = 0;
2195                 temp.last_frame = 1;
2196                 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2197
2198                 xhci_setup_generic_chain_sub(&temp);
2199         }
2200
2201         td = temp.td;
2202
2203         /* must have at least one frame! */
2204
2205         xfer->td_transfer_last = td;
2206
2207         DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2208 }
2209
2210 static void
2211 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2212 {
2213         struct usb_page_search buf_res;
2214         struct xhci_dev_ctx_addr *pdctxa;
2215
2216         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2217
2218         pdctxa = buf_res.buffer;
2219
2220         DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2221
2222         pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2223
2224         usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2225 }
2226
2227 static usb_error_t
2228 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2229 {
2230         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2231         struct usb_page_search buf_inp;
2232         struct xhci_input_dev_ctx *pinp;
2233         uint32_t temp;
2234         uint8_t index;
2235         uint8_t x;
2236
2237         index = udev->controller_slot_id;
2238
2239         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2240
2241         pinp = buf_inp.buffer;
2242
2243         if (drop) {
2244                 mask &= XHCI_INCTX_NON_CTRL_MASK;
2245                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2246                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2247         } else {
2248                 /*
2249                  * Some hardware requires that we drop the endpoint
2250                  * context before adding it again:
2251                  */
2252                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0,
2253                     mask & XHCI_INCTX_NON_CTRL_MASK);
2254
2255                 /* Add new endpoint context */
2256                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2257
2258                 /* find most significant set bit */
2259                 for (x = 31; x != 1; x--) {
2260                         if (mask & (1 << x))
2261                                 break;
2262                 }
2263
2264                 /* adjust */
2265                 x--;
2266
2267                 /* figure out the maximum number of contexts */
2268                 if (x > sc->sc_hw.devs[index].context_num)
2269                         sc->sc_hw.devs[index].context_num = x;
2270                 else
2271                         x = sc->sc_hw.devs[index].context_num;
2272
2273                 /* update number of contexts */
2274                 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2275                 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2276                 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2277                 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2278         }
2279         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2280         return (0);
2281 }
2282
2283 static usb_error_t
2284 xhci_configure_endpoint(struct usb_device *udev,
2285     struct usb_endpoint_descriptor *edesc, uint64_t ring_addr,
2286     uint16_t interval, uint8_t max_packet_count, uint8_t mult,
2287     uint8_t fps_shift, uint16_t max_packet_size, uint16_t max_frame_size)
2288 {
2289         struct usb_page_search buf_inp;
2290         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2291         struct xhci_input_dev_ctx *pinp;
2292         uint32_t temp;
2293         uint8_t index;
2294         uint8_t epno;
2295         uint8_t type;
2296
2297         index = udev->controller_slot_id;
2298
2299         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2300
2301         pinp = buf_inp.buffer;
2302
2303         epno = edesc->bEndpointAddress;
2304         type = edesc->bmAttributes & UE_XFERTYPE;
2305
2306         if (type == UE_CONTROL)
2307                 epno |= UE_DIR_IN;
2308
2309         epno = XHCI_EPNO2EPID(epno);
2310
2311         if (epno == 0)
2312                 return (USB_ERR_NO_PIPE);               /* invalid */
2313
2314         if (max_packet_count == 0)
2315                 return (USB_ERR_BAD_BUFSIZE);
2316
2317         max_packet_count--;
2318
2319         if (mult == 0)
2320                 return (USB_ERR_BAD_BUFSIZE);
2321
2322         temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2323             XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2324             XHCI_EPCTX_0_LSA_SET(0);
2325
2326         switch (udev->speed) {
2327         case USB_SPEED_FULL:
2328         case USB_SPEED_LOW:
2329                 /* 1ms -> 125us */
2330                 fps_shift += 3;
2331                 break;
2332         default:
2333                 break;
2334         }
2335
2336         switch (type) {
2337         case UE_INTERRUPT:
2338                 if (fps_shift > 3)
2339                         fps_shift--;
2340                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2341                 break;
2342         case UE_ISOCHRONOUS:
2343                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2344
2345                 switch (udev->speed) {
2346                 case USB_SPEED_SUPER:
2347                         if (mult > 3)
2348                                 mult = 3;
2349                         temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2350                         max_packet_count /= mult;
2351                         break;
2352                 default:
2353                         break;
2354                 }
2355                 break;
2356         default:
2357                 break;
2358         }
2359
2360         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2361
2362         temp =
2363             XHCI_EPCTX_1_HID_SET(0) |
2364             XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2365             XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2366
2367         /*
2368          * Always enable the "three strikes and you are gone" feature
2369          * except for ISOCHRONOUS endpoints. This is suggested by
2370          * section 4.3.3 in the XHCI specification about device slot
2371          * initialisation.
2372          */
2373         if (type != UE_ISOCHRONOUS)
2374                 temp |= XHCI_EPCTX_1_CERR_SET(3);
2375
2376         switch (type) {
2377         case UE_CONTROL:
2378                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2379                 break;
2380         case UE_ISOCHRONOUS:
2381                 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2382                 break;
2383         case UE_BULK:
2384                 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2385                 break;
2386         default:
2387                 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2388                 break;
2389         }
2390
2391         /* check for IN direction */
2392         if (epno & 1)
2393                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2394
2395         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2396
2397         ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2398
2399         xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2400
2401         switch (edesc->bmAttributes & UE_XFERTYPE) {
2402         case UE_INTERRUPT:
2403         case UE_ISOCHRONOUS:
2404                 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2405                     XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2406                     max_frame_size));
2407                 break;
2408         case UE_CONTROL:
2409                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2410                 break;
2411         default:
2412                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2413                 break;
2414         }
2415
2416         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2417
2418 #ifdef USB_DEBUG
2419         xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2420 #endif
2421         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2422
2423         return (0);             /* success */
2424 }
2425
2426 static usb_error_t
2427 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2428 {
2429         struct xhci_endpoint_ext *pepext;
2430         struct usb_endpoint_ss_comp_descriptor *ecomp;
2431
2432         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2433             xfer->endpoint->edesc);
2434
2435         ecomp = xfer->endpoint->ecomp;
2436
2437         pepext->trb[0].dwTrb3 = 0;      /* halt any transfers */
2438         usb_pc_cpu_flush(pepext->page_cache);
2439
2440         return (xhci_configure_endpoint(xfer->xroot->udev,
2441             xfer->endpoint->edesc, pepext->physaddr,
2442             xfer->interval, xfer->max_packet_count,
2443             (ecomp != NULL) ? (ecomp->bmAttributes & 3) + 1 : 1,
2444             usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2445             xfer->max_frame_size));
2446 }
2447
2448 static usb_error_t
2449 xhci_configure_device(struct usb_device *udev)
2450 {
2451         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2452         struct usb_page_search buf_inp;
2453         struct usb_page_cache *pcinp;
2454         struct xhci_input_dev_ctx *pinp;
2455         struct usb_device *hubdev;
2456         uint32_t temp;
2457         uint32_t route;
2458         uint32_t rh_port;
2459         uint8_t is_hub;
2460         uint8_t index;
2461         uint8_t depth;
2462
2463         index = udev->controller_slot_id;
2464
2465         DPRINTF("index=%u\n", index);
2466
2467         pcinp = &sc->sc_hw.devs[index].input_pc;
2468
2469         usbd_get_page(pcinp, 0, &buf_inp);
2470
2471         pinp = buf_inp.buffer;
2472
2473         rh_port = 0;
2474         route = 0;
2475
2476         /* figure out route string and root HUB port number */
2477
2478         for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2479
2480                 if (hubdev->parent_hub == NULL)
2481                         break;
2482
2483                 depth = hubdev->parent_hub->depth;
2484
2485                 /*
2486                  * NOTE: HS/FS/LS devices and the SS root HUB can have
2487                  * more than 15 ports
2488                  */
2489
2490                 rh_port = hubdev->port_no;
2491
2492                 if (depth == 0)
2493                         break;
2494
2495                 if (rh_port > 15)
2496                         rh_port = 15;
2497
2498                 if (depth < 6)
2499                         route |= rh_port << (4 * (depth - 1));
2500         }
2501
2502         DPRINTF("Route=0x%08x\n", route);
2503
2504         temp = XHCI_SCTX_0_ROUTE_SET(route) |
2505             XHCI_SCTX_0_CTX_NUM_SET(
2506             sc->sc_hw.devs[index].context_num + 1);
2507
2508         switch (udev->speed) {
2509         case USB_SPEED_LOW:
2510                 temp |= XHCI_SCTX_0_SPEED_SET(2);
2511                 if (udev->parent_hs_hub != NULL &&
2512                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2513                     UDPROTO_HSHUBMTT) {
2514                         DPRINTF("Device inherits MTT\n");
2515                         temp |= XHCI_SCTX_0_MTT_SET(1);
2516                 }
2517                 break;
2518         case USB_SPEED_HIGH:
2519                 temp |= XHCI_SCTX_0_SPEED_SET(3);
2520                 if (sc->sc_hw.devs[index].nports != 0 &&
2521                     udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2522                         DPRINTF("HUB supports MTT\n");
2523                         temp |= XHCI_SCTX_0_MTT_SET(1);
2524                 }
2525                 break;
2526         case USB_SPEED_FULL:
2527                 temp |= XHCI_SCTX_0_SPEED_SET(1);
2528                 if (udev->parent_hs_hub != NULL &&
2529                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2530                     UDPROTO_HSHUBMTT) {
2531                         DPRINTF("Device inherits MTT\n");
2532                         temp |= XHCI_SCTX_0_MTT_SET(1);
2533                 }
2534                 break;
2535         default:
2536                 temp |= XHCI_SCTX_0_SPEED_SET(4);
2537                 break;
2538         }
2539
2540         is_hub = sc->sc_hw.devs[index].nports != 0 &&
2541             (udev->speed == USB_SPEED_SUPER ||
2542             udev->speed == USB_SPEED_HIGH);
2543
2544         if (is_hub)
2545                 temp |= XHCI_SCTX_0_HUB_SET(1);
2546
2547         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2548
2549         temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2550
2551         if (is_hub) {
2552                 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2553                     sc->sc_hw.devs[index].nports);
2554         }
2555
2556         switch (udev->speed) {
2557         case USB_SPEED_SUPER:
2558                 switch (sc->sc_hw.devs[index].state) {
2559                 case XHCI_ST_ADDRESSED:
2560                 case XHCI_ST_CONFIGURED:
2561                         /* enable power save */
2562                         temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2563                         break;
2564                 default:
2565                         /* disable power save */
2566                         break;
2567                 }
2568                 break;
2569         default:
2570                 break;
2571         }
2572
2573         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2574
2575         temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2576
2577         if (is_hub) {
2578                 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2579                     sc->sc_hw.devs[index].tt);
2580         }
2581
2582         hubdev = udev->parent_hs_hub;
2583
2584         /* check if we should activate the transaction translator */
2585         switch (udev->speed) {
2586         case USB_SPEED_FULL:
2587         case USB_SPEED_LOW:
2588                 if (hubdev != NULL) {
2589                         temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2590                             hubdev->controller_slot_id);
2591                         temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2592                             udev->hs_port_no);
2593                 }
2594                 break;
2595         default:
2596                 break;
2597         }
2598
2599         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2600
2601         /*
2602          * These fields should be initialized to zero, according to
2603          * XHCI section 6.2.2 - slot context:
2604          */
2605         temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2606             XHCI_SCTX_3_SLOT_STATE_SET(0);
2607
2608         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2609
2610 #ifdef USB_DEBUG
2611         xhci_dump_device(sc, &pinp->ctx_slot);
2612 #endif
2613         usb_pc_cpu_flush(pcinp);
2614
2615         return (0);             /* success */
2616 }
2617
2618 static usb_error_t
2619 xhci_alloc_device_ext(struct usb_device *udev)
2620 {
2621         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2622         struct usb_page_search buf_dev;
2623         struct usb_page_search buf_ep;
2624         struct xhci_trb *trb;
2625         struct usb_page_cache *pc;
2626         struct usb_page *pg;
2627         uint64_t addr;
2628         uint8_t index;
2629         uint8_t i;
2630
2631         index = udev->controller_slot_id;
2632
2633         pc = &sc->sc_hw.devs[index].device_pc;
2634         pg = &sc->sc_hw.devs[index].device_pg;
2635
2636         /* need to initialize the page cache */
2637         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2638
2639         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2640             (2 * sizeof(struct xhci_dev_ctx)) :
2641             sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2642                 goto error;
2643
2644         usbd_get_page(pc, 0, &buf_dev);
2645
2646         pc = &sc->sc_hw.devs[index].input_pc;
2647         pg = &sc->sc_hw.devs[index].input_pg;
2648
2649         /* need to initialize the page cache */
2650         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2651
2652         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2653             (2 * sizeof(struct xhci_input_dev_ctx)) :
2654             sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2655                 goto error;
2656         }
2657
2658         pc = &sc->sc_hw.devs[index].endpoint_pc;
2659         pg = &sc->sc_hw.devs[index].endpoint_pg;
2660
2661         /* need to initialize the page cache */
2662         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2663
2664         if (usb_pc_alloc_mem(pc, pg,
2665             sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) {
2666                 goto error;
2667         }
2668
2669         /* initialise all endpoint LINK TRBs */
2670
2671         for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2672
2673                 /* lookup endpoint TRB ring */
2674                 usbd_get_page(pc, (uintptr_t)&
2675                     ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep);
2676
2677                 /* get TRB pointer */
2678                 trb = buf_ep.buffer;
2679                 trb += XHCI_MAX_TRANSFERS - 1;
2680
2681                 /* get TRB start address */
2682                 addr = buf_ep.physaddr;
2683
2684                 /* create LINK TRB */
2685                 trb->qwTrb0 = htole64(addr);
2686                 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2687                 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2688                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2689         }
2690
2691         usb_pc_cpu_flush(pc);
2692
2693         xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2694
2695         return (0);
2696
2697 error:
2698         xhci_free_device_ext(udev);
2699
2700         return (USB_ERR_NOMEM);
2701 }
2702
2703 static void
2704 xhci_free_device_ext(struct usb_device *udev)
2705 {
2706         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2707         uint8_t index;
2708
2709         index = udev->controller_slot_id;
2710         xhci_set_slot_pointer(sc, index, 0);
2711
2712         usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2713         usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2714         usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc);
2715 }
2716
2717 static struct xhci_endpoint_ext *
2718 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2719 {
2720         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2721         struct xhci_endpoint_ext *pepext;
2722         struct usb_page_cache *pc;
2723         struct usb_page_search buf_ep;
2724         uint8_t epno;
2725         uint8_t index;
2726
2727         epno = edesc->bEndpointAddress;
2728         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2729                 epno |= UE_DIR_IN;
2730
2731         epno = XHCI_EPNO2EPID(epno);
2732
2733         index = udev->controller_slot_id;
2734
2735         pc = &sc->sc_hw.devs[index].endpoint_pc;
2736
2737         usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->trb[epno][0], &buf_ep);
2738
2739         pepext = &sc->sc_hw.devs[index].endp[epno];
2740         pepext->page_cache = pc;
2741         pepext->trb = buf_ep.buffer;
2742         pepext->physaddr = buf_ep.physaddr;
2743
2744         return (pepext);
2745 }
2746
2747 static void
2748 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2749 {
2750         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2751         uint8_t epno;
2752         uint8_t index;
2753
2754         epno = xfer->endpointno;
2755         if (xfer->flags_int.control_xfr)
2756                 epno |= UE_DIR_IN;
2757
2758         epno = XHCI_EPNO2EPID(epno);
2759         index = xfer->xroot->udev->controller_slot_id;
2760
2761         if (xfer->xroot->udev->flags.self_suspended == 0) {
2762                 XWRITE4(sc, door, XHCI_DOORBELL(index),
2763                     epno | XHCI_DB_SID_SET(/*xfer->stream_id*/ 0));
2764         }
2765 }
2766
2767 static void
2768 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2769 {
2770         struct xhci_endpoint_ext *pepext;
2771
2772         if (xfer->flags_int.bandwidth_reclaimed) {
2773                 xfer->flags_int.bandwidth_reclaimed = 0;
2774
2775                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2776                     xfer->endpoint->edesc);
2777
2778                 pepext->trb_used--;
2779
2780                 pepext->xfer[xfer->qh_pos] = NULL;
2781
2782                 if (error && pepext->trb_running != 0) {
2783                         pepext->trb_halted = 1;
2784                         pepext->trb_running = 0;
2785                 }
2786         }
2787 }
2788
2789 static usb_error_t
2790 xhci_transfer_insert(struct usb_xfer *xfer)
2791 {
2792         struct xhci_td *td_first;
2793         struct xhci_td *td_last;
2794         struct xhci_trb *trb_link;
2795         struct xhci_endpoint_ext *pepext;
2796         uint64_t addr;
2797         uint8_t i;
2798         uint8_t inext;
2799         uint8_t trb_limit;
2800
2801         DPRINTFN(8, "\n");
2802
2803         /* check if already inserted */
2804         if (xfer->flags_int.bandwidth_reclaimed) {
2805                 DPRINTFN(8, "Already in schedule\n");
2806                 return (0);
2807         }
2808
2809         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2810             xfer->endpoint->edesc);
2811
2812         td_first = xfer->td_transfer_first;
2813         td_last = xfer->td_transfer_last;
2814         addr = pepext->physaddr;
2815
2816         switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2817         case UE_CONTROL:
2818         case UE_INTERRUPT:
2819                 /* single buffered */
2820                 trb_limit = 1;
2821                 break;
2822         default:
2823                 /* multi buffered */
2824                 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2825                 break;
2826         }
2827
2828         if (pepext->trb_used >= trb_limit) {
2829                 DPRINTFN(8, "Too many TDs queued.\n");
2830                 return (USB_ERR_NOMEM);
2831         }
2832
2833         /* check for stopped condition, after putting transfer on interrupt queue */
2834         if (pepext->trb_running == 0) {
2835                 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2836
2837                 DPRINTFN(8, "Not running\n");
2838
2839                 /* start configuration */
2840                 (void)usb_proc_msignal(&sc->sc_config_proc,
2841                     &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2842                 return (0);
2843         }
2844
2845         pepext->trb_used++;
2846
2847         /* get current TRB index */
2848         i = pepext->trb_index;
2849
2850         /* get next TRB index */
2851         inext = (i + 1);
2852
2853         /* the last entry of the ring is a hardcoded link TRB */
2854         if (inext >= (XHCI_MAX_TRANSFERS - 1))
2855                 inext = 0;
2856
2857         /* compute terminating return address */
2858         addr += inext * sizeof(struct xhci_trb);
2859
2860         /* compute link TRB pointer */
2861         trb_link = td_last->td_trb + td_last->ntrb;
2862
2863         /* update next pointer of last link TRB */
2864         trb_link->qwTrb0 = htole64(addr);
2865         trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2866         trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2867             XHCI_TRB_3_CYCLE_BIT |
2868             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2869
2870 #ifdef USB_DEBUG
2871         xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2872 #endif
2873         usb_pc_cpu_flush(td_last->page_cache);
2874
2875         /* write ahead chain end marker */
2876
2877         pepext->trb[inext].qwTrb0 = 0;
2878         pepext->trb[inext].dwTrb2 = 0;
2879         pepext->trb[inext].dwTrb3 = 0;
2880
2881         /* update next pointer of link TRB */
2882
2883         pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2884         pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2885
2886 #ifdef USB_DEBUG
2887         xhci_dump_trb(&pepext->trb[i]);
2888 #endif
2889         usb_pc_cpu_flush(pepext->page_cache);
2890
2891         /* toggle cycle bit which activates the transfer chain */
2892
2893         pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2894             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2895
2896         usb_pc_cpu_flush(pepext->page_cache);
2897
2898         DPRINTF("qh_pos = %u\n", i);
2899
2900         pepext->xfer[i] = xfer;
2901
2902         xfer->qh_pos = i;
2903
2904         xfer->flags_int.bandwidth_reclaimed = 1;
2905
2906         pepext->trb_index = inext;
2907
2908         xhci_endpoint_doorbell(xfer);
2909
2910         return (0);
2911 }
2912
2913 static void
2914 xhci_root_intr(struct xhci_softc *sc)
2915 {
2916         uint16_t i;
2917
2918         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2919
2920         /* clear any old interrupt data */
2921         memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2922
2923         for (i = 1; i <= sc->sc_noport; i++) {
2924                 /* pick out CHANGE bits from the status register */
2925                 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
2926                     XHCI_PS_CSC | XHCI_PS_PEC |
2927                     XHCI_PS_OCC | XHCI_PS_WRC |
2928                     XHCI_PS_PRC | XHCI_PS_PLC |
2929                     XHCI_PS_CEC)) {
2930                         sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2931                         DPRINTF("port %d changed\n", i);
2932                 }
2933         }
2934         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2935             sizeof(sc->sc_hub_idata));
2936 }
2937
2938 /*------------------------------------------------------------------------*
2939  *      xhci_device_done - XHCI done handler
2940  *
2941  * NOTE: This function can be called two times in a row on
2942  * the same USB transfer. From close and from interrupt.
2943  *------------------------------------------------------------------------*/
2944 static void
2945 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
2946 {
2947         DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2948             xfer, xfer->endpoint, error);
2949
2950         /* remove transfer from HW queue */
2951         xhci_transfer_remove(xfer, error);
2952
2953         /* dequeue transfer and start next transfer */
2954         usbd_transfer_done(xfer, error);
2955 }
2956
2957 /*------------------------------------------------------------------------*
2958  * XHCI data transfer support (generic type)
2959  *------------------------------------------------------------------------*/
2960 static void
2961 xhci_device_generic_open(struct usb_xfer *xfer)
2962 {
2963         if (xfer->flags_int.isochronous_xfr) {
2964                 switch (xfer->xroot->udev->speed) {
2965                 case USB_SPEED_FULL:
2966                         break;
2967                 default:
2968                         usb_hs_bandwidth_alloc(xfer);
2969                         break;
2970                 }
2971         }
2972 }
2973
2974 static void
2975 xhci_device_generic_close(struct usb_xfer *xfer)
2976 {
2977         DPRINTF("\n");
2978
2979         xhci_device_done(xfer, USB_ERR_CANCELLED);
2980
2981         if (xfer->flags_int.isochronous_xfr) {
2982                 switch (xfer->xroot->udev->speed) {
2983                 case USB_SPEED_FULL:
2984                         break;
2985                 default:
2986                         usb_hs_bandwidth_free(xfer);
2987                         break;
2988                 }
2989         }
2990 }
2991
2992 static void
2993 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
2994     struct usb_xfer *enter_xfer)
2995 {
2996         struct usb_xfer *xfer;
2997
2998         /* check if there is a current transfer */
2999         xfer = ep->endpoint_q.curr;
3000         if (xfer == NULL)
3001                 return;
3002
3003         /*
3004          * Check if the current transfer is started and then pickup
3005          * the next one, if any. Else wait for next start event due to
3006          * block on failure feature.
3007          */
3008         if (!xfer->flags_int.bandwidth_reclaimed)
3009                 return;
3010
3011         xfer = TAILQ_FIRST(&ep->endpoint_q.head);
3012         if (xfer == NULL) {
3013                 /*
3014                  * In case of enter we have to consider that the
3015                  * transfer is queued by the USB core after the enter
3016                  * method is called.
3017                  */
3018                 xfer = enter_xfer;
3019
3020                 if (xfer == NULL)
3021                         return;
3022         }
3023
3024         /* try to multi buffer */
3025         xhci_transfer_insert(xfer);
3026 }
3027
3028 static void
3029 xhci_device_generic_enter(struct usb_xfer *xfer)
3030 {
3031         DPRINTF("\n");
3032
3033         /* setup TD's and QH */
3034         xhci_setup_generic_chain(xfer);
3035
3036         xhci_device_generic_multi_enter(xfer->endpoint, xfer);
3037 }
3038
3039 static void
3040 xhci_device_generic_start(struct usb_xfer *xfer)
3041 {
3042         DPRINTF("\n");
3043
3044         /* try to insert xfer on HW queue */
3045         xhci_transfer_insert(xfer);
3046
3047         /* try to multi buffer */
3048         xhci_device_generic_multi_enter(xfer->endpoint, NULL);
3049
3050         /* add transfer last on interrupt queue */
3051         usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3052
3053         /* start timeout, if any */
3054         if (xfer->timeout != 0)
3055                 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3056 }
3057
3058 struct usb_pipe_methods xhci_device_generic_methods =
3059 {
3060         .open = xhci_device_generic_open,
3061         .close = xhci_device_generic_close,
3062         .enter = xhci_device_generic_enter,
3063         .start = xhci_device_generic_start,
3064 };
3065
3066 /*------------------------------------------------------------------------*
3067  * xhci root HUB support
3068  *------------------------------------------------------------------------*
3069  * Simulate a hardware HUB by handling all the necessary requests.
3070  *------------------------------------------------------------------------*/
3071
3072 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3073
3074 static const
3075 struct usb_device_descriptor xhci_devd =
3076 {
3077         .bLength = sizeof(xhci_devd),
3078         .bDescriptorType = UDESC_DEVICE,        /* type */
3079         HSETW(.bcdUSB, 0x0300),                 /* USB version */
3080         .bDeviceClass = UDCLASS_HUB,            /* class */
3081         .bDeviceSubClass = UDSUBCLASS_HUB,      /* subclass */
3082         .bDeviceProtocol = UDPROTO_SSHUB,       /* protocol */
3083         .bMaxPacketSize = 9,                    /* max packet size */
3084         HSETW(.idVendor, 0x0000),               /* vendor */
3085         HSETW(.idProduct, 0x0000),              /* product */
3086         HSETW(.bcdDevice, 0x0100),              /* device version */
3087         .iManufacturer = 1,
3088         .iProduct = 2,
3089         .iSerialNumber = 0,
3090         .bNumConfigurations = 1,                /* # of configurations */
3091 };
3092
3093 static const
3094 struct xhci_bos_desc xhci_bosd = {
3095         .bosd = {
3096                 .bLength = sizeof(xhci_bosd.bosd),
3097                 .bDescriptorType = UDESC_BOS,
3098                 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3099                 .bNumDeviceCaps = 3,
3100         },
3101         .usb2extd = {
3102                 .bLength = sizeof(xhci_bosd.usb2extd),
3103                 .bDescriptorType = 1,
3104                 .bDevCapabilityType = 2,
3105                 .bmAttributes[0] = 2,
3106         },
3107         .usbdcd = {
3108                 .bLength = sizeof(xhci_bosd.usbdcd),
3109                 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3110                 .bDevCapabilityType = 3,
3111                 .bmAttributes = 0, /* XXX */
3112                 HSETW(.wSpeedsSupported, 0x000C),
3113                 .bFunctionalitySupport = 8,
3114                 .bU1DevExitLat = 255,   /* dummy - not used */
3115                 .wU2DevExitLat = { 0x00, 0x08 },
3116         },
3117         .cidd = {
3118                 .bLength = sizeof(xhci_bosd.cidd),
3119                 .bDescriptorType = 1,
3120                 .bDevCapabilityType = 4,
3121                 .bReserved = 0,
3122                 .bContainerID = 0, /* XXX */
3123         },
3124 };
3125
3126 static const
3127 struct xhci_config_desc xhci_confd = {
3128         .confd = {
3129                 .bLength = sizeof(xhci_confd.confd),
3130                 .bDescriptorType = UDESC_CONFIG,
3131                 .wTotalLength[0] = sizeof(xhci_confd),
3132                 .bNumInterface = 1,
3133                 .bConfigurationValue = 1,
3134                 .iConfiguration = 0,
3135                 .bmAttributes = UC_SELF_POWERED,
3136                 .bMaxPower = 0          /* max power */
3137         },
3138         .ifcd = {
3139                 .bLength = sizeof(xhci_confd.ifcd),
3140                 .bDescriptorType = UDESC_INTERFACE,
3141                 .bNumEndpoints = 1,
3142                 .bInterfaceClass = UICLASS_HUB,
3143                 .bInterfaceSubClass = UISUBCLASS_HUB,
3144                 .bInterfaceProtocol = 0,
3145         },
3146         .endpd = {
3147                 .bLength = sizeof(xhci_confd.endpd),
3148                 .bDescriptorType = UDESC_ENDPOINT,
3149                 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3150                 .bmAttributes = UE_INTERRUPT,
3151                 .wMaxPacketSize[0] = 2,         /* max 15 ports */
3152                 .bInterval = 255,
3153         },
3154         .endpcd = {
3155                 .bLength = sizeof(xhci_confd.endpcd),
3156                 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3157                 .bMaxBurst = 0,
3158                 .bmAttributes = 0,
3159         },
3160 };
3161
3162 static const
3163 struct usb_hub_ss_descriptor xhci_hubd = {
3164         .bLength = sizeof(xhci_hubd),
3165         .bDescriptorType = UDESC_SS_HUB,
3166 };
3167
3168 static usb_error_t
3169 xhci_roothub_exec(struct usb_device *udev,
3170     struct usb_device_request *req, const void **pptr, uint16_t *plength)
3171 {
3172         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3173         const char *str_ptr;
3174         const void *ptr;
3175         uint32_t port;
3176         uint32_t v;
3177         uint16_t len;
3178         uint16_t i;
3179         uint16_t value;
3180         uint16_t index;
3181         uint8_t j;
3182         usb_error_t err;
3183
3184         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3185
3186         /* buffer reset */
3187         ptr = (const void *)&sc->sc_hub_desc;
3188         len = 0;
3189         err = 0;
3190
3191         value = UGETW(req->wValue);
3192         index = UGETW(req->wIndex);
3193
3194         DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3195             "wValue=0x%04x wIndex=0x%04x\n",
3196             req->bmRequestType, req->bRequest,
3197             UGETW(req->wLength), value, index);
3198
3199 #define C(x,y) ((x) | ((y) << 8))
3200         switch (C(req->bRequest, req->bmRequestType)) {
3201         case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3202         case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3203         case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3204                 /*
3205                  * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3206                  * for the integrated root hub.
3207                  */
3208                 break;
3209         case C(UR_GET_CONFIG, UT_READ_DEVICE):
3210                 len = 1;
3211                 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3212                 break;
3213         case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3214                 switch (value >> 8) {
3215                 case UDESC_DEVICE:
3216                         if ((value & 0xff) != 0) {
3217                                 err = USB_ERR_IOERROR;
3218                                 goto done;
3219                         }
3220                         len = sizeof(xhci_devd);
3221                         ptr = (const void *)&xhci_devd;
3222                         break;
3223
3224                 case UDESC_BOS:
3225                         if ((value & 0xff) != 0) {
3226                                 err = USB_ERR_IOERROR;
3227                                 goto done;
3228                         }
3229                         len = sizeof(xhci_bosd);
3230                         ptr = (const void *)&xhci_bosd;
3231                         break;
3232
3233                 case UDESC_CONFIG:
3234                         if ((value & 0xff) != 0) {
3235                                 err = USB_ERR_IOERROR;
3236                                 goto done;
3237                         }
3238                         len = sizeof(xhci_confd);
3239                         ptr = (const void *)&xhci_confd;
3240                         break;
3241
3242                 case UDESC_STRING:
3243                         switch (value & 0xff) {
3244                         case 0: /* Language table */
3245                                 str_ptr = "\001";
3246                                 break;
3247
3248                         case 1: /* Vendor */
3249                                 str_ptr = sc->sc_vendor;
3250                                 break;
3251
3252                         case 2: /* Product */
3253                                 str_ptr = "XHCI root HUB";
3254                                 break;
3255
3256                         default:
3257                                 str_ptr = "";
3258                                 break;
3259                         }
3260
3261                         len = usb_make_str_desc(
3262                             sc->sc_hub_desc.temp,
3263                             sizeof(sc->sc_hub_desc.temp),
3264                             str_ptr);
3265                         break;
3266
3267                 default:
3268                         err = USB_ERR_IOERROR;
3269                         goto done;
3270                 }
3271                 break;
3272         case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3273                 len = 1;
3274                 sc->sc_hub_desc.temp[0] = 0;
3275                 break;
3276         case C(UR_GET_STATUS, UT_READ_DEVICE):
3277                 len = 2;
3278                 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3279                 break;
3280         case C(UR_GET_STATUS, UT_READ_INTERFACE):
3281         case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3282                 len = 2;
3283                 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3284                 break;
3285         case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3286                 if (value >= XHCI_MAX_DEVICES) {
3287                         err = USB_ERR_IOERROR;
3288                         goto done;
3289                 }
3290                 break;
3291         case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3292                 if (value != 0 && value != 1) {
3293                         err = USB_ERR_IOERROR;
3294                         goto done;
3295                 }
3296                 sc->sc_conf = value;
3297                 break;
3298         case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3299                 break;
3300         case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3301         case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3302         case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3303                 err = USB_ERR_IOERROR;
3304                 goto done;
3305         case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3306                 break;
3307         case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3308                 break;
3309                 /* Hub requests */
3310         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3311                 break;
3312         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3313                 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3314
3315                 if ((index < 1) ||
3316                     (index > sc->sc_noport)) {
3317                         err = USB_ERR_IOERROR;
3318                         goto done;
3319                 }
3320                 port = XHCI_PORTSC(index);
3321
3322                 v = XREAD4(sc, oper, port);
3323                 i = XHCI_PS_PLS_GET(v);
3324                 v &= ~XHCI_PS_CLEAR;
3325
3326                 switch (value) {
3327                 case UHF_C_BH_PORT_RESET:
3328                         XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3329                         break;
3330                 case UHF_C_PORT_CONFIG_ERROR:
3331                         XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3332                         break;
3333                 case UHF_C_PORT_SUSPEND:
3334                 case UHF_C_PORT_LINK_STATE:
3335                         XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3336                         break;
3337                 case UHF_C_PORT_CONNECTION:
3338                         XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3339                         break;
3340                 case UHF_C_PORT_ENABLE:
3341                         XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3342                         break;
3343                 case UHF_C_PORT_OVER_CURRENT:
3344                         XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3345                         break;
3346                 case UHF_C_PORT_RESET:
3347                         XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3348                         break;
3349                 case UHF_PORT_ENABLE:
3350                         XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3351                         break;
3352                 case UHF_PORT_POWER:
3353                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3354                         break;
3355                 case UHF_PORT_INDICATOR:
3356                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3357                         break;
3358                 case UHF_PORT_SUSPEND:
3359
3360                         /* U3 -> U15 */
3361                         if (i == 3) {
3362                                 XWRITE4(sc, oper, port, v |
3363                                     XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3364                         }
3365
3366                         /* wait 20ms for resume sequence to complete */
3367                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3368
3369                         /* U0 */
3370                         XWRITE4(sc, oper, port, v |
3371                             XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3372                         break;
3373                 default:
3374                         err = USB_ERR_IOERROR;
3375                         goto done;
3376                 }
3377                 break;
3378
3379         case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3380                 if ((value & 0xff) != 0) {
3381                         err = USB_ERR_IOERROR;
3382                         goto done;
3383                 }
3384
3385                 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3386
3387                 sc->sc_hub_desc.hubd = xhci_hubd;
3388
3389                 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3390
3391                 if (XHCI_HCS0_PPC(v))
3392                         i = UHD_PWR_INDIVIDUAL;
3393                 else
3394                         i = UHD_PWR_GANGED;
3395
3396                 if (XHCI_HCS0_PIND(v))
3397                         i |= UHD_PORT_IND;
3398
3399                 i |= UHD_OC_INDIVIDUAL;
3400
3401                 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3402
3403                 /* see XHCI section 5.4.9: */
3404                 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3405
3406                 for (j = 1; j <= sc->sc_noport; j++) {
3407
3408                         v = XREAD4(sc, oper, XHCI_PORTSC(j));
3409                         if (v & XHCI_PS_DR) {
3410                                 sc->sc_hub_desc.hubd.
3411                                     DeviceRemovable[j / 8] |= 1U << (j % 8);
3412                         }
3413                 }
3414                 len = sc->sc_hub_desc.hubd.bLength;
3415                 break;
3416
3417         case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3418                 len = 16;
3419                 memset(sc->sc_hub_desc.temp, 0, 16);
3420                 break;
3421
3422         case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3423                 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3424
3425                 if ((index < 1) ||
3426                     (index > sc->sc_noport)) {
3427                         err = USB_ERR_IOERROR;
3428                         goto done;
3429                 }
3430
3431                 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3432
3433                 DPRINTFN(9, "port status=0x%08x\n", v);
3434
3435                 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3436
3437                 switch (XHCI_PS_SPEED_GET(v)) {
3438                 case 3:
3439                         i |= UPS_HIGH_SPEED;
3440                         break;
3441                 case 2:
3442                         i |= UPS_LOW_SPEED;
3443                         break;
3444                 case 1:
3445                         /* FULL speed */
3446                         break;
3447                 default:
3448                         i |= UPS_OTHER_SPEED;
3449                         break;
3450                 }
3451
3452                 if (v & XHCI_PS_CCS)
3453                         i |= UPS_CURRENT_CONNECT_STATUS;
3454                 if (v & XHCI_PS_PED)
3455                         i |= UPS_PORT_ENABLED;
3456                 if (v & XHCI_PS_OCA)
3457                         i |= UPS_OVERCURRENT_INDICATOR;
3458                 if (v & XHCI_PS_PR)
3459                         i |= UPS_RESET;
3460                 if (v & XHCI_PS_PP) {
3461                         /*
3462                          * The USB 3.0 RH is using the
3463                          * USB 2.0's power bit
3464                          */
3465                         i |= UPS_PORT_POWER;
3466                 }
3467                 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3468
3469                 i = 0;
3470                 if (v & XHCI_PS_CSC)
3471                         i |= UPS_C_CONNECT_STATUS;
3472                 if (v & XHCI_PS_PEC)
3473                         i |= UPS_C_PORT_ENABLED;
3474                 if (v & XHCI_PS_OCC)
3475                         i |= UPS_C_OVERCURRENT_INDICATOR;
3476                 if (v & XHCI_PS_WRC)
3477                         i |= UPS_C_BH_PORT_RESET;
3478                 if (v & XHCI_PS_PRC)
3479                         i |= UPS_C_PORT_RESET;
3480                 if (v & XHCI_PS_PLC)
3481                         i |= UPS_C_PORT_LINK_STATE;
3482                 if (v & XHCI_PS_CEC)
3483                         i |= UPS_C_PORT_CONFIG_ERROR;
3484
3485                 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3486                 len = sizeof(sc->sc_hub_desc.ps);
3487                 break;
3488
3489         case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3490                 err = USB_ERR_IOERROR;
3491                 goto done;
3492
3493         case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3494                 break;
3495
3496         case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3497
3498                 i = index >> 8;
3499                 index &= 0x00FF;
3500
3501                 if ((index < 1) ||
3502                     (index > sc->sc_noport)) {
3503                         err = USB_ERR_IOERROR;
3504                         goto done;
3505                 }
3506
3507                 port = XHCI_PORTSC(index);
3508                 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3509
3510                 switch (value) {
3511                 case UHF_PORT_U1_TIMEOUT:
3512                         if (XHCI_PS_SPEED_GET(v) != 4) {
3513                                 err = USB_ERR_IOERROR;
3514                                 goto done;
3515                         }
3516                         port = XHCI_PORTPMSC(index);
3517                         v = XREAD4(sc, oper, port);
3518                         v &= ~XHCI_PM3_U1TO_SET(0xFF);
3519                         v |= XHCI_PM3_U1TO_SET(i);
3520                         XWRITE4(sc, oper, port, v);
3521                         break;
3522                 case UHF_PORT_U2_TIMEOUT:
3523                         if (XHCI_PS_SPEED_GET(v) != 4) {
3524                                 err = USB_ERR_IOERROR;
3525                                 goto done;
3526                         }
3527                         port = XHCI_PORTPMSC(index);
3528                         v = XREAD4(sc, oper, port);
3529                         v &= ~XHCI_PM3_U2TO_SET(0xFF);
3530                         v |= XHCI_PM3_U2TO_SET(i);
3531                         XWRITE4(sc, oper, port, v);
3532                         break;
3533                 case UHF_BH_PORT_RESET:
3534                         XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3535                         break;
3536                 case UHF_PORT_LINK_STATE:
3537                         XWRITE4(sc, oper, port, v |
3538                             XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3539                         /* 4ms settle time */
3540                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3541                         break;
3542                 case UHF_PORT_ENABLE:
3543                         DPRINTFN(3, "set port enable %d\n", index);
3544                         break;
3545                 case UHF_PORT_SUSPEND:
3546                         DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3547                         j = XHCI_PS_SPEED_GET(v);
3548                         if ((j < 1) || (j > 3)) {
3549                                 /* non-supported speed */
3550                                 err = USB_ERR_IOERROR;
3551                                 goto done;
3552                         }
3553                         XWRITE4(sc, oper, port, v |
3554                             XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3555                         break;
3556                 case UHF_PORT_RESET:
3557                         DPRINTFN(6, "reset port %d\n", index);
3558                         XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3559                         break;
3560                 case UHF_PORT_POWER:
3561                         DPRINTFN(3, "set port power %d\n", index);
3562                         XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3563                         break;
3564                 case UHF_PORT_TEST:
3565                         DPRINTFN(3, "set port test %d\n", index);
3566                         break;
3567                 case UHF_PORT_INDICATOR:
3568                         DPRINTFN(3, "set port indicator %d\n", index);
3569
3570                         v &= ~XHCI_PS_PIC_SET(3);
3571                         v |= XHCI_PS_PIC_SET(1);
3572
3573                         XWRITE4(sc, oper, port, v);
3574                         break;
3575                 default:
3576                         err = USB_ERR_IOERROR;
3577                         goto done;
3578                 }
3579                 break;
3580
3581         case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3582         case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3583         case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3584         case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3585                 break;
3586         default:
3587                 err = USB_ERR_IOERROR;
3588                 goto done;
3589         }
3590 done:
3591         *plength = len;
3592         *pptr = ptr;
3593         return (err);
3594 }
3595
3596 static void
3597 xhci_xfer_setup(struct usb_setup_params *parm)
3598 {
3599         struct usb_page_search page_info;
3600         struct usb_page_cache *pc;
3601         struct xhci_softc *sc;
3602         struct usb_xfer *xfer;
3603         void *last_obj;
3604         uint32_t ntd;
3605         uint32_t n;
3606
3607         sc = XHCI_BUS2SC(parm->udev->bus);
3608         xfer = parm->curr_xfer;
3609
3610         /*
3611          * The proof for the "ntd" formula is illustrated like this:
3612          *
3613          * +------------------------------------+
3614          * |                                    |
3615          * |         |remainder ->              |
3616          * |   +-----+---+                      |
3617          * |   | xxx | x | frm 0                |
3618          * |   +-----+---++                     |
3619          * |   | xxx | xx | frm 1               |
3620          * |   +-----+----+                     |
3621          * |            ...                     |
3622          * +------------------------------------+
3623          *
3624          * "xxx" means a completely full USB transfer descriptor
3625          *
3626          * "x" and "xx" means a short USB packet
3627          *
3628          * For the remainder of an USB transfer modulo
3629          * "max_data_length" we need two USB transfer descriptors.
3630          * One to transfer the remaining data and one to finalise with
3631          * a zero length packet in case the "force_short_xfer" flag is
3632          * set. We only need two USB transfer descriptors in the case
3633          * where the transfer length of the first one is a factor of
3634          * "max_frame_size". The rest of the needed USB transfer
3635          * descriptors is given by the buffer size divided by the
3636          * maximum data payload.
3637          */
3638         parm->hc_max_packet_size = 0x400;
3639         parm->hc_max_packet_count = 16 * 3;
3640         parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3641
3642         xfer->flags_int.bdma_enable = 1;
3643
3644         usbd_transfer_setup_sub(parm);
3645
3646         if (xfer->flags_int.isochronous_xfr) {
3647                 ntd = ((1 * xfer->nframes)
3648                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3649         } else if (xfer->flags_int.control_xfr) {
3650                 ntd = ((2 * xfer->nframes) + 1  /* STATUS */
3651                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3652         } else {
3653                 ntd = ((2 * xfer->nframes)
3654                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3655         }
3656
3657 alloc_dma_set:
3658
3659         if (parm->err)
3660                 return;
3661
3662         /*
3663          * Allocate queue heads and transfer descriptors
3664          */
3665         last_obj = NULL;
3666
3667         if (usbd_transfer_setup_sub_malloc(
3668             parm, &pc, sizeof(struct xhci_td),
3669             XHCI_TD_ALIGN, ntd)) {
3670                 parm->err = USB_ERR_NOMEM;
3671                 return;
3672         }
3673         if (parm->buf) {
3674                 for (n = 0; n != ntd; n++) {
3675                         struct xhci_td *td;
3676
3677                         usbd_get_page(pc + n, 0, &page_info);
3678
3679                         td = page_info.buffer;
3680
3681                         /* init TD */
3682                         td->td_self = page_info.physaddr;
3683                         td->obj_next = last_obj;
3684                         td->page_cache = pc + n;
3685
3686                         last_obj = td;
3687
3688                         usb_pc_cpu_flush(pc + n);
3689                 }
3690         }
3691         xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3692
3693         if (!xfer->flags_int.curr_dma_set) {
3694                 xfer->flags_int.curr_dma_set = 1;
3695                 goto alloc_dma_set;
3696         }
3697 }
3698
3699 static usb_error_t
3700 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3701 {
3702         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3703         struct usb_page_search buf_inp;
3704         struct usb_device *udev;
3705         struct xhci_endpoint_ext *pepext;
3706         struct usb_endpoint_descriptor *edesc;
3707         struct usb_page_cache *pcinp;
3708         usb_error_t err;
3709         uint8_t index;
3710         uint8_t epno;
3711
3712         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3713             xfer->endpoint->edesc);
3714
3715         udev = xfer->xroot->udev;
3716         index = udev->controller_slot_id;
3717
3718         pcinp = &sc->sc_hw.devs[index].input_pc;
3719
3720         usbd_get_page(pcinp, 0, &buf_inp);
3721
3722         edesc = xfer->endpoint->edesc;
3723
3724         epno = edesc->bEndpointAddress;
3725
3726         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3727                 epno |= UE_DIR_IN;
3728
3729         epno = XHCI_EPNO2EPID(epno);
3730
3731         if (epno == 0)
3732                 return (USB_ERR_NO_PIPE);               /* invalid */
3733
3734         XHCI_CMD_LOCK(sc);
3735
3736         /* configure endpoint */
3737
3738         err = xhci_configure_endpoint_by_xfer(xfer);
3739
3740         if (err != 0) {
3741                 XHCI_CMD_UNLOCK(sc);
3742                 return (err);
3743         }
3744
3745         /*
3746          * Get the endpoint into the stopped state according to the
3747          * endpoint context state diagram in the XHCI specification:
3748          */
3749
3750         err = xhci_cmd_stop_ep(sc, 0, epno, index);
3751
3752         if (err != 0)
3753                 DPRINTF("Could not stop endpoint %u\n", epno);
3754
3755         err = xhci_cmd_reset_ep(sc, 0, epno, index);
3756
3757         if (err != 0)
3758                 DPRINTF("Could not reset endpoint %u\n", epno);
3759
3760         err = xhci_cmd_set_tr_dequeue_ptr(sc, pepext->physaddr |
3761             XHCI_EPCTX_2_DCS_SET(1), 0, epno, index);
3762
3763         if (err != 0)
3764                 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3765
3766         /*
3767          * Get the endpoint into the running state according to the
3768          * endpoint context state diagram in the XHCI specification:
3769          */
3770
3771         xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3772
3773         err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3774
3775         if (err != 0)
3776                 DPRINTF("Could not configure endpoint %u\n", epno);
3777
3778         err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3779
3780         if (err != 0)
3781                 DPRINTF("Could not configure endpoint %u\n", epno);
3782
3783         XHCI_CMD_UNLOCK(sc);
3784
3785         return (0);
3786 }
3787
3788 static void
3789 xhci_xfer_unsetup(struct usb_xfer *xfer)
3790 {
3791         return;
3792 }
3793
3794 static void
3795 xhci_start_dma_delay(struct usb_xfer *xfer)
3796 {
3797         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3798
3799         /* put transfer on interrupt queue (again) */
3800         usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3801
3802         (void)usb_proc_msignal(&sc->sc_config_proc,
3803             &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3804 }
3805
3806 static void
3807 xhci_configure_msg(struct usb_proc_msg *pm)
3808 {
3809         struct xhci_softc *sc;
3810         struct xhci_endpoint_ext *pepext;
3811         struct usb_xfer *xfer;
3812
3813         sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3814
3815 restart:
3816         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3817
3818                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3819                     xfer->endpoint->edesc);
3820
3821                 if ((pepext->trb_halted != 0) ||
3822                     (pepext->trb_running == 0)) {
3823
3824                         uint8_t i;
3825
3826                         /* clear halted and running */
3827                         pepext->trb_halted = 0;
3828                         pepext->trb_running = 0;
3829
3830                         /* nuke remaining buffered transfers */
3831
3832                         for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
3833                                 /*
3834                                  * NOTE: We need to use the timeout
3835                                  * error code here else existing
3836                                  * isochronous clients can get
3837                                  * confused:
3838                                  */
3839                                 if (pepext->xfer[i] != NULL) {
3840                                         xhci_device_done(pepext->xfer[i],
3841                                             USB_ERR_TIMEOUT);
3842                                 }
3843                         }
3844
3845                         /*
3846                          * NOTE: The USB transfer cannot vanish in
3847                          * this state!
3848                          */
3849
3850                         USB_BUS_UNLOCK(&sc->sc_bus);
3851
3852                         xhci_configure_reset_endpoint(xfer);
3853
3854                         USB_BUS_LOCK(&sc->sc_bus);
3855
3856                         /* check if halted is still cleared */
3857                         if (pepext->trb_halted == 0) {
3858                                 pepext->trb_running = 1;
3859                                 pepext->trb_index = 0;
3860                         }
3861                         goto restart;
3862                 }
3863
3864                 if (xfer->flags_int.did_dma_delay) {
3865
3866                         /* remove transfer from interrupt queue (again) */
3867                         usbd_transfer_dequeue(xfer);
3868
3869                         /* we are finally done */
3870                         usb_dma_delay_done_cb(xfer);
3871
3872                         /* queue changed - restart */
3873                         goto restart;
3874                 }
3875         }
3876
3877         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3878
3879                 /* try to insert xfer on HW queue */
3880                 xhci_transfer_insert(xfer);
3881
3882                 /* try to multi buffer */
3883                 xhci_device_generic_multi_enter(xfer->endpoint, NULL);
3884         }
3885 }
3886
3887 static void
3888 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3889     struct usb_endpoint *ep)
3890 {
3891         struct xhci_endpoint_ext *pepext;
3892
3893         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3894             ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
3895
3896         if (udev->flags.usb_mode != USB_MODE_HOST) {
3897                 /* not supported */
3898                 return;
3899         }
3900         if (udev->parent_hub == NULL) {
3901                 /* root HUB has special endpoint handling */
3902                 return;
3903         }
3904
3905         ep->methods = &xhci_device_generic_methods;
3906
3907         pepext = xhci_get_endpoint_ext(udev, edesc);
3908
3909         USB_BUS_LOCK(udev->bus);
3910         pepext->trb_halted = 1;
3911         pepext->trb_running = 0;
3912         USB_BUS_UNLOCK(udev->bus);
3913 }
3914
3915 static void
3916 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
3917 {
3918
3919 }
3920
3921 static void
3922 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3923 {
3924         struct xhci_endpoint_ext *pepext;
3925
3926         DPRINTF("\n");
3927
3928         if (udev->flags.usb_mode != USB_MODE_HOST) {
3929                 /* not supported */
3930                 return;
3931         }
3932         if (udev->parent_hub == NULL) {
3933                 /* root HUB has special endpoint handling */
3934                 return;
3935         }
3936
3937         pepext = xhci_get_endpoint_ext(udev, ep->edesc);
3938
3939         USB_BUS_LOCK(udev->bus);
3940         pepext->trb_halted = 1;
3941         pepext->trb_running = 0;
3942         USB_BUS_UNLOCK(udev->bus);
3943 }
3944
3945 static usb_error_t
3946 xhci_device_init(struct usb_device *udev)
3947 {
3948         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3949         usb_error_t err;
3950         uint8_t temp;
3951
3952         /* no init for root HUB */
3953         if (udev->parent_hub == NULL)
3954                 return (0);
3955
3956         XHCI_CMD_LOCK(sc);
3957
3958         /* set invalid default */
3959
3960         udev->controller_slot_id = sc->sc_noslot + 1;
3961
3962         /* try to get a new slot ID from the XHCI */
3963
3964         err = xhci_cmd_enable_slot(sc, &temp);
3965
3966         if (err) {
3967                 XHCI_CMD_UNLOCK(sc);
3968                 return (err);
3969         }
3970
3971         if (temp > sc->sc_noslot) {
3972                 XHCI_CMD_UNLOCK(sc);
3973                 return (USB_ERR_BAD_ADDRESS);
3974         }
3975
3976         if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
3977                 DPRINTF("slot %u already allocated.\n", temp);
3978                 XHCI_CMD_UNLOCK(sc);
3979                 return (USB_ERR_BAD_ADDRESS);
3980         }
3981
3982         /* store slot ID for later reference */
3983
3984         udev->controller_slot_id = temp;
3985
3986         /* reset data structure */
3987
3988         memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
3989
3990         /* set mark slot allocated */
3991
3992         sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
3993
3994         err = xhci_alloc_device_ext(udev);
3995
3996         XHCI_CMD_UNLOCK(sc);
3997
3998         /* get device into default state */
3999
4000         if (err == 0)
4001                 err = xhci_set_address(udev, NULL, 0);
4002
4003         return (err);
4004 }
4005
4006 static void
4007 xhci_device_uninit(struct usb_device *udev)
4008 {
4009         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4010         uint8_t index;
4011
4012         /* no init for root HUB */
4013         if (udev->parent_hub == NULL)
4014                 return;
4015
4016         XHCI_CMD_LOCK(sc);
4017
4018         index = udev->controller_slot_id;
4019
4020         if (index <= sc->sc_noslot) {
4021                 xhci_cmd_disable_slot(sc, index);
4022                 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
4023
4024                 /* free device extension */
4025                 xhci_free_device_ext(udev);
4026         }
4027
4028         XHCI_CMD_UNLOCK(sc);
4029 }
4030
4031 static void
4032 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4033 {
4034         /*
4035          * Wait until the hardware has finished any possible use of
4036          * the transfer descriptor(s)
4037          */
4038         *pus = 2048;                    /* microseconds */
4039 }
4040
4041 static void
4042 xhci_device_resume(struct usb_device *udev)
4043 {
4044         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4045         uint8_t index;
4046         uint8_t n;
4047         uint8_t p;
4048
4049         DPRINTF("\n");
4050
4051         /* check for root HUB */
4052         if (udev->parent_hub == NULL)
4053                 return;
4054
4055         index = udev->controller_slot_id;
4056
4057         XHCI_CMD_LOCK(sc);
4058
4059         /* blindly resume all endpoints */
4060
4061         USB_BUS_LOCK(udev->bus);
4062
4063         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4064                 for (p = 0; p != 1 /*XHCI_MAX_STREAMS*/; p++) {
4065                         XWRITE4(sc, door, XHCI_DOORBELL(index),
4066                             n | XHCI_DB_SID_SET(p));
4067                 }
4068         }
4069
4070         USB_BUS_UNLOCK(udev->bus);
4071
4072         XHCI_CMD_UNLOCK(sc);
4073 }
4074
4075 static void
4076 xhci_device_suspend(struct usb_device *udev)
4077 {
4078         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4079         uint8_t index;
4080         uint8_t n;
4081         usb_error_t err;
4082
4083         DPRINTF("\n");
4084
4085         /* check for root HUB */
4086         if (udev->parent_hub == NULL)
4087                 return;
4088
4089         index = udev->controller_slot_id;
4090
4091         XHCI_CMD_LOCK(sc);
4092
4093         /* blindly suspend all endpoints */
4094
4095         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4096                 err = xhci_cmd_stop_ep(sc, 1, n, index);
4097                 if (err != 0) {
4098                         DPRINTF("Failed to suspend endpoint "
4099                             "%u on slot %u (ignored).\n", n, index);
4100                 }
4101         }
4102
4103         XHCI_CMD_UNLOCK(sc);
4104 }
4105
4106 static void
4107 xhci_set_hw_power(struct usb_bus *bus)
4108 {
4109         DPRINTF("\n");
4110 }
4111
4112 static void
4113 xhci_device_state_change(struct usb_device *udev)
4114 {
4115         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4116         struct usb_page_search buf_inp;
4117         usb_error_t err;
4118         uint8_t index;
4119
4120         /* check for root HUB */
4121         if (udev->parent_hub == NULL)
4122                 return;
4123
4124         index = udev->controller_slot_id;
4125
4126         DPRINTF("\n");
4127
4128         if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4129                 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4130                     &sc->sc_hw.devs[index].tt);
4131                 if (err != 0)
4132                         sc->sc_hw.devs[index].nports = 0;
4133         }
4134
4135         XHCI_CMD_LOCK(sc);
4136
4137         switch (usb_get_device_state(udev)) {
4138         case USB_STATE_POWERED:
4139                 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4140                         break;
4141
4142                 /* set default state */
4143                 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4144
4145                 /* reset number of contexts */
4146                 sc->sc_hw.devs[index].context_num = 0;
4147
4148                 err = xhci_cmd_reset_dev(sc, index);
4149
4150                 if (err != 0) {
4151                         DPRINTF("Device reset failed "
4152                             "for slot %u.\n", index);
4153                 }
4154                 break;
4155
4156         case USB_STATE_ADDRESSED:
4157                 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4158                         break;
4159
4160                 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4161
4162                 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4163
4164                 if (err) {
4165                         DPRINTF("Failed to deconfigure "
4166                             "slot %u.\n", index);
4167                 }
4168                 break;
4169
4170         case USB_STATE_CONFIGURED:
4171                 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4172                         break;
4173
4174                 /* set configured state */
4175                 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4176
4177                 /* reset number of contexts */
4178                 sc->sc_hw.devs[index].context_num = 0;
4179
4180                 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4181
4182                 xhci_configure_mask(udev, 3, 0);
4183
4184                 err = xhci_configure_device(udev);
4185                 if (err != 0) {
4186                         DPRINTF("Could not configure device "
4187                             "at slot %u.\n", index);
4188                 }
4189
4190                 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4191                 if (err != 0) {
4192                         DPRINTF("Could not evaluate device "
4193                             "context at slot %u.\n", index);
4194                 }
4195                 break;
4196
4197         default:
4198                 break;
4199         }
4200         XHCI_CMD_UNLOCK(sc);
4201 }
4202
4203 struct usb_bus_methods xhci_bus_methods = {
4204         .endpoint_init = xhci_ep_init,
4205         .endpoint_uninit = xhci_ep_uninit,
4206         .xfer_setup = xhci_xfer_setup,
4207         .xfer_unsetup = xhci_xfer_unsetup,
4208         .get_dma_delay = xhci_get_dma_delay,
4209         .device_init = xhci_device_init,
4210         .device_uninit = xhci_device_uninit,
4211         .device_resume = xhci_device_resume,
4212         .device_suspend = xhci_device_suspend,
4213         .set_hw_power = xhci_set_hw_power,
4214         .roothub_exec = xhci_roothub_exec,
4215         .xfer_poll = xhci_do_poll,
4216         .start_dma_delay = xhci_start_dma_delay,
4217         .set_address = xhci_set_address,
4218         .clear_stall = xhci_ep_clear_stall,
4219         .device_state_change = xhci_device_state_change,
4220         .set_hw_power_sleep = xhci_set_hw_power_sleep,
4221 };