sys/dev/usb/controller/xhci.c

   1 /*-
   2  * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  */
  25
  26 /*
  27  * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
  28  *
  29  * The XHCI 1.0 spec can be found at
  30  * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
  31  * and the USB 3.0 spec at
  32  * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
  33  */
  34
  35 /*
  36  * A few words about the design implementation: This driver emulates
  37  * the concept about TDs which is found in EHCI specification. This
  38  * way we avoid too much diveration among USB drivers.
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include <sys/stdint.h>
  45 #include <sys/stddef.h>
  46 #include <sys/param.h>
  47 #include <sys/queue.h>
  48 #include <sys/types.h>
  49 #include <sys/systm.h>
  50 #include <sys/kernel.h>
  51 #include <sys/bus.h>
  52 #include <sys/module.h>
  53 #include <sys/lock.h>
  54 #include <sys/mutex.h>
  55 #include <sys/condvar.h>
  56 #include <sys/sysctl.h>
  57 #include <sys/sx.h>
  58 #include <sys/unistd.h>
  59 #include <sys/callout.h>
  60 #include <sys/malloc.h>
  61 #include <sys/priv.h>
  62
  63 #include <dev/usb/usb.h>
  64 #include <dev/usb/usbdi.h>
  65
  66 #define USB_DEBUG_VAR xhcidebug
  67
  68 #include <dev/usb/usb_core.h>
  69 #include <dev/usb/usb_debug.h>
  70 #include <dev/usb/usb_busdma.h>
  71 #include <dev/usb/usb_process.h>
  72 #include <dev/usb/usb_transfer.h>
  73 #include <dev/usb/usb_device.h>
  74 #include <dev/usb/usb_hub.h>
  75 #include <dev/usb/usb_util.h>
  76
  77 #include <dev/usb/usb_controller.h>
  78 #include <dev/usb/usb_bus.h>
  79 #include <dev/usb/controller/xhci.h>
  80 #include <dev/usb/controller/xhcireg.h>
  81
  82 #define XHCI_BUS2SC(bus) \
  83    ((struct xhci_softc *)(((uint8_t *)(bus)) - \
  84     ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
  85
  86 #ifdef USB_DEBUG
  87 static int xhcidebug;
  88 static int xhciroute;
  89
  90 SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
  91 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
  92     &xhcidebug, 0, "Debug level");
  93 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
  94 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN,
  95     &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller");
  96 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
  97 #else
  98 #define xhciroute 0
  99 #endif
 100
 101 #define XHCI_INTR_ENDPT 1
 102
 103 struct xhci_std_temp {
 104         struct xhci_softc       *sc;
 105         struct usb_page_cache   *pc;
 106         struct xhci_td          *td;
 107         struct xhci_td          *td_next;
 108         uint32_t                len;
 109         uint32_t                offset;
 110         uint32_t                max_packet_size;
 111         uint32_t                average;
 112         uint16_t                isoc_delta;
 113         uint16_t                isoc_frame;
 114         uint8_t                 shortpkt;
 115         uint8_t                 multishort;
 116         uint8_t                 last_frame;
 117         uint8_t                 trb_type;
 118         uint8_t                 direction;
 119         uint8_t                 tbc;
 120         uint8_t                 tlbpc;
 121         uint8_t                 step_td;
 122         uint8_t                 do_isoc_sync;
 123 };
 124
 125 static void     xhci_do_poll(struct usb_bus *);
 126 static void     xhci_device_done(struct usb_xfer *, usb_error_t);
 127 static void     xhci_root_intr(struct xhci_softc *);
 128 static void     xhci_free_device_ext(struct usb_device *);
 129 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
 130                     struct usb_endpoint_descriptor *);
 131 static usb_proc_callback_t xhci_configure_msg;
 132 static usb_error_t xhci_configure_device(struct usb_device *);
 133 static usb_error_t xhci_configure_endpoint(struct usb_device *,
 134                     struct usb_endpoint_descriptor *, uint64_t, uint16_t,
 135                     uint8_t, uint8_t, uint8_t, uint16_t, uint16_t);
 136 static usb_error_t xhci_configure_mask(struct usb_device *,
 137                     uint32_t, uint8_t);
 138 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
 139                     uint64_t, uint8_t);
 140 static void xhci_endpoint_doorbell(struct usb_xfer *);
 141 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
 142 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
 143 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
 144 #ifdef USB_DEBUG
 145 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
 146 #endif
 147
 148 extern struct usb_bus_methods xhci_bus_methods;
 149
 150 #ifdef USB_DEBUG
 151 static void
 152 xhci_dump_trb(struct xhci_trb *trb)
 153 {
 154         DPRINTFN(5, "trb = %p\n", trb);
 155         DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
 156         DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
 157         DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
 158 }
 159
 160 static void
 161 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
 162 {
 163         DPRINTFN(5, "pep = %p\n", pep);
 164         DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
 165         DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
 166         DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
 167         DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
 168         DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
 169         DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
 170         DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
 171 }
 172
 173 static void
 174 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
 175 {
 176         DPRINTFN(5, "psl = %p\n", psl);
 177         DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
 178         DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
 179         DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
 180         DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
 181 }
 182 #endif
 183
 184 static void
 185 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
 186 {
 187         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 188         uint8_t i;
 189
 190         cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
 191            sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
 192
 193         cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
 194            sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
 195
 196         for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) {
 197                 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
 198                     XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
 199         }
 200 }
 201
 202 static void
 203 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
 204 {
 205         if (sc->sc_ctx_is_64_byte) {
 206                 uint32_t offset;
 207                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 208                 /* all contexts are initially 32-bytes */
 209                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 210                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 211         }
 212         *ptr = htole32(val);
 213 }
 214
 215 static uint32_t
 216 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
 217 {
 218         if (sc->sc_ctx_is_64_byte) {
 219                 uint32_t offset;
 220                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 221                 /* all contexts are initially 32-bytes */
 222                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 223                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 224         }
 225         return (le32toh(*ptr));
 226 }
 227
 228 static void
 229 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
 230 {
 231         if (sc->sc_ctx_is_64_byte) {
 232                 uint32_t offset;
 233                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 234                 /* all contexts are initially 32-bytes */
 235                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 236                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 237         }
 238         *ptr = htole64(val);
 239 }
 240
 241 #ifdef USB_DEBUG
 242 static uint64_t
 243 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
 244 {
 245         if (sc->sc_ctx_is_64_byte) {
 246                 uint32_t offset;
 247                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 248                 /* all contexts are initially 32-bytes */
 249                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 250                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 251         }
 252         return (le64toh(*ptr));
 253 }
 254 #endif
 255
 256 static int
 257 xhci_reset_command_queue_locked(struct xhci_softc *sc)
 258 {
 259         struct usb_page_search buf_res;
 260         struct xhci_hw_root *phwr;
 261         uint64_t addr;
 262         uint32_t temp;
 263
 264         DPRINTF("\n");
 265
 266         temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 267         if (temp & XHCI_CRCR_LO_CRR) {
 268                 DPRINTF("Command ring running\n");
 269                 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
 270
 271                 /*
 272                  * Try to abort the last command as per section
 273                  * 4.6.1.2 "Aborting a Command" of the XHCI
 274                  * specification:
 275                  */
 276
 277                 /* stop and cancel */
 278                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
 279                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 280
 281                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
 282                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 283
 284                 /* wait 250ms */
 285                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
 286
 287                 /* check if command ring is still running */
 288                 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 289                 if (temp & XHCI_CRCR_LO_CRR) {
 290                         DPRINTF("Comand ring still running\n");
 291                         return (USB_ERR_IOERROR);
 292                 }
 293         }
 294
 295         /* reset command ring */
 296         sc->sc_command_ccs = 1;
 297         sc->sc_command_idx = 0;
 298
 299         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 300
 301         /* setup command ring control base address */
 302         addr = buf_res.physaddr;
 303         phwr = buf_res.buffer;
 304         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 305
 306         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 307
 308         memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
 309         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 310
 311         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
 312
 313         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 314         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 315
 316         return (0);
 317 }
 318
 319 usb_error_t
 320 xhci_start_controller(struct xhci_softc *sc)
 321 {
 322         struct usb_page_search buf_res;
 323         struct xhci_hw_root *phwr;
 324         struct xhci_dev_ctx_addr *pdctxa;
 325         uint64_t addr;
 326         uint32_t temp;
 327         uint16_t i;
 328
 329         DPRINTF("\n");
 330
 331         sc->sc_capa_off = 0;
 332         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 333         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
 334         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 335
 336         DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
 337         DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
 338         DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
 339
 340         sc->sc_event_ccs = 1;
 341         sc->sc_event_idx = 0;
 342         sc->sc_command_ccs = 1;
 343         sc->sc_command_idx = 0;
 344
 345         DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
 346
 347         temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
 348
 349         DPRINTF("HCS0 = 0x%08x\n", temp);
 350
 351         if (XHCI_HCS0_CSZ(temp)) {
 352                 sc->sc_ctx_is_64_byte = 1;
 353                 device_printf(sc->sc_bus.parent, "64 byte context size.\n");
 354         } else {
 355                 sc->sc_ctx_is_64_byte = 0;
 356                 device_printf(sc->sc_bus.parent, "32 byte context size.\n");
 357         }
 358
 359         /* Reset controller */
 360         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
 361
 362         for (i = 0; i != 100; i++) {
 363                 usb_pause_mtx(NULL, hz / 100);
 364                 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
 365                     (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
 366                 if (!temp)
 367                         break;
 368         }
 369
 370         if (temp) {
 371                 device_printf(sc->sc_bus.parent, "Controller "
 372                     "reset timeout.\n");
 373                 return (USB_ERR_IOERROR);
 374         }
 375
 376         if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
 377                 device_printf(sc->sc_bus.parent, "Controller does "
 378                     "not support 4K page size.\n");
 379                 return (USB_ERR_IOERROR);
 380         }
 381
 382         temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
 383
 384         i = XHCI_HCS1_N_PORTS(temp);
 385
 386         if (i == 0) {
 387                 device_printf(sc->sc_bus.parent, "Invalid number "
 388                     "of ports: %u\n", i);
 389                 return (USB_ERR_IOERROR);
 390         }
 391
 392         sc->sc_noport = i;
 393         sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
 394
 395         if (sc->sc_noslot > XHCI_MAX_DEVICES)
 396                 sc->sc_noslot = XHCI_MAX_DEVICES;
 397
 398         /* setup number of device slots */
 399
 400         DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
 401             XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
 402
 403         XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
 404
 405         DPRINTF("Max slots: %u\n", sc->sc_noslot);
 406
 407         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 408
 409         sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
 410
 411         if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
 412                 device_printf(sc->sc_bus.parent, "XHCI request "
 413                     "too many scratchpads\n");
 414                 return (USB_ERR_NOMEM);
 415         }
 416
 417         DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
 418
 419         temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
 420
 421         sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
 422             XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
 423
 424         temp = XREAD4(sc, oper, XHCI_USBSTS);
 425
 426         /* clear interrupts */
 427         XWRITE4(sc, oper, XHCI_USBSTS, temp);
 428         /* disable all device notifications */
 429         XWRITE4(sc, oper, XHCI_DNCTRL, 0);
 430
 431         /* setup device context base address */
 432         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
 433         pdctxa = buf_res.buffer;
 434         memset(pdctxa, 0, sizeof(*pdctxa));
 435
 436         addr = buf_res.physaddr;
 437         addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
 438
 439         /* slot 0 points to the table of scratchpad pointers */
 440         pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
 441
 442         for (i = 0; i != sc->sc_noscratch; i++) {
 443                 struct usb_page_search buf_scp;
 444                 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
 445                 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
 446         }
 447
 448         addr = buf_res.physaddr;
 449
 450         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 451         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 452         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 453         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 454
 455         /* Setup event table size */
 456
 457         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 458
 459         DPRINTF("HCS2=0x%08x\n", temp);
 460
 461         temp = XHCI_HCS2_ERST_MAX(temp);
 462         temp = 1U << temp;
 463         if (temp > XHCI_MAX_RSEG)
 464                 temp = XHCI_MAX_RSEG;
 465
 466         sc->sc_erst_max = temp;
 467
 468         DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
 469             XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp);
 470
 471         XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp));
 472
 473         /* Setup interrupt rate */
 474         XWRITE4(sc, runt, XHCI_IMOD(0), XHCI_IMOD_DEFAULT);
 475
 476         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 477
 478         phwr = buf_res.buffer;
 479         addr = buf_res.physaddr;
 480         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
 481
 482         /* reset hardware root structure */
 483         memset(phwr, 0, sizeof(*phwr));
 484
 485         phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
 486         phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
 487
 488         DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
 489
 490         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
 491         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
 492
 493         addr = (uint64_t)buf_res.physaddr;
 494
 495         DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
 496
 497         XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
 498         XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
 499
 500         /* Setup interrupter registers */
 501
 502         temp = XREAD4(sc, runt, XHCI_IMAN(0));
 503         temp |= XHCI_IMAN_INTR_ENA;
 504         XWRITE4(sc, runt, XHCI_IMAN(0), temp);
 505
 506         /* setup command ring control base address */
 507         addr = buf_res.physaddr;
 508         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 509
 510         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 511
 512         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 513         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 514
 515         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 516
 517         usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 518
 519         /* Go! */
 520         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
 521             XHCI_CMD_INTE | XHCI_CMD_HSEE);
 522
 523         for (i = 0; i != 100; i++) {
 524                 usb_pause_mtx(NULL, hz / 100);
 525                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 526                 if (!temp)
 527                         break;
 528         }
 529         if (temp) {
 530                 XWRITE4(sc, oper, XHCI_USBCMD, 0);
 531                 device_printf(sc->sc_bus.parent, "Run timeout.\n");
 532                 return (USB_ERR_IOERROR);
 533         }
 534
 535         /* catch any lost interrupts */
 536         xhci_do_poll(&sc->sc_bus);
 537
 538         if (sc->sc_port_route != NULL) {
 539                 /* Route all ports to the XHCI by default */
 540                 sc->sc_port_route(sc->sc_bus.parent,
 541                     ~xhciroute, xhciroute);
 542         }
 543         return (0);
 544 }
 545
 546 usb_error_t
 547 xhci_halt_controller(struct xhci_softc *sc)
 548 {
 549         uint32_t temp;
 550         uint16_t i;
 551
 552         DPRINTF("\n");
 553
 554         sc->sc_capa_off = 0;
 555         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 556         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
 557         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 558
 559         /* Halt controller */
 560         XWRITE4(sc, oper, XHCI_USBCMD, 0);
 561
 562         for (i = 0; i != 100; i++) {
 563                 usb_pause_mtx(NULL, hz / 100);
 564                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 565                 if (temp)
 566                         break;
 567         }
 568
 569         if (!temp) {
 570                 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
 571                 return (USB_ERR_IOERROR);
 572         }
 573         return (0);
 574 }
 575
 576 usb_error_t
 577 xhci_init(struct xhci_softc *sc, device_t self)
 578 {
 579         /* initialise some bus fields */
 580         sc->sc_bus.parent = self;
 581
 582         /* set the bus revision */
 583         sc->sc_bus.usbrev = USB_REV_3_0;
 584
 585         /* set up the bus struct */
 586         sc->sc_bus.methods = &xhci_bus_methods;
 587
 588         /* setup devices array */
 589         sc->sc_bus.devices = sc->sc_devices;
 590         sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
 591
 592         /* setup command queue mutex and condition varible */
 593         cv_init(&sc->sc_cmd_cv, "CMDQ");
 594         sx_init(&sc->sc_cmd_sx, "CMDQ lock");
 595
 596         /* get all DMA memory */
 597         if (usb_bus_mem_alloc_all(&sc->sc_bus,
 598             USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
 599                 return (ENOMEM);
 600         }
 601
 602         sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
 603         sc->sc_config_msg[0].bus = &sc->sc_bus;
 604         sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
 605         sc->sc_config_msg[1].bus = &sc->sc_bus;
 606
 607         if (usb_proc_create(&sc->sc_config_proc,
 608             &sc->sc_bus.bus_mtx, device_get_nameunit(self), USB_PRI_MED)) {
 609                 printf("WARNING: Creation of XHCI configure "
 610                     "callback process failed.\n");
 611         }
 612         return (0);
 613 }
 614
 615 void
 616 xhci_uninit(struct xhci_softc *sc)
 617 {
 618         usb_proc_free(&sc->sc_config_proc);
 619
 620         usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 621
 622         cv_destroy(&sc->sc_cmd_cv);
 623         sx_destroy(&sc->sc_cmd_sx);
 624 }
 625
 626 static void
 627 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
 628 {
 629         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 630
 631         switch (state) {
 632         case USB_HW_POWER_SUSPEND:
 633                 DPRINTF("Stopping the XHCI\n");
 634                 xhci_halt_controller(sc);
 635                 break;
 636         case USB_HW_POWER_SHUTDOWN:
 637                 DPRINTF("Stopping the XHCI\n");
 638                 xhci_halt_controller(sc);
 639                 break;
 640         case USB_HW_POWER_RESUME:
 641                 DPRINTF("Starting the XHCI\n");
 642                 xhci_start_controller(sc);
 643                 break;
 644         default:
 645                 break;
 646         }
 647 }
 648
 649 static usb_error_t
 650 xhci_generic_done_sub(struct usb_xfer *xfer)
 651 {
 652         struct xhci_td *td;
 653         struct xhci_td *td_alt_next;
 654         uint32_t len;
 655         uint8_t status;
 656
 657         td = xfer->td_transfer_cache;
 658         td_alt_next = td->alt_next;
 659
 660         if (xfer->aframes != xfer->nframes)
 661                 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
 662
 663         while (1) {
 664
 665                 usb_pc_cpu_invalidate(td->page_cache);
 666
 667                 status = td->status;
 668                 len = td->remainder;
 669
 670                 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
 671                     xfer, (unsigned int)xfer->aframes,
 672                     (unsigned int)xfer->nframes,
 673                     (unsigned int)len, (unsigned int)td->len,
 674                     (unsigned int)status);
 675
 676                 /*
 677                  * Verify the status length and
 678                  * add the length to "frlengths[]":
 679                  */
 680                 if (len > td->len) {
 681                         /* should not happen */
 682                         DPRINTF("Invalid status length, "
 683                             "0x%04x/0x%04x bytes\n", len, td->len);
 684                         status = XHCI_TRB_ERROR_LENGTH;
 685                 } else if (xfer->aframes != xfer->nframes) {
 686                         xfer->frlengths[xfer->aframes] += td->len - len;
 687                 }
 688                 /* Check for last transfer */
 689                 if (((void *)td) == xfer->td_transfer_last) {
 690                         td = NULL;
 691                         break;
 692                 }
 693                 /* Check for transfer error */
 694                 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
 695                     status != XHCI_TRB_ERROR_SUCCESS) {
 696                         /* the transfer is finished */
 697                         td = NULL;
 698                         break;
 699                 }
 700                 /* Check for short transfer */
 701                 if (len > 0) {
 702                         if (xfer->flags_int.short_frames_ok ||
 703                             xfer->flags_int.isochronous_xfr ||
 704                             xfer->flags_int.control_xfr) {
 705                                 /* follow alt next */
 706                                 td = td->alt_next;
 707                         } else {
 708                                 /* the transfer is finished */
 709                                 td = NULL;
 710                         }
 711                         break;
 712                 }
 713                 td = td->obj_next;
 714
 715                 if (td->alt_next != td_alt_next) {
 716                         /* this USB frame is complete */
 717                         break;
 718                 }
 719         }
 720
 721         /* update transfer cache */
 722
 723         xfer->td_transfer_cache = td;
 724
 725         return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
 726             (status != XHCI_TRB_ERROR_SHORT_PKT &&
 727             status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
 728             USB_ERR_NORMAL_COMPLETION);
 729 }
 730
 731 static void
 732 xhci_generic_done(struct usb_xfer *xfer)
 733 {
 734         usb_error_t err = 0;
 735
 736         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
 737             xfer, xfer->endpoint);
 738
 739         /* reset scanner */
 740
 741         xfer->td_transfer_cache = xfer->td_transfer_first;
 742
 743         if (xfer->flags_int.control_xfr) {
 744
 745                 if (xfer->flags_int.control_hdr)
 746                         err = xhci_generic_done_sub(xfer);
 747
 748                 xfer->aframes = 1;
 749
 750                 if (xfer->td_transfer_cache == NULL)
 751                         goto done;
 752         }
 753
 754         while (xfer->aframes != xfer->nframes) {
 755
 756                 err = xhci_generic_done_sub(xfer);
 757                 xfer->aframes++;
 758
 759                 if (xfer->td_transfer_cache == NULL)
 760                         goto done;
 761         }
 762
 763         if (xfer->flags_int.control_xfr &&
 764             !xfer->flags_int.control_act)
 765                 err = xhci_generic_done_sub(xfer);
 766 done:
 767         /* transfer is complete */
 768         xhci_device_done(xfer, err);
 769 }
 770
 771 static void
 772 xhci_activate_transfer(struct usb_xfer *xfer)
 773 {
 774         struct xhci_td *td;
 775
 776         td = xfer->td_transfer_cache;
 777
 778         usb_pc_cpu_invalidate(td->page_cache);
 779
 780         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 781
 782                 /* activate the transfer */
 783
 784                 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
 785                 usb_pc_cpu_flush(td->page_cache);
 786
 787                 xhci_endpoint_doorbell(xfer);
 788         }
 789 }
 790
 791 static void
 792 xhci_skip_transfer(struct usb_xfer *xfer)
 793 {
 794         struct xhci_td *td;
 795         struct xhci_td *td_last;
 796
 797         td = xfer->td_transfer_cache;
 798         td_last = xfer->td_transfer_last;
 799
 800         td = td->alt_next;
 801
 802         usb_pc_cpu_invalidate(td->page_cache);
 803
 804         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 805
 806                 usb_pc_cpu_invalidate(td_last->page_cache);
 807
 808                 /* copy LINK TRB to current waiting location */
 809
 810                 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
 811                 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
 812                 usb_pc_cpu_flush(td->page_cache);
 813
 814                 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
 815                 usb_pc_cpu_flush(td->page_cache);
 816
 817                 xhci_endpoint_doorbell(xfer);
 818         }
 819 }
 820
 821 /*------------------------------------------------------------------------*
 822  *      xhci_check_transfer
 823  *------------------------------------------------------------------------*/
 824 static void
 825 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
 826 {
 827         int64_t offset;
 828         uint64_t td_event;
 829         uint32_t temp;
 830         uint32_t remainder;
 831         uint8_t status;
 832         uint8_t halted;
 833         uint8_t epno;
 834         uint8_t index;
 835         uint8_t i;
 836
 837         /* decode TRB */
 838         td_event = le64toh(trb->qwTrb0);
 839         temp = le32toh(trb->dwTrb2);
 840
 841         remainder = XHCI_TRB_2_REM_GET(temp);
 842         status = XHCI_TRB_2_ERROR_GET(temp);
 843
 844         temp = le32toh(trb->dwTrb3);
 845         epno = XHCI_TRB_3_EP_GET(temp);
 846         index = XHCI_TRB_3_SLOT_GET(temp);
 847
 848         /* check if error means halted */
 849         halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
 850             status != XHCI_TRB_ERROR_SUCCESS);
 851
 852         DPRINTF("slot=%u epno=%u remainder=%u status=%u\n",
 853             index, epno, remainder, status);
 854
 855         if (index > sc->sc_noslot) {
 856                 DPRINTF("Invalid slot.\n");
 857                 return;
 858         }
 859
 860         if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
 861                 DPRINTF("Invalid endpoint.\n");
 862                 return;
 863         }
 864
 865         /* try to find the USB transfer that generated the event */
 866         for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
 867                 struct usb_xfer *xfer;
 868                 struct xhci_td *td;
 869                 struct xhci_endpoint_ext *pepext;
 870
 871                 pepext = &sc->sc_hw.devs[index].endp[epno];
 872
 873                 xfer = pepext->xfer[i];
 874                 if (xfer == NULL)
 875                         continue;
 876
 877                 td = xfer->td_transfer_cache;
 878
 879                 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
 880                         (long long)td_event,
 881                         (long long)td->td_self,
 882                         (long long)td->td_self + sizeof(td->td_trb));
 883
 884                 /*
 885                  * NOTE: Some XHCI implementations might not trigger
 886                  * an event on the last LINK TRB so we need to
 887                  * consider both the last and second last event
 888                  * address as conditions for a successful transfer.
 889                  *
 890                  * NOTE: We assume that the XHCI will only trigger one
 891                  * event per chain of TRBs.
 892                  */
 893
 894                 offset = td_event - td->td_self;
 895
 896                 if (offset >= 0 &&
 897                     offset < (int64_t)sizeof(td->td_trb)) {
 898
 899                         usb_pc_cpu_invalidate(td->page_cache);
 900
 901                         /* compute rest of remainder, if any */
 902                         for (i = (offset / 16) + 1; i < td->ntrb; i++) {
 903                                 temp = le32toh(td->td_trb[i].dwTrb2);
 904                                 remainder += XHCI_TRB_2_BYTES_GET(temp);
 905                         }
 906
 907                         DPRINTFN(5, "New remainder: %u\n", remainder);
 908
 909                         /* clear isochronous transfer errors */
 910                         if (xfer->flags_int.isochronous_xfr) {
 911                                 if (halted) {
 912                                         halted = 0;
 913                                         status = XHCI_TRB_ERROR_SUCCESS;
 914                                         remainder = td->len;
 915                                 }
 916                         }
 917
 918                         /* "td->remainder" is verified later */
 919                         td->remainder = remainder;
 920                         td->status = status;
 921
 922                         usb_pc_cpu_flush(td->page_cache);
 923
 924                         /*
 925                          * 1) Last transfer descriptor makes the
 926                          * transfer done
 927                          */
 928                         if (((void *)td) == xfer->td_transfer_last) {
 929                                 DPRINTF("TD is last\n");
 930                                 xhci_generic_done(xfer);
 931                                 break;
 932                         }
 933
 934                         /*
 935                          * 2) Any kind of error makes the transfer
 936                          * done
 937                          */
 938                         if (halted) {
 939                                 DPRINTF("TD has I/O error\n");
 940                                 xhci_generic_done(xfer);
 941                                 break;
 942                         }
 943
 944                         /*
 945                          * 3) If there is no alternate next transfer,
 946                          * a short packet also makes the transfer done
 947                          */
 948                         if (td->remainder > 0) {
 949                                 if (td->alt_next == NULL) {
 950                                         DPRINTF(
 951                                             "short TD has no alternate next\n");
 952                                         xhci_generic_done(xfer);
 953                                         break;
 954                                 }
 955                                 DPRINTF("TD has short pkt\n");
 956                                 if (xfer->flags_int.short_frames_ok ||
 957                                     xfer->flags_int.isochronous_xfr ||
 958                                     xfer->flags_int.control_xfr) {
 959                                         /* follow the alt next */
 960                                         xfer->td_transfer_cache = td->alt_next;
 961                                         xhci_activate_transfer(xfer);
 962                                         break;
 963                                 }
 964                                 xhci_skip_transfer(xfer);
 965                                 xhci_generic_done(xfer);
 966                                 break;
 967                         }
 968
 969                         /*
 970                          * 4) Transfer complete - go to next TD
 971                          */
 972                         DPRINTF("Following next TD\n");
 973                         xfer->td_transfer_cache = td->obj_next;
 974                         xhci_activate_transfer(xfer);
 975                         break;          /* there should only be one match */
 976                 }
 977         }
 978 }
 979
 980 static int
 981 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
 982 {
 983         if (sc->sc_cmd_addr == trb->qwTrb0) {
 984                 DPRINTF("Received command event\n");
 985                 sc->sc_cmd_result[0] = trb->dwTrb2;
 986                 sc->sc_cmd_result[1] = trb->dwTrb3;
 987                 cv_signal(&sc->sc_cmd_cv);
 988                 return (1);     /* command match */
 989         }
 990         return (0);
 991 }
 992
 993 static int
 994 xhci_interrupt_poll(struct xhci_softc *sc)
 995 {
 996         struct usb_page_search buf_res;
 997         struct xhci_hw_root *phwr;
 998         uint64_t addr;
 999         uint32_t temp;
1000         int retval = 0;
1001         uint16_t i;
1002         uint8_t event;
1003         uint8_t j;
1004         uint8_t k;
1005         uint8_t t;
1006
1007         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1008
1009         phwr = buf_res.buffer;
1010
1011         /* Receive any events */
1012
1013         usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1014
1015         i = sc->sc_event_idx;
1016         j = sc->sc_event_ccs;
1017         t = 2;
1018
1019         while (1) {
1020
1021                 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1022
1023                 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1024
1025                 if (j != k)
1026                         break;
1027
1028                 event = XHCI_TRB_3_TYPE_GET(temp);
1029
1030                 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1031                     i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1032                     (long)le32toh(phwr->hwr_events[i].dwTrb2),
1033                     (long)le32toh(phwr->hwr_events[i].dwTrb3));
1034
1035                 switch (event) {
1036                 case XHCI_TRB_EVENT_TRANSFER:
1037                         xhci_check_transfer(sc, &phwr->hwr_events[i]);
1038                         break;
1039                 case XHCI_TRB_EVENT_CMD_COMPLETE:
1040                         retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1041                         break;
1042                 default:
1043                         DPRINTF("Unhandled event = %u\n", event);
1044                         break;
1045                 }
1046
1047                 i++;
1048
1049                 if (i == XHCI_MAX_EVENTS) {
1050                         i = 0;
1051                         j ^= 1;
1052
1053                         /* check for timeout */
1054                         if (!--t)
1055                                 break;
1056                 }
1057         }
1058
1059         sc->sc_event_idx = i;
1060         sc->sc_event_ccs = j;
1061
1062         /*
1063          * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1064          * latched. That means to activate the register we need to
1065          * write both the low and high double word of the 64-bit
1066          * register.
1067          */
1068
1069         addr = (uint32_t)buf_res.physaddr;
1070         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1071
1072         /* try to clear busy bit */
1073         addr |= XHCI_ERDP_LO_BUSY;
1074
1075         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1076         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1077
1078         return (retval);
1079 }
1080
1081 static usb_error_t
1082 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1083     uint16_t timeout_ms)
1084 {
1085         struct usb_page_search buf_res;
1086         struct xhci_hw_root *phwr;
1087         uint64_t addr;
1088         uint32_t temp;
1089         uint8_t i;
1090         uint8_t j;
1091         uint8_t timeout = 0;
1092         int err;
1093
1094         XHCI_CMD_ASSERT_LOCKED(sc);
1095
1096         /* get hardware root structure */
1097
1098         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1099
1100         phwr = buf_res.buffer;
1101
1102         /* Queue command */
1103
1104         USB_BUS_LOCK(&sc->sc_bus);
1105 retry:
1106         i = sc->sc_command_idx;
1107         j = sc->sc_command_ccs;
1108
1109         DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1110             i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1111             (long long)le64toh(trb->qwTrb0),
1112             (long)le32toh(trb->dwTrb2),
1113             (long)le32toh(trb->dwTrb3));
1114
1115         phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1116         phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1117
1118         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1119
1120         temp = trb->dwTrb3;
1121
1122         if (j)
1123                 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1124         else
1125                 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1126
1127         temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1128
1129         phwr->hwr_commands[i].dwTrb3 = temp;
1130
1131         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1132
1133         addr = buf_res.physaddr;
1134         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1135
1136         sc->sc_cmd_addr = htole64(addr);
1137
1138         i++;
1139
1140         if (i == (XHCI_MAX_COMMANDS - 1)) {
1141
1142                 if (j) {
1143                         temp = htole32(XHCI_TRB_3_TC_BIT |
1144                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1145                             XHCI_TRB_3_CYCLE_BIT);
1146                 } else {
1147                         temp = htole32(XHCI_TRB_3_TC_BIT |
1148                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1149                 }
1150
1151                 phwr->hwr_commands[i].dwTrb3 = temp;
1152
1153                 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1154
1155                 i = 0;
1156                 j ^= 1;
1157         }
1158
1159         sc->sc_command_idx = i;
1160         sc->sc_command_ccs = j;
1161
1162         XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1163
1164         err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1165             USB_MS_TO_TICKS(timeout_ms));
1166
1167         /*
1168          * In some error cases event interrupts are not generated.
1169          * Poll one time to see if the command has completed.
1170          */
1171         if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1172                 DPRINTF("Command was completed when polling\n");
1173                 err = 0;
1174         }
1175         if (err != 0) {
1176                 DPRINTF("Command timeout!\n");
1177                 /*
1178                  * After some weeks of continuous operation, it has
1179                  * been observed that the ASMedia Technology, ASM1042
1180                  * SuperSpeed USB Host Controller can suddenly stop
1181                  * accepting commands via the command queue. Try to
1182                  * first reset the command queue. If that fails do a
1183                  * host controller reset.
1184                  */
1185                 if (timeout == 0 &&
1186                     xhci_reset_command_queue_locked(sc) == 0) {
1187                         timeout = 1;
1188                         goto retry;
1189                 } else {
1190                         DPRINTF("Controller reset!\n");
1191                         usb_bus_reset_async_locked(&sc->sc_bus);
1192                 }
1193                 err = USB_ERR_TIMEOUT;
1194                 trb->dwTrb2 = 0;
1195                 trb->dwTrb3 = 0;
1196         } else {
1197                 temp = le32toh(sc->sc_cmd_result[0]);
1198                 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1199                         err = USB_ERR_IOERROR;
1200
1201                 trb->dwTrb2 = sc->sc_cmd_result[0];
1202                 trb->dwTrb3 = sc->sc_cmd_result[1];
1203         }
1204
1205         USB_BUS_UNLOCK(&sc->sc_bus);
1206
1207         return (err);
1208 }
1209
1210 #if 0
1211 static usb_error_t
1212 xhci_cmd_nop(struct xhci_softc *sc)
1213 {
1214         struct xhci_trb trb;
1215         uint32_t temp;
1216
1217         DPRINTF("\n");
1218
1219         trb.qwTrb0 = 0;
1220         trb.dwTrb2 = 0;
1221         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1222
1223         trb.dwTrb3 = htole32(temp);
1224
1225         return (xhci_do_command(sc, &trb, 100 /* ms */));
1226 }
1227 #endif
1228
1229 static usb_error_t
1230 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1231 {
1232         struct xhci_trb trb;
1233         uint32_t temp;
1234         usb_error_t err;
1235
1236         DPRINTF("\n");
1237
1238         trb.qwTrb0 = 0;
1239         trb.dwTrb2 = 0;
1240         trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1241
1242         err = xhci_do_command(sc, &trb, 100 /* ms */);
1243         if (err)
1244                 goto done;
1245
1246         temp = le32toh(trb.dwTrb3);
1247
1248         *pslot = XHCI_TRB_3_SLOT_GET(temp);
1249
1250 done:
1251         return (err);
1252 }
1253
1254 static usb_error_t
1255 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1256 {
1257         struct xhci_trb trb;
1258         uint32_t temp;
1259
1260         DPRINTF("\n");
1261
1262         trb.qwTrb0 = 0;
1263         trb.dwTrb2 = 0;
1264         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1265             XHCI_TRB_3_SLOT_SET(slot_id);
1266
1267         trb.dwTrb3 = htole32(temp);
1268
1269         return (xhci_do_command(sc, &trb, 100 /* ms */));
1270 }
1271
1272 static usb_error_t
1273 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1274     uint8_t bsr, uint8_t slot_id)
1275 {
1276         struct xhci_trb trb;
1277         uint32_t temp;
1278
1279         DPRINTF("\n");
1280
1281         trb.qwTrb0 = htole64(input_ctx);
1282         trb.dwTrb2 = 0;
1283         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1284             XHCI_TRB_3_SLOT_SET(slot_id);
1285
1286         if (bsr)
1287                 temp |= XHCI_TRB_3_BSR_BIT;
1288
1289         trb.dwTrb3 = htole32(temp);
1290
1291         return (xhci_do_command(sc, &trb, 500 /* ms */));
1292 }
1293
1294 static usb_error_t
1295 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1296 {
1297         struct usb_page_search buf_inp;
1298         struct usb_page_search buf_dev;
1299         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1300         struct xhci_hw_dev *hdev;
1301         struct xhci_dev_ctx *pdev;
1302         struct xhci_endpoint_ext *pepext;
1303         uint32_t temp;
1304         uint16_t mps;
1305         usb_error_t err;
1306         uint8_t index;
1307
1308         /* the root HUB case is not handled here */
1309         if (udev->parent_hub == NULL)
1310                 return (USB_ERR_INVAL);
1311
1312         index = udev->controller_slot_id;
1313
1314         hdev =  &sc->sc_hw.devs[index];
1315
1316         if (mtx != NULL)
1317                 mtx_unlock(mtx);
1318
1319         XHCI_CMD_LOCK(sc);
1320
1321         switch (hdev->state) {
1322         case XHCI_ST_DEFAULT:
1323         case XHCI_ST_ENABLED:
1324
1325                 hdev->state = XHCI_ST_ENABLED;
1326
1327                 /* set configure mask to slot and EP0 */
1328                 xhci_configure_mask(udev, 3, 0);
1329
1330                 /* configure input slot context structure */
1331                 err = xhci_configure_device(udev);
1332
1333                 if (err != 0) {
1334                         DPRINTF("Could not configure device\n");
1335                         break;
1336                 }
1337
1338                 /* configure input endpoint context structure */
1339                 switch (udev->speed) {
1340                 case USB_SPEED_LOW:
1341                 case USB_SPEED_FULL:
1342                         mps = 8;
1343                         break;
1344                 case USB_SPEED_HIGH:
1345                         mps = 64;
1346                         break;
1347                 default:
1348                         mps = 512;
1349                         break;
1350                 }
1351
1352                 pepext = xhci_get_endpoint_ext(udev,
1353                     &udev->ctrl_ep_desc);
1354                 err = xhci_configure_endpoint(udev,
1355                     &udev->ctrl_ep_desc, pepext->physaddr,
1356                     0, 1, 1, 0, mps, mps);
1357
1358                 if (err != 0) {
1359                         DPRINTF("Could not configure default endpoint\n");
1360                         break;
1361                 }
1362
1363                 /* execute set address command */
1364                 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1365
1366                 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1367                     (address == 0), index);
1368
1369                 if (err != 0) {
1370                         temp = le32toh(sc->sc_cmd_result[0]);
1371                         if (address == 0 && sc->sc_port_route != NULL &&
1372                             XHCI_TRB_2_ERROR_GET(temp) ==
1373                             XHCI_TRB_ERROR_PARAMETER) {
1374                                 /* LynxPoint XHCI - ports are not switchable */
1375                                 /* Un-route all ports from the XHCI */
1376                                 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1377                         }
1378                         DPRINTF("Could not set address "
1379                             "for slot %u.\n", index);
1380                         if (address != 0)
1381                                 break;
1382                 }
1383
1384                 /* update device address to new value */
1385
1386                 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1387                 pdev = buf_dev.buffer;
1388                 usb_pc_cpu_invalidate(&hdev->device_pc);
1389
1390                 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1391                 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1392
1393                 /* update device state to new value */
1394
1395                 if (address != 0)
1396                         hdev->state = XHCI_ST_ADDRESSED;
1397                 else
1398                         hdev->state = XHCI_ST_DEFAULT;
1399                 break;
1400
1401         default:
1402                 DPRINTF("Wrong state for set address.\n");
1403                 err = USB_ERR_IOERROR;
1404                 break;
1405         }
1406         XHCI_CMD_UNLOCK(sc);
1407
1408         if (mtx != NULL)
1409                 mtx_lock(mtx);
1410
1411         return (err);
1412 }
1413
1414 static usb_error_t
1415 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1416     uint8_t deconfigure, uint8_t slot_id)
1417 {
1418         struct xhci_trb trb;
1419         uint32_t temp;
1420
1421         DPRINTF("\n");
1422
1423         trb.qwTrb0 = htole64(input_ctx);
1424         trb.dwTrb2 = 0;
1425         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1426             XHCI_TRB_3_SLOT_SET(slot_id);
1427
1428         if (deconfigure)
1429                 temp |= XHCI_TRB_3_DCEP_BIT;
1430
1431         trb.dwTrb3 = htole32(temp);
1432
1433         return (xhci_do_command(sc, &trb, 100 /* ms */));
1434 }
1435
1436 static usb_error_t
1437 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1438     uint8_t slot_id)
1439 {
1440         struct xhci_trb trb;
1441         uint32_t temp;
1442
1443         DPRINTF("\n");
1444
1445         trb.qwTrb0 = htole64(input_ctx);
1446         trb.dwTrb2 = 0;
1447         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1448             XHCI_TRB_3_SLOT_SET(slot_id);
1449         trb.dwTrb3 = htole32(temp);
1450
1451         return (xhci_do_command(sc, &trb, 100 /* ms */));
1452 }
1453
1454 static usb_error_t
1455 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1456     uint8_t ep_id, uint8_t slot_id)
1457 {
1458         struct xhci_trb trb;
1459         uint32_t temp;
1460
1461         DPRINTF("\n");
1462
1463         trb.qwTrb0 = 0;
1464         trb.dwTrb2 = 0;
1465         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1466             XHCI_TRB_3_SLOT_SET(slot_id) |
1467             XHCI_TRB_3_EP_SET(ep_id);
1468
1469         if (preserve)
1470                 temp |= XHCI_TRB_3_PRSV_BIT;
1471
1472         trb.dwTrb3 = htole32(temp);
1473
1474         return (xhci_do_command(sc, &trb, 100 /* ms */));
1475 }
1476
1477 static usb_error_t
1478 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1479     uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1480 {
1481         struct xhci_trb trb;
1482         uint32_t temp;
1483
1484         DPRINTF("\n");
1485
1486         trb.qwTrb0 = htole64(dequeue_ptr);
1487
1488         temp = XHCI_TRB_2_STREAM_SET(stream_id);
1489         trb.dwTrb2 = htole32(temp);
1490
1491         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1492             XHCI_TRB_3_SLOT_SET(slot_id) |
1493             XHCI_TRB_3_EP_SET(ep_id);
1494         trb.dwTrb3 = htole32(temp);
1495
1496         return (xhci_do_command(sc, &trb, 100 /* ms */));
1497 }
1498
1499 static usb_error_t
1500 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1501     uint8_t ep_id, uint8_t slot_id)
1502 {
1503         struct xhci_trb trb;
1504         uint32_t temp;
1505
1506         DPRINTF("\n");
1507
1508         trb.qwTrb0 = 0;
1509         trb.dwTrb2 = 0;
1510         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1511             XHCI_TRB_3_SLOT_SET(slot_id) |
1512             XHCI_TRB_3_EP_SET(ep_id);
1513
1514         if (suspend)
1515                 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1516
1517         trb.dwTrb3 = htole32(temp);
1518
1519         return (xhci_do_command(sc, &trb, 100 /* ms */));
1520 }
1521
1522 static usb_error_t
1523 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1524 {
1525         struct xhci_trb trb;
1526         uint32_t temp;
1527
1528         DPRINTF("\n");
1529
1530         trb.qwTrb0 = 0;
1531         trb.dwTrb2 = 0;
1532         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1533             XHCI_TRB_3_SLOT_SET(slot_id);
1534
1535         trb.dwTrb3 = htole32(temp);
1536
1537         return (xhci_do_command(sc, &trb, 100 /* ms */));
1538 }
1539
1540 /*------------------------------------------------------------------------*
1541  *      xhci_interrupt - XHCI interrupt handler
1542  *------------------------------------------------------------------------*/
1543 void
1544 xhci_interrupt(struct xhci_softc *sc)
1545 {
1546         uint32_t status;
1547
1548         USB_BUS_LOCK(&sc->sc_bus);
1549
1550         status = XREAD4(sc, oper, XHCI_USBSTS);
1551         if (status == 0)
1552                 goto done;
1553
1554         /* acknowledge interrupts */
1555
1556         XWRITE4(sc, oper, XHCI_USBSTS, status);
1557
1558         DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1559
1560         if (status & XHCI_STS_EINT) {
1561                 /* check for event(s) */
1562                 xhci_interrupt_poll(sc);
1563         }
1564
1565         if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1566             XHCI_STS_HSE | XHCI_STS_HCE)) {
1567
1568                 if (status & XHCI_STS_PCD) {
1569                         xhci_root_intr(sc);
1570                 }
1571
1572                 if (status & XHCI_STS_HCH) {
1573                         printf("%s: host controller halted\n",
1574                             __FUNCTION__);
1575                 }
1576
1577                 if (status & XHCI_STS_HSE) {
1578                         printf("%s: host system error\n",
1579                             __FUNCTION__);
1580                 }
1581
1582                 if (status & XHCI_STS_HCE) {
1583                         printf("%s: host controller error\n",
1584                            __FUNCTION__);
1585                 }
1586         }
1587 done:
1588         USB_BUS_UNLOCK(&sc->sc_bus);
1589 }
1590
1591 /*------------------------------------------------------------------------*
1592  *      xhci_timeout - XHCI timeout handler
1593  *------------------------------------------------------------------------*/
1594 static void
1595 xhci_timeout(void *arg)
1596 {
1597         struct usb_xfer *xfer = arg;
1598
1599         DPRINTF("xfer=%p\n", xfer);
1600
1601         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1602
1603         /* transfer is transferred */
1604         xhci_device_done(xfer, USB_ERR_TIMEOUT);
1605 }
1606
1607 static void
1608 xhci_do_poll(struct usb_bus *bus)
1609 {
1610         struct xhci_softc *sc = XHCI_BUS2SC(bus);
1611
1612         USB_BUS_LOCK(&sc->sc_bus);
1613         xhci_interrupt_poll(sc);
1614         USB_BUS_UNLOCK(&sc->sc_bus);
1615 }
1616
1617 static void
1618 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1619 {
1620         struct usb_page_search buf_res;
1621         struct xhci_td *td;
1622         struct xhci_td *td_next;
1623         struct xhci_td *td_alt_next;
1624         struct xhci_td *td_first;
1625         uint32_t buf_offset;
1626         uint32_t average;
1627         uint32_t len_old;
1628         uint32_t npkt_off;
1629         uint32_t dword;
1630         uint8_t shortpkt_old;
1631         uint8_t precompute;
1632         uint8_t x;
1633
1634         td_alt_next = NULL;
1635         buf_offset = 0;
1636         shortpkt_old = temp->shortpkt;
1637         len_old = temp->len;
1638         npkt_off = 0;
1639         precompute = 1;
1640
1641 restart:
1642
1643         td = temp->td;
1644         td_next = td_first = temp->td_next;
1645
1646         while (1) {
1647
1648                 if (temp->len == 0) {
1649
1650                         if (temp->shortpkt)
1651                                 break;
1652
1653                         /* send a Zero Length Packet, ZLP, last */
1654
1655                         temp->shortpkt = 1;
1656                         average = 0;
1657
1658                 } else {
1659
1660                         average = temp->average;
1661
1662                         if (temp->len < average) {
1663                                 if (temp->len % temp->max_packet_size) {
1664                                         temp->shortpkt = 1;
1665                                 }
1666                                 average = temp->len;
1667                         }
1668                 }
1669
1670                 if (td_next == NULL)
1671                         panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1672
1673                 /* get next TD */
1674
1675                 td = td_next;
1676                 td_next = td->obj_next;
1677
1678                 /* check if we are pre-computing */
1679
1680                 if (precompute) {
1681
1682                         /* update remaining length */
1683
1684                         temp->len -= average;
1685
1686                         continue;
1687                 }
1688                 /* fill out current TD */
1689
1690                 td->len = average;
1691                 td->remainder = 0;
1692                 td->status = 0;
1693
1694                 /* update remaining length */
1695
1696                 temp->len -= average;
1697
1698                 /* reset TRB index */
1699
1700                 x = 0;
1701
1702                 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1703                         /* immediate data */
1704
1705                         if (average > 8)
1706                                 average = 8;
1707
1708                         td->td_trb[0].qwTrb0 = 0;
1709
1710                         usbd_copy_out(temp->pc, temp->offset + buf_offset,
1711                            (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1712                            average);
1713
1714                         dword = XHCI_TRB_2_BYTES_SET(8) |
1715                             XHCI_TRB_2_TDSZ_SET(0) |
1716                             XHCI_TRB_2_IRQ_SET(0);
1717
1718                         td->td_trb[0].dwTrb2 = htole32(dword);
1719
1720                         dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1721                           XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1722
1723                         /* check wLength */
1724                         if (td->td_trb[0].qwTrb0 &
1725                            htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1726                                 if (td->td_trb[0].qwTrb0 & htole64(1))
1727                                         dword |= XHCI_TRB_3_TRT_IN;
1728                                 else
1729                                         dword |= XHCI_TRB_3_TRT_OUT;
1730                         }
1731
1732                         td->td_trb[0].dwTrb3 = htole32(dword);
1733 #ifdef USB_DEBUG
1734                         xhci_dump_trb(&td->td_trb[x]);
1735 #endif
1736                         x++;
1737
1738                 } else do {
1739
1740                         uint32_t npkt;
1741
1742                         /* fill out buffer pointers */
1743
1744                         if (average == 0) {
1745                                 memset(&buf_res, 0, sizeof(buf_res));
1746                         } else {
1747                                 usbd_get_page(temp->pc, temp->offset +
1748                                     buf_offset, &buf_res);
1749
1750                                 /* get length to end of page */
1751                                 if (buf_res.length > average)
1752                                         buf_res.length = average;
1753
1754                                 /* check for maximum length */
1755                                 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1756                                         buf_res.length = XHCI_TD_PAGE_SIZE;
1757
1758                                 npkt_off += buf_res.length;
1759                         }
1760
1761                         /* setup npkt */
1762                         npkt = (len_old - npkt_off + temp->max_packet_size - 1) /
1763                             temp->max_packet_size;
1764
1765                         if (npkt == 0)
1766                                 npkt = 1;
1767                         else if (npkt > 31)
1768                                 npkt = 31;
1769
1770                         /* fill out TRB's */
1771                         td->td_trb[x].qwTrb0 =
1772                             htole64((uint64_t)buf_res.physaddr);
1773
1774                         dword =
1775                           XHCI_TRB_2_BYTES_SET(buf_res.length) |
1776                           XHCI_TRB_2_TDSZ_SET(npkt) |
1777                           XHCI_TRB_2_IRQ_SET(0);
1778
1779                         td->td_trb[x].dwTrb2 = htole32(dword);
1780
1781                         switch (temp->trb_type) {
1782                         case XHCI_TRB_TYPE_ISOCH:
1783                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1784                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1785                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1786                                 if (td != td_first) {
1787                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1788                                 } else if (temp->do_isoc_sync != 0) {
1789                                         temp->do_isoc_sync = 0;
1790                                         /* wait until "isoc_frame" */
1791                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1792                                             XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1793                                 } else {
1794                                         /* start data transfer at next interval */
1795                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1796                                             XHCI_TRB_3_ISO_SIA_BIT;
1797                                 }
1798                                 if (temp->direction == UE_DIR_IN)
1799                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1800                                 break;
1801                         case XHCI_TRB_TYPE_DATA_STAGE:
1802                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1803                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) |
1804                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1805                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1806                                 if (temp->direction == UE_DIR_IN)
1807                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1808                                 break;
1809                         case XHCI_TRB_TYPE_STATUS_STAGE:
1810                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1811                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) |
1812                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1813                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1814                                 if (temp->direction == UE_DIR_IN)
1815                                         dword |= XHCI_TRB_3_DIR_IN;
1816                                 break;
1817                         default:        /* XHCI_TRB_TYPE_NORMAL */
1818                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1819                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) |
1820                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1821                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1822                                 if (temp->direction == UE_DIR_IN)
1823                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1824                                 break;
1825                         }
1826                         td->td_trb[x].dwTrb3 = htole32(dword);
1827
1828                         average -= buf_res.length;
1829                         buf_offset += buf_res.length;
1830 #ifdef USB_DEBUG
1831                         xhci_dump_trb(&td->td_trb[x]);
1832 #endif
1833                         x++;
1834
1835                 } while (average != 0);
1836
1837                 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1838
1839                 /* store number of data TRB's */
1840
1841                 td->ntrb = x;
1842
1843                 DPRINTF("NTRB=%u\n", x);
1844
1845                 /* fill out link TRB */
1846
1847                 if (td_next != NULL) {
1848                         /* link the current TD with the next one */
1849                         td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1850                         DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1851                 } else {
1852                         /* this field will get updated later */
1853                         DPRINTF("NOLINK\n");
1854                 }
1855
1856                 dword = XHCI_TRB_2_IRQ_SET(0);
1857
1858                 td->td_trb[x].dwTrb2 = htole32(dword);
1859
1860                 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1861                     XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1862                     /*
1863                      * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1864                      * frame only receives a single short packet event
1865                      * by setting the CHAIN bit in the LINK field. In
1866                      * addition some XHCI controllers have problems
1867                      * sending a ZLP unless the CHAIN-BIT is set in
1868                      * the LINK TRB.
1869                      */
1870                     XHCI_TRB_3_CHAIN_BIT;
1871
1872                 td->td_trb[x].dwTrb3 = htole32(dword);
1873
1874                 td->alt_next = td_alt_next;
1875 #ifdef USB_DEBUG
1876                 xhci_dump_trb(&td->td_trb[x]);
1877 #endif
1878                 usb_pc_cpu_flush(td->page_cache);
1879         }
1880
1881         if (precompute) {
1882                 precompute = 0;
1883
1884                 /* setup alt next pointer, if any */
1885                 if (temp->last_frame) {
1886                         td_alt_next = NULL;
1887                 } else {
1888                         /* we use this field internally */
1889                         td_alt_next = td_next;
1890                 }
1891
1892                 /* restore */
1893                 temp->shortpkt = shortpkt_old;
1894                 temp->len = len_old;
1895                 goto restart;
1896         }
1897
1898         /*
1899          * Remove cycle bit from the first TRB if we are
1900          * stepping them:
1901          */
1902         if (temp->step_td != 0) {
1903                 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1904                 usb_pc_cpu_flush(td_first->page_cache);
1905         }
1906
1907         /* clear TD SIZE to zero, hence this is the last TRB */
1908         /* remove chain bit because this is the last data TRB in the chain */
1909         td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1910         td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1911         /* remove CHAIN-BIT from last LINK TRB */
1912         td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1913
1914         usb_pc_cpu_flush(td->page_cache);
1915
1916         temp->td = td;
1917         temp->td_next = td_next;
1918 }
1919
1920 static void
1921 xhci_setup_generic_chain(struct usb_xfer *xfer)
1922 {
1923         struct xhci_std_temp temp;
1924         struct xhci_td *td;
1925         uint32_t x;
1926         uint32_t y;
1927         uint8_t mult;
1928
1929         temp.do_isoc_sync = 0;
1930         temp.step_td = 0;
1931         temp.tbc = 0;
1932         temp.tlbpc = 0;
1933         temp.average = xfer->max_hc_frame_size;
1934         temp.max_packet_size = xfer->max_packet_size;
1935         temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
1936         temp.pc = NULL;
1937         temp.last_frame = 0;
1938         temp.offset = 0;
1939         temp.multishort = xfer->flags_int.isochronous_xfr ||
1940             xfer->flags_int.control_xfr ||
1941             xfer->flags_int.short_frames_ok;
1942
1943         /* toggle the DMA set we are using */
1944         xfer->flags_int.curr_dma_set ^= 1;
1945
1946         /* get next DMA set */
1947         td = xfer->td_start[xfer->flags_int.curr_dma_set];
1948
1949         temp.td = NULL;
1950         temp.td_next = td;
1951
1952         xfer->td_transfer_first = td;
1953         xfer->td_transfer_cache = td;
1954
1955         if (xfer->flags_int.isochronous_xfr) {
1956                 uint8_t shift;
1957
1958                 /* compute multiplier for ISOCHRONOUS transfers */
1959                 mult = xfer->endpoint->ecomp ?
1960                     (xfer->endpoint->ecomp->bmAttributes & 3) : 0;
1961                 /* check for USB 2.0 multiplier */
1962                 if (mult == 0) {
1963                         mult = (xfer->endpoint->edesc->
1964                             wMaxPacketSize[1] >> 3) & 3;
1965                 }
1966                 /* range check */
1967                 if (mult > 2)
1968                         mult = 3;
1969                 else
1970                         mult++;
1971
1972                 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
1973
1974                 DPRINTF("MFINDEX=0x%08x\n", x);
1975
1976                 switch (usbd_get_speed(xfer->xroot->udev)) {
1977                 case USB_SPEED_FULL:
1978                         shift = 3;
1979                         temp.isoc_delta = 8;    /* 1ms */
1980                         x += temp.isoc_delta - 1;
1981                         x &= ~(temp.isoc_delta - 1);
1982                         break;
1983                 default:
1984                         shift = usbd_xfer_get_fps_shift(xfer);
1985                         temp.isoc_delta = 1U << shift;
1986                         x += temp.isoc_delta - 1;
1987                         x &= ~(temp.isoc_delta - 1);
1988                         /* simple frame load balancing */
1989                         x += xfer->endpoint->usb_uframe;
1990                         break;
1991                 }
1992
1993                 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
1994
1995                 if ((xfer->endpoint->is_synced == 0) ||
1996                     (y < (xfer->nframes << shift)) ||
1997                     (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
1998                         /*
1999                          * If there is data underflow or the pipe
2000                          * queue is empty we schedule the transfer a
2001                          * few frames ahead of the current frame
2002                          * position. Else two isochronous transfers
2003                          * might overlap.
2004                          */
2005                         xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2006                         xfer->endpoint->is_synced = 1;
2007                         temp.do_isoc_sync = 1;
2008
2009                         DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2010                 }
2011
2012                 /* compute isochronous completion time */
2013
2014                 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2015
2016                 xfer->isoc_time_complete =
2017                     usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2018                     (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2019
2020                 x = 0;
2021                 temp.isoc_frame = xfer->endpoint->isoc_next;
2022                 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2023
2024                 xfer->endpoint->isoc_next += xfer->nframes << shift;
2025
2026         } else if (xfer->flags_int.control_xfr) {
2027
2028                 /* check if we should prepend a setup message */
2029
2030                 if (xfer->flags_int.control_hdr) {
2031
2032                         temp.len = xfer->frlengths[0];
2033                         temp.pc = xfer->frbuffers + 0;
2034                         temp.shortpkt = temp.len ? 1 : 0;
2035                         temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2036                         temp.direction = 0;
2037
2038                         /* check for last frame */
2039                         if (xfer->nframes == 1) {
2040                                 /* no STATUS stage yet, SETUP is last */
2041                                 if (xfer->flags_int.control_act)
2042                                         temp.last_frame = 1;
2043                         }
2044
2045                         xhci_setup_generic_chain_sub(&temp);
2046                 }
2047                 x = 1;
2048                 mult = 1;
2049                 temp.isoc_delta = 0;
2050                 temp.isoc_frame = 0;
2051                 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE;
2052         } else {
2053                 x = 0;
2054                 mult = 1;
2055                 temp.isoc_delta = 0;
2056                 temp.isoc_frame = 0;
2057                 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2058         }
2059
2060         if (x != xfer->nframes) {
2061                 /* setup page_cache pointer */
2062                 temp.pc = xfer->frbuffers + x;
2063                 /* set endpoint direction */
2064                 temp.direction = UE_GET_DIR(xfer->endpointno);
2065         }
2066
2067         while (x != xfer->nframes) {
2068
2069                 /* DATA0 / DATA1 message */
2070
2071                 temp.len = xfer->frlengths[x];
2072                 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2073                     x != 0 && temp.multishort == 0);
2074
2075                 x++;
2076
2077                 if (x == xfer->nframes) {
2078                         if (xfer->flags_int.control_xfr) {
2079                                 /* no STATUS stage yet, DATA is last */
2080                                 if (xfer->flags_int.control_act)
2081                                         temp.last_frame = 1;
2082                         } else {
2083                                 temp.last_frame = 1;
2084                         }
2085                 }
2086                 if (temp.len == 0) {
2087
2088                         /* make sure that we send an USB packet */
2089
2090                         temp.shortpkt = 0;
2091
2092                         temp.tbc = 0;
2093                         temp.tlbpc = mult - 1;
2094
2095                 } else if (xfer->flags_int.isochronous_xfr) {
2096
2097                         uint8_t tdpc;
2098
2099                         /*
2100                          * Isochronous transfers don't have short
2101                          * packet termination:
2102                          */
2103
2104                         temp.shortpkt = 1;
2105
2106                         /* isochronous transfers have a transfer limit */
2107
2108                         if (temp.len > xfer->max_frame_size)
2109                                 temp.len = xfer->max_frame_size;
2110
2111                         /* compute TD packet count */
2112                         tdpc = (temp.len + xfer->max_packet_size - 1) /
2113                             xfer->max_packet_size;
2114
2115                         temp.tbc = ((tdpc + mult - 1) / mult) - 1;
2116                         temp.tlbpc = (tdpc % mult);
2117
2118                         if (temp.tlbpc == 0)
2119                                 temp.tlbpc = mult - 1;
2120                         else
2121                                 temp.tlbpc--;
2122                 } else {
2123
2124                         /* regular data transfer */
2125
2126                         temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2127                 }
2128
2129                 xhci_setup_generic_chain_sub(&temp);
2130
2131                 if (xfer->flags_int.isochronous_xfr) {
2132                         temp.offset += xfer->frlengths[x - 1];
2133                         temp.isoc_frame += temp.isoc_delta;
2134                 } else {
2135                         /* get next Page Cache pointer */
2136                         temp.pc = xfer->frbuffers + x;
2137                 }
2138         }
2139
2140         /* check if we should append a status stage */
2141
2142         if (xfer->flags_int.control_xfr &&
2143             !xfer->flags_int.control_act) {
2144
2145                 /*
2146                  * Send a DATA1 message and invert the current
2147                  * endpoint direction.
2148                  */
2149                 temp.step_td = (xfer->nframes != 0);
2150                 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2151                 temp.len = 0;
2152                 temp.pc = NULL;
2153                 temp.shortpkt = 0;
2154                 temp.last_frame = 1;
2155                 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2156
2157                 xhci_setup_generic_chain_sub(&temp);
2158         }
2159
2160         td = temp.td;
2161
2162         /* must have at least one frame! */
2163
2164         xfer->td_transfer_last = td;
2165
2166         DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2167 }
2168
2169 static void
2170 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2171 {
2172         struct usb_page_search buf_res;
2173         struct xhci_dev_ctx_addr *pdctxa;
2174
2175         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2176
2177         pdctxa = buf_res.buffer;
2178
2179         DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2180
2181         pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2182
2183         usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2184 }
2185
2186 static usb_error_t
2187 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2188 {
2189         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2190         struct usb_page_search buf_inp;
2191         struct xhci_input_dev_ctx *pinp;
2192         uint32_t temp;
2193         uint8_t index;
2194         uint8_t x;
2195
2196         index = udev->controller_slot_id;
2197
2198         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2199
2200         pinp = buf_inp.buffer;
2201
2202         if (drop) {
2203                 mask &= XHCI_INCTX_NON_CTRL_MASK;
2204                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2205                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2206         } else {
2207                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0);
2208                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2209
2210                 /* find most significant set bit */
2211                 for (x = 31; x != 1; x--) {
2212                         if (mask & (1 << x))
2213                                 break;
2214                 }
2215
2216                 /* adjust */
2217                 x--;
2218
2219                 /* figure out maximum */
2220                 if (x > sc->sc_hw.devs[index].context_num) {
2221                         sc->sc_hw.devs[index].context_num = x;
2222                         temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2223                         temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2224                         temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2225                         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2226                 }
2227         }
2228         return (0);
2229 }
2230
2231 static usb_error_t
2232 xhci_configure_endpoint(struct usb_device *udev,
2233     struct usb_endpoint_descriptor *edesc, uint64_t ring_addr,
2234     uint16_t interval, uint8_t max_packet_count, uint8_t mult,
2235     uint8_t fps_shift, uint16_t max_packet_size, uint16_t max_frame_size)
2236 {
2237         struct usb_page_search buf_inp;
2238         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2239         struct xhci_input_dev_ctx *pinp;
2240         uint32_t temp;
2241         uint8_t index;
2242         uint8_t epno;
2243         uint8_t type;
2244
2245         index = udev->controller_slot_id;
2246
2247         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2248
2249         pinp = buf_inp.buffer;
2250
2251         epno = edesc->bEndpointAddress;
2252         type = edesc->bmAttributes & UE_XFERTYPE;
2253
2254         if (type == UE_CONTROL)
2255                 epno |= UE_DIR_IN;
2256
2257         epno = XHCI_EPNO2EPID(epno);
2258
2259         if (epno == 0)
2260                 return (USB_ERR_NO_PIPE);               /* invalid */
2261
2262         if (max_packet_count == 0)
2263                 return (USB_ERR_BAD_BUFSIZE);
2264
2265         max_packet_count--;
2266
2267         if (mult == 0)
2268                 return (USB_ERR_BAD_BUFSIZE);
2269
2270         temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2271             XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2272             XHCI_EPCTX_0_LSA_SET(0);
2273
2274         switch (udev->speed) {
2275         case USB_SPEED_FULL:
2276         case USB_SPEED_LOW:
2277                 /* 1ms -> 125us */
2278                 fps_shift += 3;
2279                 break;
2280         default:
2281                 break;
2282         }
2283
2284         switch (type) {
2285         case UE_INTERRUPT:
2286                 if (fps_shift > 3)
2287                         fps_shift--;
2288                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2289                 break;
2290         case UE_ISOCHRONOUS:
2291                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2292
2293                 switch (udev->speed) {
2294                 case USB_SPEED_SUPER:
2295                         if (mult > 3)
2296                                 mult = 3;
2297                         temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2298                         max_packet_count /= mult;
2299                         break;
2300                 default:
2301                         break;
2302                 }
2303                 break;
2304         default:
2305                 break;
2306         }
2307
2308         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2309
2310         temp =
2311             XHCI_EPCTX_1_HID_SET(0) |
2312             XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2313             XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2314
2315         if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) {
2316                 if (type != UE_ISOCHRONOUS)
2317                         temp |= XHCI_EPCTX_1_CERR_SET(3);
2318         }
2319
2320         switch (type) {
2321         case UE_CONTROL:
2322                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2323                 break;
2324         case UE_ISOCHRONOUS:
2325                 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2326                 break;
2327         case UE_BULK:
2328                 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2329                 break;
2330         default:
2331                 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2332                 break;
2333         }
2334
2335         /* check for IN direction */
2336         if (epno & 1)
2337                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2338
2339         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2340
2341         ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2342
2343         xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2344
2345         switch (edesc->bmAttributes & UE_XFERTYPE) {
2346         case UE_INTERRUPT:
2347         case UE_ISOCHRONOUS:
2348                 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2349                     XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2350                     max_frame_size));
2351                 break;
2352         case UE_CONTROL:
2353                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2354                 break;
2355         default:
2356                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2357                 break;
2358         }
2359
2360         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2361
2362 #ifdef USB_DEBUG
2363         xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2364 #endif
2365         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2366
2367         return (0);             /* success */
2368 }
2369
2370 static usb_error_t
2371 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2372 {
2373         struct xhci_endpoint_ext *pepext;
2374         struct usb_endpoint_ss_comp_descriptor *ecomp;
2375
2376         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2377             xfer->endpoint->edesc);
2378
2379         ecomp = xfer->endpoint->ecomp;
2380
2381         pepext->trb[0].dwTrb3 = 0;      /* halt any transfers */
2382         usb_pc_cpu_flush(pepext->page_cache);
2383
2384         return (xhci_configure_endpoint(xfer->xroot->udev,
2385             xfer->endpoint->edesc, pepext->physaddr,
2386             xfer->interval, xfer->max_packet_count,
2387             (ecomp != NULL) ? (ecomp->bmAttributes & 3) + 1 : 1,
2388             usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2389             xfer->max_frame_size));
2390 }
2391
2392 static usb_error_t
2393 xhci_configure_device(struct usb_device *udev)
2394 {
2395         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2396         struct usb_page_search buf_inp;
2397         struct usb_page_cache *pcinp;
2398         struct xhci_input_dev_ctx *pinp;
2399         struct usb_device *hubdev;
2400         uint32_t temp;
2401         uint32_t route;
2402         uint32_t rh_port;
2403         uint8_t is_hub;
2404         uint8_t index;
2405         uint8_t depth;
2406
2407         index = udev->controller_slot_id;
2408
2409         DPRINTF("index=%u\n", index);
2410
2411         pcinp = &sc->sc_hw.devs[index].input_pc;
2412
2413         usbd_get_page(pcinp, 0, &buf_inp);
2414
2415         pinp = buf_inp.buffer;
2416
2417         rh_port = 0;
2418         route = 0;
2419
2420         /* figure out route string and root HUB port number */
2421
2422         for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2423
2424                 if (hubdev->parent_hub == NULL)
2425                         break;
2426
2427                 depth = hubdev->parent_hub->depth;
2428
2429                 /*
2430                  * NOTE: HS/FS/LS devices and the SS root HUB can have
2431                  * more than 15 ports
2432                  */
2433
2434                 rh_port = hubdev->port_no;
2435
2436                 if (depth == 0)
2437                         break;
2438
2439                 if (rh_port > 15)
2440                         rh_port = 15;
2441
2442                 if (depth < 6)
2443                         route |= rh_port << (4 * (depth - 1));
2444         }
2445
2446         DPRINTF("Route=0x%08x\n", route);
2447
2448         temp = XHCI_SCTX_0_ROUTE_SET(route) |
2449             XHCI_SCTX_0_CTX_NUM_SET(
2450             sc->sc_hw.devs[index].context_num + 1);
2451
2452         switch (udev->speed) {
2453         case USB_SPEED_LOW:
2454                 temp |= XHCI_SCTX_0_SPEED_SET(2);
2455                 if (udev->parent_hs_hub != NULL &&
2456                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2457                     UDPROTO_HSHUBMTT) {
2458                         DPRINTF("Device inherits MTT\n");
2459                         temp |= XHCI_SCTX_0_MTT_SET(1);
2460                 }
2461                 break;
2462         case USB_SPEED_HIGH:
2463                 temp |= XHCI_SCTX_0_SPEED_SET(3);
2464                 if (sc->sc_hw.devs[index].nports != 0 &&
2465                     udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2466                         DPRINTF("HUB supports MTT\n");
2467                         temp |= XHCI_SCTX_0_MTT_SET(1);
2468                 }
2469                 break;
2470         case USB_SPEED_FULL:
2471                 temp |= XHCI_SCTX_0_SPEED_SET(1);
2472                 if (udev->parent_hs_hub != NULL &&
2473                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2474                     UDPROTO_HSHUBMTT) {
2475                         DPRINTF("Device inherits MTT\n");
2476                         temp |= XHCI_SCTX_0_MTT_SET(1);
2477                 }
2478                 break;
2479         default:
2480                 temp |= XHCI_SCTX_0_SPEED_SET(4);
2481                 break;
2482         }
2483
2484         is_hub = sc->sc_hw.devs[index].nports != 0 &&
2485             (udev->speed == USB_SPEED_SUPER ||
2486             udev->speed == USB_SPEED_HIGH);
2487
2488         if (is_hub)
2489                 temp |= XHCI_SCTX_0_HUB_SET(1);
2490
2491         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2492
2493         temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2494
2495         if (is_hub) {
2496                 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2497                     sc->sc_hw.devs[index].nports);
2498         }
2499
2500         switch (udev->speed) {
2501         case USB_SPEED_SUPER:
2502                 switch (sc->sc_hw.devs[index].state) {
2503                 case XHCI_ST_ADDRESSED:
2504                 case XHCI_ST_CONFIGURED:
2505                         /* enable power save */
2506                         temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2507                         break;
2508                 default:
2509                         /* disable power save */
2510                         break;
2511                 }
2512                 break;
2513         default:
2514                 break;
2515         }
2516
2517         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2518
2519         temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2520
2521         if (is_hub) {
2522                 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2523                     sc->sc_hw.devs[index].tt);
2524         }
2525
2526         hubdev = udev->parent_hs_hub;
2527
2528         /* check if we should activate the transaction translator */
2529         switch (udev->speed) {
2530         case USB_SPEED_FULL:
2531         case USB_SPEED_LOW:
2532                 if (hubdev != NULL) {
2533                         temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2534                             hubdev->controller_slot_id);
2535                         temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2536                             udev->hs_port_no);
2537                 }
2538                 break;
2539         default:
2540                 break;
2541         }
2542
2543         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2544
2545         temp = XHCI_SCTX_3_DEV_ADDR_SET(udev->address) |
2546             XHCI_SCTX_3_SLOT_STATE_SET(0);
2547
2548         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2549
2550 #ifdef USB_DEBUG
2551         xhci_dump_device(sc, &pinp->ctx_slot);
2552 #endif
2553         usb_pc_cpu_flush(pcinp);
2554
2555         return (0);             /* success */
2556 }
2557
2558 static usb_error_t
2559 xhci_alloc_device_ext(struct usb_device *udev)
2560 {
2561         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2562         struct usb_page_search buf_dev;
2563         struct usb_page_search buf_ep;
2564         struct xhci_trb *trb;
2565         struct usb_page_cache *pc;
2566         struct usb_page *pg;
2567         uint64_t addr;
2568         uint8_t index;
2569         uint8_t i;
2570
2571         index = udev->controller_slot_id;
2572
2573         pc = &sc->sc_hw.devs[index].device_pc;
2574         pg = &sc->sc_hw.devs[index].device_pg;
2575
2576         /* need to initialize the page cache */
2577         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2578
2579         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2580             (2 * sizeof(struct xhci_dev_ctx)) :
2581             sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2582                 goto error;
2583
2584         usbd_get_page(pc, 0, &buf_dev);
2585
2586         pc = &sc->sc_hw.devs[index].input_pc;
2587         pg = &sc->sc_hw.devs[index].input_pg;
2588
2589         /* need to initialize the page cache */
2590         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2591
2592         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2593             (2 * sizeof(struct xhci_input_dev_ctx)) :
2594             sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2595                 goto error;
2596         }
2597
2598         pc = &sc->sc_hw.devs[index].endpoint_pc;
2599         pg = &sc->sc_hw.devs[index].endpoint_pg;
2600
2601         /* need to initialize the page cache */
2602         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2603
2604         if (usb_pc_alloc_mem(pc, pg,
2605             sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) {
2606                 goto error;
2607         }
2608
2609         /* initialise all endpoint LINK TRBs */
2610
2611         for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2612
2613                 /* lookup endpoint TRB ring */
2614                 usbd_get_page(pc, (uintptr_t)&
2615                     ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep);
2616
2617                 /* get TRB pointer */
2618                 trb = buf_ep.buffer;
2619                 trb += XHCI_MAX_TRANSFERS - 1;
2620
2621                 /* get TRB start address */
2622                 addr = buf_ep.physaddr;
2623
2624                 /* create LINK TRB */
2625                 trb->qwTrb0 = htole64(addr);
2626                 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2627                 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2628                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2629         }
2630
2631         usb_pc_cpu_flush(pc);
2632
2633         xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2634
2635         return (0);
2636
2637 error:
2638         xhci_free_device_ext(udev);
2639
2640         return (USB_ERR_NOMEM);
2641 }
2642
2643 static void
2644 xhci_free_device_ext(struct usb_device *udev)
2645 {
2646         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2647         uint8_t index;
2648
2649         index = udev->controller_slot_id;
2650         xhci_set_slot_pointer(sc, index, 0);
2651
2652         usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2653         usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2654         usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc);
2655 }
2656
2657 static struct xhci_endpoint_ext *
2658 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2659 {
2660         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2661         struct xhci_endpoint_ext *pepext;
2662         struct usb_page_cache *pc;
2663         struct usb_page_search buf_ep;
2664         uint8_t epno;
2665         uint8_t index;
2666
2667         epno = edesc->bEndpointAddress;
2668         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2669                 epno |= UE_DIR_IN;
2670
2671         epno = XHCI_EPNO2EPID(epno);
2672
2673         index = udev->controller_slot_id;
2674
2675         pc = &sc->sc_hw.devs[index].endpoint_pc;
2676
2677         usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->trb[epno][0], &buf_ep);
2678
2679         pepext = &sc->sc_hw.devs[index].endp[epno];
2680         pepext->page_cache = pc;
2681         pepext->trb = buf_ep.buffer;
2682         pepext->physaddr = buf_ep.physaddr;
2683
2684         return (pepext);
2685 }
2686
2687 static void
2688 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2689 {
2690         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2691         uint8_t epno;
2692         uint8_t index;
2693
2694         epno = xfer->endpointno;
2695         if (xfer->flags_int.control_xfr)
2696                 epno |= UE_DIR_IN;
2697
2698         epno = XHCI_EPNO2EPID(epno);
2699         index = xfer->xroot->udev->controller_slot_id;
2700
2701         if (xfer->xroot->udev->flags.self_suspended == 0) {
2702                 XWRITE4(sc, door, XHCI_DOORBELL(index),
2703                     epno | XHCI_DB_SID_SET(/*xfer->stream_id*/ 0));
2704         }
2705 }
2706
2707 static void
2708 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2709 {
2710         struct xhci_endpoint_ext *pepext;
2711
2712         if (xfer->flags_int.bandwidth_reclaimed) {
2713                 xfer->flags_int.bandwidth_reclaimed = 0;
2714
2715                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2716                     xfer->endpoint->edesc);
2717
2718                 pepext->trb_used--;
2719
2720                 pepext->xfer[xfer->qh_pos] = NULL;
2721
2722                 if (error && pepext->trb_running != 0) {
2723                         pepext->trb_halted = 1;
2724                         pepext->trb_running = 0;
2725                 }
2726         }
2727 }
2728
2729 static usb_error_t
2730 xhci_transfer_insert(struct usb_xfer *xfer)
2731 {
2732         struct xhci_td *td_first;
2733         struct xhci_td *td_last;
2734         struct xhci_trb *trb_link;
2735         struct xhci_endpoint_ext *pepext;
2736         uint64_t addr;
2737         uint8_t i;
2738         uint8_t inext;
2739         uint8_t trb_limit;
2740
2741         DPRINTFN(8, "\n");
2742
2743         /* check if already inserted */
2744         if (xfer->flags_int.bandwidth_reclaimed) {
2745                 DPRINTFN(8, "Already in schedule\n");
2746                 return (0);
2747         }
2748
2749         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2750             xfer->endpoint->edesc);
2751
2752         td_first = xfer->td_transfer_first;
2753         td_last = xfer->td_transfer_last;
2754         addr = pepext->physaddr;
2755
2756         switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2757         case UE_CONTROL:
2758         case UE_INTERRUPT:
2759                 /* single buffered */
2760                 trb_limit = 1;
2761                 break;
2762         default:
2763                 /* multi buffered */
2764                 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2765                 break;
2766         }
2767
2768         if (pepext->trb_used >= trb_limit) {
2769                 DPRINTFN(8, "Too many TDs queued.\n");
2770                 return (USB_ERR_NOMEM);
2771         }
2772
2773         /* check for stopped condition, after putting transfer on interrupt queue */
2774         if (pepext->trb_running == 0) {
2775                 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2776
2777                 DPRINTFN(8, "Not running\n");
2778
2779                 /* start configuration */
2780                 (void)usb_proc_msignal(&sc->sc_config_proc,
2781                     &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2782                 return (0);
2783         }
2784
2785         pepext->trb_used++;
2786
2787         /* get current TRB index */
2788         i = pepext->trb_index;
2789
2790         /* get next TRB index */
2791         inext = (i + 1);
2792
2793         /* the last entry of the ring is a hardcoded link TRB */
2794         if (inext >= (XHCI_MAX_TRANSFERS - 1))
2795                 inext = 0;
2796
2797         /* compute terminating return address */
2798         addr += inext * sizeof(struct xhci_trb);
2799
2800         /* compute link TRB pointer */
2801         trb_link = td_last->td_trb + td_last->ntrb;
2802
2803         /* update next pointer of last link TRB */
2804         trb_link->qwTrb0 = htole64(addr);
2805         trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2806         trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2807             XHCI_TRB_3_CYCLE_BIT |
2808             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2809
2810 #ifdef USB_DEBUG
2811         xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2812 #endif
2813         usb_pc_cpu_flush(td_last->page_cache);
2814
2815         /* write ahead chain end marker */
2816
2817         pepext->trb[inext].qwTrb0 = 0;
2818         pepext->trb[inext].dwTrb2 = 0;
2819         pepext->trb[inext].dwTrb3 = 0;
2820
2821         /* update next pointer of link TRB */
2822
2823         pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2824         pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2825
2826 #ifdef USB_DEBUG
2827         xhci_dump_trb(&pepext->trb[i]);
2828 #endif
2829         usb_pc_cpu_flush(pepext->page_cache);
2830
2831         /* toggle cycle bit which activates the transfer chain */
2832
2833         pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2834             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2835
2836         usb_pc_cpu_flush(pepext->page_cache);
2837
2838         DPRINTF("qh_pos = %u\n", i);
2839
2840         pepext->xfer[i] = xfer;
2841
2842         xfer->qh_pos = i;
2843
2844         xfer->flags_int.bandwidth_reclaimed = 1;
2845
2846         pepext->trb_index = inext;
2847
2848         xhci_endpoint_doorbell(xfer);
2849
2850         return (0);
2851 }
2852
2853 static void
2854 xhci_root_intr(struct xhci_softc *sc)
2855 {
2856         uint16_t i;
2857
2858         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2859
2860         /* clear any old interrupt data */
2861         memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2862
2863         for (i = 1; i <= sc->sc_noport; i++) {
2864                 /* pick out CHANGE bits from the status register */
2865                 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
2866                     XHCI_PS_CSC | XHCI_PS_PEC |
2867                     XHCI_PS_OCC | XHCI_PS_WRC |
2868                     XHCI_PS_PRC | XHCI_PS_PLC |
2869                     XHCI_PS_CEC)) {
2870                         sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2871                         DPRINTF("port %d changed\n", i);
2872                 }
2873         }
2874         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2875             sizeof(sc->sc_hub_idata));
2876 }
2877
2878 /*------------------------------------------------------------------------*
2879  *      xhci_device_done - XHCI done handler
2880  *
2881  * NOTE: This function can be called two times in a row on
2882  * the same USB transfer. From close and from interrupt.
2883  *------------------------------------------------------------------------*/
2884 static void
2885 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
2886 {
2887         DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2888             xfer, xfer->endpoint, error);
2889
2890         /* remove transfer from HW queue */
2891         xhci_transfer_remove(xfer, error);
2892
2893         /* dequeue transfer and start next transfer */
2894         usbd_transfer_done(xfer, error);
2895 }
2896
2897 /*------------------------------------------------------------------------*
2898  * XHCI data transfer support (generic type)
2899  *------------------------------------------------------------------------*/
2900 static void
2901 xhci_device_generic_open(struct usb_xfer *xfer)
2902 {
2903         if (xfer->flags_int.isochronous_xfr) {
2904                 switch (xfer->xroot->udev->speed) {
2905                 case USB_SPEED_FULL:
2906                         break;
2907                 default:
2908                         usb_hs_bandwidth_alloc(xfer);
2909                         break;
2910                 }
2911         }
2912 }
2913
2914 static void
2915 xhci_device_generic_close(struct usb_xfer *xfer)
2916 {
2917         DPRINTF("\n");
2918
2919         xhci_device_done(xfer, USB_ERR_CANCELLED);
2920
2921         if (xfer->flags_int.isochronous_xfr) {
2922                 switch (xfer->xroot->udev->speed) {
2923                 case USB_SPEED_FULL:
2924                         break;
2925                 default:
2926                         usb_hs_bandwidth_free(xfer);
2927                         break;
2928                 }
2929         }
2930 }
2931
2932 static void
2933 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
2934     struct usb_xfer *enter_xfer)
2935 {
2936         struct usb_xfer *xfer;
2937
2938         /* check if there is a current transfer */
2939         xfer = ep->endpoint_q.curr;
2940         if (xfer == NULL)
2941                 return;
2942
2943         /*
2944          * Check if the current transfer is started and then pickup
2945          * the next one, if any. Else wait for next start event due to
2946          * block on failure feature.
2947          */
2948         if (!xfer->flags_int.bandwidth_reclaimed)
2949                 return;
2950
2951         xfer = TAILQ_FIRST(&ep->endpoint_q.head);
2952         if (xfer == NULL) {
2953                 /*
2954                  * In case of enter we have to consider that the
2955                  * transfer is queued by the USB core after the enter
2956                  * method is called.
2957                  */
2958                 xfer = enter_xfer;
2959
2960                 if (xfer == NULL)
2961                         return;
2962         }
2963
2964         /* try to multi buffer */
2965         xhci_transfer_insert(xfer);
2966 }
2967
2968 static void
2969 xhci_device_generic_enter(struct usb_xfer *xfer)
2970 {
2971         DPRINTF("\n");
2972
2973         /* setup TD's and QH */
2974         xhci_setup_generic_chain(xfer);
2975
2976         xhci_device_generic_multi_enter(xfer->endpoint, xfer);
2977 }
2978
2979 static void
2980 xhci_device_generic_start(struct usb_xfer *xfer)
2981 {
2982         DPRINTF("\n");
2983
2984         /* try to insert xfer on HW queue */
2985         xhci_transfer_insert(xfer);
2986
2987         /* try to multi buffer */
2988         xhci_device_generic_multi_enter(xfer->endpoint, NULL);
2989
2990         /* add transfer last on interrupt queue */
2991         usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
2992
2993         /* start timeout, if any */
2994         if (xfer->timeout != 0)
2995                 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
2996 }
2997
2998 struct usb_pipe_methods xhci_device_generic_methods =
2999 {
3000         .open = xhci_device_generic_open,
3001         .close = xhci_device_generic_close,
3002         .enter = xhci_device_generic_enter,
3003         .start = xhci_device_generic_start,
3004 };
3005
3006 /*------------------------------------------------------------------------*
3007  * xhci root HUB support
3008  *------------------------------------------------------------------------*
3009  * Simulate a hardware HUB by handling all the necessary requests.
3010  *------------------------------------------------------------------------*/
3011
3012 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3013
3014 static const
3015 struct usb_device_descriptor xhci_devd =
3016 {
3017         .bLength = sizeof(xhci_devd),
3018         .bDescriptorType = UDESC_DEVICE,        /* type */
3019         HSETW(.bcdUSB, 0x0300),                 /* USB version */
3020         .bDeviceClass = UDCLASS_HUB,            /* class */
3021         .bDeviceSubClass = UDSUBCLASS_HUB,      /* subclass */
3022         .bDeviceProtocol = UDPROTO_SSHUB,       /* protocol */
3023         .bMaxPacketSize = 9,                    /* max packet size */
3024         HSETW(.idVendor, 0x0000),               /* vendor */
3025         HSETW(.idProduct, 0x0000),              /* product */
3026         HSETW(.bcdDevice, 0x0100),              /* device version */
3027         .iManufacturer = 1,
3028         .iProduct = 2,
3029         .iSerialNumber = 0,
3030         .bNumConfigurations = 1,                /* # of configurations */
3031 };
3032
3033 static const
3034 struct xhci_bos_desc xhci_bosd = {
3035         .bosd = {
3036                 .bLength = sizeof(xhci_bosd.bosd),
3037                 .bDescriptorType = UDESC_BOS,
3038                 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3039                 .bNumDeviceCaps = 3,
3040         },
3041         .usb2extd = {
3042                 .bLength = sizeof(xhci_bosd.usb2extd),
3043                 .bDescriptorType = 1,
3044                 .bDevCapabilityType = 2,
3045                 .bmAttributes[0] = 2,
3046         },
3047         .usbdcd = {
3048                 .bLength = sizeof(xhci_bosd.usbdcd),
3049                 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3050                 .bDevCapabilityType = 3,
3051                 .bmAttributes = 0, /* XXX */
3052                 HSETW(.wSpeedsSupported, 0x000C),
3053                 .bFunctionalitySupport = 8,
3054                 .bU1DevExitLat = 255,   /* dummy - not used */
3055                 .wU2DevExitLat = { 0x00, 0x08 },
3056         },
3057         .cidd = {
3058                 .bLength = sizeof(xhci_bosd.cidd),
3059                 .bDescriptorType = 1,
3060                 .bDevCapabilityType = 4,
3061                 .bReserved = 0,
3062                 .bContainerID = 0, /* XXX */
3063         },
3064 };
3065
3066 static const
3067 struct xhci_config_desc xhci_confd = {
3068         .confd = {
3069                 .bLength = sizeof(xhci_confd.confd),
3070                 .bDescriptorType = UDESC_CONFIG,
3071                 .wTotalLength[0] = sizeof(xhci_confd),
3072                 .bNumInterface = 1,
3073                 .bConfigurationValue = 1,
3074                 .iConfiguration = 0,
3075                 .bmAttributes = UC_SELF_POWERED,
3076                 .bMaxPower = 0          /* max power */
3077         },
3078         .ifcd = {
3079                 .bLength = sizeof(xhci_confd.ifcd),
3080                 .bDescriptorType = UDESC_INTERFACE,
3081                 .bNumEndpoints = 1,
3082                 .bInterfaceClass = UICLASS_HUB,
3083                 .bInterfaceSubClass = UISUBCLASS_HUB,
3084                 .bInterfaceProtocol = 0,
3085         },
3086         .endpd = {
3087                 .bLength = sizeof(xhci_confd.endpd),
3088                 .bDescriptorType = UDESC_ENDPOINT,
3089                 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3090                 .bmAttributes = UE_INTERRUPT,
3091                 .wMaxPacketSize[0] = 2,         /* max 15 ports */
3092                 .bInterval = 255,
3093         },
3094         .endpcd = {
3095                 .bLength = sizeof(xhci_confd.endpcd),
3096                 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3097                 .bMaxBurst = 0,
3098                 .bmAttributes = 0,
3099         },
3100 };
3101
3102 static const
3103 struct usb_hub_ss_descriptor xhci_hubd = {
3104         .bLength = sizeof(xhci_hubd),
3105         .bDescriptorType = UDESC_SS_HUB,
3106 };
3107
3108 static usb_error_t
3109 xhci_roothub_exec(struct usb_device *udev,
3110     struct usb_device_request *req, const void **pptr, uint16_t *plength)
3111 {
3112         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3113         const char *str_ptr;
3114         const void *ptr;
3115         uint32_t port;
3116         uint32_t v;
3117         uint16_t len;
3118         uint16_t i;
3119         uint16_t value;
3120         uint16_t index;
3121         uint8_t j;
3122         usb_error_t err;
3123
3124         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3125
3126         /* buffer reset */
3127         ptr = (const void *)&sc->sc_hub_desc;
3128         len = 0;
3129         err = 0;
3130
3131         value = UGETW(req->wValue);
3132         index = UGETW(req->wIndex);
3133
3134         DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3135             "wValue=0x%04x wIndex=0x%04x\n",
3136             req->bmRequestType, req->bRequest,
3137             UGETW(req->wLength), value, index);
3138
3139 #define C(x,y) ((x) | ((y) << 8))
3140         switch (C(req->bRequest, req->bmRequestType)) {
3141         case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3142         case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3143         case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3144                 /*
3145                  * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3146                  * for the integrated root hub.
3147                  */
3148                 break;
3149         case C(UR_GET_CONFIG, UT_READ_DEVICE):
3150                 len = 1;
3151                 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3152                 break;
3153         case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3154                 switch (value >> 8) {
3155                 case UDESC_DEVICE:
3156                         if ((value & 0xff) != 0) {
3157                                 err = USB_ERR_IOERROR;
3158                                 goto done;
3159                         }
3160                         len = sizeof(xhci_devd);
3161                         ptr = (const void *)&xhci_devd;
3162                         break;
3163
3164                 case UDESC_BOS:
3165                         if ((value & 0xff) != 0) {
3166                                 err = USB_ERR_IOERROR;
3167                                 goto done;
3168                         }
3169                         len = sizeof(xhci_bosd);
3170                         ptr = (const void *)&xhci_bosd;
3171                         break;
3172
3173                 case UDESC_CONFIG:
3174                         if ((value & 0xff) != 0) {
3175                                 err = USB_ERR_IOERROR;
3176                                 goto done;
3177                         }
3178                         len = sizeof(xhci_confd);
3179                         ptr = (const void *)&xhci_confd;
3180                         break;
3181
3182                 case UDESC_STRING:
3183                         switch (value & 0xff) {
3184                         case 0: /* Language table */
3185                                 str_ptr = "\001";
3186                                 break;
3187
3188                         case 1: /* Vendor */
3189                                 str_ptr = sc->sc_vendor;
3190                                 break;
3191
3192                         case 2: /* Product */
3193                                 str_ptr = "XHCI root HUB";
3194                                 break;
3195
3196                         default:
3197                                 str_ptr = "";
3198                                 break;
3199                         }
3200
3201                         len = usb_make_str_desc(
3202                             sc->sc_hub_desc.temp,
3203                             sizeof(sc->sc_hub_desc.temp),
3204                             str_ptr);
3205                         break;
3206
3207                 default:
3208                         err = USB_ERR_IOERROR;
3209                         goto done;
3210                 }
3211                 break;
3212         case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3213                 len = 1;
3214                 sc->sc_hub_desc.temp[0] = 0;
3215                 break;
3216         case C(UR_GET_STATUS, UT_READ_DEVICE):
3217                 len = 2;
3218                 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3219                 break;
3220         case C(UR_GET_STATUS, UT_READ_INTERFACE):
3221         case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3222                 len = 2;
3223                 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3224                 break;
3225         case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3226                 if (value >= XHCI_MAX_DEVICES) {
3227                         err = USB_ERR_IOERROR;
3228                         goto done;
3229                 }
3230                 break;
3231         case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3232                 if (value != 0 && value != 1) {
3233                         err = USB_ERR_IOERROR;
3234                         goto done;
3235                 }
3236                 sc->sc_conf = value;
3237                 break;
3238         case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3239                 break;
3240         case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3241         case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3242         case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3243                 err = USB_ERR_IOERROR;
3244                 goto done;
3245         case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3246                 break;
3247         case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3248                 break;
3249                 /* Hub requests */
3250         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3251                 break;
3252         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3253                 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3254
3255                 if ((index < 1) ||
3256                     (index > sc->sc_noport)) {
3257                         err = USB_ERR_IOERROR;
3258                         goto done;
3259                 }
3260                 port = XHCI_PORTSC(index);
3261
3262                 v = XREAD4(sc, oper, port);
3263                 i = XHCI_PS_PLS_GET(v);
3264                 v &= ~XHCI_PS_CLEAR;
3265
3266                 switch (value) {
3267                 case UHF_C_BH_PORT_RESET:
3268                         XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3269                         break;
3270                 case UHF_C_PORT_CONFIG_ERROR:
3271                         XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3272                         break;
3273                 case UHF_C_PORT_SUSPEND:
3274                 case UHF_C_PORT_LINK_STATE:
3275                         XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3276                         break;
3277                 case UHF_C_PORT_CONNECTION:
3278                         XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3279                         break;
3280                 case UHF_C_PORT_ENABLE:
3281                         XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3282                         break;
3283                 case UHF_C_PORT_OVER_CURRENT:
3284                         XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3285                         break;
3286                 case UHF_C_PORT_RESET:
3287                         XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3288                         break;
3289                 case UHF_PORT_ENABLE:
3290                         XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3291                         break;
3292                 case UHF_PORT_POWER:
3293                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3294                         break;
3295                 case UHF_PORT_INDICATOR:
3296                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3297                         break;
3298                 case UHF_PORT_SUSPEND:
3299
3300                         /* U3 -> U15 */
3301                         if (i == 3) {
3302                                 XWRITE4(sc, oper, port, v |
3303                                     XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3304                         }
3305
3306                         /* wait 20ms for resume sequence to complete */
3307                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3308
3309                         /* U0 */
3310                         XWRITE4(sc, oper, port, v |
3311                             XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3312                         break;
3313                 default:
3314                         err = USB_ERR_IOERROR;
3315                         goto done;
3316                 }
3317                 break;
3318
3319         case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3320                 if ((value & 0xff) != 0) {
3321                         err = USB_ERR_IOERROR;
3322                         goto done;
3323                 }
3324
3325                 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3326
3327                 sc->sc_hub_desc.hubd = xhci_hubd;
3328
3329                 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3330
3331                 if (XHCI_HCS0_PPC(v))
3332                         i = UHD_PWR_INDIVIDUAL;
3333                 else
3334                         i = UHD_PWR_GANGED;
3335
3336                 if (XHCI_HCS0_PIND(v))
3337                         i |= UHD_PORT_IND;
3338
3339                 i |= UHD_OC_INDIVIDUAL;
3340
3341                 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3342
3343                 /* see XHCI section 5.4.9: */
3344                 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3345
3346                 for (j = 1; j <= sc->sc_noport; j++) {
3347
3348                         v = XREAD4(sc, oper, XHCI_PORTSC(j));
3349                         if (v & XHCI_PS_DR) {
3350                                 sc->sc_hub_desc.hubd.
3351                                     DeviceRemovable[j / 8] |= 1U << (j % 8);
3352                         }
3353                 }
3354                 len = sc->sc_hub_desc.hubd.bLength;
3355                 break;
3356
3357         case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3358                 len = 16;
3359                 memset(sc->sc_hub_desc.temp, 0, 16);
3360                 break;
3361
3362         case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3363                 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3364
3365                 if ((index < 1) ||
3366                     (index > sc->sc_noport)) {
3367                         err = USB_ERR_IOERROR;
3368                         goto done;
3369                 }
3370
3371                 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3372
3373                 DPRINTFN(9, "port status=0x%08x\n", v);
3374
3375                 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3376
3377                 switch (XHCI_PS_SPEED_GET(v)) {
3378                 case 3:
3379                         i |= UPS_HIGH_SPEED;
3380                         break;
3381                 case 2:
3382                         i |= UPS_LOW_SPEED;
3383                         break;
3384                 case 1:
3385                         /* FULL speed */
3386                         break;
3387                 default:
3388                         i |= UPS_OTHER_SPEED;
3389                         break;
3390                 }
3391
3392                 if (v & XHCI_PS_CCS)
3393                         i |= UPS_CURRENT_CONNECT_STATUS;
3394                 if (v & XHCI_PS_PED)
3395                         i |= UPS_PORT_ENABLED;
3396                 if (v & XHCI_PS_OCA)
3397                         i |= UPS_OVERCURRENT_INDICATOR;
3398                 if (v & XHCI_PS_PR)
3399                         i |= UPS_RESET;
3400                 if (v & XHCI_PS_PP) {
3401                         /*
3402                          * The USB 3.0 RH is using the
3403                          * USB 2.0's power bit
3404                          */
3405                         i |= UPS_PORT_POWER;
3406                 }
3407                 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3408
3409                 i = 0;
3410                 if (v & XHCI_PS_CSC)
3411                         i |= UPS_C_CONNECT_STATUS;
3412                 if (v & XHCI_PS_PEC)
3413                         i |= UPS_C_PORT_ENABLED;
3414                 if (v & XHCI_PS_OCC)
3415                         i |= UPS_C_OVERCURRENT_INDICATOR;
3416                 if (v & XHCI_PS_WRC)
3417                         i |= UPS_C_BH_PORT_RESET;
3418                 if (v & XHCI_PS_PRC)
3419                         i |= UPS_C_PORT_RESET;
3420                 if (v & XHCI_PS_PLC)
3421                         i |= UPS_C_PORT_LINK_STATE;
3422                 if (v & XHCI_PS_CEC)
3423                         i |= UPS_C_PORT_CONFIG_ERROR;
3424
3425                 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3426                 len = sizeof(sc->sc_hub_desc.ps);
3427                 break;
3428
3429         case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3430                 err = USB_ERR_IOERROR;
3431                 goto done;
3432
3433         case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3434                 break;
3435
3436         case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3437
3438                 i = index >> 8;
3439                 index &= 0x00FF;
3440
3441                 if ((index < 1) ||
3442                     (index > sc->sc_noport)) {
3443                         err = USB_ERR_IOERROR;
3444                         goto done;
3445                 }
3446
3447                 port = XHCI_PORTSC(index);
3448                 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3449
3450                 switch (value) {
3451                 case UHF_PORT_U1_TIMEOUT:
3452                         if (XHCI_PS_SPEED_GET(v) != 4) {
3453                                 err = USB_ERR_IOERROR;
3454                                 goto done;
3455                         }
3456                         port = XHCI_PORTPMSC(index);
3457                         v = XREAD4(sc, oper, port);
3458                         v &= ~XHCI_PM3_U1TO_SET(0xFF);
3459                         v |= XHCI_PM3_U1TO_SET(i);
3460                         XWRITE4(sc, oper, port, v);
3461                         break;
3462                 case UHF_PORT_U2_TIMEOUT:
3463                         if (XHCI_PS_SPEED_GET(v) != 4) {
3464                                 err = USB_ERR_IOERROR;
3465                                 goto done;
3466                         }
3467                         port = XHCI_PORTPMSC(index);
3468                         v = XREAD4(sc, oper, port);
3469                         v &= ~XHCI_PM3_U2TO_SET(0xFF);
3470                         v |= XHCI_PM3_U2TO_SET(i);
3471                         XWRITE4(sc, oper, port, v);
3472                         break;
3473                 case UHF_BH_PORT_RESET:
3474                         XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3475                         break;
3476                 case UHF_PORT_LINK_STATE:
3477                         XWRITE4(sc, oper, port, v |
3478                             XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3479                         /* 4ms settle time */
3480                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3481                         break;
3482                 case UHF_PORT_ENABLE:
3483                         DPRINTFN(3, "set port enable %d\n", index);
3484                         break;
3485                 case UHF_PORT_SUSPEND:
3486                         DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3487                         j = XHCI_PS_SPEED_GET(v);
3488                         if ((j < 1) || (j > 3)) {
3489                                 /* non-supported speed */
3490                                 err = USB_ERR_IOERROR;
3491                                 goto done;
3492                         }
3493                         XWRITE4(sc, oper, port, v |
3494                             XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3495                         break;
3496                 case UHF_PORT_RESET:
3497                         DPRINTFN(6, "reset port %d\n", index);
3498                         XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3499                         break;
3500                 case UHF_PORT_POWER:
3501                         DPRINTFN(3, "set port power %d\n", index);
3502                         XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3503                         break;
3504                 case UHF_PORT_TEST:
3505                         DPRINTFN(3, "set port test %d\n", index);
3506                         break;
3507                 case UHF_PORT_INDICATOR:
3508                         DPRINTFN(3, "set port indicator %d\n", index);
3509
3510                         v &= ~XHCI_PS_PIC_SET(3);
3511                         v |= XHCI_PS_PIC_SET(1);
3512
3513                         XWRITE4(sc, oper, port, v);
3514                         break;
3515                 default:
3516                         err = USB_ERR_IOERROR;
3517                         goto done;
3518                 }
3519                 break;
3520
3521         case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3522         case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3523         case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3524         case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3525                 break;
3526         default:
3527                 err = USB_ERR_IOERROR;
3528                 goto done;
3529         }
3530 done:
3531         *plength = len;
3532         *pptr = ptr;
3533         return (err);
3534 }
3535
3536 static void
3537 xhci_xfer_setup(struct usb_setup_params *parm)
3538 {
3539         struct usb_page_search page_info;
3540         struct usb_page_cache *pc;
3541         struct xhci_softc *sc;
3542         struct usb_xfer *xfer;
3543         void *last_obj;
3544         uint32_t ntd;
3545         uint32_t n;
3546
3547         sc = XHCI_BUS2SC(parm->udev->bus);
3548         xfer = parm->curr_xfer;
3549
3550         /*
3551          * The proof for the "ntd" formula is illustrated like this:
3552          *
3553          * +------------------------------------+
3554          * |                                    |
3555          * |         |remainder ->              |
3556          * |   +-----+---+                      |
3557          * |   | xxx | x | frm 0                |
3558          * |   +-----+---++                     |
3559          * |   | xxx | xx | frm 1               |
3560          * |   +-----+----+                     |
3561          * |            ...                     |
3562          * +------------------------------------+
3563          *
3564          * "xxx" means a completely full USB transfer descriptor
3565          *
3566          * "x" and "xx" means a short USB packet
3567          *
3568          * For the remainder of an USB transfer modulo
3569          * "max_data_length" we need two USB transfer descriptors.
3570          * One to transfer the remaining data and one to finalise with
3571          * a zero length packet in case the "force_short_xfer" flag is
3572          * set. We only need two USB transfer descriptors in the case
3573          * where the transfer length of the first one is a factor of
3574          * "max_frame_size". The rest of the needed USB transfer
3575          * descriptors is given by the buffer size divided by the
3576          * maximum data payload.
3577          */
3578         parm->hc_max_packet_size = 0x400;
3579         parm->hc_max_packet_count = 16 * 3;
3580         parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3581
3582         xfer->flags_int.bdma_enable = 1;
3583
3584         usbd_transfer_setup_sub(parm);
3585
3586         if (xfer->flags_int.isochronous_xfr) {
3587                 ntd = ((1 * xfer->nframes)
3588                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3589         } else if (xfer->flags_int.control_xfr) {
3590                 ntd = ((2 * xfer->nframes) + 1  /* STATUS */
3591                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3592         } else {
3593                 ntd = ((2 * xfer->nframes)
3594                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3595         }
3596
3597 alloc_dma_set:
3598
3599         if (parm->err)
3600                 return;
3601
3602         /*
3603          * Allocate queue heads and transfer descriptors
3604          */
3605         last_obj = NULL;
3606
3607         if (usbd_transfer_setup_sub_malloc(
3608             parm, &pc, sizeof(struct xhci_td),
3609             XHCI_TD_ALIGN, ntd)) {
3610                 parm->err = USB_ERR_NOMEM;
3611                 return;
3612         }
3613         if (parm->buf) {
3614                 for (n = 0; n != ntd; n++) {
3615                         struct xhci_td *td;
3616
3617                         usbd_get_page(pc + n, 0, &page_info);
3618
3619                         td = page_info.buffer;
3620
3621                         /* init TD */
3622                         td->td_self = page_info.physaddr;
3623                         td->obj_next = last_obj;
3624                         td->page_cache = pc + n;
3625
3626                         last_obj = td;
3627
3628                         usb_pc_cpu_flush(pc + n);
3629                 }
3630         }
3631         xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3632
3633         if (!xfer->flags_int.curr_dma_set) {
3634                 xfer->flags_int.curr_dma_set = 1;
3635                 goto alloc_dma_set;
3636         }
3637 }
3638
3639 static usb_error_t
3640 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3641 {
3642         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3643         struct usb_page_search buf_inp;
3644         struct usb_device *udev;
3645         struct xhci_endpoint_ext *pepext;
3646         struct usb_endpoint_descriptor *edesc;
3647         struct usb_page_cache *pcinp;
3648         usb_error_t err;
3649         uint8_t index;
3650         uint8_t epno;
3651
3652         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3653             xfer->endpoint->edesc);
3654
3655         udev = xfer->xroot->udev;
3656         index = udev->controller_slot_id;
3657
3658         pcinp = &sc->sc_hw.devs[index].input_pc;
3659
3660         usbd_get_page(pcinp, 0, &buf_inp);
3661
3662         edesc = xfer->endpoint->edesc;
3663
3664         epno = edesc->bEndpointAddress;
3665
3666         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3667                 epno |= UE_DIR_IN;
3668
3669         epno = XHCI_EPNO2EPID(epno);
3670
3671         if (epno == 0)
3672                 return (USB_ERR_NO_PIPE);               /* invalid */
3673
3674         XHCI_CMD_LOCK(sc);
3675
3676         /* configure endpoint */
3677
3678         err = xhci_configure_endpoint_by_xfer(xfer);
3679
3680         if (err != 0) {
3681                 XHCI_CMD_UNLOCK(sc);
3682                 return (err);
3683         }
3684
3685         /*
3686          * Get the endpoint into the stopped state according to the
3687          * endpoint context state diagram in the XHCI specification:
3688          */
3689
3690         err = xhci_cmd_stop_ep(sc, 0, epno, index);
3691
3692         if (err != 0)
3693                 DPRINTF("Could not stop endpoint %u\n", epno);
3694
3695         err = xhci_cmd_reset_ep(sc, 0, epno, index);
3696
3697         if (err != 0)
3698                 DPRINTF("Could not reset endpoint %u\n", epno);
3699
3700         err = xhci_cmd_set_tr_dequeue_ptr(sc, pepext->physaddr |
3701             XHCI_EPCTX_2_DCS_SET(1), 0, epno, index);
3702
3703         if (err != 0)
3704                 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3705
3706         /*
3707          * Get the endpoint into the running state according to the
3708          * endpoint context state diagram in the XHCI specification:
3709          */
3710
3711         xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3712
3713         err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3714
3715         if (err != 0)
3716                 DPRINTF("Could not configure endpoint %u\n", epno);
3717
3718         err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3719
3720         if (err != 0)
3721                 DPRINTF("Could not configure endpoint %u\n", epno);
3722
3723         XHCI_CMD_UNLOCK(sc);
3724
3725         return (0);
3726 }
3727
3728 static void
3729 xhci_xfer_unsetup(struct usb_xfer *xfer)
3730 {
3731         return;
3732 }
3733
3734 static void
3735 xhci_start_dma_delay(struct usb_xfer *xfer)
3736 {
3737         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3738
3739         /* put transfer on interrupt queue (again) */
3740         usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3741
3742         (void)usb_proc_msignal(&sc->sc_config_proc,
3743             &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3744 }
3745
3746 static void
3747 xhci_configure_msg(struct usb_proc_msg *pm)
3748 {
3749         struct xhci_softc *sc;
3750         struct xhci_endpoint_ext *pepext;
3751         struct usb_xfer *xfer;
3752
3753         sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3754
3755 restart:
3756         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3757
3758                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3759                     xfer->endpoint->edesc);
3760
3761                 if ((pepext->trb_halted != 0) ||
3762                     (pepext->trb_running == 0)) {
3763
3764                         uint8_t i;
3765
3766                         /* clear halted and running */
3767                         pepext->trb_halted = 0;
3768                         pepext->trb_running = 0;
3769
3770                         /* nuke remaining buffered transfers */
3771
3772                         for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
3773                                 /*
3774                                  * NOTE: We need to use the timeout
3775                                  * error code here else existing
3776                                  * isochronous clients can get
3777                                  * confused:
3778                                  */
3779                                 if (pepext->xfer[i] != NULL) {
3780                                         xhci_device_done(pepext->xfer[i],
3781                                             USB_ERR_TIMEOUT);
3782                                 }
3783                         }
3784
3785                         /*
3786                          * NOTE: The USB transfer cannot vanish in
3787                          * this state!
3788                          */
3789
3790                         USB_BUS_UNLOCK(&sc->sc_bus);
3791
3792                         xhci_configure_reset_endpoint(xfer);
3793
3794                         USB_BUS_LOCK(&sc->sc_bus);
3795
3796                         /* check if halted is still cleared */
3797                         if (pepext->trb_halted == 0) {
3798                                 pepext->trb_running = 1;
3799                                 pepext->trb_index = 0;
3800                         }
3801                         goto restart;
3802                 }
3803
3804                 if (xfer->flags_int.did_dma_delay) {
3805
3806                         /* remove transfer from interrupt queue (again) */
3807                         usbd_transfer_dequeue(xfer);
3808
3809                         /* we are finally done */
3810                         usb_dma_delay_done_cb(xfer);
3811
3812                         /* queue changed - restart */
3813                         goto restart;
3814                 }
3815         }
3816
3817         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3818
3819                 /* try to insert xfer on HW queue */
3820                 xhci_transfer_insert(xfer);
3821
3822                 /* try to multi buffer */
3823                 xhci_device_generic_multi_enter(xfer->endpoint, NULL);
3824         }
3825 }
3826
3827 static void
3828 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3829     struct usb_endpoint *ep)
3830 {
3831         struct xhci_endpoint_ext *pepext;
3832
3833         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3834             ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
3835
3836         if (udev->flags.usb_mode != USB_MODE_HOST) {
3837                 /* not supported */
3838                 return;
3839         }
3840         if (udev->parent_hub == NULL) {
3841                 /* root HUB has special endpoint handling */
3842                 return;
3843         }
3844
3845         ep->methods = &xhci_device_generic_methods;
3846
3847         pepext = xhci_get_endpoint_ext(udev, edesc);
3848
3849         USB_BUS_LOCK(udev->bus);
3850         pepext->trb_halted = 1;
3851         pepext->trb_running = 0;
3852         USB_BUS_UNLOCK(udev->bus);
3853 }
3854
3855 static void
3856 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
3857 {
3858
3859 }
3860
3861 static void
3862 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3863 {
3864         struct xhci_endpoint_ext *pepext;
3865
3866         DPRINTF("\n");
3867
3868         if (udev->flags.usb_mode != USB_MODE_HOST) {
3869                 /* not supported */
3870                 return;
3871         }
3872         if (udev->parent_hub == NULL) {
3873                 /* root HUB has special endpoint handling */
3874                 return;
3875         }
3876
3877         pepext = xhci_get_endpoint_ext(udev, ep->edesc);
3878
3879         USB_BUS_LOCK(udev->bus);
3880         pepext->trb_halted = 1;
3881         pepext->trb_running = 0;
3882         USB_BUS_UNLOCK(udev->bus);
3883 }
3884
3885 static usb_error_t
3886 xhci_device_init(struct usb_device *udev)
3887 {
3888         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3889         usb_error_t err;
3890         uint8_t temp;
3891
3892         /* no init for root HUB */
3893         if (udev->parent_hub == NULL)
3894                 return (0);
3895
3896         XHCI_CMD_LOCK(sc);
3897
3898         /* set invalid default */
3899
3900         udev->controller_slot_id = sc->sc_noslot + 1;
3901
3902         /* try to get a new slot ID from the XHCI */
3903
3904         err = xhci_cmd_enable_slot(sc, &temp);
3905
3906         if (err) {
3907                 XHCI_CMD_UNLOCK(sc);
3908                 return (err);
3909         }
3910
3911         if (temp > sc->sc_noslot) {
3912                 XHCI_CMD_UNLOCK(sc);
3913                 return (USB_ERR_BAD_ADDRESS);
3914         }
3915
3916         if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
3917                 DPRINTF("slot %u already allocated.\n", temp);
3918                 XHCI_CMD_UNLOCK(sc);
3919                 return (USB_ERR_BAD_ADDRESS);
3920         }
3921
3922         /* store slot ID for later reference */
3923
3924         udev->controller_slot_id = temp;
3925
3926         /* reset data structure */
3927
3928         memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
3929
3930         /* set mark slot allocated */
3931
3932         sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
3933
3934         err = xhci_alloc_device_ext(udev);
3935
3936         XHCI_CMD_UNLOCK(sc);
3937
3938         /* get device into default state */
3939
3940         if (err == 0)
3941                 err = xhci_set_address(udev, NULL, 0);
3942
3943         return (err);
3944 }
3945
3946 static void
3947 xhci_device_uninit(struct usb_device *udev)
3948 {
3949         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3950         uint8_t index;
3951
3952         /* no init for root HUB */
3953         if (udev->parent_hub == NULL)
3954                 return;
3955
3956         XHCI_CMD_LOCK(sc);
3957
3958         index = udev->controller_slot_id;
3959
3960         if (index <= sc->sc_noslot) {
3961                 xhci_cmd_disable_slot(sc, index);
3962                 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
3963
3964                 /* free device extension */
3965                 xhci_free_device_ext(udev);
3966         }
3967
3968         XHCI_CMD_UNLOCK(sc);
3969 }
3970
3971 static void
3972 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
3973 {
3974         /*
3975          * Wait until the hardware has finished any possible use of
3976          * the transfer descriptor(s)
3977          */
3978         *pus = 2048;                    /* microseconds */
3979 }
3980
3981 static void
3982 xhci_device_resume(struct usb_device *udev)
3983 {
3984         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3985         uint8_t index;
3986         uint8_t n;
3987         uint8_t p;
3988
3989         DPRINTF("\n");
3990
3991         /* check for root HUB */
3992         if (udev->parent_hub == NULL)
3993                 return;
3994
3995         index = udev->controller_slot_id;
3996
3997         XHCI_CMD_LOCK(sc);
3998
3999         /* blindly resume all endpoints */
4000
4001         USB_BUS_LOCK(udev->bus);
4002
4003         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4004                 for (p = 0; p != 1 /*XHCI_MAX_STREAMS*/; p++) {
4005                         XWRITE4(sc, door, XHCI_DOORBELL(index),
4006                             n | XHCI_DB_SID_SET(p));
4007                 }
4008         }
4009
4010         USB_BUS_UNLOCK(udev->bus);
4011
4012         XHCI_CMD_UNLOCK(sc);
4013 }
4014
4015 static void
4016 xhci_device_suspend(struct usb_device *udev)
4017 {
4018         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4019         uint8_t index;
4020         uint8_t n;
4021         usb_error_t err;
4022
4023         DPRINTF("\n");
4024
4025         /* check for root HUB */
4026         if (udev->parent_hub == NULL)
4027                 return;
4028
4029         index = udev->controller_slot_id;
4030
4031         XHCI_CMD_LOCK(sc);
4032
4033         /* blindly suspend all endpoints */
4034
4035         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4036                 err = xhci_cmd_stop_ep(sc, 1, n, index);
4037                 if (err != 0) {
4038                         DPRINTF("Failed to suspend endpoint "
4039                             "%u on slot %u (ignored).\n", n, index);
4040                 }
4041         }
4042
4043         XHCI_CMD_UNLOCK(sc);
4044 }
4045
4046 static void
4047 xhci_set_hw_power(struct usb_bus *bus)
4048 {
4049         DPRINTF("\n");
4050 }
4051
4052 static void
4053 xhci_device_state_change(struct usb_device *udev)
4054 {
4055         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4056         struct usb_page_search buf_inp;
4057         usb_error_t err;
4058         uint8_t index;
4059
4060         /* check for root HUB */
4061         if (udev->parent_hub == NULL)
4062                 return;
4063
4064         index = udev->controller_slot_id;
4065
4066         DPRINTF("\n");
4067
4068         if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4069                 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4070                     &sc->sc_hw.devs[index].tt);
4071                 if (err != 0)
4072                         sc->sc_hw.devs[index].nports = 0;
4073         }
4074
4075         XHCI_CMD_LOCK(sc);
4076
4077         switch (usb_get_device_state(udev)) {
4078         case USB_STATE_POWERED:
4079                 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4080                         break;
4081
4082                 /* set default state */
4083                 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4084
4085                 /* reset number of contexts */
4086                 sc->sc_hw.devs[index].context_num = 0;
4087
4088                 err = xhci_cmd_reset_dev(sc, index);
4089
4090                 if (err != 0) {
4091                         DPRINTF("Device reset failed "
4092                             "for slot %u.\n", index);
4093                 }
4094                 break;
4095
4096         case USB_STATE_ADDRESSED:
4097                 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4098                         break;
4099
4100                 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4101
4102                 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4103
4104                 if (err) {
4105                         DPRINTF("Failed to deconfigure "
4106                             "slot %u.\n", index);
4107                 }
4108                 break;
4109
4110         case USB_STATE_CONFIGURED:
4111                 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4112                         break;
4113
4114                 /* set configured state */
4115                 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4116
4117                 /* reset number of contexts */
4118                 sc->sc_hw.devs[index].context_num = 0;
4119
4120                 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4121
4122                 xhci_configure_mask(udev, 3, 0);
4123
4124                 err = xhci_configure_device(udev);
4125                 if (err != 0) {
4126                         DPRINTF("Could not configure device "
4127                             "at slot %u.\n", index);
4128                 }
4129
4130                 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4131                 if (err != 0) {
4132                         DPRINTF("Could not evaluate device "
4133                             "context at slot %u.\n", index);
4134                 }
4135                 break;
4136
4137         default:
4138                 break;
4139         }
4140         XHCI_CMD_UNLOCK(sc);
4141 }
4142
4143 struct usb_bus_methods xhci_bus_methods = {
4144         .endpoint_init = xhci_ep_init,
4145         .endpoint_uninit = xhci_ep_uninit,
4146         .xfer_setup = xhci_xfer_setup,
4147         .xfer_unsetup = xhci_xfer_unsetup,
4148         .get_dma_delay = xhci_get_dma_delay,
4149         .device_init = xhci_device_init,
4150         .device_uninit = xhci_device_uninit,
4151         .device_resume = xhci_device_resume,
4152         .device_suspend = xhci_device_suspend,
4153         .set_hw_power = xhci_set_hw_power,
4154         .roothub_exec = xhci_roothub_exec,
4155         .xfer_poll = xhci_do_poll,
4156         .start_dma_delay = xhci_start_dma_delay,
4157         .set_address = xhci_set_address,
4158         .clear_stall = xhci_ep_clear_stall,
4159         .device_state_change = xhci_device_state_change,
4160         .set_hw_power_sleep = xhci_set_hw_power_sleep,
4161 };