sys/dev/usb/controller/xhci.c

   1 /*-
   2  * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  */
  25
  26 /*
  27  * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
  28  *
  29  * The XHCI 1.0 spec can be found at
  30  * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
  31  * and the USB 3.0 spec at
  32  * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
  33  */
  34
  35 /*
  36  * A few words about the design implementation: This driver emulates
  37  * the concept about TDs which is found in EHCI specification. This
  38  * way we avoid too much diveration among USB drivers.
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include <sys/stdint.h>
  45 #include <sys/stddef.h>
  46 #include <sys/param.h>
  47 #include <sys/queue.h>
  48 #include <sys/types.h>
  49 #include <sys/systm.h>
  50 #include <sys/kernel.h>
  51 #include <sys/bus.h>
  52 #include <sys/module.h>
  53 #include <sys/lock.h>
  54 #include <sys/mutex.h>
  55 #include <sys/condvar.h>
  56 #include <sys/sysctl.h>
  57 #include <sys/sx.h>
  58 #include <sys/unistd.h>
  59 #include <sys/callout.h>
  60 #include <sys/malloc.h>
  61 #include <sys/priv.h>
  62
  63 #include <dev/usb/usb.h>
  64 #include <dev/usb/usbdi.h>
  65
  66 #define USB_DEBUG_VAR xhcidebug
  67
  68 #include <dev/usb/usb_core.h>
  69 #include <dev/usb/usb_debug.h>
  70 #include <dev/usb/usb_busdma.h>
  71 #include <dev/usb/usb_process.h>
  72 #include <dev/usb/usb_transfer.h>
  73 #include <dev/usb/usb_device.h>
  74 #include <dev/usb/usb_hub.h>
  75 #include <dev/usb/usb_util.h>
  76
  77 #include <dev/usb/usb_controller.h>
  78 #include <dev/usb/usb_bus.h>
  79 #include <dev/usb/controller/xhci.h>
  80 #include <dev/usb/controller/xhcireg.h>
  81
  82 #define XHCI_BUS2SC(bus) \
  83    ((struct xhci_softc *)(((uint8_t *)(bus)) - \
  84     ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
  85
  86 #ifdef USB_DEBUG
  87 static int xhcidebug;
  88 static int xhciroute;
  89
  90 SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
  91 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
  92     &xhcidebug, 0, "Debug level");
  93 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
  94 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN,
  95     &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller");
  96 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
  97 #endif
  98
  99 #define XHCI_INTR_ENDPT 1
 100
 101 struct xhci_std_temp {
 102         struct xhci_softc       *sc;
 103         struct usb_page_cache   *pc;
 104         struct xhci_td          *td;
 105         struct xhci_td          *td_next;
 106         uint32_t                len;
 107         uint32_t                offset;
 108         uint32_t                max_packet_size;
 109         uint32_t                average;
 110         uint16_t                isoc_delta;
 111         uint16_t                isoc_frame;
 112         uint8_t                 shortpkt;
 113         uint8_t                 multishort;
 114         uint8_t                 last_frame;
 115         uint8_t                 trb_type;
 116         uint8_t                 direction;
 117         uint8_t                 tbc;
 118         uint8_t                 tlbpc;
 119         uint8_t                 step_td;
 120         uint8_t                 do_isoc_sync;
 121 };
 122
 123 static void     xhci_do_poll(struct usb_bus *);
 124 static void     xhci_device_done(struct usb_xfer *, usb_error_t);
 125 static void     xhci_root_intr(struct xhci_softc *);
 126 static void     xhci_free_device_ext(struct usb_device *);
 127 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
 128                     struct usb_endpoint_descriptor *);
 129 static usb_proc_callback_t xhci_configure_msg;
 130 static usb_error_t xhci_configure_device(struct usb_device *);
 131 static usb_error_t xhci_configure_endpoint(struct usb_device *,
 132                     struct usb_endpoint_descriptor *, uint64_t, uint16_t,
 133                     uint8_t, uint8_t, uint8_t, uint16_t, uint16_t);
 134 static usb_error_t xhci_configure_mask(struct usb_device *,
 135                     uint32_t, uint8_t);
 136 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
 137                     uint64_t, uint8_t);
 138 static void xhci_endpoint_doorbell(struct usb_xfer *);
 139 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
 140 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
 141 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
 142 #ifdef USB_DEBUG
 143 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
 144 #endif
 145
 146 extern struct usb_bus_methods xhci_bus_methods;
 147
 148 #ifdef USB_DEBUG
 149 static void
 150 xhci_dump_trb(struct xhci_trb *trb)
 151 {
 152         DPRINTFN(5, "trb = %p\n", trb);
 153         DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
 154         DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
 155         DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
 156 }
 157
 158 static void
 159 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
 160 {
 161         DPRINTFN(5, "pep = %p\n", pep);
 162         DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
 163         DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
 164         DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
 165         DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
 166         DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
 167         DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
 168         DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
 169 }
 170
 171 static void
 172 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
 173 {
 174         DPRINTFN(5, "psl = %p\n", psl);
 175         DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
 176         DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
 177         DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
 178         DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
 179 }
 180 #endif
 181
 182 uint32_t
 183 xhci_get_port_route(void)
 184 {
 185 #ifdef USB_DEBUG
 186         return (0xFFFFFFFFU ^ ((uint32_t)xhciroute));
 187 #else
 188         return (0xFFFFFFFFU);
 189 #endif
 190 }
 191
 192 static void
 193 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
 194 {
 195         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 196         uint8_t i;
 197
 198         cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
 199            sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
 200
 201         cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
 202            sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
 203
 204         for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) {
 205                 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
 206                     XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
 207         }
 208 }
 209
 210 static void
 211 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
 212 {
 213         if (sc->sc_ctx_is_64_byte) {
 214                 uint32_t offset;
 215                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 216                 /* all contexts are initially 32-bytes */
 217                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 218                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 219         }
 220         *ptr = htole32(val);
 221 }
 222
 223 static uint32_t
 224 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
 225 {
 226         if (sc->sc_ctx_is_64_byte) {
 227                 uint32_t offset;
 228                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 229                 /* all contexts are initially 32-bytes */
 230                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 231                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 232         }
 233         return (le32toh(*ptr));
 234 }
 235
 236 static void
 237 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
 238 {
 239         if (sc->sc_ctx_is_64_byte) {
 240                 uint32_t offset;
 241                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 242                 /* all contexts are initially 32-bytes */
 243                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 244                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 245         }
 246         *ptr = htole64(val);
 247 }
 248
 249 #ifdef USB_DEBUG
 250 static uint64_t
 251 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
 252 {
 253         if (sc->sc_ctx_is_64_byte) {
 254                 uint32_t offset;
 255                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 256                 /* all contexts are initially 32-bytes */
 257                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 258                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 259         }
 260         return (le64toh(*ptr));
 261 }
 262 #endif
 263
 264 usb_error_t
 265 xhci_start_controller(struct xhci_softc *sc)
 266 {
 267         struct usb_page_search buf_res;
 268         struct xhci_hw_root *phwr;
 269         struct xhci_dev_ctx_addr *pdctxa;
 270         uint64_t addr;
 271         uint32_t temp;
 272         uint16_t i;
 273
 274         DPRINTF("\n");
 275
 276         sc->sc_capa_off = 0;
 277         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 278         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
 279         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 280
 281         DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
 282         DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
 283         DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
 284
 285         sc->sc_event_ccs = 1;
 286         sc->sc_event_idx = 0;
 287         sc->sc_command_ccs = 1;
 288         sc->sc_command_idx = 0;
 289
 290         DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
 291
 292         temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
 293
 294         DPRINTF("HCS0 = 0x%08x\n", temp);
 295
 296         if (XHCI_HCS0_CSZ(temp)) {
 297                 sc->sc_ctx_is_64_byte = 1;
 298                 device_printf(sc->sc_bus.parent, "64 byte context size.\n");
 299         } else {
 300                 sc->sc_ctx_is_64_byte = 0;
 301                 device_printf(sc->sc_bus.parent, "32 byte context size.\n");
 302         }
 303
 304         /* Reset controller */
 305         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
 306
 307         for (i = 0; i != 100; i++) {
 308                 usb_pause_mtx(NULL, hz / 100);
 309                 temp = XREAD4(sc, oper, XHCI_USBCMD) &
 310                     (XHCI_CMD_HCRST | XHCI_STS_CNR);
 311                 if (!temp)
 312                         break;
 313         }
 314
 315         if (temp) {
 316                 device_printf(sc->sc_bus.parent, "Controller "
 317                     "reset timeout.\n");
 318                 return (USB_ERR_IOERROR);
 319         }
 320
 321         if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
 322                 device_printf(sc->sc_bus.parent, "Controller does "
 323                     "not support 4K page size.\n");
 324                 return (USB_ERR_IOERROR);
 325         }
 326
 327         temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
 328
 329         i = XHCI_HCS1_N_PORTS(temp);
 330
 331         if (i == 0) {
 332                 device_printf(sc->sc_bus.parent, "Invalid number "
 333                     "of ports: %u\n", i);
 334                 return (USB_ERR_IOERROR);
 335         }
 336
 337         sc->sc_noport = i;
 338         sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
 339
 340         if (sc->sc_noslot > XHCI_MAX_DEVICES)
 341                 sc->sc_noslot = XHCI_MAX_DEVICES;
 342
 343         /* setup number of device slots */
 344
 345         DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
 346             XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
 347
 348         XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
 349
 350         DPRINTF("Max slots: %u\n", sc->sc_noslot);
 351
 352         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 353
 354         sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
 355
 356         if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
 357                 device_printf(sc->sc_bus.parent, "XHCI request "
 358                     "too many scratchpads\n");
 359                 return (USB_ERR_NOMEM);
 360         }
 361
 362         DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
 363
 364         temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
 365
 366         sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
 367             XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
 368
 369         temp = XREAD4(sc, oper, XHCI_USBSTS);
 370
 371         /* clear interrupts */
 372         XWRITE4(sc, oper, XHCI_USBSTS, temp);
 373         /* disable all device notifications */
 374         XWRITE4(sc, oper, XHCI_DNCTRL, 0);
 375
 376         /* setup device context base address */
 377         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
 378         pdctxa = buf_res.buffer;
 379         memset(pdctxa, 0, sizeof(*pdctxa));
 380
 381         addr = buf_res.physaddr;
 382         addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
 383
 384         /* slot 0 points to the table of scratchpad pointers */
 385         pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
 386
 387         for (i = 0; i != sc->sc_noscratch; i++) {
 388                 struct usb_page_search buf_scp;
 389                 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
 390                 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
 391         }
 392
 393         addr = buf_res.physaddr;
 394
 395         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 396         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 397         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 398         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 399
 400         /* Setup event table size */
 401
 402         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 403
 404         DPRINTF("HCS2=0x%08x\n", temp);
 405
 406         temp = XHCI_HCS2_ERST_MAX(temp);
 407         temp = 1U << temp;
 408         if (temp > XHCI_MAX_RSEG)
 409                 temp = XHCI_MAX_RSEG;
 410
 411         sc->sc_erst_max = temp;
 412
 413         DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
 414             XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp);
 415
 416         XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp));
 417
 418         /* Setup interrupt rate */
 419         XWRITE4(sc, runt, XHCI_IMOD(0), XHCI_IMOD_DEFAULT);
 420
 421         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 422
 423         phwr = buf_res.buffer;
 424         addr = buf_res.physaddr;
 425         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
 426
 427         /* reset hardware root structure */
 428         memset(phwr, 0, sizeof(*phwr));
 429
 430         phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
 431         phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
 432
 433         DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
 434
 435         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
 436         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
 437
 438         addr = (uint64_t)buf_res.physaddr;
 439
 440         DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
 441
 442         XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
 443         XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
 444
 445         /* Setup interrupter registers */
 446
 447         temp = XREAD4(sc, runt, XHCI_IMAN(0));
 448         temp |= XHCI_IMAN_INTR_ENA;
 449         XWRITE4(sc, runt, XHCI_IMAN(0), temp);
 450
 451         /* setup command ring control base address */
 452         addr = buf_res.physaddr;
 453         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 454
 455         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 456
 457         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 458         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 459
 460         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 461
 462         usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 463
 464         /* Go! */
 465         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
 466             XHCI_CMD_INTE | XHCI_CMD_HSEE);
 467
 468         for (i = 0; i != 100; i++) {
 469                 usb_pause_mtx(NULL, hz / 100);
 470                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 471                 if (!temp)
 472                         break;
 473         }
 474         if (temp) {
 475                 XWRITE4(sc, oper, XHCI_USBCMD, 0);
 476                 device_printf(sc->sc_bus.parent, "Run timeout.\n");
 477                 return (USB_ERR_IOERROR);
 478         }
 479
 480         /* catch any lost interrupts */
 481         xhci_do_poll(&sc->sc_bus);
 482
 483         return (0);
 484 }
 485
 486 usb_error_t
 487 xhci_halt_controller(struct xhci_softc *sc)
 488 {
 489         uint32_t temp;
 490         uint16_t i;
 491
 492         DPRINTF("\n");
 493
 494         sc->sc_capa_off = 0;
 495         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 496         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
 497         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 498
 499         /* Halt controller */
 500         XWRITE4(sc, oper, XHCI_USBCMD, 0);
 501
 502         for (i = 0; i != 100; i++) {
 503                 usb_pause_mtx(NULL, hz / 100);
 504                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 505                 if (temp)
 506                         break;
 507         }
 508
 509         if (!temp) {
 510                 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
 511                 return (USB_ERR_IOERROR);
 512         }
 513         return (0);
 514 }
 515
 516 usb_error_t
 517 xhci_init(struct xhci_softc *sc, device_t self)
 518 {
 519         /* initialise some bus fields */
 520         sc->sc_bus.parent = self;
 521
 522         /* set the bus revision */
 523         sc->sc_bus.usbrev = USB_REV_3_0;
 524
 525         /* set up the bus struct */
 526         sc->sc_bus.methods = &xhci_bus_methods;
 527
 528         /* setup devices array */
 529         sc->sc_bus.devices = sc->sc_devices;
 530         sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
 531
 532         /* setup command queue mutex and condition varible */
 533         cv_init(&sc->sc_cmd_cv, "CMDQ");
 534         sx_init(&sc->sc_cmd_sx, "CMDQ lock");
 535
 536         /* get all DMA memory */
 537         if (usb_bus_mem_alloc_all(&sc->sc_bus,
 538             USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
 539                 return (ENOMEM);
 540         }
 541
 542         sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
 543         sc->sc_config_msg[0].bus = &sc->sc_bus;
 544         sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
 545         sc->sc_config_msg[1].bus = &sc->sc_bus;
 546
 547         if (usb_proc_create(&sc->sc_config_proc,
 548             &sc->sc_bus.bus_mtx, device_get_nameunit(self), USB_PRI_MED)) {
 549                 printf("WARNING: Creation of XHCI configure "
 550                     "callback process failed.\n");
 551         }
 552         return (0);
 553 }
 554
 555 void
 556 xhci_uninit(struct xhci_softc *sc)
 557 {
 558         usb_proc_free(&sc->sc_config_proc);
 559
 560         usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 561
 562         cv_destroy(&sc->sc_cmd_cv);
 563         sx_destroy(&sc->sc_cmd_sx);
 564 }
 565
 566 static void
 567 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
 568 {
 569         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 570
 571         switch (state) {
 572         case USB_HW_POWER_SUSPEND:
 573                 DPRINTF("Stopping the XHCI\n");
 574                 xhci_halt_controller(sc);
 575                 break;
 576         case USB_HW_POWER_SHUTDOWN:
 577                 DPRINTF("Stopping the XHCI\n");
 578                 xhci_halt_controller(sc);
 579                 break;
 580         case USB_HW_POWER_RESUME:
 581                 DPRINTF("Starting the XHCI\n");
 582                 xhci_start_controller(sc);
 583                 break;
 584         default:
 585                 break;
 586         }
 587 }
 588
 589 static usb_error_t
 590 xhci_generic_done_sub(struct usb_xfer *xfer)
 591 {
 592         struct xhci_td *td;
 593         struct xhci_td *td_alt_next;
 594         uint32_t len;
 595         uint8_t status;
 596
 597         td = xfer->td_transfer_cache;
 598         td_alt_next = td->alt_next;
 599
 600         if (xfer->aframes != xfer->nframes)
 601                 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
 602
 603         while (1) {
 604
 605                 usb_pc_cpu_invalidate(td->page_cache);
 606
 607                 status = td->status;
 608                 len = td->remainder;
 609
 610                 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
 611                     xfer, (unsigned int)xfer->aframes,
 612                     (unsigned int)xfer->nframes,
 613                     (unsigned int)len, (unsigned int)td->len,
 614                     (unsigned int)status);
 615
 616                 /*
 617                  * Verify the status length and
 618                  * add the length to "frlengths[]":
 619                  */
 620                 if (len > td->len) {
 621                         /* should not happen */
 622                         DPRINTF("Invalid status length, "
 623                             "0x%04x/0x%04x bytes\n", len, td->len);
 624                         status = XHCI_TRB_ERROR_LENGTH;
 625                 } else if (xfer->aframes != xfer->nframes) {
 626                         xfer->frlengths[xfer->aframes] += td->len - len;
 627                 }
 628                 /* Check for last transfer */
 629                 if (((void *)td) == xfer->td_transfer_last) {
 630                         td = NULL;
 631                         break;
 632                 }
 633                 /* Check for transfer error */
 634                 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
 635                     status != XHCI_TRB_ERROR_SUCCESS) {
 636                         /* the transfer is finished */
 637                         td = NULL;
 638                         break;
 639                 }
 640                 /* Check for short transfer */
 641                 if (len > 0) {
 642                         if (xfer->flags_int.short_frames_ok ||
 643                             xfer->flags_int.isochronous_xfr ||
 644                             xfer->flags_int.control_xfr) {
 645                                 /* follow alt next */
 646                                 td = td->alt_next;
 647                         } else {
 648                                 /* the transfer is finished */
 649                                 td = NULL;
 650                         }
 651                         break;
 652                 }
 653                 td = td->obj_next;
 654
 655                 if (td->alt_next != td_alt_next) {
 656                         /* this USB frame is complete */
 657                         break;
 658                 }
 659         }
 660
 661         /* update transfer cache */
 662
 663         xfer->td_transfer_cache = td;
 664
 665         return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
 666             (status != XHCI_TRB_ERROR_SHORT_PKT &&
 667             status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
 668             USB_ERR_NORMAL_COMPLETION);
 669 }
 670
 671 static void
 672 xhci_generic_done(struct usb_xfer *xfer)
 673 {
 674         usb_error_t err = 0;
 675
 676         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
 677             xfer, xfer->endpoint);
 678
 679         /* reset scanner */
 680
 681         xfer->td_transfer_cache = xfer->td_transfer_first;
 682
 683         if (xfer->flags_int.control_xfr) {
 684
 685                 if (xfer->flags_int.control_hdr)
 686                         err = xhci_generic_done_sub(xfer);
 687
 688                 xfer->aframes = 1;
 689
 690                 if (xfer->td_transfer_cache == NULL)
 691                         goto done;
 692         }
 693
 694         while (xfer->aframes != xfer->nframes) {
 695
 696                 err = xhci_generic_done_sub(xfer);
 697                 xfer->aframes++;
 698
 699                 if (xfer->td_transfer_cache == NULL)
 700                         goto done;
 701         }
 702
 703         if (xfer->flags_int.control_xfr &&
 704             !xfer->flags_int.control_act)
 705                 err = xhci_generic_done_sub(xfer);
 706 done:
 707         /* transfer is complete */
 708         xhci_device_done(xfer, err);
 709 }
 710
 711 static void
 712 xhci_activate_transfer(struct usb_xfer *xfer)
 713 {
 714         struct xhci_td *td;
 715
 716         td = xfer->td_transfer_cache;
 717
 718         usb_pc_cpu_invalidate(td->page_cache);
 719
 720         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 721
 722                 /* activate the transfer */
 723
 724                 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
 725                 usb_pc_cpu_flush(td->page_cache);
 726
 727                 xhci_endpoint_doorbell(xfer);
 728         }
 729 }
 730
 731 static void
 732 xhci_skip_transfer(struct usb_xfer *xfer)
 733 {
 734         struct xhci_td *td;
 735         struct xhci_td *td_last;
 736
 737         td = xfer->td_transfer_cache;
 738         td_last = xfer->td_transfer_last;
 739
 740         td = td->alt_next;
 741
 742         usb_pc_cpu_invalidate(td->page_cache);
 743
 744         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 745
 746                 usb_pc_cpu_invalidate(td_last->page_cache);
 747
 748                 /* copy LINK TRB to current waiting location */
 749
 750                 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
 751                 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
 752                 usb_pc_cpu_flush(td->page_cache);
 753
 754                 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
 755                 usb_pc_cpu_flush(td->page_cache);
 756
 757                 xhci_endpoint_doorbell(xfer);
 758         }
 759 }
 760
 761 /*------------------------------------------------------------------------*
 762  *      xhci_check_transfer
 763  *------------------------------------------------------------------------*/
 764 static void
 765 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
 766 {
 767         int64_t offset;
 768         uint64_t td_event;
 769         uint32_t temp;
 770         uint32_t remainder;
 771         uint8_t status;
 772         uint8_t halted;
 773         uint8_t epno;
 774         uint8_t index;
 775         uint8_t i;
 776
 777         /* decode TRB */
 778         td_event = le64toh(trb->qwTrb0);
 779         temp = le32toh(trb->dwTrb2);
 780
 781         remainder = XHCI_TRB_2_REM_GET(temp);
 782         status = XHCI_TRB_2_ERROR_GET(temp);
 783
 784         temp = le32toh(trb->dwTrb3);
 785         epno = XHCI_TRB_3_EP_GET(temp);
 786         index = XHCI_TRB_3_SLOT_GET(temp);
 787
 788         /* check if error means halted */
 789         halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
 790             status != XHCI_TRB_ERROR_SUCCESS);
 791
 792         DPRINTF("slot=%u epno=%u remainder=%u status=%u\n",
 793             index, epno, remainder, status);
 794
 795         if (index > sc->sc_noslot) {
 796                 DPRINTF("Invalid slot.\n");
 797                 return;
 798         }
 799
 800         if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
 801                 DPRINTF("Invalid endpoint.\n");
 802                 return;
 803         }
 804
 805         /* try to find the USB transfer that generated the event */
 806         for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
 807                 struct usb_xfer *xfer;
 808                 struct xhci_td *td;
 809                 struct xhci_endpoint_ext *pepext;
 810
 811                 pepext = &sc->sc_hw.devs[index].endp[epno];
 812
 813                 xfer = pepext->xfer[i];
 814                 if (xfer == NULL)
 815                         continue;
 816
 817                 td = xfer->td_transfer_cache;
 818
 819                 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
 820                         (long long)td_event,
 821                         (long long)td->td_self,
 822                         (long long)td->td_self + sizeof(td->td_trb));
 823
 824                 /*
 825                  * NOTE: Some XHCI implementations might not trigger
 826                  * an event on the last LINK TRB so we need to
 827                  * consider both the last and second last event
 828                  * address as conditions for a successful transfer.
 829                  *
 830                  * NOTE: We assume that the XHCI will only trigger one
 831                  * event per chain of TRBs.
 832                  */
 833
 834                 offset = td_event - td->td_self;
 835
 836                 if (offset >= 0 &&
 837                     offset < (int64_t)sizeof(td->td_trb)) {
 838
 839                         usb_pc_cpu_invalidate(td->page_cache);
 840
 841                         /* compute rest of remainder, if any */
 842                         for (i = (offset / 16) + 1; i < td->ntrb; i++) {
 843                                 temp = le32toh(td->td_trb[i].dwTrb2);
 844                                 remainder += XHCI_TRB_2_BYTES_GET(temp);
 845                         }
 846
 847                         DPRINTFN(5, "New remainder: %u\n", remainder);
 848
 849                         /* clear isochronous transfer errors */
 850                         if (xfer->flags_int.isochronous_xfr) {
 851                                 if (halted) {
 852                                         halted = 0;
 853                                         status = XHCI_TRB_ERROR_SUCCESS;
 854                                         remainder = td->len;
 855                                 }
 856                         }
 857
 858                         /* "td->remainder" is verified later */
 859                         td->remainder = remainder;
 860                         td->status = status;
 861
 862                         usb_pc_cpu_flush(td->page_cache);
 863
 864                         /*
 865                          * 1) Last transfer descriptor makes the
 866                          * transfer done
 867                          */
 868                         if (((void *)td) == xfer->td_transfer_last) {
 869                                 DPRINTF("TD is last\n");
 870                                 xhci_generic_done(xfer);
 871                                 break;
 872                         }
 873
 874                         /*
 875                          * 2) Any kind of error makes the transfer
 876                          * done
 877                          */
 878                         if (halted) {
 879                                 DPRINTF("TD has I/O error\n");
 880                                 xhci_generic_done(xfer);
 881                                 break;
 882                         }
 883
 884                         /*
 885                          * 3) If there is no alternate next transfer,
 886                          * a short packet also makes the transfer done
 887                          */
 888                         if (td->remainder > 0) {
 889                                 if (td->alt_next == NULL) {
 890                                         DPRINTF(
 891                                             "short TD has no alternate next\n");
 892                                         xhci_generic_done(xfer);
 893                                         break;
 894                                 }
 895                                 DPRINTF("TD has short pkt\n");
 896                                 if (xfer->flags_int.short_frames_ok ||
 897                                     xfer->flags_int.isochronous_xfr ||
 898                                     xfer->flags_int.control_xfr) {
 899                                         /* follow the alt next */
 900                                         xfer->td_transfer_cache = td->alt_next;
 901                                         xhci_activate_transfer(xfer);
 902                                         break;
 903                                 }
 904                                 xhci_skip_transfer(xfer);
 905                                 xhci_generic_done(xfer);
 906                                 break;
 907                         }
 908
 909                         /*
 910                          * 4) Transfer complete - go to next TD
 911                          */
 912                         DPRINTF("Following next TD\n");
 913                         xfer->td_transfer_cache = td->obj_next;
 914                         xhci_activate_transfer(xfer);
 915                         break;          /* there should only be one match */
 916                 }
 917         }
 918 }
 919
 920 static void
 921 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
 922 {
 923         if (sc->sc_cmd_addr == trb->qwTrb0) {
 924                 DPRINTF("Received command event\n");
 925                 sc->sc_cmd_result[0] = trb->dwTrb2;
 926                 sc->sc_cmd_result[1] = trb->dwTrb3;
 927                 cv_signal(&sc->sc_cmd_cv);
 928         }
 929 }
 930
 931 static void
 932 xhci_interrupt_poll(struct xhci_softc *sc)
 933 {
 934         struct usb_page_search buf_res;
 935         struct xhci_hw_root *phwr;
 936         uint64_t addr;
 937         uint32_t temp;
 938         uint16_t i;
 939         uint8_t event;
 940         uint8_t j;
 941         uint8_t k;
 942         uint8_t t;
 943
 944         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 945
 946         phwr = buf_res.buffer;
 947
 948         /* Receive any events */
 949
 950         usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
 951
 952         i = sc->sc_event_idx;
 953         j = sc->sc_event_ccs;
 954         t = 2;
 955
 956         while (1) {
 957
 958                 temp = le32toh(phwr->hwr_events[i].dwTrb3);
 959
 960                 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
 961
 962                 if (j != k)
 963                         break;
 964
 965                 event = XHCI_TRB_3_TYPE_GET(temp);
 966
 967                 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
 968                     i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
 969                     (long)le32toh(phwr->hwr_events[i].dwTrb2),
 970                     (long)le32toh(phwr->hwr_events[i].dwTrb3));
 971
 972                 switch (event) {
 973                 case XHCI_TRB_EVENT_TRANSFER:
 974                         xhci_check_transfer(sc, &phwr->hwr_events[i]);
 975                         break;
 976                 case XHCI_TRB_EVENT_CMD_COMPLETE:
 977                         xhci_check_command(sc, &phwr->hwr_events[i]);
 978                         break;
 979                 default:
 980                         DPRINTF("Unhandled event = %u\n", event);
 981                         break;
 982                 }
 983
 984                 i++;
 985
 986                 if (i == XHCI_MAX_EVENTS) {
 987                         i = 0;
 988                         j ^= 1;
 989
 990                         /* check for timeout */
 991                         if (!--t)
 992                                 break;
 993                 }
 994         }
 995
 996         sc->sc_event_idx = i;
 997         sc->sc_event_ccs = j;
 998
 999         /*
1000          * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1001          * latched. That means to activate the register we need to
1002          * write both the low and high double word of the 64-bit
1003          * register.
1004          */
1005
1006         addr = (uint32_t)buf_res.physaddr;
1007         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1008
1009         /* try to clear busy bit */
1010         addr |= XHCI_ERDP_LO_BUSY;
1011
1012         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1013         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1014 }
1015
1016 static usb_error_t
1017 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1018     uint16_t timeout_ms)
1019 {
1020         struct usb_page_search buf_res;
1021         struct xhci_hw_root *phwr;
1022         uint64_t addr;
1023         uint32_t temp;
1024         uint8_t i;
1025         uint8_t j;
1026         int err;
1027
1028         XHCI_CMD_ASSERT_LOCKED(sc);
1029
1030         /* get hardware root structure */
1031
1032         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1033
1034         phwr = buf_res.buffer;
1035
1036         /* Queue command */
1037
1038         USB_BUS_LOCK(&sc->sc_bus);
1039
1040         i = sc->sc_command_idx;
1041         j = sc->sc_command_ccs;
1042
1043         DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1044             i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1045             (long long)le64toh(trb->qwTrb0),
1046             (long)le32toh(trb->dwTrb2),
1047             (long)le32toh(trb->dwTrb3));
1048
1049         phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1050         phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1051
1052         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1053
1054         temp = trb->dwTrb3;
1055
1056         if (j)
1057                 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1058         else
1059                 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1060
1061         temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1062
1063         phwr->hwr_commands[i].dwTrb3 = temp;
1064
1065         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1066
1067         addr = buf_res.physaddr;
1068         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1069
1070         sc->sc_cmd_addr = htole64(addr);
1071
1072         i++;
1073
1074         if (i == (XHCI_MAX_COMMANDS - 1)) {
1075
1076                 if (j) {
1077                         temp = htole32(XHCI_TRB_3_TC_BIT |
1078                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1079                             XHCI_TRB_3_CYCLE_BIT);
1080                 } else {
1081                         temp = htole32(XHCI_TRB_3_TC_BIT |
1082                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1083                 }
1084
1085                 phwr->hwr_commands[i].dwTrb3 = temp;
1086
1087                 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1088
1089                 i = 0;
1090                 j ^= 1;
1091         }
1092
1093         sc->sc_command_idx = i;
1094         sc->sc_command_ccs = j;
1095
1096         XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1097
1098         err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1099             USB_MS_TO_TICKS(timeout_ms));
1100
1101         if (err) {
1102                 DPRINTFN(0, "Command timeout!\n");
1103                 err = USB_ERR_TIMEOUT;
1104                 trb->dwTrb2 = 0;
1105                 trb->dwTrb3 = 0;
1106         } else {
1107                 temp = le32toh(sc->sc_cmd_result[0]);
1108                 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1109                         err = USB_ERR_IOERROR;
1110
1111                 trb->dwTrb2 = sc->sc_cmd_result[0];
1112                 trb->dwTrb3 = sc->sc_cmd_result[1];
1113         }
1114
1115         USB_BUS_UNLOCK(&sc->sc_bus);
1116
1117         return (err);
1118 }
1119
1120 #if 0
1121 static usb_error_t
1122 xhci_cmd_nop(struct xhci_softc *sc)
1123 {
1124         struct xhci_trb trb;
1125         uint32_t temp;
1126
1127         DPRINTF("\n");
1128
1129         trb.qwTrb0 = 0;
1130         trb.dwTrb2 = 0;
1131         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1132
1133         trb.dwTrb3 = htole32(temp);
1134
1135         return (xhci_do_command(sc, &trb, 100 /* ms */));
1136 }
1137 #endif
1138
1139 static usb_error_t
1140 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1141 {
1142         struct xhci_trb trb;
1143         uint32_t temp;
1144         usb_error_t err;
1145
1146         DPRINTF("\n");
1147
1148         trb.qwTrb0 = 0;
1149         trb.dwTrb2 = 0;
1150         trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1151
1152         err = xhci_do_command(sc, &trb, 100 /* ms */);
1153         if (err)
1154                 goto done;
1155
1156         temp = le32toh(trb.dwTrb3);
1157
1158         *pslot = XHCI_TRB_3_SLOT_GET(temp);
1159
1160 done:
1161         return (err);
1162 }
1163
1164 static usb_error_t
1165 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1166 {
1167         struct xhci_trb trb;
1168         uint32_t temp;
1169
1170         DPRINTF("\n");
1171
1172         trb.qwTrb0 = 0;
1173         trb.dwTrb2 = 0;
1174         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1175             XHCI_TRB_3_SLOT_SET(slot_id);
1176
1177         trb.dwTrb3 = htole32(temp);
1178
1179         return (xhci_do_command(sc, &trb, 100 /* ms */));
1180 }
1181
1182 static usb_error_t
1183 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1184     uint8_t bsr, uint8_t slot_id)
1185 {
1186         struct xhci_trb trb;
1187         uint32_t temp;
1188
1189         DPRINTF("\n");
1190
1191         trb.qwTrb0 = htole64(input_ctx);
1192         trb.dwTrb2 = 0;
1193         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1194             XHCI_TRB_3_SLOT_SET(slot_id);
1195
1196         if (bsr)
1197                 temp |= XHCI_TRB_3_BSR_BIT;
1198
1199         trb.dwTrb3 = htole32(temp);
1200
1201         return (xhci_do_command(sc, &trb, 500 /* ms */));
1202 }
1203
1204 static usb_error_t
1205 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1206 {
1207         struct usb_page_search buf_inp;
1208         struct usb_page_search buf_dev;
1209         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1210         struct xhci_hw_dev *hdev;
1211         struct xhci_dev_ctx *pdev;
1212         struct xhci_endpoint_ext *pepext;
1213         uint32_t temp;
1214         uint16_t mps;
1215         usb_error_t err;
1216         uint8_t index;
1217
1218         /* the root HUB case is not handled here */
1219         if (udev->parent_hub == NULL)
1220                 return (USB_ERR_INVAL);
1221
1222         index = udev->controller_slot_id;
1223
1224         hdev =  &sc->sc_hw.devs[index];
1225
1226         if (mtx != NULL)
1227                 mtx_unlock(mtx);
1228
1229         XHCI_CMD_LOCK(sc);
1230
1231         switch (hdev->state) {
1232         case XHCI_ST_DEFAULT:
1233         case XHCI_ST_ENABLED:
1234
1235                 hdev->state = XHCI_ST_ENABLED;
1236
1237                 /* set configure mask to slot and EP0 */
1238                 xhci_configure_mask(udev, 3, 0);
1239
1240                 /* configure input slot context structure */
1241                 err = xhci_configure_device(udev);
1242
1243                 if (err != 0) {
1244                         DPRINTF("Could not configure device\n");
1245                         break;
1246                 }
1247
1248                 /* configure input endpoint context structure */
1249                 switch (udev->speed) {
1250                 case USB_SPEED_LOW:
1251                 case USB_SPEED_FULL:
1252                         mps = 8;
1253                         break;
1254                 case USB_SPEED_HIGH:
1255                         mps = 64;
1256                         break;
1257                 default:
1258                         mps = 512;
1259                         break;
1260                 }
1261
1262                 pepext = xhci_get_endpoint_ext(udev,
1263                     &udev->ctrl_ep_desc);
1264                 err = xhci_configure_endpoint(udev,
1265                     &udev->ctrl_ep_desc, pepext->physaddr,
1266                     0, 1, 1, 0, mps, mps);
1267
1268                 if (err != 0) {
1269                         DPRINTF("Could not configure default endpoint\n");
1270                         break;
1271                 }
1272
1273                 /* execute set address command */
1274                 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1275
1276                 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1277                     (address == 0), index);
1278
1279                 if (err != 0) {
1280                         DPRINTF("Could not set address "
1281                             "for slot %u.\n", index);
1282                         if (address != 0)
1283                                 break;
1284                 }
1285
1286                 /* update device address to new value */
1287
1288                 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1289                 pdev = buf_dev.buffer;
1290                 usb_pc_cpu_invalidate(&hdev->device_pc);
1291
1292                 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1293                 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1294
1295                 /* update device state to new value */
1296
1297                 if (address != 0)
1298                         hdev->state = XHCI_ST_ADDRESSED;
1299                 else
1300                         hdev->state = XHCI_ST_DEFAULT;
1301                 break;
1302
1303         default:
1304                 DPRINTF("Wrong state for set address.\n");
1305                 err = USB_ERR_IOERROR;
1306                 break;
1307         }
1308         XHCI_CMD_UNLOCK(sc);
1309
1310         if (mtx != NULL)
1311                 mtx_lock(mtx);
1312
1313         return (err);
1314 }
1315
1316 static usb_error_t
1317 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1318     uint8_t deconfigure, uint8_t slot_id)
1319 {
1320         struct xhci_trb trb;
1321         uint32_t temp;
1322
1323         DPRINTF("\n");
1324
1325         trb.qwTrb0 = htole64(input_ctx);
1326         trb.dwTrb2 = 0;
1327         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1328             XHCI_TRB_3_SLOT_SET(slot_id);
1329
1330         if (deconfigure)
1331                 temp |= XHCI_TRB_3_DCEP_BIT;
1332
1333         trb.dwTrb3 = htole32(temp);
1334
1335         return (xhci_do_command(sc, &trb, 100 /* ms */));
1336 }
1337
1338 static usb_error_t
1339 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1340     uint8_t slot_id)
1341 {
1342         struct xhci_trb trb;
1343         uint32_t temp;
1344
1345         DPRINTF("\n");
1346
1347         trb.qwTrb0 = htole64(input_ctx);
1348         trb.dwTrb2 = 0;
1349         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1350             XHCI_TRB_3_SLOT_SET(slot_id);
1351         trb.dwTrb3 = htole32(temp);
1352
1353         return (xhci_do_command(sc, &trb, 100 /* ms */));
1354 }
1355
1356 static usb_error_t
1357 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1358     uint8_t ep_id, uint8_t slot_id)
1359 {
1360         struct xhci_trb trb;
1361         uint32_t temp;
1362
1363         DPRINTF("\n");
1364
1365         trb.qwTrb0 = 0;
1366         trb.dwTrb2 = 0;
1367         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1368             XHCI_TRB_3_SLOT_SET(slot_id) |
1369             XHCI_TRB_3_EP_SET(ep_id);
1370
1371         if (preserve)
1372                 temp |= XHCI_TRB_3_PRSV_BIT;
1373
1374         trb.dwTrb3 = htole32(temp);
1375
1376         return (xhci_do_command(sc, &trb, 100 /* ms */));
1377 }
1378
1379 static usb_error_t
1380 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1381     uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1382 {
1383         struct xhci_trb trb;
1384         uint32_t temp;
1385
1386         DPRINTF("\n");
1387
1388         trb.qwTrb0 = htole64(dequeue_ptr);
1389
1390         temp = XHCI_TRB_2_STREAM_SET(stream_id);
1391         trb.dwTrb2 = htole32(temp);
1392
1393         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1394             XHCI_TRB_3_SLOT_SET(slot_id) |
1395             XHCI_TRB_3_EP_SET(ep_id);
1396         trb.dwTrb3 = htole32(temp);
1397
1398         return (xhci_do_command(sc, &trb, 100 /* ms */));
1399 }
1400
1401 static usb_error_t
1402 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1403     uint8_t ep_id, uint8_t slot_id)
1404 {
1405         struct xhci_trb trb;
1406         uint32_t temp;
1407
1408         DPRINTF("\n");
1409
1410         trb.qwTrb0 = 0;
1411         trb.dwTrb2 = 0;
1412         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1413             XHCI_TRB_3_SLOT_SET(slot_id) |
1414             XHCI_TRB_3_EP_SET(ep_id);
1415
1416         if (suspend)
1417                 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1418
1419         trb.dwTrb3 = htole32(temp);
1420
1421         return (xhci_do_command(sc, &trb, 100 /* ms */));
1422 }
1423
1424 static usb_error_t
1425 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1426 {
1427         struct xhci_trb trb;
1428         uint32_t temp;
1429
1430         DPRINTF("\n");
1431
1432         trb.qwTrb0 = 0;
1433         trb.dwTrb2 = 0;
1434         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1435             XHCI_TRB_3_SLOT_SET(slot_id);
1436
1437         trb.dwTrb3 = htole32(temp);
1438
1439         return (xhci_do_command(sc, &trb, 100 /* ms */));
1440 }
1441
1442 /*------------------------------------------------------------------------*
1443  *      xhci_interrupt - XHCI interrupt handler
1444  *------------------------------------------------------------------------*/
1445 void
1446 xhci_interrupt(struct xhci_softc *sc)
1447 {
1448         uint32_t status;
1449
1450         USB_BUS_LOCK(&sc->sc_bus);
1451
1452         status = XREAD4(sc, oper, XHCI_USBSTS);
1453         if (status == 0)
1454                 goto done;
1455
1456         /* acknowledge interrupts */
1457
1458         XWRITE4(sc, oper, XHCI_USBSTS, status);
1459
1460         DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1461
1462         if (status & XHCI_STS_EINT) {
1463                 /* check for event(s) */
1464                 xhci_interrupt_poll(sc);
1465         }
1466
1467         if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1468             XHCI_STS_HSE | XHCI_STS_HCE)) {
1469
1470                 if (status & XHCI_STS_PCD) {
1471                         xhci_root_intr(sc);
1472                 }
1473
1474                 if (status & XHCI_STS_HCH) {
1475                         printf("%s: host controller halted\n",
1476                             __FUNCTION__);
1477                 }
1478
1479                 if (status & XHCI_STS_HSE) {
1480                         printf("%s: host system error\n",
1481                             __FUNCTION__);
1482                 }
1483
1484                 if (status & XHCI_STS_HCE) {
1485                         printf("%s: host controller error\n",
1486                            __FUNCTION__);
1487                 }
1488         }
1489 done:
1490         USB_BUS_UNLOCK(&sc->sc_bus);
1491 }
1492
1493 /*------------------------------------------------------------------------*
1494  *      xhci_timeout - XHCI timeout handler
1495  *------------------------------------------------------------------------*/
1496 static void
1497 xhci_timeout(void *arg)
1498 {
1499         struct usb_xfer *xfer = arg;
1500
1501         DPRINTF("xfer=%p\n", xfer);
1502
1503         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1504
1505         /* transfer is transferred */
1506         xhci_device_done(xfer, USB_ERR_TIMEOUT);
1507 }
1508
1509 static void
1510 xhci_do_poll(struct usb_bus *bus)
1511 {
1512         struct xhci_softc *sc = XHCI_BUS2SC(bus);
1513
1514         USB_BUS_LOCK(&sc->sc_bus);
1515         xhci_interrupt_poll(sc);
1516         USB_BUS_UNLOCK(&sc->sc_bus);
1517 }
1518
1519 static void
1520 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1521 {
1522         struct usb_page_search buf_res;
1523         struct xhci_td *td;
1524         struct xhci_td *td_next;
1525         struct xhci_td *td_alt_next;
1526         struct xhci_td *td_first;
1527         uint32_t buf_offset;
1528         uint32_t average;
1529         uint32_t len_old;
1530         uint32_t npkt_off;
1531         uint32_t dword;
1532         uint8_t shortpkt_old;
1533         uint8_t precompute;
1534         uint8_t x;
1535
1536         td_alt_next = NULL;
1537         buf_offset = 0;
1538         shortpkt_old = temp->shortpkt;
1539         len_old = temp->len;
1540         npkt_off = 0;
1541         precompute = 1;
1542
1543 restart:
1544
1545         td = temp->td;
1546         td_next = td_first = temp->td_next;
1547
1548         while (1) {
1549
1550                 if (temp->len == 0) {
1551
1552                         if (temp->shortpkt)
1553                                 break;
1554
1555                         /* send a Zero Length Packet, ZLP, last */
1556
1557                         temp->shortpkt = 1;
1558                         average = 0;
1559
1560                 } else {
1561
1562                         average = temp->average;
1563
1564                         if (temp->len < average) {
1565                                 if (temp->len % temp->max_packet_size) {
1566                                         temp->shortpkt = 1;
1567                                 }
1568                                 average = temp->len;
1569                         }
1570                 }
1571
1572                 if (td_next == NULL)
1573                         panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1574
1575                 /* get next TD */
1576
1577                 td = td_next;
1578                 td_next = td->obj_next;
1579
1580                 /* check if we are pre-computing */
1581
1582                 if (precompute) {
1583
1584                         /* update remaining length */
1585
1586                         temp->len -= average;
1587
1588                         continue;
1589                 }
1590                 /* fill out current TD */
1591
1592                 td->len = average;
1593                 td->remainder = 0;
1594                 td->status = 0;
1595
1596                 /* update remaining length */
1597
1598                 temp->len -= average;
1599
1600                 /* reset TRB index */
1601
1602                 x = 0;
1603
1604                 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1605                         /* immediate data */
1606
1607                         if (average > 8)
1608                                 average = 8;
1609
1610                         td->td_trb[0].qwTrb0 = 0;
1611
1612                         usbd_copy_out(temp->pc, temp->offset + buf_offset,
1613                            (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1614                            average);
1615
1616                         dword = XHCI_TRB_2_BYTES_SET(8) |
1617                             XHCI_TRB_2_TDSZ_SET(0) |
1618                             XHCI_TRB_2_IRQ_SET(0);
1619
1620                         td->td_trb[0].dwTrb2 = htole32(dword);
1621
1622                         dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1623                           XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1624
1625                         /* check wLength */
1626                         if (td->td_trb[0].qwTrb0 &
1627                            htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1628                                 if (td->td_trb[0].qwTrb0 & htole64(1))
1629                                         dword |= XHCI_TRB_3_TRT_IN;
1630                                 else
1631                                         dword |= XHCI_TRB_3_TRT_OUT;
1632                         }
1633
1634                         td->td_trb[0].dwTrb3 = htole32(dword);
1635 #ifdef USB_DEBUG
1636                         xhci_dump_trb(&td->td_trb[x]);
1637 #endif
1638                         x++;
1639
1640                 } else do {
1641
1642                         uint32_t npkt;
1643
1644                         /* fill out buffer pointers */
1645
1646                         if (average == 0) {
1647                                 memset(&buf_res, 0, sizeof(buf_res));
1648                         } else {
1649                                 usbd_get_page(temp->pc, temp->offset +
1650                                     buf_offset, &buf_res);
1651
1652                                 /* get length to end of page */
1653                                 if (buf_res.length > average)
1654                                         buf_res.length = average;
1655
1656                                 /* check for maximum length */
1657                                 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1658                                         buf_res.length = XHCI_TD_PAGE_SIZE;
1659
1660                                 npkt_off += buf_res.length;
1661                         }
1662
1663                         /* setup npkt */
1664                         npkt = (len_old - npkt_off + temp->max_packet_size - 1) /
1665                             temp->max_packet_size;
1666
1667                         if (npkt == 0)
1668                                 npkt = 1;
1669                         else if (npkt > 31)
1670                                 npkt = 31;
1671
1672                         /* fill out TRB's */
1673                         td->td_trb[x].qwTrb0 =
1674                             htole64((uint64_t)buf_res.physaddr);
1675
1676                         dword =
1677                           XHCI_TRB_2_BYTES_SET(buf_res.length) |
1678                           XHCI_TRB_2_TDSZ_SET(npkt) |
1679                           XHCI_TRB_2_IRQ_SET(0);
1680
1681                         td->td_trb[x].dwTrb2 = htole32(dword);
1682
1683                         switch (temp->trb_type) {
1684                         case XHCI_TRB_TYPE_ISOCH:
1685                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1686                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1687                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1688                                 if (td != td_first) {
1689                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1690                                 } else if (temp->do_isoc_sync != 0) {
1691                                         temp->do_isoc_sync = 0;
1692                                         /* wait until "isoc_frame" */
1693                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1694                                             XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1695                                 } else {
1696                                         /* start data transfer at next interval */
1697                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1698                                             XHCI_TRB_3_ISO_SIA_BIT;
1699                                 }
1700                                 if (temp->direction == UE_DIR_IN)
1701                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1702                                 break;
1703                         case XHCI_TRB_TYPE_DATA_STAGE:
1704                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1705                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) |
1706                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1707                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1708                                 if (temp->direction == UE_DIR_IN)
1709                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1710                                 break;
1711                         case XHCI_TRB_TYPE_STATUS_STAGE:
1712                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1713                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) |
1714                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1715                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1716                                 if (temp->direction == UE_DIR_IN)
1717                                         dword |= XHCI_TRB_3_DIR_IN;
1718                                 break;
1719                         default:        /* XHCI_TRB_TYPE_NORMAL */
1720                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1721                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) |
1722                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1723                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1724                                 if (temp->direction == UE_DIR_IN)
1725                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1726                                 break;
1727                         }
1728                         td->td_trb[x].dwTrb3 = htole32(dword);
1729
1730                         average -= buf_res.length;
1731                         buf_offset += buf_res.length;
1732 #ifdef USB_DEBUG
1733                         xhci_dump_trb(&td->td_trb[x]);
1734 #endif
1735                         x++;
1736
1737                 } while (average != 0);
1738
1739                 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1740
1741                 /* store number of data TRB's */
1742
1743                 td->ntrb = x;
1744
1745                 DPRINTF("NTRB=%u\n", x);
1746
1747                 /* fill out link TRB */
1748
1749                 if (td_next != NULL) {
1750                         /* link the current TD with the next one */
1751                         td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1752                         DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1753                 } else {
1754                         /* this field will get updated later */
1755                         DPRINTF("NOLINK\n");
1756                 }
1757
1758                 dword = XHCI_TRB_2_IRQ_SET(0);
1759
1760                 td->td_trb[x].dwTrb2 = htole32(dword);
1761
1762                 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1763                     XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT;
1764
1765                 td->td_trb[x].dwTrb3 = htole32(dword);
1766
1767                 td->alt_next = td_alt_next;
1768 #ifdef USB_DEBUG
1769                 xhci_dump_trb(&td->td_trb[x]);
1770 #endif
1771                 usb_pc_cpu_flush(td->page_cache);
1772         }
1773
1774         if (precompute) {
1775                 precompute = 0;
1776
1777                 /* setup alt next pointer, if any */
1778                 if (temp->last_frame) {
1779                         td_alt_next = NULL;
1780                 } else {
1781                         /* we use this field internally */
1782                         td_alt_next = td_next;
1783                 }
1784
1785                 /* restore */
1786                 temp->shortpkt = shortpkt_old;
1787                 temp->len = len_old;
1788                 goto restart;
1789         }
1790
1791         /*
1792          * Remove cycle bit from the first TRB if we are
1793          * stepping them:
1794          */
1795         if (temp->step_td != 0) {
1796                 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1797                 usb_pc_cpu_flush(td_first->page_cache);
1798         }
1799
1800         /* clear TD SIZE to zero, hence this is the last TRB */
1801         /* remove chain bit because this is the last TRB in the chain */
1802         td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1803         td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1804
1805         usb_pc_cpu_flush(td->page_cache);
1806
1807         temp->td = td;
1808         temp->td_next = td_next;
1809 }
1810
1811 static void
1812 xhci_setup_generic_chain(struct usb_xfer *xfer)
1813 {
1814         struct xhci_std_temp temp;
1815         struct xhci_td *td;
1816         uint32_t x;
1817         uint32_t y;
1818         uint8_t mult;
1819
1820         temp.do_isoc_sync = 0;
1821         temp.step_td = 0;
1822         temp.tbc = 0;
1823         temp.tlbpc = 0;
1824         temp.average = xfer->max_hc_frame_size;
1825         temp.max_packet_size = xfer->max_packet_size;
1826         temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
1827         temp.pc = NULL;
1828         temp.last_frame = 0;
1829         temp.offset = 0;
1830         temp.multishort = xfer->flags_int.isochronous_xfr ||
1831             xfer->flags_int.control_xfr ||
1832             xfer->flags_int.short_frames_ok;
1833
1834         /* toggle the DMA set we are using */
1835         xfer->flags_int.curr_dma_set ^= 1;
1836
1837         /* get next DMA set */
1838         td = xfer->td_start[xfer->flags_int.curr_dma_set];
1839
1840         temp.td = NULL;
1841         temp.td_next = td;
1842
1843         xfer->td_transfer_first = td;
1844         xfer->td_transfer_cache = td;
1845
1846         if (xfer->flags_int.isochronous_xfr) {
1847                 uint8_t shift;
1848
1849                 /* compute multiplier for ISOCHRONOUS transfers */
1850                 mult = xfer->endpoint->ecomp ?
1851                     (xfer->endpoint->ecomp->bmAttributes & 3) : 0;
1852                 /* check for USB 2.0 multiplier */
1853                 if (mult == 0) {
1854                         mult = (xfer->endpoint->edesc->
1855                             wMaxPacketSize[1] >> 3) & 3;
1856                 }
1857                 /* range check */
1858                 if (mult > 2)
1859                         mult = 3;
1860                 else
1861                         mult++;
1862
1863                 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
1864
1865                 DPRINTF("MFINDEX=0x%08x\n", x);
1866
1867                 switch (usbd_get_speed(xfer->xroot->udev)) {
1868                 case USB_SPEED_FULL:
1869                         shift = 3;
1870                         temp.isoc_delta = 8;    /* 1ms */
1871                         x += temp.isoc_delta - 1;
1872                         x &= ~(temp.isoc_delta - 1);
1873                         break;
1874                 default:
1875                         shift = usbd_xfer_get_fps_shift(xfer);
1876                         temp.isoc_delta = 1U << shift;
1877                         x += temp.isoc_delta - 1;
1878                         x &= ~(temp.isoc_delta - 1);
1879                         /* simple frame load balancing */
1880                         x += xfer->endpoint->usb_uframe;
1881                         break;
1882                 }
1883
1884                 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
1885
1886                 if ((xfer->endpoint->is_synced == 0) ||
1887                     (y < (xfer->nframes << shift)) ||
1888                     (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
1889                         /*
1890                          * If there is data underflow or the pipe
1891                          * queue is empty we schedule the transfer a
1892                          * few frames ahead of the current frame
1893                          * position. Else two isochronous transfers
1894                          * might overlap.
1895                          */
1896                         xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
1897                         xfer->endpoint->is_synced = 1;
1898                         temp.do_isoc_sync = 1;
1899
1900                         DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
1901                 }
1902
1903                 /* compute isochronous completion time */
1904
1905                 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
1906
1907                 xfer->isoc_time_complete =
1908                     usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
1909                     (y / 8) + (((xfer->nframes << shift) + 7) / 8);
1910
1911                 x = 0;
1912                 temp.isoc_frame = xfer->endpoint->isoc_next;
1913                 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
1914
1915                 xfer->endpoint->isoc_next += xfer->nframes << shift;
1916
1917         } else if (xfer->flags_int.control_xfr) {
1918
1919                 /* check if we should prepend a setup message */
1920
1921                 if (xfer->flags_int.control_hdr) {
1922
1923                         temp.len = xfer->frlengths[0];
1924                         temp.pc = xfer->frbuffers + 0;
1925                         temp.shortpkt = temp.len ? 1 : 0;
1926                         temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
1927                         temp.direction = 0;
1928
1929                         /* check for last frame */
1930                         if (xfer->nframes == 1) {
1931                                 /* no STATUS stage yet, SETUP is last */
1932                                 if (xfer->flags_int.control_act)
1933                                         temp.last_frame = 1;
1934                         }
1935
1936                         xhci_setup_generic_chain_sub(&temp);
1937                 }
1938                 x = 1;
1939                 mult = 1;
1940                 temp.isoc_delta = 0;
1941                 temp.isoc_frame = 0;
1942                 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE;
1943         } else {
1944                 x = 0;
1945                 mult = 1;
1946                 temp.isoc_delta = 0;
1947                 temp.isoc_frame = 0;
1948                 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
1949         }
1950
1951         if (x != xfer->nframes) {
1952                 /* setup page_cache pointer */
1953                 temp.pc = xfer->frbuffers + x;
1954                 /* set endpoint direction */
1955                 temp.direction = UE_GET_DIR(xfer->endpointno);
1956         }
1957
1958         while (x != xfer->nframes) {
1959
1960                 /* DATA0 / DATA1 message */
1961
1962                 temp.len = xfer->frlengths[x];
1963                 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
1964                     x != 0 && temp.multishort == 0);
1965
1966                 x++;
1967
1968                 if (x == xfer->nframes) {
1969                         if (xfer->flags_int.control_xfr) {
1970                                 /* no STATUS stage yet, DATA is last */
1971                                 if (xfer->flags_int.control_act)
1972                                         temp.last_frame = 1;
1973                         } else {
1974                                 temp.last_frame = 1;
1975                         }
1976                 }
1977                 if (temp.len == 0) {
1978
1979                         /* make sure that we send an USB packet */
1980
1981                         temp.shortpkt = 0;
1982
1983                         temp.tbc = 0;
1984                         temp.tlbpc = mult - 1;
1985
1986                 } else if (xfer->flags_int.isochronous_xfr) {
1987
1988                         uint8_t tdpc;
1989
1990                         /*
1991                          * Isochronous transfers don't have short
1992                          * packet termination:
1993                          */
1994
1995                         temp.shortpkt = 1;
1996
1997                         /* isochronous transfers have a transfer limit */
1998
1999                         if (temp.len > xfer->max_frame_size)
2000                                 temp.len = xfer->max_frame_size;
2001
2002                         /* compute TD packet count */
2003                         tdpc = (temp.len + xfer->max_packet_size - 1) /
2004                             xfer->max_packet_size;
2005
2006                         temp.tbc = ((tdpc + mult - 1) / mult) - 1;
2007                         temp.tlbpc = (tdpc % mult);
2008
2009                         if (temp.tlbpc == 0)
2010                                 temp.tlbpc = mult - 1;
2011                         else
2012                                 temp.tlbpc--;
2013                 } else {
2014
2015                         /* regular data transfer */
2016
2017                         temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2018                 }
2019
2020                 xhci_setup_generic_chain_sub(&temp);
2021
2022                 if (xfer->flags_int.isochronous_xfr) {
2023                         temp.offset += xfer->frlengths[x - 1];
2024                         temp.isoc_frame += temp.isoc_delta;
2025                 } else {
2026                         /* get next Page Cache pointer */
2027                         temp.pc = xfer->frbuffers + x;
2028                 }
2029         }
2030
2031         /* check if we should append a status stage */
2032
2033         if (xfer->flags_int.control_xfr &&
2034             !xfer->flags_int.control_act) {
2035
2036                 /*
2037                  * Send a DATA1 message and invert the current
2038                  * endpoint direction.
2039                  */
2040                 temp.step_td = (xfer->nframes != 0);
2041                 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2042                 temp.len = 0;
2043                 temp.pc = NULL;
2044                 temp.shortpkt = 0;
2045                 temp.last_frame = 1;
2046                 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2047
2048                 xhci_setup_generic_chain_sub(&temp);
2049         }
2050
2051         td = temp.td;
2052
2053         /* must have at least one frame! */
2054
2055         xfer->td_transfer_last = td;
2056
2057         DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2058 }
2059
2060 static void
2061 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2062 {
2063         struct usb_page_search buf_res;
2064         struct xhci_dev_ctx_addr *pdctxa;
2065
2066         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2067
2068         pdctxa = buf_res.buffer;
2069
2070         DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2071
2072         pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2073
2074         usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2075 }
2076
2077 static usb_error_t
2078 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2079 {
2080         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2081         struct usb_page_search buf_inp;
2082         struct xhci_input_dev_ctx *pinp;
2083         uint32_t temp;
2084         uint8_t index;
2085         uint8_t x;
2086
2087         index = udev->controller_slot_id;
2088
2089         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2090
2091         pinp = buf_inp.buffer;
2092
2093         if (drop) {
2094                 mask &= XHCI_INCTX_NON_CTRL_MASK;
2095                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2096                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2097         } else {
2098                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0);
2099                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2100
2101                 /* find most significant set bit */
2102                 for (x = 31; x != 1; x--) {
2103                         if (mask & (1 << x))
2104                                 break;
2105                 }
2106
2107                 /* adjust */
2108                 x--;
2109
2110                 /* figure out maximum */
2111                 if (x > sc->sc_hw.devs[index].context_num) {
2112                         sc->sc_hw.devs[index].context_num = x;
2113                         temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2114                         temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2115                         temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2116                         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2117                 }
2118         }
2119         return (0);
2120 }
2121
2122 static usb_error_t
2123 xhci_configure_endpoint(struct usb_device *udev,
2124     struct usb_endpoint_descriptor *edesc, uint64_t ring_addr,
2125     uint16_t interval, uint8_t max_packet_count, uint8_t mult,
2126     uint8_t fps_shift, uint16_t max_packet_size, uint16_t max_frame_size)
2127 {
2128         struct usb_page_search buf_inp;
2129         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2130         struct xhci_input_dev_ctx *pinp;
2131         uint32_t temp;
2132         uint8_t index;
2133         uint8_t epno;
2134         uint8_t type;
2135
2136         index = udev->controller_slot_id;
2137
2138         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2139
2140         pinp = buf_inp.buffer;
2141
2142         epno = edesc->bEndpointAddress;
2143         type = edesc->bmAttributes & UE_XFERTYPE;
2144
2145         if (type == UE_CONTROL)
2146                 epno |= UE_DIR_IN;
2147
2148         epno = XHCI_EPNO2EPID(epno);
2149
2150         if (epno == 0)
2151                 return (USB_ERR_NO_PIPE);               /* invalid */
2152
2153         if (max_packet_count == 0)
2154                 return (USB_ERR_BAD_BUFSIZE);
2155
2156         max_packet_count--;
2157
2158         if (mult == 0)
2159                 return (USB_ERR_BAD_BUFSIZE);
2160
2161         temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2162             XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2163             XHCI_EPCTX_0_LSA_SET(0);
2164
2165         switch (udev->speed) {
2166         case USB_SPEED_FULL:
2167         case USB_SPEED_LOW:
2168                 /* 1ms -> 125us */
2169                 fps_shift += 3;
2170                 break;
2171         default:
2172                 break;
2173         }
2174
2175         switch (type) {
2176         case UE_INTERRUPT:
2177                 if (fps_shift > 3)
2178                         fps_shift--;
2179                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2180                 break;
2181         case UE_ISOCHRONOUS:
2182                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2183
2184                 switch (udev->speed) {
2185                 case USB_SPEED_SUPER:
2186                         if (mult > 3)
2187                                 mult = 3;
2188                         temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2189                         max_packet_count /= mult;
2190                         break;
2191                 default:
2192                         break;
2193                 }
2194                 break;
2195         default:
2196                 break;
2197         }
2198
2199         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2200
2201         temp =
2202             XHCI_EPCTX_1_HID_SET(0) |
2203             XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2204             XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2205
2206         if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) {
2207                 if (type != UE_ISOCHRONOUS)
2208                         temp |= XHCI_EPCTX_1_CERR_SET(3);
2209         }
2210
2211         switch (type) {
2212         case UE_CONTROL:
2213                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2214                 break;
2215         case UE_ISOCHRONOUS:
2216                 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2217                 break;
2218         case UE_BULK:
2219                 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2220                 break;
2221         default:
2222                 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2223                 break;
2224         }
2225
2226         /* check for IN direction */
2227         if (epno & 1)
2228                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2229
2230         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2231
2232         ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2233
2234         xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2235
2236         switch (edesc->bmAttributes & UE_XFERTYPE) {
2237         case UE_INTERRUPT:
2238         case UE_ISOCHRONOUS:
2239                 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2240                     XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2241                     max_frame_size));
2242                 break;
2243         case UE_CONTROL:
2244                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2245                 break;
2246         default:
2247                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2248                 break;
2249         }
2250
2251         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2252
2253 #ifdef USB_DEBUG
2254         xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2255 #endif
2256         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2257
2258         return (0);             /* success */
2259 }
2260
2261 static usb_error_t
2262 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2263 {
2264         struct xhci_endpoint_ext *pepext;
2265         struct usb_endpoint_ss_comp_descriptor *ecomp;
2266
2267         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2268             xfer->endpoint->edesc);
2269
2270         ecomp = xfer->endpoint->ecomp;
2271
2272         pepext->trb[0].dwTrb3 = 0;      /* halt any transfers */
2273         usb_pc_cpu_flush(pepext->page_cache);
2274
2275         return (xhci_configure_endpoint(xfer->xroot->udev,
2276             xfer->endpoint->edesc, pepext->physaddr,
2277             xfer->interval, xfer->max_packet_count,
2278             (ecomp != NULL) ? (ecomp->bmAttributes & 3) + 1 : 1,
2279             usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2280             xfer->max_frame_size));
2281 }
2282
2283 static usb_error_t
2284 xhci_configure_device(struct usb_device *udev)
2285 {
2286         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2287         struct usb_page_search buf_inp;
2288         struct usb_page_cache *pcinp;
2289         struct xhci_input_dev_ctx *pinp;
2290         struct usb_device *hubdev;
2291         uint32_t temp;
2292         uint32_t route;
2293         uint32_t rh_port;
2294         uint8_t is_hub;
2295         uint8_t index;
2296         uint8_t depth;
2297
2298         index = udev->controller_slot_id;
2299
2300         DPRINTF("index=%u\n", index);
2301
2302         pcinp = &sc->sc_hw.devs[index].input_pc;
2303
2304         usbd_get_page(pcinp, 0, &buf_inp);
2305
2306         pinp = buf_inp.buffer;
2307
2308         rh_port = 0;
2309         route = 0;
2310
2311         /* figure out route string and root HUB port number */
2312
2313         for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2314
2315                 if (hubdev->parent_hub == NULL)
2316                         break;
2317
2318                 depth = hubdev->parent_hub->depth;
2319
2320                 /*
2321                  * NOTE: HS/FS/LS devices and the SS root HUB can have
2322                  * more than 15 ports
2323                  */
2324
2325                 rh_port = hubdev->port_no;
2326
2327                 if (depth == 0)
2328                         break;
2329
2330                 if (rh_port > 15)
2331                         rh_port = 15;
2332
2333                 if (depth < 6)
2334                         route |= rh_port << (4 * (depth - 1));
2335         }
2336
2337         DPRINTF("Route=0x%08x\n", route);
2338
2339         temp = XHCI_SCTX_0_ROUTE_SET(route) |
2340             XHCI_SCTX_0_CTX_NUM_SET(
2341             sc->sc_hw.devs[index].context_num + 1);
2342
2343         switch (udev->speed) {
2344         case USB_SPEED_LOW:
2345                 temp |= XHCI_SCTX_0_SPEED_SET(2);
2346                 if (udev->parent_hs_hub != NULL &&
2347                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2348                     UDPROTO_HSHUBMTT) {
2349                         DPRINTF("Device inherits MTT\n");
2350                         temp |= XHCI_SCTX_0_MTT_SET(1);
2351                 }
2352                 break;
2353         case USB_SPEED_HIGH:
2354                 temp |= XHCI_SCTX_0_SPEED_SET(3);
2355                 if (sc->sc_hw.devs[index].nports != 0 &&
2356                     udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2357                         DPRINTF("HUB supports MTT\n");
2358                         temp |= XHCI_SCTX_0_MTT_SET(1);
2359                 }
2360                 break;
2361         case USB_SPEED_FULL:
2362                 temp |= XHCI_SCTX_0_SPEED_SET(1);
2363                 if (udev->parent_hs_hub != NULL &&
2364                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2365                     UDPROTO_HSHUBMTT) {
2366                         DPRINTF("Device inherits MTT\n");
2367                         temp |= XHCI_SCTX_0_MTT_SET(1);
2368                 }
2369                 break;
2370         default:
2371                 temp |= XHCI_SCTX_0_SPEED_SET(4);
2372                 break;
2373         }
2374
2375         is_hub = sc->sc_hw.devs[index].nports != 0 &&
2376             (udev->speed == USB_SPEED_SUPER ||
2377             udev->speed == USB_SPEED_HIGH);
2378
2379         if (is_hub)
2380                 temp |= XHCI_SCTX_0_HUB_SET(1);
2381
2382         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2383
2384         temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2385
2386         if (is_hub) {
2387                 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2388                     sc->sc_hw.devs[index].nports);
2389         }
2390
2391         switch (udev->speed) {
2392         case USB_SPEED_SUPER:
2393                 switch (sc->sc_hw.devs[index].state) {
2394                 case XHCI_ST_ADDRESSED:
2395                 case XHCI_ST_CONFIGURED:
2396                         /* enable power save */
2397                         temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2398                         break;
2399                 default:
2400                         /* disable power save */
2401                         break;
2402                 }
2403                 break;
2404         default:
2405                 break;
2406         }
2407
2408         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2409
2410         temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2411
2412         if (is_hub) {
2413                 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2414                     sc->sc_hw.devs[index].tt);
2415         }
2416
2417         hubdev = udev->parent_hs_hub;
2418
2419         /* check if we should activate the transaction translator */
2420         switch (udev->speed) {
2421         case USB_SPEED_FULL:
2422         case USB_SPEED_LOW:
2423                 if (hubdev != NULL) {
2424                         temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2425                             hubdev->controller_slot_id);
2426                         temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2427                             udev->hs_port_no);
2428                 }
2429                 break;
2430         default:
2431                 break;
2432         }
2433
2434         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2435
2436         temp = XHCI_SCTX_3_DEV_ADDR_SET(udev->address) |
2437             XHCI_SCTX_3_SLOT_STATE_SET(0);
2438
2439         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2440
2441 #ifdef USB_DEBUG
2442         xhci_dump_device(sc, &pinp->ctx_slot);
2443 #endif
2444         usb_pc_cpu_flush(pcinp);
2445
2446         return (0);             /* success */
2447 }
2448
2449 static usb_error_t
2450 xhci_alloc_device_ext(struct usb_device *udev)
2451 {
2452         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2453         struct usb_page_search buf_dev;
2454         struct usb_page_search buf_ep;
2455         struct xhci_trb *trb;
2456         struct usb_page_cache *pc;
2457         struct usb_page *pg;
2458         uint64_t addr;
2459         uint8_t index;
2460         uint8_t i;
2461
2462         index = udev->controller_slot_id;
2463
2464         pc = &sc->sc_hw.devs[index].device_pc;
2465         pg = &sc->sc_hw.devs[index].device_pg;
2466
2467         /* need to initialize the page cache */
2468         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2469
2470         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2471             (2 * sizeof(struct xhci_dev_ctx)) :
2472             sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2473                 goto error;
2474
2475         usbd_get_page(pc, 0, &buf_dev);
2476
2477         pc = &sc->sc_hw.devs[index].input_pc;
2478         pg = &sc->sc_hw.devs[index].input_pg;
2479
2480         /* need to initialize the page cache */
2481         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2482
2483         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2484             (2 * sizeof(struct xhci_input_dev_ctx)) :
2485             sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2486                 goto error;
2487         }
2488
2489         pc = &sc->sc_hw.devs[index].endpoint_pc;
2490         pg = &sc->sc_hw.devs[index].endpoint_pg;
2491
2492         /* need to initialize the page cache */
2493         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2494
2495         if (usb_pc_alloc_mem(pc, pg,
2496             sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) {
2497                 goto error;
2498         }
2499
2500         /* initialise all endpoint LINK TRBs */
2501
2502         for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2503
2504                 /* lookup endpoint TRB ring */
2505                 usbd_get_page(pc, (uintptr_t)&
2506                     ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep);
2507
2508                 /* get TRB pointer */
2509                 trb = buf_ep.buffer;
2510                 trb += XHCI_MAX_TRANSFERS - 1;
2511
2512                 /* get TRB start address */
2513                 addr = buf_ep.physaddr;
2514
2515                 /* create LINK TRB */
2516                 trb->qwTrb0 = htole64(addr);
2517                 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2518                 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2519                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2520         }
2521
2522         usb_pc_cpu_flush(pc);
2523
2524         xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2525
2526         return (0);
2527
2528 error:
2529         xhci_free_device_ext(udev);
2530
2531         return (USB_ERR_NOMEM);
2532 }
2533
2534 static void
2535 xhci_free_device_ext(struct usb_device *udev)
2536 {
2537         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2538         uint8_t index;
2539
2540         index = udev->controller_slot_id;
2541         xhci_set_slot_pointer(sc, index, 0);
2542
2543         usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2544         usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2545         usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc);
2546 }
2547
2548 static struct xhci_endpoint_ext *
2549 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2550 {
2551         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2552         struct xhci_endpoint_ext *pepext;
2553         struct usb_page_cache *pc;
2554         struct usb_page_search buf_ep;
2555         uint8_t epno;
2556         uint8_t index;
2557
2558         epno = edesc->bEndpointAddress;
2559         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2560                 epno |= UE_DIR_IN;
2561
2562         epno = XHCI_EPNO2EPID(epno);
2563
2564         index = udev->controller_slot_id;
2565
2566         pc = &sc->sc_hw.devs[index].endpoint_pc;
2567
2568         usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->trb[epno][0], &buf_ep);
2569
2570         pepext = &sc->sc_hw.devs[index].endp[epno];
2571         pepext->page_cache = pc;
2572         pepext->trb = buf_ep.buffer;
2573         pepext->physaddr = buf_ep.physaddr;
2574
2575         return (pepext);
2576 }
2577
2578 static void
2579 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2580 {
2581         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2582         uint8_t epno;
2583         uint8_t index;
2584
2585         epno = xfer->endpointno;
2586         if (xfer->flags_int.control_xfr)
2587                 epno |= UE_DIR_IN;
2588
2589         epno = XHCI_EPNO2EPID(epno);
2590         index = xfer->xroot->udev->controller_slot_id;
2591
2592         if (xfer->xroot->udev->flags.self_suspended == 0) {
2593                 XWRITE4(sc, door, XHCI_DOORBELL(index),
2594                     epno | XHCI_DB_SID_SET(/*xfer->stream_id*/ 0));
2595         }
2596 }
2597
2598 static void
2599 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2600 {
2601         struct xhci_endpoint_ext *pepext;
2602
2603         if (xfer->flags_int.bandwidth_reclaimed) {
2604                 xfer->flags_int.bandwidth_reclaimed = 0;
2605
2606                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2607                     xfer->endpoint->edesc);
2608
2609                 pepext->trb_used--;
2610
2611                 pepext->xfer[xfer->qh_pos] = NULL;
2612
2613                 if (error && pepext->trb_running != 0) {
2614                         pepext->trb_halted = 1;
2615                         pepext->trb_running = 0;
2616                 }
2617         }
2618 }
2619
2620 static usb_error_t
2621 xhci_transfer_insert(struct usb_xfer *xfer)
2622 {
2623         struct xhci_td *td_first;
2624         struct xhci_td *td_last;
2625         struct xhci_trb *trb_link;
2626         struct xhci_endpoint_ext *pepext;
2627         uint64_t addr;
2628         uint8_t i;
2629         uint8_t inext;
2630         uint8_t trb_limit;
2631
2632         DPRINTFN(8, "\n");
2633
2634         /* check if already inserted */
2635         if (xfer->flags_int.bandwidth_reclaimed) {
2636                 DPRINTFN(8, "Already in schedule\n");
2637                 return (0);
2638         }
2639
2640         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2641             xfer->endpoint->edesc);
2642
2643         td_first = xfer->td_transfer_first;
2644         td_last = xfer->td_transfer_last;
2645         addr = pepext->physaddr;
2646
2647         switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2648         case UE_CONTROL:
2649         case UE_INTERRUPT:
2650                 /* single buffered */
2651                 trb_limit = 1;
2652                 break;
2653         default:
2654                 /* multi buffered */
2655                 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2656                 break;
2657         }
2658
2659         if (pepext->trb_used >= trb_limit) {
2660                 DPRINTFN(8, "Too many TDs queued.\n");
2661                 return (USB_ERR_NOMEM);
2662         }
2663
2664         /* check for stopped condition, after putting transfer on interrupt queue */
2665         if (pepext->trb_running == 0) {
2666                 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2667
2668                 DPRINTFN(8, "Not running\n");
2669
2670                 /* start configuration */
2671                 (void)usb_proc_msignal(&sc->sc_config_proc,
2672                     &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2673                 return (0);
2674         }
2675
2676         pepext->trb_used++;
2677
2678         /* get current TRB index */
2679         i = pepext->trb_index;
2680
2681         /* get next TRB index */
2682         inext = (i + 1);
2683
2684         /* the last entry of the ring is a hardcoded link TRB */
2685         if (inext >= (XHCI_MAX_TRANSFERS - 1))
2686                 inext = 0;
2687
2688         /* compute terminating return address */
2689         addr += inext * sizeof(struct xhci_trb);
2690
2691         /* compute link TRB pointer */
2692         trb_link = td_last->td_trb + td_last->ntrb;
2693
2694         /* update next pointer of last link TRB */
2695         trb_link->qwTrb0 = htole64(addr);
2696         trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2697         trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2698             XHCI_TRB_3_CYCLE_BIT |
2699             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2700
2701 #ifdef USB_DEBUG
2702         xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2703 #endif
2704         usb_pc_cpu_flush(td_last->page_cache);
2705
2706         /* write ahead chain end marker */
2707
2708         pepext->trb[inext].qwTrb0 = 0;
2709         pepext->trb[inext].dwTrb2 = 0;
2710         pepext->trb[inext].dwTrb3 = 0;
2711
2712         /* update next pointer of link TRB */
2713
2714         pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2715         pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2716
2717 #ifdef USB_DEBUG
2718         xhci_dump_trb(&pepext->trb[i]);
2719 #endif
2720         usb_pc_cpu_flush(pepext->page_cache);
2721
2722         /* toggle cycle bit which activates the transfer chain */
2723
2724         pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2725             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2726
2727         usb_pc_cpu_flush(pepext->page_cache);
2728
2729         DPRINTF("qh_pos = %u\n", i);
2730
2731         pepext->xfer[i] = xfer;
2732
2733         xfer->qh_pos = i;
2734
2735         xfer->flags_int.bandwidth_reclaimed = 1;
2736
2737         pepext->trb_index = inext;
2738
2739         xhci_endpoint_doorbell(xfer);
2740
2741         return (0);
2742 }
2743
2744 static void
2745 xhci_root_intr(struct xhci_softc *sc)
2746 {
2747         uint16_t i;
2748
2749         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2750
2751         /* clear any old interrupt data */
2752         memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2753
2754         for (i = 1; i <= sc->sc_noport; i++) {
2755                 /* pick out CHANGE bits from the status register */
2756                 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
2757                     XHCI_PS_CSC | XHCI_PS_PEC |
2758                     XHCI_PS_OCC | XHCI_PS_WRC |
2759                     XHCI_PS_PRC | XHCI_PS_PLC |
2760                     XHCI_PS_CEC)) {
2761                         sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2762                         DPRINTF("port %d changed\n", i);
2763                 }
2764         }
2765         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2766             sizeof(sc->sc_hub_idata));
2767 }
2768
2769 /*------------------------------------------------------------------------*
2770  *      xhci_device_done - XHCI done handler
2771  *
2772  * NOTE: This function can be called two times in a row on
2773  * the same USB transfer. From close and from interrupt.
2774  *------------------------------------------------------------------------*/
2775 static void
2776 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
2777 {
2778         DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2779             xfer, xfer->endpoint, error);
2780
2781         /* remove transfer from HW queue */
2782         xhci_transfer_remove(xfer, error);
2783
2784         /* dequeue transfer and start next transfer */
2785         usbd_transfer_done(xfer, error);
2786 }
2787
2788 /*------------------------------------------------------------------------*
2789  * XHCI data transfer support (generic type)
2790  *------------------------------------------------------------------------*/
2791 static void
2792 xhci_device_generic_open(struct usb_xfer *xfer)
2793 {
2794         if (xfer->flags_int.isochronous_xfr) {
2795                 switch (xfer->xroot->udev->speed) {
2796                 case USB_SPEED_FULL:
2797                         break;
2798                 default:
2799                         usb_hs_bandwidth_alloc(xfer);
2800                         break;
2801                 }
2802         }
2803 }
2804
2805 static void
2806 xhci_device_generic_close(struct usb_xfer *xfer)
2807 {
2808         DPRINTF("\n");
2809
2810         xhci_device_done(xfer, USB_ERR_CANCELLED);
2811
2812         if (xfer->flags_int.isochronous_xfr) {
2813                 switch (xfer->xroot->udev->speed) {
2814                 case USB_SPEED_FULL:
2815                         break;
2816                 default:
2817                         usb_hs_bandwidth_free(xfer);
2818                         break;
2819                 }
2820         }
2821 }
2822
2823 static void
2824 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
2825     struct usb_xfer *enter_xfer)
2826 {
2827         struct usb_xfer *xfer;
2828
2829         /* check if there is a current transfer */
2830         xfer = ep->endpoint_q.curr;
2831         if (xfer == NULL)
2832                 return;
2833
2834         /*
2835          * Check if the current transfer is started and then pickup
2836          * the next one, if any. Else wait for next start event due to
2837          * block on failure feature.
2838          */
2839         if (!xfer->flags_int.bandwidth_reclaimed)
2840                 return;
2841
2842         xfer = TAILQ_FIRST(&ep->endpoint_q.head);
2843         if (xfer == NULL) {
2844                 /*
2845                  * In case of enter we have to consider that the
2846                  * transfer is queued by the USB core after the enter
2847                  * method is called.
2848                  */
2849                 xfer = enter_xfer;
2850
2851                 if (xfer == NULL)
2852                         return;
2853         }
2854
2855         /* try to multi buffer */
2856         xhci_transfer_insert(xfer);
2857 }
2858
2859 static void
2860 xhci_device_generic_enter(struct usb_xfer *xfer)
2861 {
2862         DPRINTF("\n");
2863
2864         /* setup TD's and QH */
2865         xhci_setup_generic_chain(xfer);
2866
2867         xhci_device_generic_multi_enter(xfer->endpoint, xfer);
2868 }
2869
2870 static void
2871 xhci_device_generic_start(struct usb_xfer *xfer)
2872 {
2873         DPRINTF("\n");
2874
2875         /* try to insert xfer on HW queue */
2876         xhci_transfer_insert(xfer);
2877
2878         /* try to multi buffer */
2879         xhci_device_generic_multi_enter(xfer->endpoint, NULL);
2880
2881         /* add transfer last on interrupt queue */
2882         usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
2883
2884         /* start timeout, if any */
2885         if (xfer->timeout != 0)
2886                 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
2887 }
2888
2889 struct usb_pipe_methods xhci_device_generic_methods =
2890 {
2891         .open = xhci_device_generic_open,
2892         .close = xhci_device_generic_close,
2893         .enter = xhci_device_generic_enter,
2894         .start = xhci_device_generic_start,
2895 };
2896
2897 /*------------------------------------------------------------------------*
2898  * xhci root HUB support
2899  *------------------------------------------------------------------------*
2900  * Simulate a hardware HUB by handling all the necessary requests.
2901  *------------------------------------------------------------------------*/
2902
2903 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
2904
2905 static const
2906 struct usb_device_descriptor xhci_devd =
2907 {
2908         .bLength = sizeof(xhci_devd),
2909         .bDescriptorType = UDESC_DEVICE,        /* type */
2910         HSETW(.bcdUSB, 0x0300),                 /* USB version */
2911         .bDeviceClass = UDCLASS_HUB,            /* class */
2912         .bDeviceSubClass = UDSUBCLASS_HUB,      /* subclass */
2913         .bDeviceProtocol = UDPROTO_SSHUB,       /* protocol */
2914         .bMaxPacketSize = 9,                    /* max packet size */
2915         HSETW(.idVendor, 0x0000),               /* vendor */
2916         HSETW(.idProduct, 0x0000),              /* product */
2917         HSETW(.bcdDevice, 0x0100),              /* device version */
2918         .iManufacturer = 1,
2919         .iProduct = 2,
2920         .iSerialNumber = 0,
2921         .bNumConfigurations = 1,                /* # of configurations */
2922 };
2923
2924 static const
2925 struct xhci_bos_desc xhci_bosd = {
2926         .bosd = {
2927                 .bLength = sizeof(xhci_bosd.bosd),
2928                 .bDescriptorType = UDESC_BOS,
2929                 HSETW(.wTotalLength, sizeof(xhci_bosd)),
2930                 .bNumDeviceCaps = 3,
2931         },
2932         .usb2extd = {
2933                 .bLength = sizeof(xhci_bosd.usb2extd),
2934                 .bDescriptorType = 1,
2935                 .bDevCapabilityType = 2,
2936                 .bmAttributes[0] = 2,
2937         },
2938         .usbdcd = {
2939                 .bLength = sizeof(xhci_bosd.usbdcd),
2940                 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
2941                 .bDevCapabilityType = 3,
2942                 .bmAttributes = 0, /* XXX */
2943                 HSETW(.wSpeedsSupported, 0x000C),
2944                 .bFunctionalitySupport = 8,
2945                 .bU1DevExitLat = 255,   /* dummy - not used */
2946                 .wU2DevExitLat = { 0x00, 0x08 },
2947         },
2948         .cidd = {
2949                 .bLength = sizeof(xhci_bosd.cidd),
2950                 .bDescriptorType = 1,
2951                 .bDevCapabilityType = 4,
2952                 .bReserved = 0,
2953                 .bContainerID = 0, /* XXX */
2954         },
2955 };
2956
2957 static const
2958 struct xhci_config_desc xhci_confd = {
2959         .confd = {
2960                 .bLength = sizeof(xhci_confd.confd),
2961                 .bDescriptorType = UDESC_CONFIG,
2962                 .wTotalLength[0] = sizeof(xhci_confd),
2963                 .bNumInterface = 1,
2964                 .bConfigurationValue = 1,
2965                 .iConfiguration = 0,
2966                 .bmAttributes = UC_SELF_POWERED,
2967                 .bMaxPower = 0          /* max power */
2968         },
2969         .ifcd = {
2970                 .bLength = sizeof(xhci_confd.ifcd),
2971                 .bDescriptorType = UDESC_INTERFACE,
2972                 .bNumEndpoints = 1,
2973                 .bInterfaceClass = UICLASS_HUB,
2974                 .bInterfaceSubClass = UISUBCLASS_HUB,
2975                 .bInterfaceProtocol = 0,
2976         },
2977         .endpd = {
2978                 .bLength = sizeof(xhci_confd.endpd),
2979                 .bDescriptorType = UDESC_ENDPOINT,
2980                 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
2981                 .bmAttributes = UE_INTERRUPT,
2982                 .wMaxPacketSize[0] = 2,         /* max 15 ports */
2983                 .bInterval = 255,
2984         },
2985         .endpcd = {
2986                 .bLength = sizeof(xhci_confd.endpcd),
2987                 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
2988                 .bMaxBurst = 0,
2989                 .bmAttributes = 0,
2990         },
2991 };
2992
2993 static const
2994 struct usb_hub_ss_descriptor xhci_hubd = {
2995         .bLength = sizeof(xhci_hubd),
2996         .bDescriptorType = UDESC_SS_HUB,
2997 };
2998
2999 static usb_error_t
3000 xhci_roothub_exec(struct usb_device *udev,
3001     struct usb_device_request *req, const void **pptr, uint16_t *plength)
3002 {
3003         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3004         const char *str_ptr;
3005         const void *ptr;
3006         uint32_t port;
3007         uint32_t v;
3008         uint16_t len;
3009         uint16_t i;
3010         uint16_t value;
3011         uint16_t index;
3012         uint8_t j;
3013         usb_error_t err;
3014
3015         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3016
3017         /* buffer reset */
3018         ptr = (const void *)&sc->sc_hub_desc;
3019         len = 0;
3020         err = 0;
3021
3022         value = UGETW(req->wValue);
3023         index = UGETW(req->wIndex);
3024
3025         DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3026             "wValue=0x%04x wIndex=0x%04x\n",
3027             req->bmRequestType, req->bRequest,
3028             UGETW(req->wLength), value, index);
3029
3030 #define C(x,y) ((x) | ((y) << 8))
3031         switch (C(req->bRequest, req->bmRequestType)) {
3032         case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3033         case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3034         case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3035                 /*
3036                  * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3037                  * for the integrated root hub.
3038                  */
3039                 break;
3040         case C(UR_GET_CONFIG, UT_READ_DEVICE):
3041                 len = 1;
3042                 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3043                 break;
3044         case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3045                 switch (value >> 8) {
3046                 case UDESC_DEVICE:
3047                         if ((value & 0xff) != 0) {
3048                                 err = USB_ERR_IOERROR;
3049                                 goto done;
3050                         }
3051                         len = sizeof(xhci_devd);
3052                         ptr = (const void *)&xhci_devd;
3053                         break;
3054
3055                 case UDESC_BOS:
3056                         if ((value & 0xff) != 0) {
3057                                 err = USB_ERR_IOERROR;
3058                                 goto done;
3059                         }
3060                         len = sizeof(xhci_bosd);
3061                         ptr = (const void *)&xhci_bosd;
3062                         break;
3063
3064                 case UDESC_CONFIG:
3065                         if ((value & 0xff) != 0) {
3066                                 err = USB_ERR_IOERROR;
3067                                 goto done;
3068                         }
3069                         len = sizeof(xhci_confd);
3070                         ptr = (const void *)&xhci_confd;
3071                         break;
3072
3073                 case UDESC_STRING:
3074                         switch (value & 0xff) {
3075                         case 0: /* Language table */
3076                                 str_ptr = "\001";
3077                                 break;
3078
3079                         case 1: /* Vendor */
3080                                 str_ptr = sc->sc_vendor;
3081                                 break;
3082
3083                         case 2: /* Product */
3084                                 str_ptr = "XHCI root HUB";
3085                                 break;
3086
3087                         default:
3088                                 str_ptr = "";
3089                                 break;
3090                         }
3091
3092                         len = usb_make_str_desc(
3093                             sc->sc_hub_desc.temp,
3094                             sizeof(sc->sc_hub_desc.temp),
3095                             str_ptr);
3096                         break;
3097
3098                 default:
3099                         err = USB_ERR_IOERROR;
3100                         goto done;
3101                 }
3102                 break;
3103         case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3104                 len = 1;
3105                 sc->sc_hub_desc.temp[0] = 0;
3106                 break;
3107         case C(UR_GET_STATUS, UT_READ_DEVICE):
3108                 len = 2;
3109                 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3110                 break;
3111         case C(UR_GET_STATUS, UT_READ_INTERFACE):
3112         case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3113                 len = 2;
3114                 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3115                 break;
3116         case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3117                 if (value >= XHCI_MAX_DEVICES) {
3118                         err = USB_ERR_IOERROR;
3119                         goto done;
3120                 }
3121                 break;
3122         case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3123                 if (value != 0 && value != 1) {
3124                         err = USB_ERR_IOERROR;
3125                         goto done;
3126                 }
3127                 sc->sc_conf = value;
3128                 break;
3129         case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3130                 break;
3131         case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3132         case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3133         case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3134                 err = USB_ERR_IOERROR;
3135                 goto done;
3136         case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3137                 break;
3138         case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3139                 break;
3140                 /* Hub requests */
3141         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3142                 break;
3143         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3144                 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3145
3146                 if ((index < 1) ||
3147                     (index > sc->sc_noport)) {
3148                         err = USB_ERR_IOERROR;
3149                         goto done;
3150                 }
3151                 port = XHCI_PORTSC(index);
3152
3153                 v = XREAD4(sc, oper, port);
3154                 i = XHCI_PS_PLS_GET(v);
3155                 v &= ~XHCI_PS_CLEAR;
3156
3157                 switch (value) {
3158                 case UHF_C_BH_PORT_RESET:
3159                         XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3160                         break;
3161                 case UHF_C_PORT_CONFIG_ERROR:
3162                         XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3163                         break;
3164                 case UHF_C_PORT_SUSPEND:
3165                 case UHF_C_PORT_LINK_STATE:
3166                         XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3167                         break;
3168                 case UHF_C_PORT_CONNECTION:
3169                         XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3170                         break;
3171                 case UHF_C_PORT_ENABLE:
3172                         XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3173                         break;
3174                 case UHF_C_PORT_OVER_CURRENT:
3175                         XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3176                         break;
3177                 case UHF_C_PORT_RESET:
3178                         XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3179                         break;
3180                 case UHF_PORT_ENABLE:
3181                         XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3182                         break;
3183                 case UHF_PORT_POWER:
3184                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3185                         break;
3186                 case UHF_PORT_INDICATOR:
3187                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3188                         break;
3189                 case UHF_PORT_SUSPEND:
3190
3191                         /* U3 -> U15 */
3192                         if (i == 3) {
3193                                 XWRITE4(sc, oper, port, v |
3194                                     XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3195                         }
3196
3197                         /* wait 20ms for resume sequence to complete */
3198                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3199
3200                         /* U0 */
3201                         XWRITE4(sc, oper, port, v |
3202                             XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3203                         break;
3204                 default:
3205                         err = USB_ERR_IOERROR;
3206                         goto done;
3207                 }
3208                 break;
3209
3210         case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3211                 if ((value & 0xff) != 0) {
3212                         err = USB_ERR_IOERROR;
3213                         goto done;
3214                 }
3215
3216                 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3217
3218                 sc->sc_hub_desc.hubd = xhci_hubd;
3219
3220                 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3221
3222                 if (XHCI_HCS0_PPC(v))
3223                         i = UHD_PWR_INDIVIDUAL;
3224                 else
3225                         i = UHD_PWR_GANGED;
3226
3227                 if (XHCI_HCS0_PIND(v))
3228                         i |= UHD_PORT_IND;
3229
3230                 i |= UHD_OC_INDIVIDUAL;
3231
3232                 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3233
3234                 /* see XHCI section 5.4.9: */
3235                 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3236
3237                 for (j = 1; j <= sc->sc_noport; j++) {
3238
3239                         v = XREAD4(sc, oper, XHCI_PORTSC(j));
3240                         if (v & XHCI_PS_DR) {
3241                                 sc->sc_hub_desc.hubd.
3242                                     DeviceRemovable[j / 8] |= 1U << (j % 8);
3243                         }
3244                 }
3245                 len = sc->sc_hub_desc.hubd.bLength;
3246                 break;
3247
3248         case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3249                 len = 16;
3250                 memset(sc->sc_hub_desc.temp, 0, 16);
3251                 break;
3252
3253         case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3254                 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3255
3256                 if ((index < 1) ||
3257                     (index > sc->sc_noport)) {
3258                         err = USB_ERR_IOERROR;
3259                         goto done;
3260                 }
3261
3262                 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3263
3264                 DPRINTFN(9, "port status=0x%08x\n", v);
3265
3266                 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3267
3268                 switch (XHCI_PS_SPEED_GET(v)) {
3269                 case 3:
3270                         i |= UPS_HIGH_SPEED;
3271                         break;
3272                 case 2:
3273                         i |= UPS_LOW_SPEED;
3274                         break;
3275                 case 1:
3276                         /* FULL speed */
3277                         break;
3278                 default:
3279                         i |= UPS_OTHER_SPEED;
3280                         break;
3281                 }
3282
3283                 if (v & XHCI_PS_CCS)
3284                         i |= UPS_CURRENT_CONNECT_STATUS;
3285                 if (v & XHCI_PS_PED)
3286                         i |= UPS_PORT_ENABLED;
3287                 if (v & XHCI_PS_OCA)
3288                         i |= UPS_OVERCURRENT_INDICATOR;
3289                 if (v & XHCI_PS_PR)
3290                         i |= UPS_RESET;
3291                 if (v & XHCI_PS_PP) {
3292                         /*
3293                          * The USB 3.0 RH is using the
3294                          * USB 2.0's power bit
3295                          */
3296                         i |= UPS_PORT_POWER;
3297                 }
3298                 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3299
3300                 i = 0;
3301                 if (v & XHCI_PS_CSC)
3302                         i |= UPS_C_CONNECT_STATUS;
3303                 if (v & XHCI_PS_PEC)
3304                         i |= UPS_C_PORT_ENABLED;
3305                 if (v & XHCI_PS_OCC)
3306                         i |= UPS_C_OVERCURRENT_INDICATOR;
3307                 if (v & XHCI_PS_WRC)
3308                         i |= UPS_C_BH_PORT_RESET;
3309                 if (v & XHCI_PS_PRC)
3310                         i |= UPS_C_PORT_RESET;
3311                 if (v & XHCI_PS_PLC)
3312                         i |= UPS_C_PORT_LINK_STATE;
3313                 if (v & XHCI_PS_CEC)
3314                         i |= UPS_C_PORT_CONFIG_ERROR;
3315
3316                 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3317                 len = sizeof(sc->sc_hub_desc.ps);
3318                 break;
3319
3320         case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3321                 err = USB_ERR_IOERROR;
3322                 goto done;
3323
3324         case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3325                 break;
3326
3327         case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3328
3329                 i = index >> 8;
3330                 index &= 0x00FF;
3331
3332                 if ((index < 1) ||
3333                     (index > sc->sc_noport)) {
3334                         err = USB_ERR_IOERROR;
3335                         goto done;
3336                 }
3337
3338                 port = XHCI_PORTSC(index);
3339                 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3340
3341                 switch (value) {
3342                 case UHF_PORT_U1_TIMEOUT:
3343                         if (XHCI_PS_SPEED_GET(v) != 4) {
3344                                 err = USB_ERR_IOERROR;
3345                                 goto done;
3346                         }
3347                         port = XHCI_PORTPMSC(index);
3348                         v = XREAD4(sc, oper, port);
3349                         v &= ~XHCI_PM3_U1TO_SET(0xFF);
3350                         v |= XHCI_PM3_U1TO_SET(i);
3351                         XWRITE4(sc, oper, port, v);
3352                         break;
3353                 case UHF_PORT_U2_TIMEOUT:
3354                         if (XHCI_PS_SPEED_GET(v) != 4) {
3355                                 err = USB_ERR_IOERROR;
3356                                 goto done;
3357                         }
3358                         port = XHCI_PORTPMSC(index);
3359                         v = XREAD4(sc, oper, port);
3360                         v &= ~XHCI_PM3_U2TO_SET(0xFF);
3361                         v |= XHCI_PM3_U2TO_SET(i);
3362                         XWRITE4(sc, oper, port, v);
3363                         break;
3364                 case UHF_BH_PORT_RESET:
3365                         XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3366                         break;
3367                 case UHF_PORT_LINK_STATE:
3368                         XWRITE4(sc, oper, port, v |
3369                             XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3370                         /* 4ms settle time */
3371                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3372                         break;
3373                 case UHF_PORT_ENABLE:
3374                         DPRINTFN(3, "set port enable %d\n", index);
3375                         break;
3376                 case UHF_PORT_SUSPEND:
3377                         DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3378                         j = XHCI_PS_SPEED_GET(v);
3379                         if ((j < 1) || (j > 3)) {
3380                                 /* non-supported speed */
3381                                 err = USB_ERR_IOERROR;
3382                                 goto done;
3383                         }
3384                         XWRITE4(sc, oper, port, v |
3385                             XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3386                         break;
3387                 case UHF_PORT_RESET:
3388                         DPRINTFN(6, "reset port %d\n", index);
3389                         XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3390                         break;
3391                 case UHF_PORT_POWER:
3392                         DPRINTFN(3, "set port power %d\n", index);
3393                         XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3394                         break;
3395                 case UHF_PORT_TEST:
3396                         DPRINTFN(3, "set port test %d\n", index);
3397                         break;
3398                 case UHF_PORT_INDICATOR:
3399                         DPRINTFN(3, "set port indicator %d\n", index);
3400
3401                         v &= ~XHCI_PS_PIC_SET(3);
3402                         v |= XHCI_PS_PIC_SET(1);
3403
3404                         XWRITE4(sc, oper, port, v);
3405                         break;
3406                 default:
3407                         err = USB_ERR_IOERROR;
3408                         goto done;
3409                 }
3410                 break;
3411
3412         case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3413         case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3414         case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3415         case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3416                 break;
3417         default:
3418                 err = USB_ERR_IOERROR;
3419                 goto done;
3420         }
3421 done:
3422         *plength = len;
3423         *pptr = ptr;
3424         return (err);
3425 }
3426
3427 static void
3428 xhci_xfer_setup(struct usb_setup_params *parm)
3429 {
3430         struct usb_page_search page_info;
3431         struct usb_page_cache *pc;
3432         struct xhci_softc *sc;
3433         struct usb_xfer *xfer;
3434         void *last_obj;
3435         uint32_t ntd;
3436         uint32_t n;
3437
3438         sc = XHCI_BUS2SC(parm->udev->bus);
3439         xfer = parm->curr_xfer;
3440
3441         /*
3442          * The proof for the "ntd" formula is illustrated like this:
3443          *
3444          * +------------------------------------+
3445          * |                                    |
3446          * |         |remainder ->              |
3447          * |   +-----+---+                      |
3448          * |   | xxx | x | frm 0                |
3449          * |   +-----+---++                     |
3450          * |   | xxx | xx | frm 1               |
3451          * |   +-----+----+                     |
3452          * |            ...                     |
3453          * +------------------------------------+
3454          *
3455          * "xxx" means a completely full USB transfer descriptor
3456          *
3457          * "x" and "xx" means a short USB packet
3458          *
3459          * For the remainder of an USB transfer modulo
3460          * "max_data_length" we need two USB transfer descriptors.
3461          * One to transfer the remaining data and one to finalise with
3462          * a zero length packet in case the "force_short_xfer" flag is
3463          * set. We only need two USB transfer descriptors in the case
3464          * where the transfer length of the first one is a factor of
3465          * "max_frame_size". The rest of the needed USB transfer
3466          * descriptors is given by the buffer size divided by the
3467          * maximum data payload.
3468          */
3469         parm->hc_max_packet_size = 0x400;
3470         parm->hc_max_packet_count = 16 * 3;
3471         parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3472
3473         xfer->flags_int.bdma_enable = 1;
3474
3475         usbd_transfer_setup_sub(parm);
3476
3477         if (xfer->flags_int.isochronous_xfr) {
3478                 ntd = ((1 * xfer->nframes)
3479                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3480         } else if (xfer->flags_int.control_xfr) {
3481                 ntd = ((2 * xfer->nframes) + 1  /* STATUS */
3482                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3483         } else {
3484                 ntd = ((2 * xfer->nframes)
3485                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3486         }
3487
3488 alloc_dma_set:
3489
3490         if (parm->err)
3491                 return;
3492
3493         /*
3494          * Allocate queue heads and transfer descriptors
3495          */
3496         last_obj = NULL;
3497
3498         if (usbd_transfer_setup_sub_malloc(
3499             parm, &pc, sizeof(struct xhci_td),
3500             XHCI_TD_ALIGN, ntd)) {
3501                 parm->err = USB_ERR_NOMEM;
3502                 return;
3503         }
3504         if (parm->buf) {
3505                 for (n = 0; n != ntd; n++) {
3506                         struct xhci_td *td;
3507
3508                         usbd_get_page(pc + n, 0, &page_info);
3509
3510                         td = page_info.buffer;
3511
3512                         /* init TD */
3513                         td->td_self = page_info.physaddr;
3514                         td->obj_next = last_obj;
3515                         td->page_cache = pc + n;
3516
3517                         last_obj = td;
3518
3519                         usb_pc_cpu_flush(pc + n);
3520                 }
3521         }
3522         xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3523
3524         if (!xfer->flags_int.curr_dma_set) {
3525                 xfer->flags_int.curr_dma_set = 1;
3526                 goto alloc_dma_set;
3527         }
3528 }
3529
3530 static usb_error_t
3531 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3532 {
3533         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3534         struct usb_page_search buf_inp;
3535         struct usb_device *udev;
3536         struct xhci_endpoint_ext *pepext;
3537         struct usb_endpoint_descriptor *edesc;
3538         struct usb_page_cache *pcinp;
3539         usb_error_t err;
3540         uint8_t index;
3541         uint8_t epno;
3542
3543         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3544             xfer->endpoint->edesc);
3545
3546         udev = xfer->xroot->udev;
3547         index = udev->controller_slot_id;
3548
3549         pcinp = &sc->sc_hw.devs[index].input_pc;
3550
3551         usbd_get_page(pcinp, 0, &buf_inp);
3552
3553         edesc = xfer->endpoint->edesc;
3554
3555         epno = edesc->bEndpointAddress;
3556
3557         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3558                 epno |= UE_DIR_IN;
3559
3560         epno = XHCI_EPNO2EPID(epno);
3561
3562         if (epno == 0)
3563                 return (USB_ERR_NO_PIPE);               /* invalid */
3564
3565         XHCI_CMD_LOCK(sc);
3566
3567         /* configure endpoint */
3568
3569         err = xhci_configure_endpoint_by_xfer(xfer);
3570
3571         if (err != 0) {
3572                 XHCI_CMD_UNLOCK(sc);
3573                 return (err);
3574         }
3575
3576         /*
3577          * Get the endpoint into the stopped state according to the
3578          * endpoint context state diagram in the XHCI specification:
3579          */
3580
3581         err = xhci_cmd_stop_ep(sc, 0, epno, index);
3582
3583         if (err != 0)
3584                 DPRINTF("Could not stop endpoint %u\n", epno);
3585
3586         err = xhci_cmd_reset_ep(sc, 0, epno, index);
3587
3588         if (err != 0)
3589                 DPRINTF("Could not reset endpoint %u\n", epno);
3590
3591         err = xhci_cmd_set_tr_dequeue_ptr(sc, pepext->physaddr |
3592             XHCI_EPCTX_2_DCS_SET(1), 0, epno, index);
3593
3594         if (err != 0)
3595                 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3596
3597         /*
3598          * Get the endpoint into the running state according to the
3599          * endpoint context state diagram in the XHCI specification:
3600          */
3601
3602         xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3603
3604         err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3605
3606         if (err != 0)
3607                 DPRINTF("Could not configure endpoint %u\n", epno);
3608
3609         err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3610
3611         if (err != 0)
3612                 DPRINTF("Could not configure endpoint %u\n", epno);
3613
3614         XHCI_CMD_UNLOCK(sc);
3615
3616         return (0);
3617 }
3618
3619 static void
3620 xhci_xfer_unsetup(struct usb_xfer *xfer)
3621 {
3622         return;
3623 }
3624
3625 static void
3626 xhci_start_dma_delay(struct usb_xfer *xfer)
3627 {
3628         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3629
3630         /* put transfer on interrupt queue (again) */
3631         usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3632
3633         (void)usb_proc_msignal(&sc->sc_config_proc,
3634             &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3635 }
3636
3637 static void
3638 xhci_configure_msg(struct usb_proc_msg *pm)
3639 {
3640         struct xhci_softc *sc;
3641         struct xhci_endpoint_ext *pepext;
3642         struct usb_xfer *xfer;
3643
3644         sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3645
3646 restart:
3647         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3648
3649                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3650                     xfer->endpoint->edesc);
3651
3652                 if ((pepext->trb_halted != 0) ||
3653                     (pepext->trb_running == 0)) {
3654
3655                         uint8_t i;
3656
3657                         /* clear halted and running */
3658                         pepext->trb_halted = 0;
3659                         pepext->trb_running = 0;
3660
3661                         /* nuke remaining buffered transfers */
3662
3663                         for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
3664                                 /*
3665                                  * NOTE: We need to use the timeout
3666                                  * error code here else existing
3667                                  * isochronous clients can get
3668                                  * confused:
3669                                  */
3670                                 if (pepext->xfer[i] != NULL) {
3671                                         xhci_device_done(pepext->xfer[i],
3672                                             USB_ERR_TIMEOUT);
3673                                 }
3674                         }
3675
3676                         /*
3677                          * NOTE: The USB transfer cannot vanish in
3678                          * this state!
3679                          */
3680
3681                         USB_BUS_UNLOCK(&sc->sc_bus);
3682
3683                         xhci_configure_reset_endpoint(xfer);
3684
3685                         USB_BUS_LOCK(&sc->sc_bus);
3686
3687                         /* check if halted is still cleared */
3688                         if (pepext->trb_halted == 0) {
3689                                 pepext->trb_running = 1;
3690                                 pepext->trb_index = 0;
3691                         }
3692                         goto restart;
3693                 }
3694
3695                 if (xfer->flags_int.did_dma_delay) {
3696
3697                         /* remove transfer from interrupt queue (again) */
3698                         usbd_transfer_dequeue(xfer);
3699
3700                         /* we are finally done */
3701                         usb_dma_delay_done_cb(xfer);
3702
3703                         /* queue changed - restart */
3704                         goto restart;
3705                 }
3706         }
3707
3708         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3709
3710                 /* try to insert xfer on HW queue */
3711                 xhci_transfer_insert(xfer);
3712
3713                 /* try to multi buffer */
3714                 xhci_device_generic_multi_enter(xfer->endpoint, NULL);
3715         }
3716 }
3717
3718 static void
3719 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3720     struct usb_endpoint *ep)
3721 {
3722         struct xhci_endpoint_ext *pepext;
3723
3724         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3725             ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
3726
3727         if (udev->flags.usb_mode != USB_MODE_HOST) {
3728                 /* not supported */
3729                 return;
3730         }
3731         if (udev->parent_hub == NULL) {
3732                 /* root HUB has special endpoint handling */
3733                 return;
3734         }
3735
3736         ep->methods = &xhci_device_generic_methods;
3737
3738         pepext = xhci_get_endpoint_ext(udev, edesc);
3739
3740         USB_BUS_LOCK(udev->bus);
3741         pepext->trb_halted = 1;
3742         pepext->trb_running = 0;
3743         USB_BUS_UNLOCK(udev->bus);
3744 }
3745
3746 static void
3747 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
3748 {
3749
3750 }
3751
3752 static void
3753 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3754 {
3755         struct xhci_endpoint_ext *pepext;
3756
3757         DPRINTF("\n");
3758
3759         if (udev->flags.usb_mode != USB_MODE_HOST) {
3760                 /* not supported */
3761                 return;
3762         }
3763         if (udev->parent_hub == NULL) {
3764                 /* root HUB has special endpoint handling */
3765                 return;
3766         }
3767
3768         pepext = xhci_get_endpoint_ext(udev, ep->edesc);
3769
3770         USB_BUS_LOCK(udev->bus);
3771         pepext->trb_halted = 1;
3772         pepext->trb_running = 0;
3773         USB_BUS_UNLOCK(udev->bus);
3774 }
3775
3776 static usb_error_t
3777 xhci_device_init(struct usb_device *udev)
3778 {
3779         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3780         usb_error_t err;
3781         uint8_t temp;
3782
3783         /* no init for root HUB */
3784         if (udev->parent_hub == NULL)
3785                 return (0);
3786
3787         XHCI_CMD_LOCK(sc);
3788
3789         /* set invalid default */
3790
3791         udev->controller_slot_id = sc->sc_noslot + 1;
3792
3793         /* try to get a new slot ID from the XHCI */
3794
3795         err = xhci_cmd_enable_slot(sc, &temp);
3796
3797         if (err) {
3798                 XHCI_CMD_UNLOCK(sc);
3799                 return (err);
3800         }
3801
3802         if (temp > sc->sc_noslot) {
3803                 XHCI_CMD_UNLOCK(sc);
3804                 return (USB_ERR_BAD_ADDRESS);
3805         }
3806
3807         if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
3808                 DPRINTF("slot %u already allocated.\n", temp);
3809                 XHCI_CMD_UNLOCK(sc);
3810                 return (USB_ERR_BAD_ADDRESS);
3811         }
3812
3813         /* store slot ID for later reference */
3814
3815         udev->controller_slot_id = temp;
3816
3817         /* reset data structure */
3818
3819         memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
3820
3821         /* set mark slot allocated */
3822
3823         sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
3824
3825         err = xhci_alloc_device_ext(udev);
3826
3827         XHCI_CMD_UNLOCK(sc);
3828
3829         /* get device into default state */
3830
3831         if (err == 0)
3832                 err = xhci_set_address(udev, NULL, 0);
3833
3834         return (err);
3835 }
3836
3837 static void
3838 xhci_device_uninit(struct usb_device *udev)
3839 {
3840         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3841         uint8_t index;
3842
3843         /* no init for root HUB */
3844         if (udev->parent_hub == NULL)
3845                 return;
3846
3847         XHCI_CMD_LOCK(sc);
3848
3849         index = udev->controller_slot_id;
3850
3851         if (index <= sc->sc_noslot) {
3852                 xhci_cmd_disable_slot(sc, index);
3853                 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
3854
3855                 /* free device extension */
3856                 xhci_free_device_ext(udev);
3857         }
3858
3859         XHCI_CMD_UNLOCK(sc);
3860 }
3861
3862 static void
3863 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
3864 {
3865         /*
3866          * Wait until the hardware has finished any possible use of
3867          * the transfer descriptor(s)
3868          */
3869         *pus = 2048;                    /* microseconds */
3870 }
3871
3872 static void
3873 xhci_device_resume(struct usb_device *udev)
3874 {
3875         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3876         uint8_t index;
3877         uint8_t n;
3878         uint8_t p;
3879
3880         DPRINTF("\n");
3881
3882         /* check for root HUB */
3883         if (udev->parent_hub == NULL)
3884                 return;
3885
3886         index = udev->controller_slot_id;
3887
3888         XHCI_CMD_LOCK(sc);
3889
3890         /* blindly resume all endpoints */
3891
3892         USB_BUS_LOCK(udev->bus);
3893
3894         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
3895                 for (p = 0; p != 1 /*XHCI_MAX_STREAMS*/; p++) {
3896                         XWRITE4(sc, door, XHCI_DOORBELL(index),
3897                             n | XHCI_DB_SID_SET(p));
3898                 }
3899         }
3900
3901         USB_BUS_UNLOCK(udev->bus);
3902
3903         XHCI_CMD_UNLOCK(sc);
3904 }
3905
3906 static void
3907 xhci_device_suspend(struct usb_device *udev)
3908 {
3909         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3910         uint8_t index;
3911         uint8_t n;
3912         usb_error_t err;
3913
3914         DPRINTF("\n");
3915
3916         /* check for root HUB */
3917         if (udev->parent_hub == NULL)
3918                 return;
3919
3920         index = udev->controller_slot_id;
3921
3922         XHCI_CMD_LOCK(sc);
3923
3924         /* blindly suspend all endpoints */
3925
3926         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
3927                 err = xhci_cmd_stop_ep(sc, 1, n, index);
3928                 if (err != 0) {
3929                         DPRINTF("Failed to suspend endpoint "
3930                             "%u on slot %u (ignored).\n", n, index);
3931                 }
3932         }
3933
3934         XHCI_CMD_UNLOCK(sc);
3935 }
3936
3937 static void
3938 xhci_set_hw_power(struct usb_bus *bus)
3939 {
3940         DPRINTF("\n");
3941 }
3942
3943 static void
3944 xhci_device_state_change(struct usb_device *udev)
3945 {
3946         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3947         struct usb_page_search buf_inp;
3948         usb_error_t err;
3949         uint8_t index;
3950
3951         /* check for root HUB */
3952         if (udev->parent_hub == NULL)
3953                 return;
3954
3955         index = udev->controller_slot_id;
3956
3957         DPRINTF("\n");
3958
3959         if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
3960                 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
3961                     &sc->sc_hw.devs[index].tt);
3962                 if (err != 0)
3963                         sc->sc_hw.devs[index].nports = 0;
3964         }
3965
3966         XHCI_CMD_LOCK(sc);
3967
3968         switch (usb_get_device_state(udev)) {
3969         case USB_STATE_POWERED:
3970                 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
3971                         break;
3972
3973                 /* set default state */
3974                 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
3975
3976                 /* reset number of contexts */
3977                 sc->sc_hw.devs[index].context_num = 0;
3978
3979                 err = xhci_cmd_reset_dev(sc, index);
3980
3981                 if (err != 0) {
3982                         DPRINTF("Device reset failed "
3983                             "for slot %u.\n", index);
3984                 }
3985                 break;
3986
3987         case USB_STATE_ADDRESSED:
3988                 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
3989                         break;
3990
3991                 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
3992
3993                 err = xhci_cmd_configure_ep(sc, 0, 1, index);
3994
3995                 if (err) {
3996                         DPRINTF("Failed to deconfigure "
3997                             "slot %u.\n", index);
3998                 }
3999                 break;
4000
4001         case USB_STATE_CONFIGURED:
4002                 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4003                         break;
4004
4005                 /* set configured state */
4006                 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4007
4008                 /* reset number of contexts */
4009                 sc->sc_hw.devs[index].context_num = 0;
4010
4011                 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4012
4013                 xhci_configure_mask(udev, 3, 0);
4014
4015                 err = xhci_configure_device(udev);
4016                 if (err != 0) {
4017                         DPRINTF("Could not configure device "
4018                             "at slot %u.\n", index);
4019                 }
4020
4021                 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4022                 if (err != 0) {
4023                         DPRINTF("Could not evaluate device "
4024                             "context at slot %u.\n", index);
4025                 }
4026                 break;
4027
4028         default:
4029                 break;
4030         }
4031         XHCI_CMD_UNLOCK(sc);
4032 }
4033
4034 struct usb_bus_methods xhci_bus_methods = {
4035         .endpoint_init = xhci_ep_init,
4036         .endpoint_uninit = xhci_ep_uninit,
4037         .xfer_setup = xhci_xfer_setup,
4038         .xfer_unsetup = xhci_xfer_unsetup,
4039         .get_dma_delay = xhci_get_dma_delay,
4040         .device_init = xhci_device_init,
4041         .device_uninit = xhci_device_uninit,
4042         .device_resume = xhci_device_resume,
4043         .device_suspend = xhci_device_suspend,
4044         .set_hw_power = xhci_set_hw_power,
4045         .roothub_exec = xhci_roothub_exec,
4046         .xfer_poll = xhci_do_poll,
4047         .start_dma_delay = xhci_start_dma_delay,
4048         .set_address = xhci_set_address,
4049         .clear_stall = xhci_ep_clear_stall,
4050         .device_state_change = xhci_device_state_change,
4051         .set_hw_power_sleep = xhci_set_hw_power_sleep,
4052 };