2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
29 * The XHCI 1.0 spec can be found at
30 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
31 * and the USB 3.0 spec at
32 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
36 * A few words about the design implementation: This driver emulates
37 * the concept about TDs which is found in EHCI specification. This
38 * way we avoid too much diveration among USB drivers.
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
44 #include <sys/stdint.h>
45 #include <sys/stddef.h>
46 #include <sys/param.h>
47 #include <sys/queue.h>
48 #include <sys/types.h>
49 #include <sys/systm.h>
50 #include <sys/kernel.h>
52 #include <sys/module.h>
54 #include <sys/mutex.h>
55 #include <sys/condvar.h>
56 #include <sys/sysctl.h>
58 #include <sys/unistd.h>
59 #include <sys/callout.h>
60 #include <sys/malloc.h>
63 #include <dev/usb/usb.h>
64 #include <dev/usb/usbdi.h>
66 #define USB_DEBUG_VAR xhcidebug
68 #include <dev/usb/usb_core.h>
69 #include <dev/usb/usb_debug.h>
70 #include <dev/usb/usb_busdma.h>
71 #include <dev/usb/usb_process.h>
72 #include <dev/usb/usb_transfer.h>
73 #include <dev/usb/usb_device.h>
74 #include <dev/usb/usb_hub.h>
75 #include <dev/usb/usb_util.h>
77 #include <dev/usb/usb_controller.h>
78 #include <dev/usb/usb_bus.h>
79 #include <dev/usb/controller/xhci.h>
80 #include <dev/usb/controller/xhcireg.h>
82 #define XHCI_BUS2SC(bus) \
83 ((struct xhci_softc *)(((uint8_t *)(bus)) - \
84 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
90 SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
91 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
92 &xhcidebug, 0, "Debug level");
93 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
94 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN,
95 &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller");
96 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
99 #define XHCI_INTR_ENDPT 1
101 struct xhci_std_temp {
102 struct xhci_softc *sc;
103 struct usb_page_cache *pc;
105 struct xhci_td *td_next;
108 uint32_t max_packet_size;
120 uint8_t do_isoc_sync;
123 static void xhci_do_poll(struct usb_bus *);
124 static void xhci_device_done(struct usb_xfer *, usb_error_t);
125 static void xhci_root_intr(struct xhci_softc *);
126 static void xhci_free_device_ext(struct usb_device *);
127 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
128 struct usb_endpoint_descriptor *);
129 static usb_proc_callback_t xhci_configure_msg;
130 static usb_error_t xhci_configure_device(struct usb_device *);
131 static usb_error_t xhci_configure_endpoint(struct usb_device *,
132 struct usb_endpoint_descriptor *, uint64_t, uint16_t,
133 uint8_t, uint8_t, uint8_t, uint16_t, uint16_t);
134 static usb_error_t xhci_configure_mask(struct usb_device *,
136 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
138 static void xhci_endpoint_doorbell(struct usb_xfer *);
139 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
140 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
141 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
143 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
146 extern struct usb_bus_methods xhci_bus_methods;
150 xhci_dump_trb(struct xhci_trb *trb)
152 DPRINTFN(5, "trb = %p\n", trb);
153 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
154 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
155 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
159 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
161 DPRINTFN(5, "pep = %p\n", pep);
162 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
163 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
164 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
165 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
166 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
167 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
168 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
172 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
174 DPRINTFN(5, "psl = %p\n", psl);
175 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
176 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
177 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
178 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
183 xhci_get_port_route(void)
186 return (0xFFFFFFFFU ^ ((uint32_t)xhciroute));
188 return (0xFFFFFFFFU);
193 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
195 struct xhci_softc *sc = XHCI_BUS2SC(bus);
198 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
199 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
201 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
202 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
204 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) {
205 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
206 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
211 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
213 if (sc->sc_ctx_is_64_byte) {
215 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
216 /* all contexts are initially 32-bytes */
217 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
218 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
224 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
226 if (sc->sc_ctx_is_64_byte) {
228 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
229 /* all contexts are initially 32-bytes */
230 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
231 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
233 return (le32toh(*ptr));
237 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
239 if (sc->sc_ctx_is_64_byte) {
241 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
242 /* all contexts are initially 32-bytes */
243 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
244 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
251 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
253 if (sc->sc_ctx_is_64_byte) {
255 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
256 /* all contexts are initially 32-bytes */
257 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
258 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
260 return (le64toh(*ptr));
265 xhci_start_controller(struct xhci_softc *sc)
267 struct usb_page_search buf_res;
268 struct xhci_hw_root *phwr;
269 struct xhci_dev_ctx_addr *pdctxa;
277 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
278 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
279 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
281 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
282 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
283 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
285 sc->sc_event_ccs = 1;
286 sc->sc_event_idx = 0;
287 sc->sc_command_ccs = 1;
288 sc->sc_command_idx = 0;
290 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
292 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
294 DPRINTF("HCS0 = 0x%08x\n", temp);
296 if (XHCI_HCS0_CSZ(temp)) {
297 sc->sc_ctx_is_64_byte = 1;
298 device_printf(sc->sc_bus.parent, "64 byte context size.\n");
300 sc->sc_ctx_is_64_byte = 0;
301 device_printf(sc->sc_bus.parent, "32 byte context size.\n");
304 /* Reset controller */
305 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
307 for (i = 0; i != 100; i++) {
308 usb_pause_mtx(NULL, hz / 100);
309 temp = XREAD4(sc, oper, XHCI_USBCMD) &
310 (XHCI_CMD_HCRST | XHCI_STS_CNR);
316 device_printf(sc->sc_bus.parent, "Controller "
318 return (USB_ERR_IOERROR);
321 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
322 device_printf(sc->sc_bus.parent, "Controller does "
323 "not support 4K page size.\n");
324 return (USB_ERR_IOERROR);
327 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
329 i = XHCI_HCS1_N_PORTS(temp);
332 device_printf(sc->sc_bus.parent, "Invalid number "
333 "of ports: %u\n", i);
334 return (USB_ERR_IOERROR);
338 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
340 if (sc->sc_noslot > XHCI_MAX_DEVICES)
341 sc->sc_noslot = XHCI_MAX_DEVICES;
343 /* setup number of device slots */
345 DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
346 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
348 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
350 DPRINTF("Max slots: %u\n", sc->sc_noslot);
352 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
354 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
356 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
357 device_printf(sc->sc_bus.parent, "XHCI request "
358 "too many scratchpads\n");
359 return (USB_ERR_NOMEM);
362 DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
364 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
366 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
367 XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
369 temp = XREAD4(sc, oper, XHCI_USBSTS);
371 /* clear interrupts */
372 XWRITE4(sc, oper, XHCI_USBSTS, temp);
373 /* disable all device notifications */
374 XWRITE4(sc, oper, XHCI_DNCTRL, 0);
376 /* setup device context base address */
377 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
378 pdctxa = buf_res.buffer;
379 memset(pdctxa, 0, sizeof(*pdctxa));
381 addr = buf_res.physaddr;
382 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
384 /* slot 0 points to the table of scratchpad pointers */
385 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
387 for (i = 0; i != sc->sc_noscratch; i++) {
388 struct usb_page_search buf_scp;
389 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
390 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
393 addr = buf_res.physaddr;
395 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
396 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
397 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
398 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
400 /* Setup event table size */
402 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
404 DPRINTF("HCS2=0x%08x\n", temp);
406 temp = XHCI_HCS2_ERST_MAX(temp);
408 if (temp > XHCI_MAX_RSEG)
409 temp = XHCI_MAX_RSEG;
411 sc->sc_erst_max = temp;
413 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
414 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp);
416 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp));
418 /* Setup interrupt rate */
419 XWRITE4(sc, runt, XHCI_IMOD(0), XHCI_IMOD_DEFAULT);
421 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
423 phwr = buf_res.buffer;
424 addr = buf_res.physaddr;
425 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
427 /* reset hardware root structure */
428 memset(phwr, 0, sizeof(*phwr));
430 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
431 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
433 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
435 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
436 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
438 addr = (uint64_t)buf_res.physaddr;
440 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
442 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
443 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
445 /* Setup interrupter registers */
447 temp = XREAD4(sc, runt, XHCI_IMAN(0));
448 temp |= XHCI_IMAN_INTR_ENA;
449 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
451 /* setup command ring control base address */
452 addr = buf_res.physaddr;
453 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
455 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
457 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
458 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
460 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
462 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
465 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
466 XHCI_CMD_INTE | XHCI_CMD_HSEE);
468 for (i = 0; i != 100; i++) {
469 usb_pause_mtx(NULL, hz / 100);
470 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
475 XWRITE4(sc, oper, XHCI_USBCMD, 0);
476 device_printf(sc->sc_bus.parent, "Run timeout.\n");
477 return (USB_ERR_IOERROR);
480 /* catch any lost interrupts */
481 xhci_do_poll(&sc->sc_bus);
487 xhci_halt_controller(struct xhci_softc *sc)
495 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
496 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
497 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
499 /* Halt controller */
500 XWRITE4(sc, oper, XHCI_USBCMD, 0);
502 for (i = 0; i != 100; i++) {
503 usb_pause_mtx(NULL, hz / 100);
504 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
510 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
511 return (USB_ERR_IOERROR);
517 xhci_init(struct xhci_softc *sc, device_t self)
519 /* initialise some bus fields */
520 sc->sc_bus.parent = self;
522 /* set the bus revision */
523 sc->sc_bus.usbrev = USB_REV_3_0;
525 /* set up the bus struct */
526 sc->sc_bus.methods = &xhci_bus_methods;
528 /* setup devices array */
529 sc->sc_bus.devices = sc->sc_devices;
530 sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
532 /* setup command queue mutex and condition varible */
533 cv_init(&sc->sc_cmd_cv, "CMDQ");
534 sx_init(&sc->sc_cmd_sx, "CMDQ lock");
536 /* get all DMA memory */
537 if (usb_bus_mem_alloc_all(&sc->sc_bus,
538 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
542 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
543 sc->sc_config_msg[0].bus = &sc->sc_bus;
544 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
545 sc->sc_config_msg[1].bus = &sc->sc_bus;
547 if (usb_proc_create(&sc->sc_config_proc,
548 &sc->sc_bus.bus_mtx, device_get_nameunit(self), USB_PRI_MED)) {
549 printf("WARNING: Creation of XHCI configure "
550 "callback process failed.\n");
556 xhci_uninit(struct xhci_softc *sc)
558 usb_proc_free(&sc->sc_config_proc);
560 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
562 cv_destroy(&sc->sc_cmd_cv);
563 sx_destroy(&sc->sc_cmd_sx);
567 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
569 struct xhci_softc *sc = XHCI_BUS2SC(bus);
572 case USB_HW_POWER_SUSPEND:
573 DPRINTF("Stopping the XHCI\n");
574 xhci_halt_controller(sc);
576 case USB_HW_POWER_SHUTDOWN:
577 DPRINTF("Stopping the XHCI\n");
578 xhci_halt_controller(sc);
580 case USB_HW_POWER_RESUME:
581 DPRINTF("Starting the XHCI\n");
582 xhci_start_controller(sc);
590 xhci_generic_done_sub(struct usb_xfer *xfer)
593 struct xhci_td *td_alt_next;
597 td = xfer->td_transfer_cache;
598 td_alt_next = td->alt_next;
600 if (xfer->aframes != xfer->nframes)
601 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
605 usb_pc_cpu_invalidate(td->page_cache);
610 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
611 xfer, (unsigned int)xfer->aframes,
612 (unsigned int)xfer->nframes,
613 (unsigned int)len, (unsigned int)td->len,
614 (unsigned int)status);
617 * Verify the status length and
618 * add the length to "frlengths[]":
621 /* should not happen */
622 DPRINTF("Invalid status length, "
623 "0x%04x/0x%04x bytes\n", len, td->len);
624 status = XHCI_TRB_ERROR_LENGTH;
625 } else if (xfer->aframes != xfer->nframes) {
626 xfer->frlengths[xfer->aframes] += td->len - len;
628 /* Check for last transfer */
629 if (((void *)td) == xfer->td_transfer_last) {
633 /* Check for transfer error */
634 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
635 status != XHCI_TRB_ERROR_SUCCESS) {
636 /* the transfer is finished */
640 /* Check for short transfer */
642 if (xfer->flags_int.short_frames_ok ||
643 xfer->flags_int.isochronous_xfr ||
644 xfer->flags_int.control_xfr) {
645 /* follow alt next */
648 /* the transfer is finished */
655 if (td->alt_next != td_alt_next) {
656 /* this USB frame is complete */
661 /* update transfer cache */
663 xfer->td_transfer_cache = td;
665 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
666 (status != XHCI_TRB_ERROR_SHORT_PKT &&
667 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
668 USB_ERR_NORMAL_COMPLETION);
672 xhci_generic_done(struct usb_xfer *xfer)
676 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
677 xfer, xfer->endpoint);
681 xfer->td_transfer_cache = xfer->td_transfer_first;
683 if (xfer->flags_int.control_xfr) {
685 if (xfer->flags_int.control_hdr)
686 err = xhci_generic_done_sub(xfer);
690 if (xfer->td_transfer_cache == NULL)
694 while (xfer->aframes != xfer->nframes) {
696 err = xhci_generic_done_sub(xfer);
699 if (xfer->td_transfer_cache == NULL)
703 if (xfer->flags_int.control_xfr &&
704 !xfer->flags_int.control_act)
705 err = xhci_generic_done_sub(xfer);
707 /* transfer is complete */
708 xhci_device_done(xfer, err);
712 xhci_activate_transfer(struct usb_xfer *xfer)
716 td = xfer->td_transfer_cache;
718 usb_pc_cpu_invalidate(td->page_cache);
720 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
722 /* activate the transfer */
724 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
725 usb_pc_cpu_flush(td->page_cache);
727 xhci_endpoint_doorbell(xfer);
732 xhci_skip_transfer(struct usb_xfer *xfer)
735 struct xhci_td *td_last;
737 td = xfer->td_transfer_cache;
738 td_last = xfer->td_transfer_last;
742 usb_pc_cpu_invalidate(td->page_cache);
744 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
746 usb_pc_cpu_invalidate(td_last->page_cache);
748 /* copy LINK TRB to current waiting location */
750 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
751 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
752 usb_pc_cpu_flush(td->page_cache);
754 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
755 usb_pc_cpu_flush(td->page_cache);
757 xhci_endpoint_doorbell(xfer);
761 /*------------------------------------------------------------------------*
762 * xhci_check_transfer
763 *------------------------------------------------------------------------*/
765 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
778 td_event = le64toh(trb->qwTrb0);
779 temp = le32toh(trb->dwTrb2);
781 remainder = XHCI_TRB_2_REM_GET(temp);
782 status = XHCI_TRB_2_ERROR_GET(temp);
784 temp = le32toh(trb->dwTrb3);
785 epno = XHCI_TRB_3_EP_GET(temp);
786 index = XHCI_TRB_3_SLOT_GET(temp);
788 /* check if error means halted */
789 halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
790 status != XHCI_TRB_ERROR_SUCCESS);
792 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n",
793 index, epno, remainder, status);
795 if (index > sc->sc_noslot) {
796 DPRINTF("Invalid slot.\n");
800 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
801 DPRINTF("Invalid endpoint.\n");
805 /* try to find the USB transfer that generated the event */
806 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
807 struct usb_xfer *xfer;
809 struct xhci_endpoint_ext *pepext;
811 pepext = &sc->sc_hw.devs[index].endp[epno];
813 xfer = pepext->xfer[i];
817 td = xfer->td_transfer_cache;
819 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
821 (long long)td->td_self,
822 (long long)td->td_self + sizeof(td->td_trb));
825 * NOTE: Some XHCI implementations might not trigger
826 * an event on the last LINK TRB so we need to
827 * consider both the last and second last event
828 * address as conditions for a successful transfer.
830 * NOTE: We assume that the XHCI will only trigger one
831 * event per chain of TRBs.
834 offset = td_event - td->td_self;
837 offset < (int64_t)sizeof(td->td_trb)) {
839 usb_pc_cpu_invalidate(td->page_cache);
841 /* compute rest of remainder, if any */
842 for (i = (offset / 16) + 1; i < td->ntrb; i++) {
843 temp = le32toh(td->td_trb[i].dwTrb2);
844 remainder += XHCI_TRB_2_BYTES_GET(temp);
847 DPRINTFN(5, "New remainder: %u\n", remainder);
849 /* clear isochronous transfer errors */
850 if (xfer->flags_int.isochronous_xfr) {
853 status = XHCI_TRB_ERROR_SUCCESS;
858 /* "td->remainder" is verified later */
859 td->remainder = remainder;
862 usb_pc_cpu_flush(td->page_cache);
865 * 1) Last transfer descriptor makes the
868 if (((void *)td) == xfer->td_transfer_last) {
869 DPRINTF("TD is last\n");
870 xhci_generic_done(xfer);
875 * 2) Any kind of error makes the transfer
879 DPRINTF("TD has I/O error\n");
880 xhci_generic_done(xfer);
885 * 3) If there is no alternate next transfer,
886 * a short packet also makes the transfer done
888 if (td->remainder > 0) {
889 DPRINTF("TD has short pkt\n");
890 if (xfer->flags_int.short_frames_ok ||
891 xfer->flags_int.isochronous_xfr ||
892 xfer->flags_int.control_xfr) {
893 /* follow the alt next */
894 xfer->td_transfer_cache = td->alt_next;
895 xhci_activate_transfer(xfer);
898 xhci_skip_transfer(xfer);
899 xhci_generic_done(xfer);
904 * 4) Transfer complete - go to next TD
906 DPRINTF("Following next TD\n");
907 xfer->td_transfer_cache = td->obj_next;
908 xhci_activate_transfer(xfer);
909 break; /* there should only be one match */
915 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
917 if (sc->sc_cmd_addr == trb->qwTrb0) {
918 DPRINTF("Received command event\n");
919 sc->sc_cmd_result[0] = trb->dwTrb2;
920 sc->sc_cmd_result[1] = trb->dwTrb3;
921 cv_signal(&sc->sc_cmd_cv);
926 xhci_interrupt_poll(struct xhci_softc *sc)
928 struct usb_page_search buf_res;
929 struct xhci_hw_root *phwr;
938 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
940 phwr = buf_res.buffer;
942 /* Receive any events */
944 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
946 i = sc->sc_event_idx;
947 j = sc->sc_event_ccs;
952 temp = le32toh(phwr->hwr_events[i].dwTrb3);
954 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
959 event = XHCI_TRB_3_TYPE_GET(temp);
961 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
962 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
963 (long)le32toh(phwr->hwr_events[i].dwTrb2),
964 (long)le32toh(phwr->hwr_events[i].dwTrb3));
967 case XHCI_TRB_EVENT_TRANSFER:
968 xhci_check_transfer(sc, &phwr->hwr_events[i]);
970 case XHCI_TRB_EVENT_CMD_COMPLETE:
971 xhci_check_command(sc, &phwr->hwr_events[i]);
974 DPRINTF("Unhandled event = %u\n", event);
980 if (i == XHCI_MAX_EVENTS) {
984 /* check for timeout */
990 sc->sc_event_idx = i;
991 sc->sc_event_ccs = j;
994 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
995 * latched. That means to activate the register we need to
996 * write both the low and high double word of the 64-bit
1000 addr = (uint32_t)buf_res.physaddr;
1001 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1003 /* try to clear busy bit */
1004 addr |= XHCI_ERDP_LO_BUSY;
1006 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1007 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1011 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1012 uint16_t timeout_ms)
1014 struct usb_page_search buf_res;
1015 struct xhci_hw_root *phwr;
1022 XHCI_CMD_ASSERT_LOCKED(sc);
1024 /* get hardware root structure */
1026 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1028 phwr = buf_res.buffer;
1032 USB_BUS_LOCK(&sc->sc_bus);
1034 i = sc->sc_command_idx;
1035 j = sc->sc_command_ccs;
1037 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1038 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1039 (long long)le64toh(trb->qwTrb0),
1040 (long)le32toh(trb->dwTrb2),
1041 (long)le32toh(trb->dwTrb3));
1043 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1044 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1046 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1051 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1053 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1055 temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1057 phwr->hwr_commands[i].dwTrb3 = temp;
1059 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1061 addr = buf_res.physaddr;
1062 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1064 sc->sc_cmd_addr = htole64(addr);
1068 if (i == (XHCI_MAX_COMMANDS - 1)) {
1071 temp = htole32(XHCI_TRB_3_TC_BIT |
1072 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1073 XHCI_TRB_3_CYCLE_BIT);
1075 temp = htole32(XHCI_TRB_3_TC_BIT |
1076 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1079 phwr->hwr_commands[i].dwTrb3 = temp;
1081 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1087 sc->sc_command_idx = i;
1088 sc->sc_command_ccs = j;
1090 XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1092 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1093 USB_MS_TO_TICKS(timeout_ms));
1096 DPRINTFN(0, "Command timeout!\n");
1097 err = USB_ERR_TIMEOUT;
1101 temp = le32toh(sc->sc_cmd_result[0]);
1102 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1103 err = USB_ERR_IOERROR;
1105 trb->dwTrb2 = sc->sc_cmd_result[0];
1106 trb->dwTrb3 = sc->sc_cmd_result[1];
1109 USB_BUS_UNLOCK(&sc->sc_bus);
1116 xhci_cmd_nop(struct xhci_softc *sc)
1118 struct xhci_trb trb;
1125 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1127 trb.dwTrb3 = htole32(temp);
1129 return (xhci_do_command(sc, &trb, 100 /* ms */));
1134 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1136 struct xhci_trb trb;
1144 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1146 err = xhci_do_command(sc, &trb, 100 /* ms */);
1150 temp = le32toh(trb.dwTrb3);
1152 *pslot = XHCI_TRB_3_SLOT_GET(temp);
1159 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1161 struct xhci_trb trb;
1168 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1169 XHCI_TRB_3_SLOT_SET(slot_id);
1171 trb.dwTrb3 = htole32(temp);
1173 return (xhci_do_command(sc, &trb, 100 /* ms */));
1177 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1178 uint8_t bsr, uint8_t slot_id)
1180 struct xhci_trb trb;
1185 trb.qwTrb0 = htole64(input_ctx);
1187 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1188 XHCI_TRB_3_SLOT_SET(slot_id);
1191 temp |= XHCI_TRB_3_BSR_BIT;
1193 trb.dwTrb3 = htole32(temp);
1195 return (xhci_do_command(sc, &trb, 500 /* ms */));
1199 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1201 struct usb_page_search buf_inp;
1202 struct usb_page_search buf_dev;
1203 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1204 struct xhci_hw_dev *hdev;
1205 struct xhci_dev_ctx *pdev;
1206 struct xhci_endpoint_ext *pepext;
1212 /* the root HUB case is not handled here */
1213 if (udev->parent_hub == NULL)
1214 return (USB_ERR_INVAL);
1216 index = udev->controller_slot_id;
1218 hdev = &sc->sc_hw.devs[index];
1225 switch (hdev->state) {
1226 case XHCI_ST_DEFAULT:
1227 case XHCI_ST_ENABLED:
1229 hdev->state = XHCI_ST_ENABLED;
1231 /* set configure mask to slot and EP0 */
1232 xhci_configure_mask(udev, 3, 0);
1234 /* configure input slot context structure */
1235 err = xhci_configure_device(udev);
1238 DPRINTF("Could not configure device\n");
1242 /* configure input endpoint context structure */
1243 switch (udev->speed) {
1245 case USB_SPEED_FULL:
1248 case USB_SPEED_HIGH:
1256 pepext = xhci_get_endpoint_ext(udev,
1257 &udev->ctrl_ep_desc);
1258 err = xhci_configure_endpoint(udev,
1259 &udev->ctrl_ep_desc, pepext->physaddr,
1260 0, 1, 1, 0, mps, mps);
1263 DPRINTF("Could not configure default endpoint\n");
1267 /* execute set address command */
1268 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1270 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1271 (address == 0), index);
1274 DPRINTF("Could not set address "
1275 "for slot %u.\n", index);
1280 /* update device address to new value */
1282 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1283 pdev = buf_dev.buffer;
1284 usb_pc_cpu_invalidate(&hdev->device_pc);
1286 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1287 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1289 /* update device state to new value */
1292 hdev->state = XHCI_ST_ADDRESSED;
1294 hdev->state = XHCI_ST_DEFAULT;
1298 DPRINTF("Wrong state for set address.\n");
1299 err = USB_ERR_IOERROR;
1302 XHCI_CMD_UNLOCK(sc);
1311 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1312 uint8_t deconfigure, uint8_t slot_id)
1314 struct xhci_trb trb;
1319 trb.qwTrb0 = htole64(input_ctx);
1321 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1322 XHCI_TRB_3_SLOT_SET(slot_id);
1325 temp |= XHCI_TRB_3_DCEP_BIT;
1327 trb.dwTrb3 = htole32(temp);
1329 return (xhci_do_command(sc, &trb, 100 /* ms */));
1333 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1336 struct xhci_trb trb;
1341 trb.qwTrb0 = htole64(input_ctx);
1343 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1344 XHCI_TRB_3_SLOT_SET(slot_id);
1345 trb.dwTrb3 = htole32(temp);
1347 return (xhci_do_command(sc, &trb, 100 /* ms */));
1351 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1352 uint8_t ep_id, uint8_t slot_id)
1354 struct xhci_trb trb;
1361 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1362 XHCI_TRB_3_SLOT_SET(slot_id) |
1363 XHCI_TRB_3_EP_SET(ep_id);
1366 temp |= XHCI_TRB_3_PRSV_BIT;
1368 trb.dwTrb3 = htole32(temp);
1370 return (xhci_do_command(sc, &trb, 100 /* ms */));
1374 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1375 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1377 struct xhci_trb trb;
1382 trb.qwTrb0 = htole64(dequeue_ptr);
1384 temp = XHCI_TRB_2_STREAM_SET(stream_id);
1385 trb.dwTrb2 = htole32(temp);
1387 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1388 XHCI_TRB_3_SLOT_SET(slot_id) |
1389 XHCI_TRB_3_EP_SET(ep_id);
1390 trb.dwTrb3 = htole32(temp);
1392 return (xhci_do_command(sc, &trb, 100 /* ms */));
1396 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1397 uint8_t ep_id, uint8_t slot_id)
1399 struct xhci_trb trb;
1406 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1407 XHCI_TRB_3_SLOT_SET(slot_id) |
1408 XHCI_TRB_3_EP_SET(ep_id);
1411 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1413 trb.dwTrb3 = htole32(temp);
1415 return (xhci_do_command(sc, &trb, 100 /* ms */));
1419 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1421 struct xhci_trb trb;
1428 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1429 XHCI_TRB_3_SLOT_SET(slot_id);
1431 trb.dwTrb3 = htole32(temp);
1433 return (xhci_do_command(sc, &trb, 100 /* ms */));
1436 /*------------------------------------------------------------------------*
1437 * xhci_interrupt - XHCI interrupt handler
1438 *------------------------------------------------------------------------*/
1440 xhci_interrupt(struct xhci_softc *sc)
1445 USB_BUS_LOCK(&sc->sc_bus);
1447 status = XREAD4(sc, oper, XHCI_USBSTS);
1449 /* acknowledge interrupts */
1451 XWRITE4(sc, oper, XHCI_USBSTS, status);
1453 temp = XREAD4(sc, runt, XHCI_IMAN(0));
1455 /* acknowledge pending event */
1457 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1459 DPRINTFN(16, "real interrupt (sts=0x%08x, "
1460 "iman=0x%08x)\n", status, temp);
1463 if (status & XHCI_STS_PCD) {
1467 if (status & XHCI_STS_HCH) {
1468 printf("%s: host controller halted\n",
1472 if (status & XHCI_STS_HSE) {
1473 printf("%s: host system error\n",
1477 if (status & XHCI_STS_HCE) {
1478 printf("%s: host controller error\n",
1483 xhci_interrupt_poll(sc);
1485 USB_BUS_UNLOCK(&sc->sc_bus);
1488 /*------------------------------------------------------------------------*
1489 * xhci_timeout - XHCI timeout handler
1490 *------------------------------------------------------------------------*/
1492 xhci_timeout(void *arg)
1494 struct usb_xfer *xfer = arg;
1496 DPRINTF("xfer=%p\n", xfer);
1498 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1500 /* transfer is transferred */
1501 xhci_device_done(xfer, USB_ERR_TIMEOUT);
1505 xhci_do_poll(struct usb_bus *bus)
1507 struct xhci_softc *sc = XHCI_BUS2SC(bus);
1509 USB_BUS_LOCK(&sc->sc_bus);
1510 xhci_interrupt_poll(sc);
1511 USB_BUS_UNLOCK(&sc->sc_bus);
1515 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1517 struct usb_page_search buf_res;
1519 struct xhci_td *td_next;
1520 struct xhci_td *td_alt_next;
1521 uint32_t buf_offset;
1525 uint8_t shortpkt_old;
1531 shortpkt_old = temp->shortpkt;
1532 len_old = temp->len;
1538 td_next = temp->td_next;
1542 if (temp->len == 0) {
1547 /* send a Zero Length Packet, ZLP, last */
1554 average = temp->average;
1556 if (temp->len < average) {
1557 if (temp->len % temp->max_packet_size) {
1560 average = temp->len;
1564 if (td_next == NULL)
1565 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1570 td_next = td->obj_next;
1572 /* check if we are pre-computing */
1576 /* update remaining length */
1578 temp->len -= average;
1582 /* fill out current TD */
1588 /* update remaining length */
1590 temp->len -= average;
1592 /* reset TRB index */
1596 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1597 /* immediate data */
1602 td->td_trb[0].qwTrb0 = 0;
1604 usbd_copy_out(temp->pc, temp->offset + buf_offset,
1605 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1608 dword = XHCI_TRB_2_BYTES_SET(8) |
1609 XHCI_TRB_2_TDSZ_SET(0) |
1610 XHCI_TRB_2_IRQ_SET(0);
1612 td->td_trb[0].dwTrb2 = htole32(dword);
1614 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1615 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1618 if (td->td_trb[0].qwTrb0 &
1619 htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1620 if (td->td_trb[0].qwTrb0 & htole64(1))
1621 dword |= XHCI_TRB_3_TRT_IN;
1623 dword |= XHCI_TRB_3_TRT_OUT;
1626 td->td_trb[0].dwTrb3 = htole32(dword);
1628 xhci_dump_trb(&td->td_trb[x]);
1636 /* fill out buffer pointers */
1640 memset(&buf_res, 0, sizeof(buf_res));
1642 usbd_get_page(temp->pc, temp->offset +
1643 buf_offset, &buf_res);
1645 /* get length to end of page */
1646 if (buf_res.length > average)
1647 buf_res.length = average;
1649 /* check for maximum length */
1650 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1651 buf_res.length = XHCI_TD_PAGE_SIZE;
1654 npkt = (average + temp->max_packet_size - 1) /
1655 temp->max_packet_size;
1661 /* fill out TRB's */
1662 td->td_trb[x].qwTrb0 =
1663 htole64((uint64_t)buf_res.physaddr);
1666 XHCI_TRB_2_BYTES_SET(buf_res.length) |
1667 XHCI_TRB_2_TDSZ_SET(npkt) |
1668 XHCI_TRB_2_IRQ_SET(0);
1670 td->td_trb[x].dwTrb2 = htole32(dword);
1672 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1673 XHCI_TRB_3_TYPE_SET(temp->trb_type) |
1674 (temp->do_isoc_sync ?
1675 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8) :
1676 XHCI_TRB_3_ISO_SIA_BIT) |
1677 XHCI_TRB_3_TBC_SET(temp->tbc) |
1678 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1680 temp->do_isoc_sync = 0;
1682 if (temp->direction == UE_DIR_IN) {
1683 dword |= XHCI_TRB_3_DIR_IN;
1686 * NOTE: Only the SETUP stage should
1687 * use the IDT bit. Else transactions
1688 * can be sent using the wrong data
1691 if (temp->trb_type !=
1692 XHCI_TRB_TYPE_SETUP_STAGE &&
1694 XHCI_TRB_TYPE_STATUS_STAGE)
1695 dword |= XHCI_TRB_3_ISP_BIT;
1698 td->td_trb[x].dwTrb3 = htole32(dword);
1700 average -= buf_res.length;
1701 buf_offset += buf_res.length;
1703 xhci_dump_trb(&td->td_trb[x]);
1707 } while (average != 0);
1709 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1711 /* store number of data TRB's */
1715 DPRINTF("NTRB=%u\n", x);
1717 /* fill out link TRB */
1719 if (td_next != NULL) {
1720 /* link the current TD with the next one */
1721 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1722 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1724 /* this field will get updated later */
1725 DPRINTF("NOLINK\n");
1728 dword = XHCI_TRB_2_IRQ_SET(0);
1730 td->td_trb[x].dwTrb2 = htole32(dword);
1732 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1733 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT;
1735 td->td_trb[x].dwTrb3 = htole32(dword);
1737 td->alt_next = td_alt_next;
1739 xhci_dump_trb(&td->td_trb[x]);
1741 usb_pc_cpu_flush(td->page_cache);
1747 /* setup alt next pointer, if any */
1748 if (temp->last_frame) {
1751 /* we use this field internally */
1752 td_alt_next = td_next;
1756 temp->shortpkt = shortpkt_old;
1757 temp->len = len_old;
1761 /* remove cycle bit from first if we are stepping the TRBs */
1763 td->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1765 /* remove chain bit because this is the last TRB in the chain */
1766 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1767 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1769 usb_pc_cpu_flush(td->page_cache);
1772 temp->td_next = td_next;
1776 xhci_setup_generic_chain(struct usb_xfer *xfer)
1778 struct xhci_std_temp temp;
1784 temp.do_isoc_sync = 0;
1788 temp.average = xfer->max_hc_frame_size;
1789 temp.max_packet_size = xfer->max_packet_size;
1790 temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
1792 temp.last_frame = 0;
1794 temp.multishort = xfer->flags_int.isochronous_xfr ||
1795 xfer->flags_int.control_xfr ||
1796 xfer->flags_int.short_frames_ok;
1798 /* toggle the DMA set we are using */
1799 xfer->flags_int.curr_dma_set ^= 1;
1801 /* get next DMA set */
1802 td = xfer->td_start[xfer->flags_int.curr_dma_set];
1807 xfer->td_transfer_first = td;
1808 xfer->td_transfer_cache = td;
1810 if (xfer->flags_int.isochronous_xfr) {
1813 /* compute multiplier for ISOCHRONOUS transfers */
1814 mult = xfer->endpoint->ecomp ?
1815 (xfer->endpoint->ecomp->bmAttributes & 3) : 0;
1816 /* check for USB 2.0 multiplier */
1818 mult = (xfer->endpoint->edesc->
1819 wMaxPacketSize[1] >> 3) & 3;
1827 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
1829 DPRINTF("MFINDEX=0x%08x\n", x);
1831 switch (usbd_get_speed(xfer->xroot->udev)) {
1832 case USB_SPEED_FULL:
1834 temp.isoc_delta = 8; /* 1ms */
1835 x += temp.isoc_delta - 1;
1836 x &= ~(temp.isoc_delta - 1);
1839 shift = usbd_xfer_get_fps_shift(xfer);
1840 temp.isoc_delta = 1U << shift;
1841 x += temp.isoc_delta - 1;
1842 x &= ~(temp.isoc_delta - 1);
1843 /* simple frame load balancing */
1844 x += xfer->endpoint->usb_uframe;
1848 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
1850 if ((xfer->endpoint->is_synced == 0) ||
1851 (y < (xfer->nframes << shift)) ||
1852 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
1854 * If there is data underflow or the pipe
1855 * queue is empty we schedule the transfer a
1856 * few frames ahead of the current frame
1857 * position. Else two isochronous transfers
1860 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
1861 xfer->endpoint->is_synced = 1;
1862 temp.do_isoc_sync = 1;
1864 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
1867 /* compute isochronous completion time */
1869 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
1871 xfer->isoc_time_complete =
1872 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
1873 (y / 8) + (((xfer->nframes << shift) + 7) / 8);
1876 temp.isoc_frame = xfer->endpoint->isoc_next;
1877 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
1879 xfer->endpoint->isoc_next += xfer->nframes << shift;
1881 } else if (xfer->flags_int.control_xfr) {
1883 /* check if we should prepend a setup message */
1885 if (xfer->flags_int.control_hdr) {
1887 temp.len = xfer->frlengths[0];
1888 temp.pc = xfer->frbuffers + 0;
1889 temp.shortpkt = temp.len ? 1 : 0;
1890 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
1893 /* check for last frame */
1894 if (xfer->nframes == 1) {
1895 /* no STATUS stage yet, SETUP is last */
1896 if (xfer->flags_int.control_act)
1897 temp.last_frame = 1;
1900 xhci_setup_generic_chain_sub(&temp);
1904 temp.isoc_delta = 0;
1905 temp.isoc_frame = 0;
1906 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE;
1910 temp.isoc_delta = 0;
1911 temp.isoc_frame = 0;
1912 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
1915 if (x != xfer->nframes) {
1916 /* setup page_cache pointer */
1917 temp.pc = xfer->frbuffers + x;
1918 /* set endpoint direction */
1919 temp.direction = UE_GET_DIR(xfer->endpointno);
1922 while (x != xfer->nframes) {
1924 /* DATA0 / DATA1 message */
1926 temp.len = xfer->frlengths[x];
1927 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
1928 x != 0 && temp.multishort == 0);
1932 if (x == xfer->nframes) {
1933 if (xfer->flags_int.control_xfr) {
1934 /* no STATUS stage yet, DATA is last */
1935 if (xfer->flags_int.control_act)
1936 temp.last_frame = 1;
1938 temp.last_frame = 1;
1941 if (temp.len == 0) {
1943 /* make sure that we send an USB packet */
1948 temp.tlbpc = mult - 1;
1950 } else if (xfer->flags_int.isochronous_xfr) {
1955 * Isochronous transfers don't have short
1956 * packet termination:
1961 /* isochronous transfers have a transfer limit */
1963 if (temp.len > xfer->max_frame_size)
1964 temp.len = xfer->max_frame_size;
1966 /* compute TD packet count */
1967 tdpc = (temp.len + xfer->max_packet_size - 1) /
1968 xfer->max_packet_size;
1970 temp.tbc = ((tdpc + mult - 1) / mult) - 1;
1971 temp.tlbpc = (tdpc % mult);
1973 if (temp.tlbpc == 0)
1974 temp.tlbpc = mult - 1;
1979 /* regular data transfer */
1981 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
1984 xhci_setup_generic_chain_sub(&temp);
1986 if (xfer->flags_int.isochronous_xfr) {
1987 temp.offset += xfer->frlengths[x - 1];
1988 temp.isoc_frame += temp.isoc_delta;
1990 /* get next Page Cache pointer */
1991 temp.pc = xfer->frbuffers + x;
1995 /* check if we should append a status stage */
1997 if (xfer->flags_int.control_xfr &&
1998 !xfer->flags_int.control_act) {
2001 * Send a DATA1 message and invert the current
2002 * endpoint direction.
2004 temp.step_td = (xfer->nframes != 0);
2005 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2009 temp.last_frame = 1;
2010 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2012 xhci_setup_generic_chain_sub(&temp);
2017 /* must have at least one frame! */
2019 xfer->td_transfer_last = td;
2021 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2025 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2027 struct usb_page_search buf_res;
2028 struct xhci_dev_ctx_addr *pdctxa;
2030 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2032 pdctxa = buf_res.buffer;
2034 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2036 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2038 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2042 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2044 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2045 struct usb_page_search buf_inp;
2046 struct xhci_input_dev_ctx *pinp;
2049 index = udev->controller_slot_id;
2051 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2053 pinp = buf_inp.buffer;
2056 mask &= XHCI_INCTX_NON_CTRL_MASK;
2057 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2058 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2060 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0);
2061 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2067 xhci_configure_endpoint(struct usb_device *udev,
2068 struct usb_endpoint_descriptor *edesc, uint64_t ring_addr,
2069 uint16_t interval, uint8_t max_packet_count, uint8_t mult,
2070 uint8_t fps_shift, uint16_t max_packet_size, uint16_t max_frame_size)
2072 struct usb_page_search buf_inp;
2073 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2074 struct xhci_input_dev_ctx *pinp;
2080 index = udev->controller_slot_id;
2082 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2084 pinp = buf_inp.buffer;
2086 epno = edesc->bEndpointAddress;
2087 type = edesc->bmAttributes & UE_XFERTYPE;
2089 if (type == UE_CONTROL)
2092 epno = XHCI_EPNO2EPID(epno);
2095 return (USB_ERR_NO_PIPE); /* invalid */
2097 if (max_packet_count == 0)
2098 return (USB_ERR_BAD_BUFSIZE);
2103 return (USB_ERR_BAD_BUFSIZE);
2105 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2106 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2107 XHCI_EPCTX_0_LSA_SET(0);
2109 switch (udev->speed) {
2110 case USB_SPEED_FULL:
2123 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2125 case UE_ISOCHRONOUS:
2126 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2128 switch (udev->speed) {
2129 case USB_SPEED_SUPER:
2132 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2133 max_packet_count /= mult;
2143 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2146 XHCI_EPCTX_1_HID_SET(0) |
2147 XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2148 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2150 if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) {
2151 if (type != UE_ISOCHRONOUS)
2152 temp |= XHCI_EPCTX_1_CERR_SET(3);
2157 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2159 case UE_ISOCHRONOUS:
2160 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2163 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2166 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2170 /* check for IN direction */
2172 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2174 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2176 ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2178 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2180 switch (edesc->bmAttributes & UE_XFERTYPE) {
2182 case UE_ISOCHRONOUS:
2183 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2184 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2188 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2191 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2195 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2198 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2200 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2202 return (0); /* success */
2206 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2208 struct xhci_endpoint_ext *pepext;
2209 struct usb_endpoint_ss_comp_descriptor *ecomp;
2211 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2212 xfer->endpoint->edesc);
2214 ecomp = xfer->endpoint->ecomp;
2216 pepext->trb[0].dwTrb3 = 0; /* halt any transfers */
2217 usb_pc_cpu_flush(pepext->page_cache);
2219 return (xhci_configure_endpoint(xfer->xroot->udev,
2220 xfer->endpoint->edesc, pepext->physaddr,
2221 xfer->interval, xfer->max_packet_count,
2222 (ecomp != NULL) ? (ecomp->bmAttributes & 3) + 1 : 1,
2223 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2224 xfer->max_frame_size));
2228 xhci_configure_device(struct usb_device *udev)
2230 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2231 struct usb_page_search buf_inp;
2232 struct usb_page_cache *pcinp;
2233 struct xhci_input_dev_ctx *pinp;
2234 struct usb_device *hubdev;
2242 index = udev->controller_slot_id;
2244 DPRINTF("index=%u\n", index);
2246 pcinp = &sc->sc_hw.devs[index].input_pc;
2248 usbd_get_page(pcinp, 0, &buf_inp);
2250 pinp = buf_inp.buffer;
2255 /* figure out route string and root HUB port number */
2257 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2259 if (hubdev->parent_hub == NULL)
2262 depth = hubdev->parent_hub->depth;
2265 * NOTE: HS/FS/LS devices and the SS root HUB can have
2266 * more than 15 ports
2269 rh_port = hubdev->port_no;
2278 route |= rh_port << (4 * (depth - 1));
2281 DPRINTF("Route=0x%08x\n", route);
2283 temp = XHCI_SCTX_0_ROUTE_SET(route);
2285 switch (sc->sc_hw.devs[index].state) {
2286 case XHCI_ST_CONFIGURED:
2287 temp |= XHCI_SCTX_0_CTX_NUM_SET(XHCI_MAX_ENDPOINTS - 1);
2290 temp |= XHCI_SCTX_0_CTX_NUM_SET(1);
2294 switch (udev->speed) {
2296 temp |= XHCI_SCTX_0_SPEED_SET(2);
2297 if (udev->parent_hs_hub != NULL &&
2298 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2300 DPRINTF("Device inherits MTT\n");
2301 temp |= XHCI_SCTX_0_MTT_SET(1);
2304 case USB_SPEED_HIGH:
2305 temp |= XHCI_SCTX_0_SPEED_SET(3);
2306 if (sc->sc_hw.devs[index].nports != 0 &&
2307 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2308 DPRINTF("HUB supports MTT\n");
2309 temp |= XHCI_SCTX_0_MTT_SET(1);
2312 case USB_SPEED_FULL:
2313 temp |= XHCI_SCTX_0_SPEED_SET(1);
2314 if (udev->parent_hs_hub != NULL &&
2315 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2317 DPRINTF("Device inherits MTT\n");
2318 temp |= XHCI_SCTX_0_MTT_SET(1);
2322 temp |= XHCI_SCTX_0_SPEED_SET(4);
2326 is_hub = sc->sc_hw.devs[index].nports != 0 &&
2327 (udev->speed == USB_SPEED_SUPER ||
2328 udev->speed == USB_SPEED_HIGH);
2331 temp |= XHCI_SCTX_0_HUB_SET(1);
2333 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2335 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2338 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2339 sc->sc_hw.devs[index].nports);
2342 switch (udev->speed) {
2343 case USB_SPEED_SUPER:
2344 switch (sc->sc_hw.devs[index].state) {
2345 case XHCI_ST_ADDRESSED:
2346 case XHCI_ST_CONFIGURED:
2347 /* enable power save */
2348 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2351 /* disable power save */
2359 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2361 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2364 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2365 sc->sc_hw.devs[index].tt);
2368 hubdev = udev->parent_hs_hub;
2370 /* check if we should activate the transaction translator */
2371 switch (udev->speed) {
2372 case USB_SPEED_FULL:
2374 if (hubdev != NULL) {
2375 temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2376 hubdev->controller_slot_id);
2377 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2385 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2387 temp = XHCI_SCTX_3_DEV_ADDR_SET(udev->address) |
2388 XHCI_SCTX_3_SLOT_STATE_SET(0);
2390 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2393 xhci_dump_device(sc, &pinp->ctx_slot);
2395 usb_pc_cpu_flush(pcinp);
2397 return (0); /* success */
2401 xhci_alloc_device_ext(struct usb_device *udev)
2403 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2404 struct usb_page_search buf_dev;
2405 struct usb_page_search buf_ep;
2406 struct xhci_trb *trb;
2407 struct usb_page_cache *pc;
2408 struct usb_page *pg;
2413 index = udev->controller_slot_id;
2415 pc = &sc->sc_hw.devs[index].device_pc;
2416 pg = &sc->sc_hw.devs[index].device_pg;
2418 /* need to initialize the page cache */
2419 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2421 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2422 (2 * sizeof(struct xhci_dev_ctx)) :
2423 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2426 usbd_get_page(pc, 0, &buf_dev);
2428 pc = &sc->sc_hw.devs[index].input_pc;
2429 pg = &sc->sc_hw.devs[index].input_pg;
2431 /* need to initialize the page cache */
2432 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2434 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2435 (2 * sizeof(struct xhci_input_dev_ctx)) :
2436 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE))
2439 pc = &sc->sc_hw.devs[index].endpoint_pc;
2440 pg = &sc->sc_hw.devs[index].endpoint_pg;
2442 /* need to initialize the page cache */
2443 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2445 if (usb_pc_alloc_mem(pc, pg, sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE))
2448 /* initialise all endpoint LINK TRBs */
2450 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2452 /* lookup endpoint TRB ring */
2453 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep);
2455 /* get TRB pointer */
2456 trb = buf_ep.buffer;
2457 trb += XHCI_MAX_TRANSFERS - 1;
2459 /* get TRB start address */
2460 addr = buf_ep.physaddr;
2462 /* create LINK TRB */
2463 trb->qwTrb0 = htole64(addr);
2464 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2465 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2466 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2469 usb_pc_cpu_flush(pc);
2471 xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2476 xhci_free_device_ext(udev);
2478 return (USB_ERR_NOMEM);
2482 xhci_free_device_ext(struct usb_device *udev)
2484 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2487 index = udev->controller_slot_id;
2488 xhci_set_slot_pointer(sc, index, 0);
2490 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2491 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2492 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc);
2495 static struct xhci_endpoint_ext *
2496 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2498 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2499 struct xhci_endpoint_ext *pepext;
2500 struct usb_page_cache *pc;
2501 struct usb_page_search buf_ep;
2505 epno = edesc->bEndpointAddress;
2506 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2509 epno = XHCI_EPNO2EPID(epno);
2511 index = udev->controller_slot_id;
2513 pc = &sc->sc_hw.devs[index].endpoint_pc;
2515 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->trb[epno][0], &buf_ep);
2517 pepext = &sc->sc_hw.devs[index].endp[epno];
2518 pepext->page_cache = pc;
2519 pepext->trb = buf_ep.buffer;
2520 pepext->physaddr = buf_ep.physaddr;
2526 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2528 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2532 epno = xfer->endpointno;
2533 if (xfer->flags_int.control_xfr)
2536 epno = XHCI_EPNO2EPID(epno);
2537 index = xfer->xroot->udev->controller_slot_id;
2539 if (xfer->xroot->udev->flags.self_suspended == 0)
2540 XWRITE4(sc, door, XHCI_DOORBELL(index), epno | XHCI_DB_SID_SET(0));
2544 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2546 struct xhci_endpoint_ext *pepext;
2548 if (xfer->flags_int.bandwidth_reclaimed) {
2549 xfer->flags_int.bandwidth_reclaimed = 0;
2551 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2552 xfer->endpoint->edesc);
2556 pepext->xfer[xfer->qh_pos] = NULL;
2558 if (error && pepext->trb_running != 0) {
2559 pepext->trb_halted = 1;
2560 pepext->trb_running = 0;
2566 xhci_transfer_insert(struct usb_xfer *xfer)
2568 struct xhci_td *td_first;
2569 struct xhci_td *td_last;
2570 struct xhci_endpoint_ext *pepext;
2578 /* check if already inserted */
2579 if (xfer->flags_int.bandwidth_reclaimed) {
2580 DPRINTFN(8, "Already in schedule\n");
2584 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2585 xfer->endpoint->edesc);
2587 td_first = xfer->td_transfer_first;
2588 td_last = xfer->td_transfer_last;
2589 addr = pepext->physaddr;
2591 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2594 /* single buffered */
2598 /* multi buffered */
2599 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2603 if (pepext->trb_used >= trb_limit) {
2604 DPRINTFN(8, "Too many TDs queued.\n");
2605 return (USB_ERR_NOMEM);
2608 /* check for stopped condition, after putting transfer on interrupt queue */
2609 if (pepext->trb_running == 0) {
2610 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2612 DPRINTFN(8, "Not running\n");
2614 /* start configuration */
2615 (void)usb_proc_msignal(&sc->sc_config_proc,
2616 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2622 /* get current TRB index */
2623 i = pepext->trb_index;
2625 /* get next TRB index */
2628 /* the last entry of the ring is a hardcoded link TRB */
2629 if (inext >= (XHCI_MAX_TRANSFERS - 1))
2632 /* compute terminating return address */
2633 addr += inext * sizeof(struct xhci_trb);
2635 /* update next pointer of last link TRB */
2636 td_last->td_trb[td_last->ntrb].qwTrb0 = htole64(addr);
2637 td_last->td_trb[td_last->ntrb].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2638 td_last->td_trb[td_last->ntrb].dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2639 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2642 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2644 usb_pc_cpu_flush(td_last->page_cache);
2646 /* write ahead chain end marker */
2648 pepext->trb[inext].qwTrb0 = 0;
2649 pepext->trb[inext].dwTrb2 = 0;
2650 pepext->trb[inext].dwTrb3 = 0;
2652 /* update next pointer of link TRB */
2654 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2655 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2658 xhci_dump_trb(&pepext->trb[i]);
2660 usb_pc_cpu_flush(pepext->page_cache);
2662 /* toggle cycle bit which activates the transfer chain */
2664 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2665 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2667 usb_pc_cpu_flush(pepext->page_cache);
2669 DPRINTF("qh_pos = %u\n", i);
2671 pepext->xfer[i] = xfer;
2675 xfer->flags_int.bandwidth_reclaimed = 1;
2677 pepext->trb_index = inext;
2679 xhci_endpoint_doorbell(xfer);
2685 xhci_root_intr(struct xhci_softc *sc)
2689 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2691 /* clear any old interrupt data */
2692 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2694 for (i = 1; i <= sc->sc_noport; i++) {
2695 /* pick out CHANGE bits from the status register */
2696 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
2697 XHCI_PS_CSC | XHCI_PS_PEC |
2698 XHCI_PS_OCC | XHCI_PS_WRC |
2699 XHCI_PS_PRC | XHCI_PS_PLC |
2701 sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2702 DPRINTF("port %d changed\n", i);
2705 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2706 sizeof(sc->sc_hub_idata));
2709 /*------------------------------------------------------------------------*
2710 * xhci_device_done - XHCI done handler
2712 * NOTE: This function can be called two times in a row on
2713 * the same USB transfer. From close and from interrupt.
2714 *------------------------------------------------------------------------*/
2716 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
2718 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2719 xfer, xfer->endpoint, error);
2721 /* remove transfer from HW queue */
2722 xhci_transfer_remove(xfer, error);
2724 /* dequeue transfer and start next transfer */
2725 usbd_transfer_done(xfer, error);
2728 /*------------------------------------------------------------------------*
2729 * XHCI data transfer support (generic type)
2730 *------------------------------------------------------------------------*/
2732 xhci_device_generic_open(struct usb_xfer *xfer)
2734 if (xfer->flags_int.isochronous_xfr) {
2735 switch (xfer->xroot->udev->speed) {
2736 case USB_SPEED_FULL:
2739 usb_hs_bandwidth_alloc(xfer);
2746 xhci_device_generic_close(struct usb_xfer *xfer)
2750 xhci_device_done(xfer, USB_ERR_CANCELLED);
2752 if (xfer->flags_int.isochronous_xfr) {
2753 switch (xfer->xroot->udev->speed) {
2754 case USB_SPEED_FULL:
2757 usb_hs_bandwidth_free(xfer);
2764 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
2765 struct usb_xfer *enter_xfer)
2767 struct usb_xfer *xfer;
2769 /* check if there is a current transfer */
2770 xfer = ep->endpoint_q.curr;
2775 * Check if the current transfer is started and then pickup
2776 * the next one, if any. Else wait for next start event due to
2777 * block on failure feature.
2779 if (!xfer->flags_int.bandwidth_reclaimed)
2782 xfer = TAILQ_FIRST(&ep->endpoint_q.head);
2785 * In case of enter we have to consider that the
2786 * transfer is queued by the USB core after the enter
2795 /* try to multi buffer */
2796 xhci_transfer_insert(xfer);
2800 xhci_device_generic_enter(struct usb_xfer *xfer)
2804 /* setup TD's and QH */
2805 xhci_setup_generic_chain(xfer);
2807 xhci_device_generic_multi_enter(xfer->endpoint, xfer);
2811 xhci_device_generic_start(struct usb_xfer *xfer)
2815 /* try to insert xfer on HW queue */
2816 xhci_transfer_insert(xfer);
2818 /* try to multi buffer */
2819 xhci_device_generic_multi_enter(xfer->endpoint, NULL);
2821 /* add transfer last on interrupt queue */
2822 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
2824 /* start timeout, if any */
2825 if (xfer->timeout != 0)
2826 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
2829 struct usb_pipe_methods xhci_device_generic_methods =
2831 .open = xhci_device_generic_open,
2832 .close = xhci_device_generic_close,
2833 .enter = xhci_device_generic_enter,
2834 .start = xhci_device_generic_start,
2837 /*------------------------------------------------------------------------*
2838 * xhci root HUB support
2839 *------------------------------------------------------------------------*
2840 * Simulate a hardware HUB by handling all the necessary requests.
2841 *------------------------------------------------------------------------*/
2843 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
2846 struct usb_device_descriptor xhci_devd =
2848 .bLength = sizeof(xhci_devd),
2849 .bDescriptorType = UDESC_DEVICE, /* type */
2850 HSETW(.bcdUSB, 0x0300), /* USB version */
2851 .bDeviceClass = UDCLASS_HUB, /* class */
2852 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */
2853 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */
2854 .bMaxPacketSize = 9, /* max packet size */
2855 HSETW(.idVendor, 0x0000), /* vendor */
2856 HSETW(.idProduct, 0x0000), /* product */
2857 HSETW(.bcdDevice, 0x0100), /* device version */
2861 .bNumConfigurations = 1, /* # of configurations */
2865 struct xhci_bos_desc xhci_bosd = {
2867 .bLength = sizeof(xhci_bosd.bosd),
2868 .bDescriptorType = UDESC_BOS,
2869 HSETW(.wTotalLength, sizeof(xhci_bosd)),
2870 .bNumDeviceCaps = 3,
2873 .bLength = sizeof(xhci_bosd.usb2extd),
2874 .bDescriptorType = 1,
2875 .bDevCapabilityType = 2,
2876 .bmAttributes[0] = 2,
2879 .bLength = sizeof(xhci_bosd.usbdcd),
2880 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
2881 .bDevCapabilityType = 3,
2882 .bmAttributes = 0, /* XXX */
2883 HSETW(.wSpeedsSupported, 0x000C),
2884 .bFunctionalitySupport = 8,
2885 .bU1DevExitLat = 255, /* dummy - not used */
2886 .wU2DevExitLat = { 0x00, 0x08 },
2889 .bLength = sizeof(xhci_bosd.cidd),
2890 .bDescriptorType = 1,
2891 .bDevCapabilityType = 4,
2893 .bContainerID = 0, /* XXX */
2898 struct xhci_config_desc xhci_confd = {
2900 .bLength = sizeof(xhci_confd.confd),
2901 .bDescriptorType = UDESC_CONFIG,
2902 .wTotalLength[0] = sizeof(xhci_confd),
2904 .bConfigurationValue = 1,
2905 .iConfiguration = 0,
2906 .bmAttributes = UC_SELF_POWERED,
2907 .bMaxPower = 0 /* max power */
2910 .bLength = sizeof(xhci_confd.ifcd),
2911 .bDescriptorType = UDESC_INTERFACE,
2913 .bInterfaceClass = UICLASS_HUB,
2914 .bInterfaceSubClass = UISUBCLASS_HUB,
2915 .bInterfaceProtocol = 0,
2918 .bLength = sizeof(xhci_confd.endpd),
2919 .bDescriptorType = UDESC_ENDPOINT,
2920 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
2921 .bmAttributes = UE_INTERRUPT,
2922 .wMaxPacketSize[0] = 2, /* max 15 ports */
2926 .bLength = sizeof(xhci_confd.endpcd),
2927 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
2934 struct usb_hub_ss_descriptor xhci_hubd = {
2935 .bLength = sizeof(xhci_hubd),
2936 .bDescriptorType = UDESC_SS_HUB,
2940 xhci_roothub_exec(struct usb_device *udev,
2941 struct usb_device_request *req, const void **pptr, uint16_t *plength)
2943 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2944 const char *str_ptr;
2955 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2958 ptr = (const void *)&sc->sc_hub_desc;
2962 value = UGETW(req->wValue);
2963 index = UGETW(req->wIndex);
2965 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
2966 "wValue=0x%04x wIndex=0x%04x\n",
2967 req->bmRequestType, req->bRequest,
2968 UGETW(req->wLength), value, index);
2970 #define C(x,y) ((x) | ((y) << 8))
2971 switch (C(req->bRequest, req->bmRequestType)) {
2972 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
2973 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
2974 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
2976 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
2977 * for the integrated root hub.
2980 case C(UR_GET_CONFIG, UT_READ_DEVICE):
2982 sc->sc_hub_desc.temp[0] = sc->sc_conf;
2984 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
2985 switch (value >> 8) {
2987 if ((value & 0xff) != 0) {
2988 err = USB_ERR_IOERROR;
2991 len = sizeof(xhci_devd);
2992 ptr = (const void *)&xhci_devd;
2996 if ((value & 0xff) != 0) {
2997 err = USB_ERR_IOERROR;
3000 len = sizeof(xhci_bosd);
3001 ptr = (const void *)&xhci_bosd;
3005 if ((value & 0xff) != 0) {
3006 err = USB_ERR_IOERROR;
3009 len = sizeof(xhci_confd);
3010 ptr = (const void *)&xhci_confd;
3014 switch (value & 0xff) {
3015 case 0: /* Language table */
3019 case 1: /* Vendor */
3020 str_ptr = sc->sc_vendor;
3023 case 2: /* Product */
3024 str_ptr = "XHCI root HUB";
3032 len = usb_make_str_desc(
3033 sc->sc_hub_desc.temp,
3034 sizeof(sc->sc_hub_desc.temp),
3039 err = USB_ERR_IOERROR;
3043 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3045 sc->sc_hub_desc.temp[0] = 0;
3047 case C(UR_GET_STATUS, UT_READ_DEVICE):
3049 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3051 case C(UR_GET_STATUS, UT_READ_INTERFACE):
3052 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3054 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3056 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3057 if (value >= XHCI_MAX_DEVICES) {
3058 err = USB_ERR_IOERROR;
3062 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3063 if (value != 0 && value != 1) {
3064 err = USB_ERR_IOERROR;
3067 sc->sc_conf = value;
3069 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3071 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3072 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3073 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3074 err = USB_ERR_IOERROR;
3076 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3078 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3081 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3083 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3084 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3087 (index > sc->sc_noport)) {
3088 err = USB_ERR_IOERROR;
3091 port = XHCI_PORTSC(index);
3093 v = XREAD4(sc, oper, port);
3094 i = XHCI_PS_PLS_GET(v);
3095 v &= ~XHCI_PS_CLEAR;
3098 case UHF_C_BH_PORT_RESET:
3099 XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3101 case UHF_C_PORT_CONFIG_ERROR:
3102 XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3104 case UHF_C_PORT_SUSPEND:
3105 case UHF_C_PORT_LINK_STATE:
3106 XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3108 case UHF_C_PORT_CONNECTION:
3109 XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3111 case UHF_C_PORT_ENABLE:
3112 XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3114 case UHF_C_PORT_OVER_CURRENT:
3115 XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3117 case UHF_C_PORT_RESET:
3118 XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3120 case UHF_PORT_ENABLE:
3121 XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3123 case UHF_PORT_POWER:
3124 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3126 case UHF_PORT_INDICATOR:
3127 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3129 case UHF_PORT_SUSPEND:
3133 XWRITE4(sc, oper, port, v |
3134 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3137 /* wait 20ms for resume sequence to complete */
3138 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3141 XWRITE4(sc, oper, port, v |
3142 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3145 err = USB_ERR_IOERROR;
3150 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3151 if ((value & 0xff) != 0) {
3152 err = USB_ERR_IOERROR;
3156 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3158 sc->sc_hub_desc.hubd = xhci_hubd;
3160 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3162 if (XHCI_HCS0_PPC(v))
3163 i = UHD_PWR_INDIVIDUAL;
3167 if (XHCI_HCS0_PIND(v))
3170 i |= UHD_OC_INDIVIDUAL;
3172 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3174 /* see XHCI section 5.4.9: */
3175 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3177 for (j = 1; j <= sc->sc_noport; j++) {
3179 v = XREAD4(sc, oper, XHCI_PORTSC(j));
3180 if (v & XHCI_PS_DR) {
3181 sc->sc_hub_desc.hubd.
3182 DeviceRemovable[j / 8] |= 1U << (j % 8);
3185 len = sc->sc_hub_desc.hubd.bLength;
3188 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3190 memset(sc->sc_hub_desc.temp, 0, 16);
3193 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3194 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3197 (index > sc->sc_noport)) {
3198 err = USB_ERR_IOERROR;
3202 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3204 DPRINTFN(9, "port status=0x%08x\n", v);
3206 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3208 switch (XHCI_PS_SPEED_GET(v)) {
3210 i |= UPS_HIGH_SPEED;
3219 i |= UPS_OTHER_SPEED;
3223 if (v & XHCI_PS_CCS)
3224 i |= UPS_CURRENT_CONNECT_STATUS;
3225 if (v & XHCI_PS_PED)
3226 i |= UPS_PORT_ENABLED;
3227 if (v & XHCI_PS_OCA)
3228 i |= UPS_OVERCURRENT_INDICATOR;
3231 if (v & XHCI_PS_PP) {
3233 * The USB 3.0 RH is using the
3234 * USB 2.0's power bit
3236 i |= UPS_PORT_POWER;
3238 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3241 if (v & XHCI_PS_CSC)
3242 i |= UPS_C_CONNECT_STATUS;
3243 if (v & XHCI_PS_PEC)
3244 i |= UPS_C_PORT_ENABLED;
3245 if (v & XHCI_PS_OCC)
3246 i |= UPS_C_OVERCURRENT_INDICATOR;
3247 if (v & XHCI_PS_WRC)
3248 i |= UPS_C_BH_PORT_RESET;
3249 if (v & XHCI_PS_PRC)
3250 i |= UPS_C_PORT_RESET;
3251 if (v & XHCI_PS_PLC)
3252 i |= UPS_C_PORT_LINK_STATE;
3253 if (v & XHCI_PS_CEC)
3254 i |= UPS_C_PORT_CONFIG_ERROR;
3256 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3257 len = sizeof(sc->sc_hub_desc.ps);
3260 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3261 err = USB_ERR_IOERROR;
3264 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3267 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3273 (index > sc->sc_noport)) {
3274 err = USB_ERR_IOERROR;
3278 port = XHCI_PORTSC(index);
3279 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3282 case UHF_PORT_U1_TIMEOUT:
3283 if (XHCI_PS_SPEED_GET(v) != 4) {
3284 err = USB_ERR_IOERROR;
3287 port = XHCI_PORTPMSC(index);
3288 v = XREAD4(sc, oper, port);
3289 v &= ~XHCI_PM3_U1TO_SET(0xFF);
3290 v |= XHCI_PM3_U1TO_SET(i);
3291 XWRITE4(sc, oper, port, v);
3293 case UHF_PORT_U2_TIMEOUT:
3294 if (XHCI_PS_SPEED_GET(v) != 4) {
3295 err = USB_ERR_IOERROR;
3298 port = XHCI_PORTPMSC(index);
3299 v = XREAD4(sc, oper, port);
3300 v &= ~XHCI_PM3_U2TO_SET(0xFF);
3301 v |= XHCI_PM3_U2TO_SET(i);
3302 XWRITE4(sc, oper, port, v);
3304 case UHF_BH_PORT_RESET:
3305 XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3307 case UHF_PORT_LINK_STATE:
3308 XWRITE4(sc, oper, port, v |
3309 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3310 /* 4ms settle time */
3311 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3313 case UHF_PORT_ENABLE:
3314 DPRINTFN(3, "set port enable %d\n", index);
3316 case UHF_PORT_SUSPEND:
3317 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3318 j = XHCI_PS_SPEED_GET(v);
3319 if ((j < 1) || (j > 3)) {
3320 /* non-supported speed */
3321 err = USB_ERR_IOERROR;
3324 XWRITE4(sc, oper, port, v |
3325 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3327 case UHF_PORT_RESET:
3328 DPRINTFN(6, "reset port %d\n", index);
3329 XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3331 case UHF_PORT_POWER:
3332 DPRINTFN(3, "set port power %d\n", index);
3333 XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3336 DPRINTFN(3, "set port test %d\n", index);
3338 case UHF_PORT_INDICATOR:
3339 DPRINTFN(3, "set port indicator %d\n", index);
3341 v &= ~XHCI_PS_PIC_SET(3);
3342 v |= XHCI_PS_PIC_SET(1);
3344 XWRITE4(sc, oper, port, v);
3347 err = USB_ERR_IOERROR;
3352 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3353 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3354 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3355 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3358 err = USB_ERR_IOERROR;
3368 xhci_xfer_setup(struct usb_setup_params *parm)
3370 struct usb_page_search page_info;
3371 struct usb_page_cache *pc;
3372 struct xhci_softc *sc;
3373 struct usb_xfer *xfer;
3378 sc = XHCI_BUS2SC(parm->udev->bus);
3379 xfer = parm->curr_xfer;
3382 * The proof for the "ntd" formula is illustrated like this:
3384 * +------------------------------------+
3388 * | | xxx | x | frm 0 |
3390 * | | xxx | xx | frm 1 |
3393 * +------------------------------------+
3395 * "xxx" means a completely full USB transfer descriptor
3397 * "x" and "xx" means a short USB packet
3399 * For the remainder of an USB transfer modulo
3400 * "max_data_length" we need two USB transfer descriptors.
3401 * One to transfer the remaining data and one to finalise with
3402 * a zero length packet in case the "force_short_xfer" flag is
3403 * set. We only need two USB transfer descriptors in the case
3404 * where the transfer length of the first one is a factor of
3405 * "max_frame_size". The rest of the needed USB transfer
3406 * descriptors is given by the buffer size divided by the
3407 * maximum data payload.
3409 parm->hc_max_packet_size = 0x400;
3410 parm->hc_max_packet_count = 16 * 3;
3411 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3413 xfer->flags_int.bdma_enable = 1;
3415 usbd_transfer_setup_sub(parm);
3417 if (xfer->flags_int.isochronous_xfr) {
3418 ntd = ((1 * xfer->nframes)
3419 + (xfer->max_data_length / xfer->max_hc_frame_size));
3420 } else if (xfer->flags_int.control_xfr) {
3421 ntd = ((2 * xfer->nframes) + 1 /* STATUS */
3422 + (xfer->max_data_length / xfer->max_hc_frame_size));
3424 ntd = ((2 * xfer->nframes)
3425 + (xfer->max_data_length / xfer->max_hc_frame_size));
3434 * Allocate queue heads and transfer descriptors
3438 if (usbd_transfer_setup_sub_malloc(
3439 parm, &pc, sizeof(struct xhci_td),
3440 XHCI_TD_ALIGN, ntd)) {
3441 parm->err = USB_ERR_NOMEM;
3445 for (n = 0; n != ntd; n++) {
3448 usbd_get_page(pc + n, 0, &page_info);
3450 td = page_info.buffer;
3453 td->td_self = page_info.physaddr;
3454 td->obj_next = last_obj;
3455 td->page_cache = pc + n;
3459 usb_pc_cpu_flush(pc + n);
3462 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3464 if (!xfer->flags_int.curr_dma_set) {
3465 xfer->flags_int.curr_dma_set = 1;
3471 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3473 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3474 struct usb_page_search buf_inp;
3475 struct usb_device *udev;
3476 struct xhci_endpoint_ext *pepext;
3477 struct usb_endpoint_descriptor *edesc;
3478 struct usb_page_cache *pcinp;
3483 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3484 xfer->endpoint->edesc);
3486 udev = xfer->xroot->udev;
3487 index = udev->controller_slot_id;
3489 pcinp = &sc->sc_hw.devs[index].input_pc;
3491 usbd_get_page(pcinp, 0, &buf_inp);
3493 edesc = xfer->endpoint->edesc;
3495 epno = edesc->bEndpointAddress;
3497 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3500 epno = XHCI_EPNO2EPID(epno);
3503 return (USB_ERR_NO_PIPE); /* invalid */
3507 /* configure endpoint */
3509 err = xhci_configure_endpoint_by_xfer(xfer);
3512 XHCI_CMD_UNLOCK(sc);
3517 * Get the endpoint into the stopped state according to the
3518 * endpoint context state diagram in the XHCI specification:
3521 err = xhci_cmd_stop_ep(sc, 0, epno, index);
3524 DPRINTF("Could not stop endpoint %u\n", epno);
3526 err = xhci_cmd_reset_ep(sc, 0, epno, index);
3529 DPRINTF("Could not reset endpoint %u\n", epno);
3531 err = xhci_cmd_set_tr_dequeue_ptr(sc, pepext->physaddr |
3532 XHCI_EPCTX_2_DCS_SET(1), 0, epno, index);
3535 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3538 * Get the endpoint into the running state according to the
3539 * endpoint context state diagram in the XHCI specification:
3542 xhci_configure_mask(udev, 1U << epno, 0);
3544 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3547 DPRINTF("Could not configure endpoint %u\n", epno);
3549 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3552 DPRINTF("Could not configure endpoint %u\n", epno);
3554 XHCI_CMD_UNLOCK(sc);
3560 xhci_xfer_unsetup(struct usb_xfer *xfer)
3566 xhci_start_dma_delay(struct usb_xfer *xfer)
3568 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3570 /* put transfer on interrupt queue (again) */
3571 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3573 (void)usb_proc_msignal(&sc->sc_config_proc,
3574 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3578 xhci_configure_msg(struct usb_proc_msg *pm)
3580 struct xhci_softc *sc;
3581 struct xhci_endpoint_ext *pepext;
3582 struct usb_xfer *xfer;
3584 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3587 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3589 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3590 xfer->endpoint->edesc);
3592 if ((pepext->trb_halted != 0) ||
3593 (pepext->trb_running == 0)) {
3597 /* clear halted and running */
3598 pepext->trb_halted = 0;
3599 pepext->trb_running = 0;
3601 /* nuke remaining buffered transfers */
3603 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
3605 * NOTE: We need to use the timeout
3606 * error code here else existing
3607 * isochronous clients can get
3610 if (pepext->xfer[i] != NULL) {
3611 xhci_device_done(pepext->xfer[i],
3617 * NOTE: The USB transfer cannot vanish in
3621 USB_BUS_UNLOCK(&sc->sc_bus);
3623 xhci_configure_reset_endpoint(xfer);
3625 USB_BUS_LOCK(&sc->sc_bus);
3627 /* check if halted is still cleared */
3628 if (pepext->trb_halted == 0) {
3629 pepext->trb_running = 1;
3630 pepext->trb_index = 0;
3635 if (xfer->flags_int.did_dma_delay) {
3637 /* remove transfer from interrupt queue (again) */
3638 usbd_transfer_dequeue(xfer);
3640 /* we are finally done */
3641 usb_dma_delay_done_cb(xfer);
3643 /* queue changed - restart */
3648 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3650 /* try to insert xfer on HW queue */
3651 xhci_transfer_insert(xfer);
3653 /* try to multi buffer */
3654 xhci_device_generic_multi_enter(xfer->endpoint, NULL);
3659 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3660 struct usb_endpoint *ep)
3662 struct xhci_endpoint_ext *pepext;
3664 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3665 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
3667 if (udev->flags.usb_mode != USB_MODE_HOST) {
3671 if (udev->parent_hub == NULL) {
3672 /* root HUB has special endpoint handling */
3676 ep->methods = &xhci_device_generic_methods;
3678 pepext = xhci_get_endpoint_ext(udev, edesc);
3680 USB_BUS_LOCK(udev->bus);
3681 pepext->trb_halted = 1;
3682 pepext->trb_running = 0;
3683 USB_BUS_UNLOCK(udev->bus);
3687 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
3693 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3695 struct xhci_endpoint_ext *pepext;
3699 if (udev->flags.usb_mode != USB_MODE_HOST) {
3703 if (udev->parent_hub == NULL) {
3704 /* root HUB has special endpoint handling */
3708 pepext = xhci_get_endpoint_ext(udev, ep->edesc);
3710 USB_BUS_LOCK(udev->bus);
3711 pepext->trb_halted = 1;
3712 pepext->trb_running = 0;
3713 USB_BUS_UNLOCK(udev->bus);
3717 xhci_device_init(struct usb_device *udev)
3719 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3723 /* no init for root HUB */
3724 if (udev->parent_hub == NULL)
3729 /* set invalid default */
3731 udev->controller_slot_id = sc->sc_noslot + 1;
3733 /* try to get a new slot ID from the XHCI */
3735 err = xhci_cmd_enable_slot(sc, &temp);
3738 XHCI_CMD_UNLOCK(sc);
3742 if (temp > sc->sc_noslot) {
3743 XHCI_CMD_UNLOCK(sc);
3744 return (USB_ERR_BAD_ADDRESS);
3747 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
3748 DPRINTF("slot %u already allocated.\n", temp);
3749 XHCI_CMD_UNLOCK(sc);
3750 return (USB_ERR_BAD_ADDRESS);
3753 /* store slot ID for later reference */
3755 udev->controller_slot_id = temp;
3757 /* reset data structure */
3759 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
3761 /* set mark slot allocated */
3763 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
3765 err = xhci_alloc_device_ext(udev);
3767 XHCI_CMD_UNLOCK(sc);
3769 /* get device into default state */
3772 err = xhci_set_address(udev, NULL, 0);
3778 xhci_device_uninit(struct usb_device *udev)
3780 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3783 /* no init for root HUB */
3784 if (udev->parent_hub == NULL)
3789 index = udev->controller_slot_id;
3791 if (index <= sc->sc_noslot) {
3792 xhci_cmd_disable_slot(sc, index);
3793 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
3795 /* free device extension */
3796 xhci_free_device_ext(udev);
3799 XHCI_CMD_UNLOCK(sc);
3803 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
3806 * Wait until the hardware has finished any possible use of
3807 * the transfer descriptor(s)
3809 *pus = 2048; /* microseconds */
3813 xhci_device_resume(struct usb_device *udev)
3815 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3821 /* check for root HUB */
3822 if (udev->parent_hub == NULL)
3825 index = udev->controller_slot_id;
3829 /* blindly resume all endpoints */
3831 USB_BUS_LOCK(udev->bus);
3833 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++)
3834 XWRITE4(sc, door, XHCI_DOORBELL(index), n | XHCI_DB_SID_SET(0));
3836 USB_BUS_UNLOCK(udev->bus);
3838 XHCI_CMD_UNLOCK(sc);
3842 xhci_device_suspend(struct usb_device *udev)
3844 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3851 /* check for root HUB */
3852 if (udev->parent_hub == NULL)
3855 index = udev->controller_slot_id;
3859 /* blindly suspend all endpoints */
3861 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
3862 err = xhci_cmd_stop_ep(sc, 1, n, index);
3864 DPRINTF("Failed to suspend endpoint "
3865 "%u on slot %u (ignored).\n", n, index);
3869 XHCI_CMD_UNLOCK(sc);
3873 xhci_set_hw_power(struct usb_bus *bus)
3879 xhci_device_state_change(struct usb_device *udev)
3881 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3882 struct usb_page_search buf_inp;
3886 /* check for root HUB */
3887 if (udev->parent_hub == NULL)
3890 index = udev->controller_slot_id;
3894 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
3895 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
3896 &sc->sc_hw.devs[index].tt);
3898 sc->sc_hw.devs[index].nports = 0;
3903 switch (usb_get_device_state(udev)) {
3904 case USB_STATE_POWERED:
3905 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
3908 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
3910 err = xhci_cmd_reset_dev(sc, index);
3913 DPRINTF("Device reset failed "
3914 "for slot %u.\n", index);
3918 case USB_STATE_ADDRESSED:
3919 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
3922 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
3924 err = xhci_cmd_configure_ep(sc, 0, 1, index);
3927 DPRINTF("Failed to deconfigure "
3928 "slot %u.\n", index);
3932 case USB_STATE_CONFIGURED:
3933 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
3936 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
3938 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
3940 xhci_configure_mask(udev, 1, 0);
3942 err = xhci_configure_device(udev);
3944 DPRINTF("Could not configure device "
3945 "at slot %u.\n", index);
3948 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3950 DPRINTF("Could not evaluate device "
3951 "context at slot %u.\n", index);
3958 XHCI_CMD_UNLOCK(sc);
3961 struct usb_bus_methods xhci_bus_methods = {
3962 .endpoint_init = xhci_ep_init,
3963 .endpoint_uninit = xhci_ep_uninit,
3964 .xfer_setup = xhci_xfer_setup,
3965 .xfer_unsetup = xhci_xfer_unsetup,
3966 .get_dma_delay = xhci_get_dma_delay,
3967 .device_init = xhci_device_init,
3968 .device_uninit = xhci_device_uninit,
3969 .device_resume = xhci_device_resume,
3970 .device_suspend = xhci_device_suspend,
3971 .set_hw_power = xhci_set_hw_power,
3972 .roothub_exec = xhci_roothub_exec,
3973 .xfer_poll = xhci_do_poll,
3974 .start_dma_delay = xhci_start_dma_delay,
3975 .set_address = xhci_set_address,
3976 .clear_stall = xhci_ep_clear_stall,
3977 .device_state_change = xhci_device_state_change,
3978 .set_hw_power_sleep = xhci_set_hw_power_sleep,