sys/dev/usb/controller/xhci.c

   1 /*-
   2  * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  */
  25
  26 /*
  27  * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
  28  *
  29  * The XHCI 1.0 spec can be found at
  30  * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
  31  * and the USB 3.0 spec at
  32  * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
  33  */
  34
  35 /*
  36  * A few words about the design implementation: This driver emulates
  37  * the concept about TDs which is found in EHCI specification. This
  38  * way we avoid too much diveration among USB drivers.
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include <sys/stdint.h>
  45 #include <sys/stddef.h>
  46 #include <sys/param.h>
  47 #include <sys/queue.h>
  48 #include <sys/types.h>
  49 #include <sys/systm.h>
  50 #include <sys/kernel.h>
  51 #include <sys/bus.h>
  52 #include <sys/module.h>
  53 #include <sys/lock.h>
  54 #include <sys/mutex.h>
  55 #include <sys/condvar.h>
  56 #include <sys/sysctl.h>
  57 #include <sys/sx.h>
  58 #include <sys/unistd.h>
  59 #include <sys/callout.h>
  60 #include <sys/malloc.h>
  61 #include <sys/priv.h>
  62
  63 #include <dev/usb/usb.h>
  64 #include <dev/usb/usbdi.h>
  65
  66 #define USB_DEBUG_VAR xhcidebug
  67
  68 #include <dev/usb/usb_core.h>
  69 #include <dev/usb/usb_debug.h>
  70 #include <dev/usb/usb_busdma.h>
  71 #include <dev/usb/usb_process.h>
  72 #include <dev/usb/usb_transfer.h>
  73 #include <dev/usb/usb_device.h>
  74 #include <dev/usb/usb_hub.h>
  75 #include <dev/usb/usb_util.h>
  76
  77 #include <dev/usb/usb_controller.h>
  78 #include <dev/usb/usb_bus.h>
  79 #include <dev/usb/controller/xhci.h>
  80 #include <dev/usb/controller/xhcireg.h>
  81
  82 #define XHCI_BUS2SC(bus) \
  83    ((struct xhci_softc *)(((uint8_t *)(bus)) - \
  84     ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
  85
  86 #ifdef USB_DEBUG
  87 static int xhcidebug;
  88 static int xhciroute;
  89
  90 SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
  91 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
  92     &xhcidebug, 0, "Debug level");
  93 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
  94 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN,
  95     &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller");
  96 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
  97 #endif
  98
  99 #define XHCI_INTR_ENDPT 1
 100
 101 struct xhci_std_temp {
 102         struct xhci_softc       *sc;
 103         struct usb_page_cache   *pc;
 104         struct xhci_td          *td;
 105         struct xhci_td          *td_next;
 106         uint32_t                len;
 107         uint32_t                offset;
 108         uint32_t                max_packet_size;
 109         uint32_t                average;
 110         uint16_t                isoc_delta;
 111         uint16_t                isoc_frame;
 112         uint8_t                 shortpkt;
 113         uint8_t                 multishort;
 114         uint8_t                 last_frame;
 115         uint8_t                 trb_type;
 116         uint8_t                 direction;
 117         uint8_t                 tbc;
 118         uint8_t                 tlbpc;
 119         uint8_t                 step_td;
 120         uint8_t                 do_isoc_sync;
 121 };
 122
 123 static void     xhci_do_poll(struct usb_bus *);
 124 static void     xhci_device_done(struct usb_xfer *, usb_error_t);
 125 static void     xhci_root_intr(struct xhci_softc *);
 126 static void     xhci_free_device_ext(struct usb_device *);
 127 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
 128                     struct usb_endpoint_descriptor *);
 129 static usb_proc_callback_t xhci_configure_msg;
 130 static usb_error_t xhci_configure_device(struct usb_device *);
 131 static usb_error_t xhci_configure_endpoint(struct usb_device *,
 132                     struct usb_endpoint_descriptor *, uint64_t, uint16_t,
 133                     uint8_t, uint8_t, uint8_t, uint16_t, uint16_t);
 134 static usb_error_t xhci_configure_mask(struct usb_device *,
 135                     uint32_t, uint8_t);
 136 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
 137                     uint64_t, uint8_t);
 138 static void xhci_endpoint_doorbell(struct usb_xfer *);
 139 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
 140 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
 141 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
 142 #ifdef USB_DEBUG
 143 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
 144 #endif
 145
 146 extern struct usb_bus_methods xhci_bus_methods;
 147
 148 #ifdef USB_DEBUG
 149 static void
 150 xhci_dump_trb(struct xhci_trb *trb)
 151 {
 152         DPRINTFN(5, "trb = %p\n", trb);
 153         DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
 154         DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
 155         DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
 156 }
 157
 158 static void
 159 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
 160 {
 161         DPRINTFN(5, "pep = %p\n", pep);
 162         DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
 163         DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
 164         DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
 165         DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
 166         DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
 167         DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
 168         DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
 169 }
 170
 171 static void
 172 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
 173 {
 174         DPRINTFN(5, "psl = %p\n", psl);
 175         DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
 176         DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
 177         DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
 178         DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
 179 }
 180 #endif
 181
 182 uint32_t
 183 xhci_get_port_route(void)
 184 {
 185 #ifdef USB_DEBUG
 186         return (0xFFFFFFFFU ^ ((uint32_t)xhciroute));
 187 #else
 188         return (0xFFFFFFFFU);
 189 #endif
 190 }
 191
 192 static void
 193 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
 194 {
 195         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 196         uint8_t i;
 197
 198         cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
 199            sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
 200
 201         cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
 202            sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
 203
 204         for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) {
 205                 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
 206                     XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
 207         }
 208 }
 209
 210 static void
 211 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
 212 {
 213         if (sc->sc_ctx_is_64_byte) {
 214                 uint32_t offset;
 215                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 216                 /* all contexts are initially 32-bytes */
 217                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 218                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 219         }
 220         *ptr = htole32(val);
 221 }
 222
 223 static uint32_t
 224 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
 225 {
 226         if (sc->sc_ctx_is_64_byte) {
 227                 uint32_t offset;
 228                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 229                 /* all contexts are initially 32-bytes */
 230                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 231                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 232         }
 233         return (le32toh(*ptr));
 234 }
 235
 236 static void
 237 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
 238 {
 239         if (sc->sc_ctx_is_64_byte) {
 240                 uint32_t offset;
 241                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 242                 /* all contexts are initially 32-bytes */
 243                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 244                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 245         }
 246         *ptr = htole64(val);
 247 }
 248
 249 #ifdef USB_DEBUG
 250 static uint64_t
 251 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
 252 {
 253         if (sc->sc_ctx_is_64_byte) {
 254                 uint32_t offset;
 255                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 256                 /* all contexts are initially 32-bytes */
 257                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 258                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 259         }
 260         return (le64toh(*ptr));
 261 }
 262 #endif
 263
 264 usb_error_t
 265 xhci_start_controller(struct xhci_softc *sc)
 266 {
 267         struct usb_page_search buf_res;
 268         struct xhci_hw_root *phwr;
 269         struct xhci_dev_ctx_addr *pdctxa;
 270         uint64_t addr;
 271         uint32_t temp;
 272         uint16_t i;
 273
 274         DPRINTF("\n");
 275
 276         sc->sc_capa_off = 0;
 277         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 278         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
 279         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 280
 281         DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
 282         DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
 283         DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
 284
 285         sc->sc_event_ccs = 1;
 286         sc->sc_event_idx = 0;
 287         sc->sc_command_ccs = 1;
 288         sc->sc_command_idx = 0;
 289
 290         DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
 291
 292         temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
 293
 294         DPRINTF("HCS0 = 0x%08x\n", temp);
 295
 296         if (XHCI_HCS0_CSZ(temp)) {
 297                 sc->sc_ctx_is_64_byte = 1;
 298                 device_printf(sc->sc_bus.parent, "64 byte context size.\n");
 299         } else {
 300                 sc->sc_ctx_is_64_byte = 0;
 301                 device_printf(sc->sc_bus.parent, "32 byte context size.\n");
 302         }
 303
 304         /* Reset controller */
 305         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
 306
 307         for (i = 0; i != 100; i++) {
 308                 usb_pause_mtx(NULL, hz / 100);
 309                 temp = XREAD4(sc, oper, XHCI_USBCMD) &
 310                     (XHCI_CMD_HCRST | XHCI_STS_CNR);
 311                 if (!temp)
 312                         break;
 313         }
 314
 315         if (temp) {
 316                 device_printf(sc->sc_bus.parent, "Controller "
 317                     "reset timeout.\n");
 318                 return (USB_ERR_IOERROR);
 319         }
 320
 321         if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
 322                 device_printf(sc->sc_bus.parent, "Controller does "
 323                     "not support 4K page size.\n");
 324                 return (USB_ERR_IOERROR);
 325         }
 326
 327         temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
 328
 329         i = XHCI_HCS1_N_PORTS(temp);
 330
 331         if (i == 0) {
 332                 device_printf(sc->sc_bus.parent, "Invalid number "
 333                     "of ports: %u\n", i);
 334                 return (USB_ERR_IOERROR);
 335         }
 336
 337         sc->sc_noport = i;
 338         sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
 339
 340         if (sc->sc_noslot > XHCI_MAX_DEVICES)
 341                 sc->sc_noslot = XHCI_MAX_DEVICES;
 342
 343         /* setup number of device slots */
 344
 345         DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
 346             XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
 347
 348         XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
 349
 350         DPRINTF("Max slots: %u\n", sc->sc_noslot);
 351
 352         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 353
 354         sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
 355
 356         if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
 357                 device_printf(sc->sc_bus.parent, "XHCI request "
 358                     "too many scratchpads\n");
 359                 return (USB_ERR_NOMEM);
 360         }
 361
 362         DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
 363
 364         temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
 365
 366         sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
 367             XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
 368
 369         temp = XREAD4(sc, oper, XHCI_USBSTS);
 370
 371         /* clear interrupts */
 372         XWRITE4(sc, oper, XHCI_USBSTS, temp);
 373         /* disable all device notifications */
 374         XWRITE4(sc, oper, XHCI_DNCTRL, 0);
 375
 376         /* setup device context base address */
 377         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
 378         pdctxa = buf_res.buffer;
 379         memset(pdctxa, 0, sizeof(*pdctxa));
 380
 381         addr = buf_res.physaddr;
 382         addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
 383
 384         /* slot 0 points to the table of scratchpad pointers */
 385         pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
 386
 387         for (i = 0; i != sc->sc_noscratch; i++) {
 388                 struct usb_page_search buf_scp;
 389                 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
 390                 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
 391         }
 392
 393         addr = buf_res.physaddr;
 394
 395         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 396         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 397         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 398         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 399
 400         /* Setup event table size */
 401
 402         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 403
 404         DPRINTF("HCS2=0x%08x\n", temp);
 405
 406         temp = XHCI_HCS2_ERST_MAX(temp);
 407         temp = 1U << temp;
 408         if (temp > XHCI_MAX_RSEG)
 409                 temp = XHCI_MAX_RSEG;
 410
 411         sc->sc_erst_max = temp;
 412
 413         DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
 414             XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp);
 415
 416         XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp));
 417
 418         /* Setup interrupt rate */
 419         XWRITE4(sc, runt, XHCI_IMOD(0), XHCI_IMOD_DEFAULT);
 420
 421         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 422
 423         phwr = buf_res.buffer;
 424         addr = buf_res.physaddr;
 425         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
 426
 427         /* reset hardware root structure */
 428         memset(phwr, 0, sizeof(*phwr));
 429
 430         phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
 431         phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
 432
 433         DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
 434
 435         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
 436         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
 437
 438         addr = (uint64_t)buf_res.physaddr;
 439
 440         DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
 441
 442         XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
 443         XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
 444
 445         /* Setup interrupter registers */
 446
 447         temp = XREAD4(sc, runt, XHCI_IMAN(0));
 448         temp |= XHCI_IMAN_INTR_ENA;
 449         XWRITE4(sc, runt, XHCI_IMAN(0), temp);
 450
 451         /* setup command ring control base address */
 452         addr = buf_res.physaddr;
 453         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 454
 455         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 456
 457         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 458         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 459
 460         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 461
 462         usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 463
 464         /* Go! */
 465         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
 466             XHCI_CMD_INTE | XHCI_CMD_HSEE);
 467
 468         for (i = 0; i != 100; i++) {
 469                 usb_pause_mtx(NULL, hz / 100);
 470                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 471                 if (!temp)
 472                         break;
 473         }
 474         if (temp) {
 475                 XWRITE4(sc, oper, XHCI_USBCMD, 0);
 476                 device_printf(sc->sc_bus.parent, "Run timeout.\n");
 477                 return (USB_ERR_IOERROR);
 478         }
 479
 480         /* catch any lost interrupts */
 481         xhci_do_poll(&sc->sc_bus);
 482
 483         return (0);
 484 }
 485
 486 usb_error_t
 487 xhci_halt_controller(struct xhci_softc *sc)
 488 {
 489         uint32_t temp;
 490         uint16_t i;
 491
 492         DPRINTF("\n");
 493
 494         sc->sc_capa_off = 0;
 495         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 496         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
 497         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 498
 499         /* Halt controller */
 500         XWRITE4(sc, oper, XHCI_USBCMD, 0);
 501
 502         for (i = 0; i != 100; i++) {
 503                 usb_pause_mtx(NULL, hz / 100);
 504                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 505                 if (temp)
 506                         break;
 507         }
 508
 509         if (!temp) {
 510                 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
 511                 return (USB_ERR_IOERROR);
 512         }
 513         return (0);
 514 }
 515
 516 usb_error_t
 517 xhci_init(struct xhci_softc *sc, device_t self)
 518 {
 519         /* initialise some bus fields */
 520         sc->sc_bus.parent = self;
 521
 522         /* set the bus revision */
 523         sc->sc_bus.usbrev = USB_REV_3_0;
 524
 525         /* set up the bus struct */
 526         sc->sc_bus.methods = &xhci_bus_methods;
 527
 528         /* setup devices array */
 529         sc->sc_bus.devices = sc->sc_devices;
 530         sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
 531
 532         /* setup command queue mutex and condition varible */
 533         cv_init(&sc->sc_cmd_cv, "CMDQ");
 534         sx_init(&sc->sc_cmd_sx, "CMDQ lock");
 535
 536         /* get all DMA memory */
 537         if (usb_bus_mem_alloc_all(&sc->sc_bus,
 538             USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
 539                 return (ENOMEM);
 540         }
 541
 542         sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
 543         sc->sc_config_msg[0].bus = &sc->sc_bus;
 544         sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
 545         sc->sc_config_msg[1].bus = &sc->sc_bus;
 546
 547         if (usb_proc_create(&sc->sc_config_proc,
 548             &sc->sc_bus.bus_mtx, device_get_nameunit(self), USB_PRI_MED)) {
 549                 printf("WARNING: Creation of XHCI configure "
 550                     "callback process failed.\n");
 551         }
 552         return (0);
 553 }
 554
 555 void
 556 xhci_uninit(struct xhci_softc *sc)
 557 {
 558         usb_proc_free(&sc->sc_config_proc);
 559
 560         usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 561
 562         cv_destroy(&sc->sc_cmd_cv);
 563         sx_destroy(&sc->sc_cmd_sx);
 564 }
 565
 566 static void
 567 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
 568 {
 569         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 570
 571         switch (state) {
 572         case USB_HW_POWER_SUSPEND:
 573                 DPRINTF("Stopping the XHCI\n");
 574                 xhci_halt_controller(sc);
 575                 break;
 576         case USB_HW_POWER_SHUTDOWN:
 577                 DPRINTF("Stopping the XHCI\n");
 578                 xhci_halt_controller(sc);
 579                 break;
 580         case USB_HW_POWER_RESUME:
 581                 DPRINTF("Starting the XHCI\n");
 582                 xhci_start_controller(sc);
 583                 break;
 584         default:
 585                 break;
 586         }
 587 }
 588
 589 static usb_error_t
 590 xhci_generic_done_sub(struct usb_xfer *xfer)
 591 {
 592         struct xhci_td *td;
 593         struct xhci_td *td_alt_next;
 594         uint32_t len;
 595         uint8_t status;
 596
 597         td = xfer->td_transfer_cache;
 598         td_alt_next = td->alt_next;
 599
 600         if (xfer->aframes != xfer->nframes)
 601                 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
 602
 603         while (1) {
 604
 605                 usb_pc_cpu_invalidate(td->page_cache);
 606
 607                 status = td->status;
 608                 len = td->remainder;
 609
 610                 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
 611                     xfer, (unsigned int)xfer->aframes,
 612                     (unsigned int)xfer->nframes,
 613                     (unsigned int)len, (unsigned int)td->len,
 614                     (unsigned int)status);
 615
 616                 /*
 617                  * Verify the status length and
 618                  * add the length to "frlengths[]":
 619                  */
 620                 if (len > td->len) {
 621                         /* should not happen */
 622                         DPRINTF("Invalid status length, "
 623                             "0x%04x/0x%04x bytes\n", len, td->len);
 624                         status = XHCI_TRB_ERROR_LENGTH;
 625                 } else if (xfer->aframes != xfer->nframes) {
 626                         xfer->frlengths[xfer->aframes] += td->len - len;
 627                 }
 628                 /* Check for last transfer */
 629                 if (((void *)td) == xfer->td_transfer_last) {
 630                         td = NULL;
 631                         break;
 632                 }
 633                 /* Check for transfer error */
 634                 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
 635                     status != XHCI_TRB_ERROR_SUCCESS) {
 636                         /* the transfer is finished */
 637                         td = NULL;
 638                         break;
 639                 }
 640                 /* Check for short transfer */
 641                 if (len > 0) {
 642                         if (xfer->flags_int.short_frames_ok ||
 643                             xfer->flags_int.isochronous_xfr ||
 644                             xfer->flags_int.control_xfr) {
 645                                 /* follow alt next */
 646                                 td = td->alt_next;
 647                         } else {
 648                                 /* the transfer is finished */
 649                                 td = NULL;
 650                         }
 651                         break;
 652                 }
 653                 td = td->obj_next;
 654
 655                 if (td->alt_next != td_alt_next) {
 656                         /* this USB frame is complete */
 657                         break;
 658                 }
 659         }
 660
 661         /* update transfer cache */
 662
 663         xfer->td_transfer_cache = td;
 664
 665         return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
 666             (status != XHCI_TRB_ERROR_SHORT_PKT &&
 667             status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
 668             USB_ERR_NORMAL_COMPLETION);
 669 }
 670
 671 static void
 672 xhci_generic_done(struct usb_xfer *xfer)
 673 {
 674         usb_error_t err = 0;
 675
 676         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
 677             xfer, xfer->endpoint);
 678
 679         /* reset scanner */
 680
 681         xfer->td_transfer_cache = xfer->td_transfer_first;
 682
 683         if (xfer->flags_int.control_xfr) {
 684
 685                 if (xfer->flags_int.control_hdr)
 686                         err = xhci_generic_done_sub(xfer);
 687
 688                 xfer->aframes = 1;
 689
 690                 if (xfer->td_transfer_cache == NULL)
 691                         goto done;
 692         }
 693
 694         while (xfer->aframes != xfer->nframes) {
 695
 696                 err = xhci_generic_done_sub(xfer);
 697                 xfer->aframes++;
 698
 699                 if (xfer->td_transfer_cache == NULL)
 700                         goto done;
 701         }
 702
 703         if (xfer->flags_int.control_xfr &&
 704             !xfer->flags_int.control_act)
 705                 err = xhci_generic_done_sub(xfer);
 706 done:
 707         /* transfer is complete */
 708         xhci_device_done(xfer, err);
 709 }
 710
 711 static void
 712 xhci_activate_transfer(struct usb_xfer *xfer)
 713 {
 714         struct xhci_td *td;
 715
 716         td = xfer->td_transfer_cache;
 717
 718         usb_pc_cpu_invalidate(td->page_cache);
 719
 720         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 721
 722                 /* activate the transfer */
 723
 724                 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
 725                 usb_pc_cpu_flush(td->page_cache);
 726
 727                 xhci_endpoint_doorbell(xfer);
 728         }
 729 }
 730
 731 static void
 732 xhci_skip_transfer(struct usb_xfer *xfer)
 733 {
 734         struct xhci_td *td;
 735         struct xhci_td *td_last;
 736
 737         td = xfer->td_transfer_cache;
 738         td_last = xfer->td_transfer_last;
 739
 740         td = td->alt_next;
 741
 742         usb_pc_cpu_invalidate(td->page_cache);
 743
 744         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 745
 746                 usb_pc_cpu_invalidate(td_last->page_cache);
 747
 748                 /* copy LINK TRB to current waiting location */
 749
 750                 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
 751                 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
 752                 usb_pc_cpu_flush(td->page_cache);
 753
 754                 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
 755                 usb_pc_cpu_flush(td->page_cache);
 756
 757                 xhci_endpoint_doorbell(xfer);
 758         }
 759 }
 760
 761 /*------------------------------------------------------------------------*
 762  *      xhci_check_transfer
 763  *------------------------------------------------------------------------*/
 764 static void
 765 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
 766 {
 767         int64_t offset;
 768         uint64_t td_event;
 769         uint32_t temp;
 770         uint32_t remainder;
 771         uint8_t status;
 772         uint8_t halted;
 773         uint8_t epno;
 774         uint8_t index;
 775         uint8_t i;
 776
 777         /* decode TRB */
 778         td_event = le64toh(trb->qwTrb0);
 779         temp = le32toh(trb->dwTrb2);
 780
 781         remainder = XHCI_TRB_2_REM_GET(temp);
 782         status = XHCI_TRB_2_ERROR_GET(temp);
 783
 784         temp = le32toh(trb->dwTrb3);
 785         epno = XHCI_TRB_3_EP_GET(temp);
 786         index = XHCI_TRB_3_SLOT_GET(temp);
 787
 788         /* check if error means halted */
 789         halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
 790             status != XHCI_TRB_ERROR_SUCCESS);
 791
 792         DPRINTF("slot=%u epno=%u remainder=%u status=%u\n",
 793             index, epno, remainder, status);
 794
 795         if (index > sc->sc_noslot) {
 796                 DPRINTF("Invalid slot.\n");
 797                 return;
 798         }
 799
 800         if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
 801                 DPRINTF("Invalid endpoint.\n");
 802                 return;
 803         }
 804
 805         /* try to find the USB transfer that generated the event */
 806         for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
 807                 struct usb_xfer *xfer;
 808                 struct xhci_td *td;
 809                 struct xhci_endpoint_ext *pepext;
 810
 811                 pepext = &sc->sc_hw.devs[index].endp[epno];
 812
 813                 xfer = pepext->xfer[i];
 814                 if (xfer == NULL)
 815                         continue;
 816
 817                 td = xfer->td_transfer_cache;
 818
 819                 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
 820                         (long long)td_event,
 821                         (long long)td->td_self,
 822                         (long long)td->td_self + sizeof(td->td_trb));
 823
 824                 /*
 825                  * NOTE: Some XHCI implementations might not trigger
 826                  * an event on the last LINK TRB so we need to
 827                  * consider both the last and second last event
 828                  * address as conditions for a successful transfer.
 829                  *
 830                  * NOTE: We assume that the XHCI will only trigger one
 831                  * event per chain of TRBs.
 832                  */
 833
 834                 offset = td_event - td->td_self;
 835
 836                 if (offset >= 0 &&
 837                     offset < (int64_t)sizeof(td->td_trb)) {
 838
 839                         usb_pc_cpu_invalidate(td->page_cache);
 840
 841                         /* compute rest of remainder, if any */
 842                         for (i = (offset / 16) + 1; i < td->ntrb; i++) {
 843                                 temp = le32toh(td->td_trb[i].dwTrb2);
 844                                 remainder += XHCI_TRB_2_BYTES_GET(temp);
 845                         }
 846
 847                         DPRINTFN(5, "New remainder: %u\n", remainder);
 848
 849                         /* clear isochronous transfer errors */
 850                         if (xfer->flags_int.isochronous_xfr) {
 851                                 if (halted) {
 852                                         halted = 0;
 853                                         status = XHCI_TRB_ERROR_SUCCESS;
 854                                         remainder = td->len;
 855                                 }
 856                         }
 857
 858                         /* "td->remainder" is verified later */
 859                         td->remainder = remainder;
 860                         td->status = status;
 861
 862                         usb_pc_cpu_flush(td->page_cache);
 863
 864                         /*
 865                          * 1) Last transfer descriptor makes the
 866                          * transfer done
 867                          */
 868                         if (((void *)td) == xfer->td_transfer_last) {
 869                                 DPRINTF("TD is last\n");
 870                                 xhci_generic_done(xfer);
 871                                 break;
 872                         }
 873
 874                         /*
 875                          * 2) Any kind of error makes the transfer
 876                          * done
 877                          */
 878                         if (halted) {
 879                                 DPRINTF("TD has I/O error\n");
 880                                 xhci_generic_done(xfer);
 881                                 break;
 882                         }
 883
 884                         /*
 885                          * 3) If there is no alternate next transfer,
 886                          * a short packet also makes the transfer done
 887                          */
 888                         if (td->remainder > 0) {
 889                                 DPRINTF("TD has short pkt\n");
 890                                 if (xfer->flags_int.short_frames_ok ||
 891                                     xfer->flags_int.isochronous_xfr ||
 892                                     xfer->flags_int.control_xfr) {
 893                                         /* follow the alt next */
 894                                         xfer->td_transfer_cache = td->alt_next;
 895                                         xhci_activate_transfer(xfer);
 896                                         break;
 897                                 }
 898                                 xhci_skip_transfer(xfer);
 899                                 xhci_generic_done(xfer);
 900                                 break;
 901                         }
 902
 903                         /*
 904                          * 4) Transfer complete - go to next TD
 905                          */
 906                         DPRINTF("Following next TD\n");
 907                         xfer->td_transfer_cache = td->obj_next;
 908                         xhci_activate_transfer(xfer);
 909                         break;          /* there should only be one match */
 910                 }
 911         }
 912 }
 913
 914 static void
 915 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
 916 {
 917         if (sc->sc_cmd_addr == trb->qwTrb0) {
 918                 DPRINTF("Received command event\n");
 919                 sc->sc_cmd_result[0] = trb->dwTrb2;
 920                 sc->sc_cmd_result[1] = trb->dwTrb3;
 921                 cv_signal(&sc->sc_cmd_cv);
 922         }
 923 }
 924
 925 static void
 926 xhci_interrupt_poll(struct xhci_softc *sc)
 927 {
 928         struct usb_page_search buf_res;
 929         struct xhci_hw_root *phwr;
 930         uint64_t addr;
 931         uint32_t temp;
 932         uint16_t i;
 933         uint8_t event;
 934         uint8_t j;
 935         uint8_t k;
 936         uint8_t t;
 937
 938         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 939
 940         phwr = buf_res.buffer;
 941
 942         /* Receive any events */
 943
 944         usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
 945
 946         i = sc->sc_event_idx;
 947         j = sc->sc_event_ccs;
 948         t = 2;
 949
 950         while (1) {
 951
 952                 temp = le32toh(phwr->hwr_events[i].dwTrb3);
 953
 954                 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
 955
 956                 if (j != k)
 957                         break;
 958
 959                 event = XHCI_TRB_3_TYPE_GET(temp);
 960
 961                 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
 962                     i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
 963                     (long)le32toh(phwr->hwr_events[i].dwTrb2),
 964                     (long)le32toh(phwr->hwr_events[i].dwTrb3));
 965
 966                 switch (event) {
 967                 case XHCI_TRB_EVENT_TRANSFER:
 968                         xhci_check_transfer(sc, &phwr->hwr_events[i]);
 969                         break;
 970                 case XHCI_TRB_EVENT_CMD_COMPLETE:
 971                         xhci_check_command(sc, &phwr->hwr_events[i]);
 972                         break;
 973                 default:
 974                         DPRINTF("Unhandled event = %u\n", event);
 975                         break;
 976                 }
 977
 978                 i++;
 979
 980                 if (i == XHCI_MAX_EVENTS) {
 981                         i = 0;
 982                         j ^= 1;
 983
 984                         /* check for timeout */
 985                         if (!--t)
 986                                 break;
 987                 }
 988         }
 989
 990         sc->sc_event_idx = i;
 991         sc->sc_event_ccs = j;
 992
 993         /*
 994          * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
 995          * latched. That means to activate the register we need to
 996          * write both the low and high double word of the 64-bit
 997          * register.
 998          */
 999
1000         addr = (uint32_t)buf_res.physaddr;
1001         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1002
1003         /* try to clear busy bit */
1004         addr |= XHCI_ERDP_LO_BUSY;
1005
1006         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1007         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1008 }
1009
1010 static usb_error_t
1011 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1012     uint16_t timeout_ms)
1013 {
1014         struct usb_page_search buf_res;
1015         struct xhci_hw_root *phwr;
1016         uint64_t addr;
1017         uint32_t temp;
1018         uint8_t i;
1019         uint8_t j;
1020         int err;
1021
1022         XHCI_CMD_ASSERT_LOCKED(sc);
1023
1024         /* get hardware root structure */
1025
1026         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1027
1028         phwr = buf_res.buffer;
1029
1030         /* Queue command */
1031
1032         USB_BUS_LOCK(&sc->sc_bus);
1033
1034         i = sc->sc_command_idx;
1035         j = sc->sc_command_ccs;
1036
1037         DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1038             i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1039             (long long)le64toh(trb->qwTrb0),
1040             (long)le32toh(trb->dwTrb2),
1041             (long)le32toh(trb->dwTrb3));
1042
1043         phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1044         phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1045
1046         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1047
1048         temp = trb->dwTrb3;
1049
1050         if (j)
1051                 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1052         else
1053                 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1054
1055         temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1056
1057         phwr->hwr_commands[i].dwTrb3 = temp;
1058
1059         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1060
1061         addr = buf_res.physaddr;
1062         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1063
1064         sc->sc_cmd_addr = htole64(addr);
1065
1066         i++;
1067
1068         if (i == (XHCI_MAX_COMMANDS - 1)) {
1069
1070                 if (j) {
1071                         temp = htole32(XHCI_TRB_3_TC_BIT |
1072                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1073                             XHCI_TRB_3_CYCLE_BIT);
1074                 } else {
1075                         temp = htole32(XHCI_TRB_3_TC_BIT |
1076                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1077                 }
1078
1079                 phwr->hwr_commands[i].dwTrb3 = temp;
1080
1081                 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1082
1083                 i = 0;
1084                 j ^= 1;
1085         }
1086
1087         sc->sc_command_idx = i;
1088         sc->sc_command_ccs = j;
1089
1090         XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1091
1092         err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1093             USB_MS_TO_TICKS(timeout_ms));
1094
1095         if (err) {
1096                 DPRINTFN(0, "Command timeout!\n");
1097                 err = USB_ERR_TIMEOUT;
1098                 trb->dwTrb2 = 0;
1099                 trb->dwTrb3 = 0;
1100         } else {
1101                 temp = le32toh(sc->sc_cmd_result[0]);
1102                 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1103                         err = USB_ERR_IOERROR;
1104
1105                 trb->dwTrb2 = sc->sc_cmd_result[0];
1106                 trb->dwTrb3 = sc->sc_cmd_result[1];
1107         }
1108
1109         USB_BUS_UNLOCK(&sc->sc_bus);
1110
1111         return (err);
1112 }
1113
1114 #if 0
1115 static usb_error_t
1116 xhci_cmd_nop(struct xhci_softc *sc)
1117 {
1118         struct xhci_trb trb;
1119         uint32_t temp;
1120
1121         DPRINTF("\n");
1122
1123         trb.qwTrb0 = 0;
1124         trb.dwTrb2 = 0;
1125         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1126
1127         trb.dwTrb3 = htole32(temp);
1128
1129         return (xhci_do_command(sc, &trb, 100 /* ms */));
1130 }
1131 #endif
1132
1133 static usb_error_t
1134 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1135 {
1136         struct xhci_trb trb;
1137         uint32_t temp;
1138         usb_error_t err;
1139
1140         DPRINTF("\n");
1141
1142         trb.qwTrb0 = 0;
1143         trb.dwTrb2 = 0;
1144         trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1145
1146         err = xhci_do_command(sc, &trb, 100 /* ms */);
1147         if (err)
1148                 goto done;
1149
1150         temp = le32toh(trb.dwTrb3);
1151
1152         *pslot = XHCI_TRB_3_SLOT_GET(temp);
1153
1154 done:
1155         return (err);
1156 }
1157
1158 static usb_error_t
1159 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1160 {
1161         struct xhci_trb trb;
1162         uint32_t temp;
1163
1164         DPRINTF("\n");
1165
1166         trb.qwTrb0 = 0;
1167         trb.dwTrb2 = 0;
1168         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1169             XHCI_TRB_3_SLOT_SET(slot_id);
1170
1171         trb.dwTrb3 = htole32(temp);
1172
1173         return (xhci_do_command(sc, &trb, 100 /* ms */));
1174 }
1175
1176 static usb_error_t
1177 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1178     uint8_t bsr, uint8_t slot_id)
1179 {
1180         struct xhci_trb trb;
1181         uint32_t temp;
1182
1183         DPRINTF("\n");
1184
1185         trb.qwTrb0 = htole64(input_ctx);
1186         trb.dwTrb2 = 0;
1187         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1188             XHCI_TRB_3_SLOT_SET(slot_id);
1189
1190         if (bsr)
1191                 temp |= XHCI_TRB_3_BSR_BIT;
1192
1193         trb.dwTrb3 = htole32(temp);
1194
1195         return (xhci_do_command(sc, &trb, 500 /* ms */));
1196 }
1197
1198 static usb_error_t
1199 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1200 {
1201         struct usb_page_search buf_inp;
1202         struct usb_page_search buf_dev;
1203         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1204         struct xhci_hw_dev *hdev;
1205         struct xhci_dev_ctx *pdev;
1206         struct xhci_endpoint_ext *pepext;
1207         uint32_t temp;
1208         uint16_t mps;
1209         usb_error_t err;
1210         uint8_t index;
1211
1212         /* the root HUB case is not handled here */
1213         if (udev->parent_hub == NULL)
1214                 return (USB_ERR_INVAL);
1215
1216         index = udev->controller_slot_id;
1217
1218         hdev =  &sc->sc_hw.devs[index];
1219
1220         if (mtx != NULL)
1221                 mtx_unlock(mtx);
1222
1223         XHCI_CMD_LOCK(sc);
1224
1225         switch (hdev->state) {
1226         case XHCI_ST_DEFAULT:
1227         case XHCI_ST_ENABLED:
1228
1229                 hdev->state = XHCI_ST_ENABLED;
1230
1231                 /* set configure mask to slot and EP0 */
1232                 xhci_configure_mask(udev, 3, 0);
1233
1234                 /* configure input slot context structure */
1235                 err = xhci_configure_device(udev);
1236
1237                 if (err != 0) {
1238                         DPRINTF("Could not configure device\n");
1239                         break;
1240                 }
1241
1242                 /* configure input endpoint context structure */
1243                 switch (udev->speed) {
1244                 case USB_SPEED_LOW:
1245                 case USB_SPEED_FULL:
1246                         mps = 8;
1247                         break;
1248                 case USB_SPEED_HIGH:
1249                         mps = 64;
1250                         break;
1251                 default:
1252                         mps = 512;
1253                         break;
1254                 }
1255
1256                 pepext = xhci_get_endpoint_ext(udev,
1257                     &udev->ctrl_ep_desc);
1258                 err = xhci_configure_endpoint(udev,
1259                     &udev->ctrl_ep_desc, pepext->physaddr,
1260                     0, 1, 1, 0, mps, mps);
1261
1262                 if (err != 0) {
1263                         DPRINTF("Could not configure default endpoint\n");
1264                         break;
1265                 }
1266
1267                 /* execute set address command */
1268                 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1269
1270                 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1271                     (address == 0), index);
1272
1273                 if (err != 0) {
1274                         DPRINTF("Could not set address "
1275                             "for slot %u.\n", index);
1276                         if (address != 0)
1277                                 break;
1278                 }
1279
1280                 /* update device address to new value */
1281
1282                 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1283                 pdev = buf_dev.buffer;
1284                 usb_pc_cpu_invalidate(&hdev->device_pc);
1285
1286                 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1287                 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1288
1289                 /* update device state to new value */
1290
1291                 if (address != 0)
1292                         hdev->state = XHCI_ST_ADDRESSED;
1293                 else
1294                         hdev->state = XHCI_ST_DEFAULT;
1295                 break;
1296
1297         default:
1298                 DPRINTF("Wrong state for set address.\n");
1299                 err = USB_ERR_IOERROR;
1300                 break;
1301         }
1302         XHCI_CMD_UNLOCK(sc);
1303
1304         if (mtx != NULL)
1305                 mtx_lock(mtx);
1306
1307         return (err);
1308 }
1309
1310 static usb_error_t
1311 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1312     uint8_t deconfigure, uint8_t slot_id)
1313 {
1314         struct xhci_trb trb;
1315         uint32_t temp;
1316
1317         DPRINTF("\n");
1318
1319         trb.qwTrb0 = htole64(input_ctx);
1320         trb.dwTrb2 = 0;
1321         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1322             XHCI_TRB_3_SLOT_SET(slot_id);
1323
1324         if (deconfigure)
1325                 temp |= XHCI_TRB_3_DCEP_BIT;
1326
1327         trb.dwTrb3 = htole32(temp);
1328
1329         return (xhci_do_command(sc, &trb, 100 /* ms */));
1330 }
1331
1332 static usb_error_t
1333 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1334     uint8_t slot_id)
1335 {
1336         struct xhci_trb trb;
1337         uint32_t temp;
1338
1339         DPRINTF("\n");
1340
1341         trb.qwTrb0 = htole64(input_ctx);
1342         trb.dwTrb2 = 0;
1343         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1344             XHCI_TRB_3_SLOT_SET(slot_id);
1345         trb.dwTrb3 = htole32(temp);
1346
1347         return (xhci_do_command(sc, &trb, 100 /* ms */));
1348 }
1349
1350 static usb_error_t
1351 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1352     uint8_t ep_id, uint8_t slot_id)
1353 {
1354         struct xhci_trb trb;
1355         uint32_t temp;
1356
1357         DPRINTF("\n");
1358
1359         trb.qwTrb0 = 0;
1360         trb.dwTrb2 = 0;
1361         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1362             XHCI_TRB_3_SLOT_SET(slot_id) |
1363             XHCI_TRB_3_EP_SET(ep_id);
1364
1365         if (preserve)
1366                 temp |= XHCI_TRB_3_PRSV_BIT;
1367
1368         trb.dwTrb3 = htole32(temp);
1369
1370         return (xhci_do_command(sc, &trb, 100 /* ms */));
1371 }
1372
1373 static usb_error_t
1374 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1375     uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1376 {
1377         struct xhci_trb trb;
1378         uint32_t temp;
1379
1380         DPRINTF("\n");
1381
1382         trb.qwTrb0 = htole64(dequeue_ptr);
1383
1384         temp = XHCI_TRB_2_STREAM_SET(stream_id);
1385         trb.dwTrb2 = htole32(temp);
1386
1387         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1388             XHCI_TRB_3_SLOT_SET(slot_id) |
1389             XHCI_TRB_3_EP_SET(ep_id);
1390         trb.dwTrb3 = htole32(temp);
1391
1392         return (xhci_do_command(sc, &trb, 100 /* ms */));
1393 }
1394
1395 static usb_error_t
1396 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1397     uint8_t ep_id, uint8_t slot_id)
1398 {
1399         struct xhci_trb trb;
1400         uint32_t temp;
1401
1402         DPRINTF("\n");
1403
1404         trb.qwTrb0 = 0;
1405         trb.dwTrb2 = 0;
1406         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1407             XHCI_TRB_3_SLOT_SET(slot_id) |
1408             XHCI_TRB_3_EP_SET(ep_id);
1409
1410         if (suspend)
1411                 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1412
1413         trb.dwTrb3 = htole32(temp);
1414
1415         return (xhci_do_command(sc, &trb, 100 /* ms */));
1416 }
1417
1418 static usb_error_t
1419 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1420 {
1421         struct xhci_trb trb;
1422         uint32_t temp;
1423
1424         DPRINTF("\n");
1425
1426         trb.qwTrb0 = 0;
1427         trb.dwTrb2 = 0;
1428         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1429             XHCI_TRB_3_SLOT_SET(slot_id);
1430
1431         trb.dwTrb3 = htole32(temp);
1432
1433         return (xhci_do_command(sc, &trb, 100 /* ms */));
1434 }
1435
1436 /*------------------------------------------------------------------------*
1437  *      xhci_interrupt - XHCI interrupt handler
1438  *------------------------------------------------------------------------*/
1439 void
1440 xhci_interrupt(struct xhci_softc *sc)
1441 {
1442         uint32_t status;
1443         uint32_t iman;
1444
1445         USB_BUS_LOCK(&sc->sc_bus);
1446
1447         status = XREAD4(sc, oper, XHCI_USBSTS);
1448         if (status == 0)
1449                 goto done;
1450
1451         /* acknowledge interrupts */
1452
1453         XWRITE4(sc, oper, XHCI_USBSTS, status);
1454
1455         DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1456
1457         if (status & XHCI_STS_EINT) {
1458
1459                 /* acknowledge pending event */
1460                 iman = XREAD4(sc, runt, XHCI_IMAN(0));
1461
1462                 /* reset interrupt */
1463                 XWRITE4(sc, runt, XHCI_IMAN(0), iman);
1464
1465                 DPRINTFN(16, "real interrupt (iman=0x%08x)\n", iman);
1466
1467                 /* check for event(s) */
1468                 xhci_interrupt_poll(sc);
1469         }
1470
1471         if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1472             XHCI_STS_HSE | XHCI_STS_HCE)) {
1473
1474                 if (status & XHCI_STS_PCD) {
1475                         xhci_root_intr(sc);
1476                 }
1477
1478                 if (status & XHCI_STS_HCH) {
1479                         printf("%s: host controller halted\n",
1480                             __FUNCTION__);
1481                 }
1482
1483                 if (status & XHCI_STS_HSE) {
1484                         printf("%s: host system error\n",
1485                             __FUNCTION__);
1486                 }
1487
1488                 if (status & XHCI_STS_HCE) {
1489                         printf("%s: host controller error\n",
1490                            __FUNCTION__);
1491                 }
1492         }
1493 done:
1494         USB_BUS_UNLOCK(&sc->sc_bus);
1495 }
1496
1497 /*------------------------------------------------------------------------*
1498  *      xhci_timeout - XHCI timeout handler
1499  *------------------------------------------------------------------------*/
1500 static void
1501 xhci_timeout(void *arg)
1502 {
1503         struct usb_xfer *xfer = arg;
1504
1505         DPRINTF("xfer=%p\n", xfer);
1506
1507         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1508
1509         /* transfer is transferred */
1510         xhci_device_done(xfer, USB_ERR_TIMEOUT);
1511 }
1512
1513 static void
1514 xhci_do_poll(struct usb_bus *bus)
1515 {
1516         struct xhci_softc *sc = XHCI_BUS2SC(bus);
1517
1518         USB_BUS_LOCK(&sc->sc_bus);
1519         xhci_interrupt_poll(sc);
1520         USB_BUS_UNLOCK(&sc->sc_bus);
1521 }
1522
1523 static void
1524 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1525 {
1526         struct usb_page_search buf_res;
1527         struct xhci_td *td;
1528         struct xhci_td *td_next;
1529         struct xhci_td *td_alt_next;
1530         uint32_t buf_offset;
1531         uint32_t average;
1532         uint32_t len_old;
1533         uint32_t dword;
1534         uint8_t shortpkt_old;
1535         uint8_t precompute;
1536         uint8_t x;
1537
1538         td_alt_next = NULL;
1539         buf_offset = 0;
1540         shortpkt_old = temp->shortpkt;
1541         len_old = temp->len;
1542         precompute = 1;
1543
1544 restart:
1545
1546         td = temp->td;
1547         td_next = temp->td_next;
1548
1549         while (1) {
1550
1551                 if (temp->len == 0) {
1552
1553                         if (temp->shortpkt)
1554                                 break;
1555
1556                         /* send a Zero Length Packet, ZLP, last */
1557
1558                         temp->shortpkt = 1;
1559                         average = 0;
1560
1561                 } else {
1562
1563                         average = temp->average;
1564
1565                         if (temp->len < average) {
1566                                 if (temp->len % temp->max_packet_size) {
1567                                         temp->shortpkt = 1;
1568                                 }
1569                                 average = temp->len;
1570                         }
1571                 }
1572
1573                 if (td_next == NULL)
1574                         panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1575
1576                 /* get next TD */
1577
1578                 td = td_next;
1579                 td_next = td->obj_next;
1580
1581                 /* check if we are pre-computing */
1582
1583                 if (precompute) {
1584
1585                         /* update remaining length */
1586
1587                         temp->len -= average;
1588
1589                         continue;
1590                 }
1591                 /* fill out current TD */
1592
1593                 td->len = average;
1594                 td->remainder = 0;
1595                 td->status = 0;
1596
1597                 /* update remaining length */
1598
1599                 temp->len -= average;
1600
1601                 /* reset TRB index */
1602
1603                 x = 0;
1604
1605                 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1606                         /* immediate data */
1607
1608                         if (average > 8)
1609                                 average = 8;
1610
1611                         td->td_trb[0].qwTrb0 = 0;
1612
1613                         usbd_copy_out(temp->pc, temp->offset + buf_offset,
1614                            (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1615                            average);
1616
1617                         dword = XHCI_TRB_2_BYTES_SET(8) |
1618                             XHCI_TRB_2_TDSZ_SET(0) |
1619                             XHCI_TRB_2_IRQ_SET(0);
1620
1621                         td->td_trb[0].dwTrb2 = htole32(dword);
1622
1623                         dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1624                           XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1625
1626                         /* check wLength */
1627                         if (td->td_trb[0].qwTrb0 &
1628                            htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1629                                 if (td->td_trb[0].qwTrb0 & htole64(1))
1630                                         dword |= XHCI_TRB_3_TRT_IN;
1631                                 else
1632                                         dword |= XHCI_TRB_3_TRT_OUT;
1633                         }
1634
1635                         td->td_trb[0].dwTrb3 = htole32(dword);
1636 #ifdef USB_DEBUG
1637                         xhci_dump_trb(&td->td_trb[x]);
1638 #endif
1639                         x++;
1640
1641                 } else do {
1642
1643                         uint32_t npkt;
1644
1645                         /* fill out buffer pointers */
1646
1647                         if (average == 0) {
1648                                 npkt = 1;
1649                                 memset(&buf_res, 0, sizeof(buf_res));
1650                         } else {
1651                                 usbd_get_page(temp->pc, temp->offset +
1652                                     buf_offset, &buf_res);
1653
1654                                 /* get length to end of page */
1655                                 if (buf_res.length > average)
1656                                         buf_res.length = average;
1657
1658                                 /* check for maximum length */
1659                                 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1660                                         buf_res.length = XHCI_TD_PAGE_SIZE;
1661
1662                                 /* setup npkt */
1663                                 npkt = (average + temp->max_packet_size - 1) /
1664                                     temp->max_packet_size;
1665
1666                                 if (npkt > 31)
1667                                         npkt = 31;
1668                         }
1669
1670                         /* fill out TRB's */
1671                         td->td_trb[x].qwTrb0 =
1672                             htole64((uint64_t)buf_res.physaddr);
1673
1674                         dword =
1675                           XHCI_TRB_2_BYTES_SET(buf_res.length) |
1676                           XHCI_TRB_2_TDSZ_SET(npkt) |
1677                           XHCI_TRB_2_IRQ_SET(0);
1678
1679                         td->td_trb[x].dwTrb2 = htole32(dword);
1680
1681                         dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1682                           XHCI_TRB_3_TYPE_SET(temp->trb_type) |
1683                           (temp->do_isoc_sync ?
1684                            XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8) :
1685                            XHCI_TRB_3_ISO_SIA_BIT) |
1686                           XHCI_TRB_3_TBC_SET(temp->tbc) |
1687                           XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1688
1689                         temp->do_isoc_sync = 0;
1690
1691                         if (temp->direction == UE_DIR_IN) {
1692                                 dword |= XHCI_TRB_3_DIR_IN;
1693
1694                                 /*
1695                                  * NOTE: Only the SETUP stage should
1696                                  * use the IDT bit. Else transactions
1697                                  * can be sent using the wrong data
1698                                  * toggle value.
1699                                  */
1700                                 if (temp->trb_type !=
1701                                     XHCI_TRB_TYPE_SETUP_STAGE &&
1702                                     temp->trb_type !=
1703                                     XHCI_TRB_TYPE_STATUS_STAGE)
1704                                         dword |= XHCI_TRB_3_ISP_BIT;
1705                         }
1706
1707                         td->td_trb[x].dwTrb3 = htole32(dword);
1708
1709                         average -= buf_res.length;
1710                         buf_offset += buf_res.length;
1711 #ifdef USB_DEBUG
1712                         xhci_dump_trb(&td->td_trb[x]);
1713 #endif
1714                         x++;
1715
1716                 } while (average != 0);
1717
1718                 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1719
1720                 /* store number of data TRB's */
1721
1722                 td->ntrb = x;
1723
1724                 DPRINTF("NTRB=%u\n", x);
1725
1726                 /* fill out link TRB */
1727
1728                 if (td_next != NULL) {
1729                         /* link the current TD with the next one */
1730                         td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1731                         DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1732                 } else {
1733                         /* this field will get updated later */
1734                         DPRINTF("NOLINK\n");
1735                 }
1736
1737                 dword = XHCI_TRB_2_IRQ_SET(0);
1738
1739                 td->td_trb[x].dwTrb2 = htole32(dword);
1740
1741                 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1742                     XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT;
1743
1744                 td->td_trb[x].dwTrb3 = htole32(dword);
1745
1746                 td->alt_next = td_alt_next;
1747 #ifdef USB_DEBUG
1748                 xhci_dump_trb(&td->td_trb[x]);
1749 #endif
1750                 usb_pc_cpu_flush(td->page_cache);
1751         }
1752
1753         if (precompute) {
1754                 precompute = 0;
1755
1756                 /* setup alt next pointer, if any */
1757                 if (temp->last_frame) {
1758                         td_alt_next = NULL;
1759                 } else {
1760                         /* we use this field internally */
1761                         td_alt_next = td_next;
1762                 }
1763
1764                 /* restore */
1765                 temp->shortpkt = shortpkt_old;
1766                 temp->len = len_old;
1767                 goto restart;
1768         }
1769
1770         /* remove cycle bit from first if we are stepping the TRBs */
1771         if (temp->step_td)
1772                 td->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1773
1774         /* remove chain bit because this is the last TRB in the chain */
1775         td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1776         td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1777
1778         usb_pc_cpu_flush(td->page_cache);
1779
1780         temp->td = td;
1781         temp->td_next = td_next;
1782 }
1783
1784 static void
1785 xhci_setup_generic_chain(struct usb_xfer *xfer)
1786 {
1787         struct xhci_std_temp temp;
1788         struct xhci_td *td;
1789         uint32_t x;
1790         uint32_t y;
1791         uint8_t mult;
1792
1793         temp.do_isoc_sync = 0;
1794         temp.step_td = 0;
1795         temp.tbc = 0;
1796         temp.tlbpc = 0;
1797         temp.average = xfer->max_hc_frame_size;
1798         temp.max_packet_size = xfer->max_packet_size;
1799         temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
1800         temp.pc = NULL;
1801         temp.last_frame = 0;
1802         temp.offset = 0;
1803         temp.multishort = xfer->flags_int.isochronous_xfr ||
1804             xfer->flags_int.control_xfr ||
1805             xfer->flags_int.short_frames_ok;
1806
1807         /* toggle the DMA set we are using */
1808         xfer->flags_int.curr_dma_set ^= 1;
1809
1810         /* get next DMA set */
1811         td = xfer->td_start[xfer->flags_int.curr_dma_set];
1812
1813         temp.td = NULL;
1814         temp.td_next = td;
1815
1816         xfer->td_transfer_first = td;
1817         xfer->td_transfer_cache = td;
1818
1819         if (xfer->flags_int.isochronous_xfr) {
1820                 uint8_t shift;
1821
1822                 /* compute multiplier for ISOCHRONOUS transfers */
1823                 mult = xfer->endpoint->ecomp ?
1824                     (xfer->endpoint->ecomp->bmAttributes & 3) : 0;
1825                 /* check for USB 2.0 multiplier */
1826                 if (mult == 0) {
1827                         mult = (xfer->endpoint->edesc->
1828                             wMaxPacketSize[1] >> 3) & 3;
1829                 }
1830                 /* range check */
1831                 if (mult > 2)
1832                         mult = 3;
1833                 else
1834                         mult++;
1835
1836                 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
1837
1838                 DPRINTF("MFINDEX=0x%08x\n", x);
1839
1840                 switch (usbd_get_speed(xfer->xroot->udev)) {
1841                 case USB_SPEED_FULL:
1842                         shift = 3;
1843                         temp.isoc_delta = 8;    /* 1ms */
1844                         x += temp.isoc_delta - 1;
1845                         x &= ~(temp.isoc_delta - 1);
1846                         break;
1847                 default:
1848                         shift = usbd_xfer_get_fps_shift(xfer);
1849                         temp.isoc_delta = 1U << shift;
1850                         x += temp.isoc_delta - 1;
1851                         x &= ~(temp.isoc_delta - 1);
1852                         /* simple frame load balancing */
1853                         x += xfer->endpoint->usb_uframe;
1854                         break;
1855                 }
1856
1857                 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
1858
1859                 if ((xfer->endpoint->is_synced == 0) ||
1860                     (y < (xfer->nframes << shift)) ||
1861                     (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
1862                         /*
1863                          * If there is data underflow or the pipe
1864                          * queue is empty we schedule the transfer a
1865                          * few frames ahead of the current frame
1866                          * position. Else two isochronous transfers
1867                          * might overlap.
1868                          */
1869                         xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
1870                         xfer->endpoint->is_synced = 1;
1871                         temp.do_isoc_sync = 1;
1872
1873                         DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
1874                 }
1875
1876                 /* compute isochronous completion time */
1877
1878                 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
1879
1880                 xfer->isoc_time_complete =
1881                     usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
1882                     (y / 8) + (((xfer->nframes << shift) + 7) / 8);
1883
1884                 x = 0;
1885                 temp.isoc_frame = xfer->endpoint->isoc_next;
1886                 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
1887
1888                 xfer->endpoint->isoc_next += xfer->nframes << shift;
1889
1890         } else if (xfer->flags_int.control_xfr) {
1891
1892                 /* check if we should prepend a setup message */
1893
1894                 if (xfer->flags_int.control_hdr) {
1895
1896                         temp.len = xfer->frlengths[0];
1897                         temp.pc = xfer->frbuffers + 0;
1898                         temp.shortpkt = temp.len ? 1 : 0;
1899                         temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
1900                         temp.direction = 0;
1901
1902                         /* check for last frame */
1903                         if (xfer->nframes == 1) {
1904                                 /* no STATUS stage yet, SETUP is last */
1905                                 if (xfer->flags_int.control_act)
1906                                         temp.last_frame = 1;
1907                         }
1908
1909                         xhci_setup_generic_chain_sub(&temp);
1910                 }
1911                 x = 1;
1912                 mult = 1;
1913                 temp.isoc_delta = 0;
1914                 temp.isoc_frame = 0;
1915                 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE;
1916         } else {
1917                 x = 0;
1918                 mult = 1;
1919                 temp.isoc_delta = 0;
1920                 temp.isoc_frame = 0;
1921                 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
1922         }
1923
1924         if (x != xfer->nframes) {
1925                 /* setup page_cache pointer */
1926                 temp.pc = xfer->frbuffers + x;
1927                 /* set endpoint direction */
1928                 temp.direction = UE_GET_DIR(xfer->endpointno);
1929         }
1930
1931         while (x != xfer->nframes) {
1932
1933                 /* DATA0 / DATA1 message */
1934
1935                 temp.len = xfer->frlengths[x];
1936                 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
1937                     x != 0 && temp.multishort == 0);
1938
1939                 x++;
1940
1941                 if (x == xfer->nframes) {
1942                         if (xfer->flags_int.control_xfr) {
1943                                 /* no STATUS stage yet, DATA is last */
1944                                 if (xfer->flags_int.control_act)
1945                                         temp.last_frame = 1;
1946                         } else {
1947                                 temp.last_frame = 1;
1948                         }
1949                 }
1950                 if (temp.len == 0) {
1951
1952                         /* make sure that we send an USB packet */
1953
1954                         temp.shortpkt = 0;
1955
1956                         temp.tbc = 0;
1957                         temp.tlbpc = mult - 1;
1958
1959                 } else if (xfer->flags_int.isochronous_xfr) {
1960
1961                         uint8_t tdpc;
1962
1963                         /*
1964                          * Isochronous transfers don't have short
1965                          * packet termination:
1966                          */
1967
1968                         temp.shortpkt = 1;
1969
1970                         /* isochronous transfers have a transfer limit */
1971
1972                         if (temp.len > xfer->max_frame_size)
1973                                 temp.len = xfer->max_frame_size;
1974
1975                         /* compute TD packet count */
1976                         tdpc = (temp.len + xfer->max_packet_size - 1) /
1977                             xfer->max_packet_size;
1978
1979                         temp.tbc = ((tdpc + mult - 1) / mult) - 1;
1980                         temp.tlbpc = (tdpc % mult);
1981
1982                         if (temp.tlbpc == 0)
1983                                 temp.tlbpc = mult - 1;
1984                         else
1985                                 temp.tlbpc--;
1986                 } else {
1987
1988                         /* regular data transfer */
1989
1990                         temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
1991                 }
1992
1993                 xhci_setup_generic_chain_sub(&temp);
1994
1995                 if (xfer->flags_int.isochronous_xfr) {
1996                         temp.offset += xfer->frlengths[x - 1];
1997                         temp.isoc_frame += temp.isoc_delta;
1998                 } else {
1999                         /* get next Page Cache pointer */
2000                         temp.pc = xfer->frbuffers + x;
2001                 }
2002         }
2003
2004         /* check if we should append a status stage */
2005
2006         if (xfer->flags_int.control_xfr &&
2007             !xfer->flags_int.control_act) {
2008
2009                 /*
2010                  * Send a DATA1 message and invert the current
2011                  * endpoint direction.
2012                  */
2013                 temp.step_td = (xfer->nframes != 0);
2014                 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2015                 temp.len = 0;
2016                 temp.pc = NULL;
2017                 temp.shortpkt = 0;
2018                 temp.last_frame = 1;
2019                 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2020
2021                 xhci_setup_generic_chain_sub(&temp);
2022         }
2023
2024         td = temp.td;
2025
2026         /* must have at least one frame! */
2027
2028         xfer->td_transfer_last = td;
2029
2030         DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2031 }
2032
2033 static void
2034 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2035 {
2036         struct usb_page_search buf_res;
2037         struct xhci_dev_ctx_addr *pdctxa;
2038
2039         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2040
2041         pdctxa = buf_res.buffer;
2042
2043         DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2044
2045         pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2046
2047         usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2048 }
2049
2050 static usb_error_t
2051 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2052 {
2053         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2054         struct usb_page_search buf_inp;
2055         struct xhci_input_dev_ctx *pinp;
2056         uint32_t temp;
2057         uint8_t index;
2058         uint8_t x;
2059
2060         index = udev->controller_slot_id;
2061
2062         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2063
2064         pinp = buf_inp.buffer;
2065
2066         if (drop) {
2067                 mask &= XHCI_INCTX_NON_CTRL_MASK;
2068                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2069                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2070         } else {
2071                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0);
2072                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2073
2074                 /* find most significant set bit */
2075                 for (x = 31; x != 1; x--) {
2076                         if (mask & (1 << x))
2077                                 break;
2078                 }
2079
2080                 /* adjust */
2081                 x--;
2082
2083                 /* figure out maximum */
2084                 if (x > sc->sc_hw.devs[index].context_num) {
2085                         sc->sc_hw.devs[index].context_num = x;
2086                         temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2087                         temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2088                         temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2089                         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2090                 }
2091         }
2092         return (0);
2093 }
2094
2095 static usb_error_t
2096 xhci_configure_endpoint(struct usb_device *udev,
2097     struct usb_endpoint_descriptor *edesc, uint64_t ring_addr,
2098     uint16_t interval, uint8_t max_packet_count, uint8_t mult,
2099     uint8_t fps_shift, uint16_t max_packet_size, uint16_t max_frame_size)
2100 {
2101         struct usb_page_search buf_inp;
2102         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2103         struct xhci_input_dev_ctx *pinp;
2104         uint32_t temp;
2105         uint8_t index;
2106         uint8_t epno;
2107         uint8_t type;
2108
2109         index = udev->controller_slot_id;
2110
2111         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2112
2113         pinp = buf_inp.buffer;
2114
2115         epno = edesc->bEndpointAddress;
2116         type = edesc->bmAttributes & UE_XFERTYPE;
2117
2118         if (type == UE_CONTROL)
2119                 epno |= UE_DIR_IN;
2120
2121         epno = XHCI_EPNO2EPID(epno);
2122
2123         if (epno == 0)
2124                 return (USB_ERR_NO_PIPE);               /* invalid */
2125
2126         if (max_packet_count == 0)
2127                 return (USB_ERR_BAD_BUFSIZE);
2128
2129         max_packet_count--;
2130
2131         if (mult == 0)
2132                 return (USB_ERR_BAD_BUFSIZE);
2133
2134         temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2135             XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2136             XHCI_EPCTX_0_LSA_SET(0);
2137
2138         switch (udev->speed) {
2139         case USB_SPEED_FULL:
2140         case USB_SPEED_LOW:
2141                 /* 1ms -> 125us */
2142                 fps_shift += 3;
2143                 break;
2144         default:
2145                 break;
2146         }
2147
2148         switch (type) {
2149         case UE_INTERRUPT:
2150                 if (fps_shift > 3)
2151                         fps_shift--;
2152                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2153                 break;
2154         case UE_ISOCHRONOUS:
2155                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2156
2157                 switch (udev->speed) {
2158                 case USB_SPEED_SUPER:
2159                         if (mult > 3)
2160                                 mult = 3;
2161                         temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2162                         max_packet_count /= mult;
2163                         break;
2164                 default:
2165                         break;
2166                 }
2167                 break;
2168         default:
2169                 break;
2170         }
2171
2172         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2173
2174         temp =
2175             XHCI_EPCTX_1_HID_SET(0) |
2176             XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2177             XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2178
2179         if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) {
2180                 if (type != UE_ISOCHRONOUS)
2181                         temp |= XHCI_EPCTX_1_CERR_SET(3);
2182         }
2183
2184         switch (type) {
2185         case UE_CONTROL:
2186                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2187                 break;
2188         case UE_ISOCHRONOUS:
2189                 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2190                 break;
2191         case UE_BULK:
2192                 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2193                 break;
2194         default:
2195                 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2196                 break;
2197         }
2198
2199         /* check for IN direction */
2200         if (epno & 1)
2201                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2202
2203         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2204
2205         ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2206
2207         xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2208
2209         switch (edesc->bmAttributes & UE_XFERTYPE) {
2210         case UE_INTERRUPT:
2211         case UE_ISOCHRONOUS:
2212                 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2213                     XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2214                     max_frame_size));
2215                 break;
2216         case UE_CONTROL:
2217                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2218                 break;
2219         default:
2220                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2221                 break;
2222         }
2223
2224         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2225
2226 #ifdef USB_DEBUG
2227         xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2228 #endif
2229         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2230
2231         return (0);             /* success */
2232 }
2233
2234 static usb_error_t
2235 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2236 {
2237         struct xhci_endpoint_ext *pepext;
2238         struct usb_endpoint_ss_comp_descriptor *ecomp;
2239
2240         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2241             xfer->endpoint->edesc);
2242
2243         ecomp = xfer->endpoint->ecomp;
2244
2245         pepext->trb[0].dwTrb3 = 0;      /* halt any transfers */
2246         usb_pc_cpu_flush(pepext->page_cache);
2247
2248         return (xhci_configure_endpoint(xfer->xroot->udev,
2249             xfer->endpoint->edesc, pepext->physaddr,
2250             xfer->interval, xfer->max_packet_count,
2251             (ecomp != NULL) ? (ecomp->bmAttributes & 3) + 1 : 1,
2252             usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2253             xfer->max_frame_size));
2254 }
2255
2256 static usb_error_t
2257 xhci_configure_device(struct usb_device *udev)
2258 {
2259         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2260         struct usb_page_search buf_inp;
2261         struct usb_page_cache *pcinp;
2262         struct xhci_input_dev_ctx *pinp;
2263         struct usb_device *hubdev;
2264         uint32_t temp;
2265         uint32_t route;
2266         uint32_t rh_port;
2267         uint8_t is_hub;
2268         uint8_t index;
2269         uint8_t depth;
2270
2271         index = udev->controller_slot_id;
2272
2273         DPRINTF("index=%u\n", index);
2274
2275         pcinp = &sc->sc_hw.devs[index].input_pc;
2276
2277         usbd_get_page(pcinp, 0, &buf_inp);
2278
2279         pinp = buf_inp.buffer;
2280
2281         rh_port = 0;
2282         route = 0;
2283
2284         /* figure out route string and root HUB port number */
2285
2286         for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2287
2288                 if (hubdev->parent_hub == NULL)
2289                         break;
2290
2291                 depth = hubdev->parent_hub->depth;
2292
2293                 /*
2294                  * NOTE: HS/FS/LS devices and the SS root HUB can have
2295                  * more than 15 ports
2296                  */
2297
2298                 rh_port = hubdev->port_no;
2299
2300                 if (depth == 0)
2301                         break;
2302
2303                 if (rh_port > 15)
2304                         rh_port = 15;
2305
2306                 if (depth < 6)
2307                         route |= rh_port << (4 * (depth - 1));
2308         }
2309
2310         DPRINTF("Route=0x%08x\n", route);
2311
2312         temp = XHCI_SCTX_0_ROUTE_SET(route) |
2313             XHCI_SCTX_0_CTX_NUM_SET(
2314             sc->sc_hw.devs[index].context_num + 1);
2315
2316         switch (udev->speed) {
2317         case USB_SPEED_LOW:
2318                 temp |= XHCI_SCTX_0_SPEED_SET(2);
2319                 if (udev->parent_hs_hub != NULL &&
2320                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2321                     UDPROTO_HSHUBMTT) {
2322                         DPRINTF("Device inherits MTT\n");
2323                         temp |= XHCI_SCTX_0_MTT_SET(1);
2324                 }
2325                 break;
2326         case USB_SPEED_HIGH:
2327                 temp |= XHCI_SCTX_0_SPEED_SET(3);
2328                 if (sc->sc_hw.devs[index].nports != 0 &&
2329                     udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2330                         DPRINTF("HUB supports MTT\n");
2331                         temp |= XHCI_SCTX_0_MTT_SET(1);
2332                 }
2333                 break;
2334         case USB_SPEED_FULL:
2335                 temp |= XHCI_SCTX_0_SPEED_SET(1);
2336                 if (udev->parent_hs_hub != NULL &&
2337                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2338                     UDPROTO_HSHUBMTT) {
2339                         DPRINTF("Device inherits MTT\n");
2340                         temp |= XHCI_SCTX_0_MTT_SET(1);
2341                 }
2342                 break;
2343         default:
2344                 temp |= XHCI_SCTX_0_SPEED_SET(4);
2345                 break;
2346         }
2347
2348         is_hub = sc->sc_hw.devs[index].nports != 0 &&
2349             (udev->speed == USB_SPEED_SUPER ||
2350             udev->speed == USB_SPEED_HIGH);
2351
2352         if (is_hub)
2353                 temp |= XHCI_SCTX_0_HUB_SET(1);
2354
2355         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2356
2357         temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2358
2359         if (is_hub) {
2360                 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2361                     sc->sc_hw.devs[index].nports);
2362         }
2363
2364         switch (udev->speed) {
2365         case USB_SPEED_SUPER:
2366                 switch (sc->sc_hw.devs[index].state) {
2367                 case XHCI_ST_ADDRESSED:
2368                 case XHCI_ST_CONFIGURED:
2369                         /* enable power save */
2370                         temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2371                         break;
2372                 default:
2373                         /* disable power save */
2374                         break;
2375                 }
2376                 break;
2377         default:
2378                 break;
2379         }
2380
2381         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2382
2383         temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2384
2385         if (is_hub) {
2386                 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2387                     sc->sc_hw.devs[index].tt);
2388         }
2389
2390         hubdev = udev->parent_hs_hub;
2391
2392         /* check if we should activate the transaction translator */
2393         switch (udev->speed) {
2394         case USB_SPEED_FULL:
2395         case USB_SPEED_LOW:
2396                 if (hubdev != NULL) {
2397                         temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2398                             hubdev->controller_slot_id);
2399                         temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2400                             udev->hs_port_no);
2401                 }
2402                 break;
2403         default:
2404                 break;
2405         }
2406
2407         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2408
2409         temp = XHCI_SCTX_3_DEV_ADDR_SET(udev->address) |
2410             XHCI_SCTX_3_SLOT_STATE_SET(0);
2411
2412         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2413
2414 #ifdef USB_DEBUG
2415         xhci_dump_device(sc, &pinp->ctx_slot);
2416 #endif
2417         usb_pc_cpu_flush(pcinp);
2418
2419         return (0);             /* success */
2420 }
2421
2422 static usb_error_t
2423 xhci_alloc_device_ext(struct usb_device *udev)
2424 {
2425         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2426         struct usb_page_search buf_dev;
2427         struct usb_page_search buf_ep;
2428         struct xhci_trb *trb;
2429         struct usb_page_cache *pc;
2430         struct usb_page *pg;
2431         uint64_t addr;
2432         uint8_t index;
2433         uint8_t i;
2434
2435         index = udev->controller_slot_id;
2436
2437         pc = &sc->sc_hw.devs[index].device_pc;
2438         pg = &sc->sc_hw.devs[index].device_pg;
2439
2440         /* need to initialize the page cache */
2441         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2442
2443         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2444             (2 * sizeof(struct xhci_dev_ctx)) :
2445             sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2446                 goto error;
2447
2448         usbd_get_page(pc, 0, &buf_dev);
2449
2450         pc = &sc->sc_hw.devs[index].input_pc;
2451         pg = &sc->sc_hw.devs[index].input_pg;
2452
2453         /* need to initialize the page cache */
2454         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2455
2456         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2457             (2 * sizeof(struct xhci_input_dev_ctx)) :
2458             sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2459                 goto error;
2460         }
2461
2462         pc = &sc->sc_hw.devs[index].endpoint_pc;
2463         pg = &sc->sc_hw.devs[index].endpoint_pg;
2464
2465         /* need to initialize the page cache */
2466         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2467
2468         if (usb_pc_alloc_mem(pc, pg,
2469             sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) {
2470                 goto error;
2471         }
2472
2473         /* initialise all endpoint LINK TRBs */
2474
2475         for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2476
2477                 /* lookup endpoint TRB ring */
2478                 usbd_get_page(pc, (uintptr_t)&
2479                     ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep);
2480
2481                 /* get TRB pointer */
2482                 trb = buf_ep.buffer;
2483                 trb += XHCI_MAX_TRANSFERS - 1;
2484
2485                 /* get TRB start address */
2486                 addr = buf_ep.physaddr;
2487
2488                 /* create LINK TRB */
2489                 trb->qwTrb0 = htole64(addr);
2490                 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2491                 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2492                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2493         }
2494
2495         usb_pc_cpu_flush(pc);
2496
2497         xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2498
2499         return (0);
2500
2501 error:
2502         xhci_free_device_ext(udev);
2503
2504         return (USB_ERR_NOMEM);
2505 }
2506
2507 static void
2508 xhci_free_device_ext(struct usb_device *udev)
2509 {
2510         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2511         uint8_t index;
2512
2513         index = udev->controller_slot_id;
2514         xhci_set_slot_pointer(sc, index, 0);
2515
2516         usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2517         usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2518         usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc);
2519 }
2520
2521 static struct xhci_endpoint_ext *
2522 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2523 {
2524         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2525         struct xhci_endpoint_ext *pepext;
2526         struct usb_page_cache *pc;
2527         struct usb_page_search buf_ep;
2528         uint8_t epno;
2529         uint8_t index;
2530
2531         epno = edesc->bEndpointAddress;
2532         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2533                 epno |= UE_DIR_IN;
2534
2535         epno = XHCI_EPNO2EPID(epno);
2536
2537         index = udev->controller_slot_id;
2538
2539         pc = &sc->sc_hw.devs[index].endpoint_pc;
2540
2541         usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->trb[epno][0], &buf_ep);
2542
2543         pepext = &sc->sc_hw.devs[index].endp[epno];
2544         pepext->page_cache = pc;
2545         pepext->trb = buf_ep.buffer;
2546         pepext->physaddr = buf_ep.physaddr;
2547
2548         return (pepext);
2549 }
2550
2551 static void
2552 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2553 {
2554         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2555         uint8_t epno;
2556         uint8_t index;
2557
2558         epno = xfer->endpointno;
2559         if (xfer->flags_int.control_xfr)
2560                 epno |= UE_DIR_IN;
2561
2562         epno = XHCI_EPNO2EPID(epno);
2563         index = xfer->xroot->udev->controller_slot_id;
2564
2565         if (xfer->xroot->udev->flags.self_suspended == 0) {
2566                 XWRITE4(sc, door, XHCI_DOORBELL(index),
2567                     epno | XHCI_DB_SID_SET(/*xfer->stream_id*/ 0));
2568         }
2569 }
2570
2571 static void
2572 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2573 {
2574         struct xhci_endpoint_ext *pepext;
2575
2576         if (xfer->flags_int.bandwidth_reclaimed) {
2577                 xfer->flags_int.bandwidth_reclaimed = 0;
2578
2579                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2580                     xfer->endpoint->edesc);
2581
2582                 pepext->trb_used--;
2583
2584                 pepext->xfer[xfer->qh_pos] = NULL;
2585
2586                 if (error && pepext->trb_running != 0) {
2587                         pepext->trb_halted = 1;
2588                         pepext->trb_running = 0;
2589                 }
2590         }
2591 }
2592
2593 static usb_error_t
2594 xhci_transfer_insert(struct usb_xfer *xfer)
2595 {
2596         struct xhci_td *td_first;
2597         struct xhci_td *td_last;
2598         struct xhci_endpoint_ext *pepext;
2599         uint64_t addr;
2600         uint8_t i;
2601         uint8_t inext;
2602         uint8_t trb_limit;
2603
2604         DPRINTFN(8, "\n");
2605
2606         /* check if already inserted */
2607         if (xfer->flags_int.bandwidth_reclaimed) {
2608                 DPRINTFN(8, "Already in schedule\n");
2609                 return (0);
2610         }
2611
2612         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2613             xfer->endpoint->edesc);
2614
2615         td_first = xfer->td_transfer_first;
2616         td_last = xfer->td_transfer_last;
2617         addr = pepext->physaddr;
2618
2619         switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2620         case UE_CONTROL:
2621         case UE_INTERRUPT:
2622                 /* single buffered */
2623                 trb_limit = 1;
2624                 break;
2625         default:
2626                 /* multi buffered */
2627                 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2628                 break;
2629         }
2630
2631         if (pepext->trb_used >= trb_limit) {
2632                 DPRINTFN(8, "Too many TDs queued.\n");
2633                 return (USB_ERR_NOMEM);
2634         }
2635
2636         /* check for stopped condition, after putting transfer on interrupt queue */
2637         if (pepext->trb_running == 0) {
2638                 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2639
2640                 DPRINTFN(8, "Not running\n");
2641
2642                 /* start configuration */
2643                 (void)usb_proc_msignal(&sc->sc_config_proc,
2644                     &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2645                 return (0);
2646         }
2647
2648         pepext->trb_used++;
2649
2650         /* get current TRB index */
2651         i = pepext->trb_index;
2652
2653         /* get next TRB index */
2654         inext = (i + 1);
2655
2656         /* the last entry of the ring is a hardcoded link TRB */
2657         if (inext >= (XHCI_MAX_TRANSFERS - 1))
2658                 inext = 0;
2659
2660         /* compute terminating return address */
2661         addr += inext * sizeof(struct xhci_trb);
2662
2663         /* update next pointer of last link TRB */
2664         td_last->td_trb[td_last->ntrb].qwTrb0 = htole64(addr);
2665         td_last->td_trb[td_last->ntrb].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2666         td_last->td_trb[td_last->ntrb].dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2667             XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2668
2669 #ifdef USB_DEBUG
2670         xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2671 #endif
2672         usb_pc_cpu_flush(td_last->page_cache);
2673
2674         /* write ahead chain end marker */
2675
2676         pepext->trb[inext].qwTrb0 = 0;
2677         pepext->trb[inext].dwTrb2 = 0;
2678         pepext->trb[inext].dwTrb3 = 0;
2679
2680         /* update next pointer of link TRB */
2681
2682         pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2683         pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2684
2685 #ifdef USB_DEBUG
2686         xhci_dump_trb(&pepext->trb[i]);
2687 #endif
2688         usb_pc_cpu_flush(pepext->page_cache);
2689
2690         /* toggle cycle bit which activates the transfer chain */
2691
2692         pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2693             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2694
2695         usb_pc_cpu_flush(pepext->page_cache);
2696
2697         DPRINTF("qh_pos = %u\n", i);
2698
2699         pepext->xfer[i] = xfer;
2700
2701         xfer->qh_pos = i;
2702
2703         xfer->flags_int.bandwidth_reclaimed = 1;
2704
2705         pepext->trb_index = inext;
2706
2707         xhci_endpoint_doorbell(xfer);
2708
2709         return (0);
2710 }
2711
2712 static void
2713 xhci_root_intr(struct xhci_softc *sc)
2714 {
2715         uint16_t i;
2716
2717         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2718
2719         /* clear any old interrupt data */
2720         memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2721
2722         for (i = 1; i <= sc->sc_noport; i++) {
2723                 /* pick out CHANGE bits from the status register */
2724                 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
2725                     XHCI_PS_CSC | XHCI_PS_PEC |
2726                     XHCI_PS_OCC | XHCI_PS_WRC |
2727                     XHCI_PS_PRC | XHCI_PS_PLC |
2728                     XHCI_PS_CEC)) {
2729                         sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2730                         DPRINTF("port %d changed\n", i);
2731                 }
2732         }
2733         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2734             sizeof(sc->sc_hub_idata));
2735 }
2736
2737 /*------------------------------------------------------------------------*
2738  *      xhci_device_done - XHCI done handler
2739  *
2740  * NOTE: This function can be called two times in a row on
2741  * the same USB transfer. From close and from interrupt.
2742  *------------------------------------------------------------------------*/
2743 static void
2744 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
2745 {
2746         DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2747             xfer, xfer->endpoint, error);
2748
2749         /* remove transfer from HW queue */
2750         xhci_transfer_remove(xfer, error);
2751
2752         /* dequeue transfer and start next transfer */
2753         usbd_transfer_done(xfer, error);
2754 }
2755
2756 /*------------------------------------------------------------------------*
2757  * XHCI data transfer support (generic type)
2758  *------------------------------------------------------------------------*/
2759 static void
2760 xhci_device_generic_open(struct usb_xfer *xfer)
2761 {
2762         if (xfer->flags_int.isochronous_xfr) {
2763                 switch (xfer->xroot->udev->speed) {
2764                 case USB_SPEED_FULL:
2765                         break;
2766                 default:
2767                         usb_hs_bandwidth_alloc(xfer);
2768                         break;
2769                 }
2770         }
2771 }
2772
2773 static void
2774 xhci_device_generic_close(struct usb_xfer *xfer)
2775 {
2776         DPRINTF("\n");
2777
2778         xhci_device_done(xfer, USB_ERR_CANCELLED);
2779
2780         if (xfer->flags_int.isochronous_xfr) {
2781                 switch (xfer->xroot->udev->speed) {
2782                 case USB_SPEED_FULL:
2783                         break;
2784                 default:
2785                         usb_hs_bandwidth_free(xfer);
2786                         break;
2787                 }
2788         }
2789 }
2790
2791 static void
2792 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
2793     struct usb_xfer *enter_xfer)
2794 {
2795         struct usb_xfer *xfer;
2796
2797         /* check if there is a current transfer */
2798         xfer = ep->endpoint_q.curr;
2799         if (xfer == NULL)
2800                 return;
2801
2802         /*
2803          * Check if the current transfer is started and then pickup
2804          * the next one, if any. Else wait for next start event due to
2805          * block on failure feature.
2806          */
2807         if (!xfer->flags_int.bandwidth_reclaimed)
2808                 return;
2809
2810         xfer = TAILQ_FIRST(&ep->endpoint_q.head);
2811         if (xfer == NULL) {
2812                 /*
2813                  * In case of enter we have to consider that the
2814                  * transfer is queued by the USB core after the enter
2815                  * method is called.
2816                  */
2817                 xfer = enter_xfer;
2818
2819                 if (xfer == NULL)
2820                         return;
2821         }
2822
2823         /* try to multi buffer */
2824         xhci_transfer_insert(xfer);
2825 }
2826
2827 static void
2828 xhci_device_generic_enter(struct usb_xfer *xfer)
2829 {
2830         DPRINTF("\n");
2831
2832         /* setup TD's and QH */
2833         xhci_setup_generic_chain(xfer);
2834
2835         xhci_device_generic_multi_enter(xfer->endpoint, xfer);
2836 }
2837
2838 static void
2839 xhci_device_generic_start(struct usb_xfer *xfer)
2840 {
2841         DPRINTF("\n");
2842
2843         /* try to insert xfer on HW queue */
2844         xhci_transfer_insert(xfer);
2845
2846         /* try to multi buffer */
2847         xhci_device_generic_multi_enter(xfer->endpoint, NULL);
2848
2849         /* add transfer last on interrupt queue */
2850         usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
2851
2852         /* start timeout, if any */
2853         if (xfer->timeout != 0)
2854                 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
2855 }
2856
2857 struct usb_pipe_methods xhci_device_generic_methods =
2858 {
2859         .open = xhci_device_generic_open,
2860         .close = xhci_device_generic_close,
2861         .enter = xhci_device_generic_enter,
2862         .start = xhci_device_generic_start,
2863 };
2864
2865 /*------------------------------------------------------------------------*
2866  * xhci root HUB support
2867  *------------------------------------------------------------------------*
2868  * Simulate a hardware HUB by handling all the necessary requests.
2869  *------------------------------------------------------------------------*/
2870
2871 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
2872
2873 static const
2874 struct usb_device_descriptor xhci_devd =
2875 {
2876         .bLength = sizeof(xhci_devd),
2877         .bDescriptorType = UDESC_DEVICE,        /* type */
2878         HSETW(.bcdUSB, 0x0300),                 /* USB version */
2879         .bDeviceClass = UDCLASS_HUB,            /* class */
2880         .bDeviceSubClass = UDSUBCLASS_HUB,      /* subclass */
2881         .bDeviceProtocol = UDPROTO_SSHUB,       /* protocol */
2882         .bMaxPacketSize = 9,                    /* max packet size */
2883         HSETW(.idVendor, 0x0000),               /* vendor */
2884         HSETW(.idProduct, 0x0000),              /* product */
2885         HSETW(.bcdDevice, 0x0100),              /* device version */
2886         .iManufacturer = 1,
2887         .iProduct = 2,
2888         .iSerialNumber = 0,
2889         .bNumConfigurations = 1,                /* # of configurations */
2890 };
2891
2892 static const
2893 struct xhci_bos_desc xhci_bosd = {
2894         .bosd = {
2895                 .bLength = sizeof(xhci_bosd.bosd),
2896                 .bDescriptorType = UDESC_BOS,
2897                 HSETW(.wTotalLength, sizeof(xhci_bosd)),
2898                 .bNumDeviceCaps = 3,
2899         },
2900         .usb2extd = {
2901                 .bLength = sizeof(xhci_bosd.usb2extd),
2902                 .bDescriptorType = 1,
2903                 .bDevCapabilityType = 2,
2904                 .bmAttributes[0] = 2,
2905         },
2906         .usbdcd = {
2907                 .bLength = sizeof(xhci_bosd.usbdcd),
2908                 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
2909                 .bDevCapabilityType = 3,
2910                 .bmAttributes = 0, /* XXX */
2911                 HSETW(.wSpeedsSupported, 0x000C),
2912                 .bFunctionalitySupport = 8,
2913                 .bU1DevExitLat = 255,   /* dummy - not used */
2914                 .wU2DevExitLat = { 0x00, 0x08 },
2915         },
2916         .cidd = {
2917                 .bLength = sizeof(xhci_bosd.cidd),
2918                 .bDescriptorType = 1,
2919                 .bDevCapabilityType = 4,
2920                 .bReserved = 0,
2921                 .bContainerID = 0, /* XXX */
2922         },
2923 };
2924
2925 static const
2926 struct xhci_config_desc xhci_confd = {
2927         .confd = {
2928                 .bLength = sizeof(xhci_confd.confd),
2929                 .bDescriptorType = UDESC_CONFIG,
2930                 .wTotalLength[0] = sizeof(xhci_confd),
2931                 .bNumInterface = 1,
2932                 .bConfigurationValue = 1,
2933                 .iConfiguration = 0,
2934                 .bmAttributes = UC_SELF_POWERED,
2935                 .bMaxPower = 0          /* max power */
2936         },
2937         .ifcd = {
2938                 .bLength = sizeof(xhci_confd.ifcd),
2939                 .bDescriptorType = UDESC_INTERFACE,
2940                 .bNumEndpoints = 1,
2941                 .bInterfaceClass = UICLASS_HUB,
2942                 .bInterfaceSubClass = UISUBCLASS_HUB,
2943                 .bInterfaceProtocol = 0,
2944         },
2945         .endpd = {
2946                 .bLength = sizeof(xhci_confd.endpd),
2947                 .bDescriptorType = UDESC_ENDPOINT,
2948                 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
2949                 .bmAttributes = UE_INTERRUPT,
2950                 .wMaxPacketSize[0] = 2,         /* max 15 ports */
2951                 .bInterval = 255,
2952         },
2953         .endpcd = {
2954                 .bLength = sizeof(xhci_confd.endpcd),
2955                 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
2956                 .bMaxBurst = 0,
2957                 .bmAttributes = 0,
2958         },
2959 };
2960
2961 static const
2962 struct usb_hub_ss_descriptor xhci_hubd = {
2963         .bLength = sizeof(xhci_hubd),
2964         .bDescriptorType = UDESC_SS_HUB,
2965 };
2966
2967 static usb_error_t
2968 xhci_roothub_exec(struct usb_device *udev,
2969     struct usb_device_request *req, const void **pptr, uint16_t *plength)
2970 {
2971         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2972         const char *str_ptr;
2973         const void *ptr;
2974         uint32_t port;
2975         uint32_t v;
2976         uint16_t len;
2977         uint16_t i;
2978         uint16_t value;
2979         uint16_t index;
2980         uint8_t j;
2981         usb_error_t err;
2982
2983         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2984
2985         /* buffer reset */
2986         ptr = (const void *)&sc->sc_hub_desc;
2987         len = 0;
2988         err = 0;
2989
2990         value = UGETW(req->wValue);
2991         index = UGETW(req->wIndex);
2992
2993         DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
2994             "wValue=0x%04x wIndex=0x%04x\n",
2995             req->bmRequestType, req->bRequest,
2996             UGETW(req->wLength), value, index);
2997
2998 #define C(x,y) ((x) | ((y) << 8))
2999         switch (C(req->bRequest, req->bmRequestType)) {
3000         case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3001         case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3002         case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3003                 /*
3004                  * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3005                  * for the integrated root hub.
3006                  */
3007                 break;
3008         case C(UR_GET_CONFIG, UT_READ_DEVICE):
3009                 len = 1;
3010                 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3011                 break;
3012         case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3013                 switch (value >> 8) {
3014                 case UDESC_DEVICE:
3015                         if ((value & 0xff) != 0) {
3016                                 err = USB_ERR_IOERROR;
3017                                 goto done;
3018                         }
3019                         len = sizeof(xhci_devd);
3020                         ptr = (const void *)&xhci_devd;
3021                         break;
3022
3023                 case UDESC_BOS:
3024                         if ((value & 0xff) != 0) {
3025                                 err = USB_ERR_IOERROR;
3026                                 goto done;
3027                         }
3028                         len = sizeof(xhci_bosd);
3029                         ptr = (const void *)&xhci_bosd;
3030                         break;
3031
3032                 case UDESC_CONFIG:
3033                         if ((value & 0xff) != 0) {
3034                                 err = USB_ERR_IOERROR;
3035                                 goto done;
3036                         }
3037                         len = sizeof(xhci_confd);
3038                         ptr = (const void *)&xhci_confd;
3039                         break;
3040
3041                 case UDESC_STRING:
3042                         switch (value & 0xff) {
3043                         case 0: /* Language table */
3044                                 str_ptr = "\001";
3045                                 break;
3046
3047                         case 1: /* Vendor */
3048                                 str_ptr = sc->sc_vendor;
3049                                 break;
3050
3051                         case 2: /* Product */
3052                                 str_ptr = "XHCI root HUB";
3053                                 break;
3054
3055                         default:
3056                                 str_ptr = "";
3057                                 break;
3058                         }
3059
3060                         len = usb_make_str_desc(
3061                             sc->sc_hub_desc.temp,
3062                             sizeof(sc->sc_hub_desc.temp),
3063                             str_ptr);
3064                         break;
3065
3066                 default:
3067                         err = USB_ERR_IOERROR;
3068                         goto done;
3069                 }
3070                 break;
3071         case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3072                 len = 1;
3073                 sc->sc_hub_desc.temp[0] = 0;
3074                 break;
3075         case C(UR_GET_STATUS, UT_READ_DEVICE):
3076                 len = 2;
3077                 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3078                 break;
3079         case C(UR_GET_STATUS, UT_READ_INTERFACE):
3080         case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3081                 len = 2;
3082                 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3083                 break;
3084         case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3085                 if (value >= XHCI_MAX_DEVICES) {
3086                         err = USB_ERR_IOERROR;
3087                         goto done;
3088                 }
3089                 break;
3090         case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3091                 if (value != 0 && value != 1) {
3092                         err = USB_ERR_IOERROR;
3093                         goto done;
3094                 }
3095                 sc->sc_conf = value;
3096                 break;
3097         case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3098                 break;
3099         case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3100         case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3101         case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3102                 err = USB_ERR_IOERROR;
3103                 goto done;
3104         case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3105                 break;
3106         case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3107                 break;
3108                 /* Hub requests */
3109         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3110                 break;
3111         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3112                 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3113
3114                 if ((index < 1) ||
3115                     (index > sc->sc_noport)) {
3116                         err = USB_ERR_IOERROR;
3117                         goto done;
3118                 }
3119                 port = XHCI_PORTSC(index);
3120
3121                 v = XREAD4(sc, oper, port);
3122                 i = XHCI_PS_PLS_GET(v);
3123                 v &= ~XHCI_PS_CLEAR;
3124
3125                 switch (value) {
3126                 case UHF_C_BH_PORT_RESET:
3127                         XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3128                         break;
3129                 case UHF_C_PORT_CONFIG_ERROR:
3130                         XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3131                         break;
3132                 case UHF_C_PORT_SUSPEND:
3133                 case UHF_C_PORT_LINK_STATE:
3134                         XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3135                         break;
3136                 case UHF_C_PORT_CONNECTION:
3137                         XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3138                         break;
3139                 case UHF_C_PORT_ENABLE:
3140                         XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3141                         break;
3142                 case UHF_C_PORT_OVER_CURRENT:
3143                         XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3144                         break;
3145                 case UHF_C_PORT_RESET:
3146                         XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3147                         break;
3148                 case UHF_PORT_ENABLE:
3149                         XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3150                         break;
3151                 case UHF_PORT_POWER:
3152                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3153                         break;
3154                 case UHF_PORT_INDICATOR:
3155                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3156                         break;
3157                 case UHF_PORT_SUSPEND:
3158
3159                         /* U3 -> U15 */
3160                         if (i == 3) {
3161                                 XWRITE4(sc, oper, port, v |
3162                                     XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3163                         }
3164
3165                         /* wait 20ms for resume sequence to complete */
3166                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3167
3168                         /* U0 */
3169                         XWRITE4(sc, oper, port, v |
3170                             XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3171                         break;
3172                 default:
3173                         err = USB_ERR_IOERROR;
3174                         goto done;
3175                 }
3176                 break;
3177
3178         case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3179                 if ((value & 0xff) != 0) {
3180                         err = USB_ERR_IOERROR;
3181                         goto done;
3182                 }
3183
3184                 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3185
3186                 sc->sc_hub_desc.hubd = xhci_hubd;
3187
3188                 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3189
3190                 if (XHCI_HCS0_PPC(v))
3191                         i = UHD_PWR_INDIVIDUAL;
3192                 else
3193                         i = UHD_PWR_GANGED;
3194
3195                 if (XHCI_HCS0_PIND(v))
3196                         i |= UHD_PORT_IND;
3197
3198                 i |= UHD_OC_INDIVIDUAL;
3199
3200                 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3201
3202                 /* see XHCI section 5.4.9: */
3203                 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3204
3205                 for (j = 1; j <= sc->sc_noport; j++) {
3206
3207                         v = XREAD4(sc, oper, XHCI_PORTSC(j));
3208                         if (v & XHCI_PS_DR) {
3209                                 sc->sc_hub_desc.hubd.
3210                                     DeviceRemovable[j / 8] |= 1U << (j % 8);
3211                         }
3212                 }
3213                 len = sc->sc_hub_desc.hubd.bLength;
3214                 break;
3215
3216         case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3217                 len = 16;
3218                 memset(sc->sc_hub_desc.temp, 0, 16);
3219                 break;
3220
3221         case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3222                 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3223
3224                 if ((index < 1) ||
3225                     (index > sc->sc_noport)) {
3226                         err = USB_ERR_IOERROR;
3227                         goto done;
3228                 }
3229
3230                 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3231
3232                 DPRINTFN(9, "port status=0x%08x\n", v);
3233
3234                 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3235
3236                 switch (XHCI_PS_SPEED_GET(v)) {
3237                 case 3:
3238                         i |= UPS_HIGH_SPEED;
3239                         break;
3240                 case 2:
3241                         i |= UPS_LOW_SPEED;
3242                         break;
3243                 case 1:
3244                         /* FULL speed */
3245                         break;
3246                 default:
3247                         i |= UPS_OTHER_SPEED;
3248                         break;
3249                 }
3250
3251                 if (v & XHCI_PS_CCS)
3252                         i |= UPS_CURRENT_CONNECT_STATUS;
3253                 if (v & XHCI_PS_PED)
3254                         i |= UPS_PORT_ENABLED;
3255                 if (v & XHCI_PS_OCA)
3256                         i |= UPS_OVERCURRENT_INDICATOR;
3257                 if (v & XHCI_PS_PR)
3258                         i |= UPS_RESET;
3259                 if (v & XHCI_PS_PP) {
3260                         /*
3261                          * The USB 3.0 RH is using the
3262                          * USB 2.0's power bit
3263                          */
3264                         i |= UPS_PORT_POWER;
3265                 }
3266                 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3267
3268                 i = 0;
3269                 if (v & XHCI_PS_CSC)
3270                         i |= UPS_C_CONNECT_STATUS;
3271                 if (v & XHCI_PS_PEC)
3272                         i |= UPS_C_PORT_ENABLED;
3273                 if (v & XHCI_PS_OCC)
3274                         i |= UPS_C_OVERCURRENT_INDICATOR;
3275                 if (v & XHCI_PS_WRC)
3276                         i |= UPS_C_BH_PORT_RESET;
3277                 if (v & XHCI_PS_PRC)
3278                         i |= UPS_C_PORT_RESET;
3279                 if (v & XHCI_PS_PLC)
3280                         i |= UPS_C_PORT_LINK_STATE;
3281                 if (v & XHCI_PS_CEC)
3282                         i |= UPS_C_PORT_CONFIG_ERROR;
3283
3284                 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3285                 len = sizeof(sc->sc_hub_desc.ps);
3286                 break;
3287
3288         case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3289                 err = USB_ERR_IOERROR;
3290                 goto done;
3291
3292         case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3293                 break;
3294
3295         case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3296
3297                 i = index >> 8;
3298                 index &= 0x00FF;
3299
3300                 if ((index < 1) ||
3301                     (index > sc->sc_noport)) {
3302                         err = USB_ERR_IOERROR;
3303                         goto done;
3304                 }
3305
3306                 port = XHCI_PORTSC(index);
3307                 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3308
3309                 switch (value) {
3310                 case UHF_PORT_U1_TIMEOUT:
3311                         if (XHCI_PS_SPEED_GET(v) != 4) {
3312                                 err = USB_ERR_IOERROR;
3313                                 goto done;
3314                         }
3315                         port = XHCI_PORTPMSC(index);
3316                         v = XREAD4(sc, oper, port);
3317                         v &= ~XHCI_PM3_U1TO_SET(0xFF);
3318                         v |= XHCI_PM3_U1TO_SET(i);
3319                         XWRITE4(sc, oper, port, v);
3320                         break;
3321                 case UHF_PORT_U2_TIMEOUT:
3322                         if (XHCI_PS_SPEED_GET(v) != 4) {
3323                                 err = USB_ERR_IOERROR;
3324                                 goto done;
3325                         }
3326                         port = XHCI_PORTPMSC(index);
3327                         v = XREAD4(sc, oper, port);
3328                         v &= ~XHCI_PM3_U2TO_SET(0xFF);
3329                         v |= XHCI_PM3_U2TO_SET(i);
3330                         XWRITE4(sc, oper, port, v);
3331                         break;
3332                 case UHF_BH_PORT_RESET:
3333                         XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3334                         break;
3335                 case UHF_PORT_LINK_STATE:
3336                         XWRITE4(sc, oper, port, v |
3337                             XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3338                         /* 4ms settle time */
3339                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3340                         break;
3341                 case UHF_PORT_ENABLE:
3342                         DPRINTFN(3, "set port enable %d\n", index);
3343                         break;
3344                 case UHF_PORT_SUSPEND:
3345                         DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3346                         j = XHCI_PS_SPEED_GET(v);
3347                         if ((j < 1) || (j > 3)) {
3348                                 /* non-supported speed */
3349                                 err = USB_ERR_IOERROR;
3350                                 goto done;
3351                         }
3352                         XWRITE4(sc, oper, port, v |
3353                             XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3354                         break;
3355                 case UHF_PORT_RESET:
3356                         DPRINTFN(6, "reset port %d\n", index);
3357                         XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3358                         break;
3359                 case UHF_PORT_POWER:
3360                         DPRINTFN(3, "set port power %d\n", index);
3361                         XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3362                         break;
3363                 case UHF_PORT_TEST:
3364                         DPRINTFN(3, "set port test %d\n", index);
3365                         break;
3366                 case UHF_PORT_INDICATOR:
3367                         DPRINTFN(3, "set port indicator %d\n", index);
3368
3369                         v &= ~XHCI_PS_PIC_SET(3);
3370                         v |= XHCI_PS_PIC_SET(1);
3371
3372                         XWRITE4(sc, oper, port, v);
3373                         break;
3374                 default:
3375                         err = USB_ERR_IOERROR;
3376                         goto done;
3377                 }
3378                 break;
3379
3380         case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3381         case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3382         case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3383         case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3384                 break;
3385         default:
3386                 err = USB_ERR_IOERROR;
3387                 goto done;
3388         }
3389 done:
3390         *plength = len;
3391         *pptr = ptr;
3392         return (err);
3393 }
3394
3395 static void
3396 xhci_xfer_setup(struct usb_setup_params *parm)
3397 {
3398         struct usb_page_search page_info;
3399         struct usb_page_cache *pc;
3400         struct xhci_softc *sc;
3401         struct usb_xfer *xfer;
3402         void *last_obj;
3403         uint32_t ntd;
3404         uint32_t n;
3405
3406         sc = XHCI_BUS2SC(parm->udev->bus);
3407         xfer = parm->curr_xfer;
3408
3409         /*
3410          * The proof for the "ntd" formula is illustrated like this:
3411          *
3412          * +------------------------------------+
3413          * |                                    |
3414          * |         |remainder ->              |
3415          * |   +-----+---+                      |
3416          * |   | xxx | x | frm 0                |
3417          * |   +-----+---++                     |
3418          * |   | xxx | xx | frm 1               |
3419          * |   +-----+----+                     |
3420          * |            ...                     |
3421          * +------------------------------------+
3422          *
3423          * "xxx" means a completely full USB transfer descriptor
3424          *
3425          * "x" and "xx" means a short USB packet
3426          *
3427          * For the remainder of an USB transfer modulo
3428          * "max_data_length" we need two USB transfer descriptors.
3429          * One to transfer the remaining data and one to finalise with
3430          * a zero length packet in case the "force_short_xfer" flag is
3431          * set. We only need two USB transfer descriptors in the case
3432          * where the transfer length of the first one is a factor of
3433          * "max_frame_size". The rest of the needed USB transfer
3434          * descriptors is given by the buffer size divided by the
3435          * maximum data payload.
3436          */
3437         parm->hc_max_packet_size = 0x400;
3438         parm->hc_max_packet_count = 16 * 3;
3439         parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3440
3441         xfer->flags_int.bdma_enable = 1;
3442
3443         usbd_transfer_setup_sub(parm);
3444
3445         if (xfer->flags_int.isochronous_xfr) {
3446                 ntd = ((1 * xfer->nframes)
3447                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3448         } else if (xfer->flags_int.control_xfr) {
3449                 ntd = ((2 * xfer->nframes) + 1  /* STATUS */
3450                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3451         } else {
3452                 ntd = ((2 * xfer->nframes)
3453                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3454         }
3455
3456 alloc_dma_set:
3457
3458         if (parm->err)
3459                 return;
3460
3461         /*
3462          * Allocate queue heads and transfer descriptors
3463          */
3464         last_obj = NULL;
3465
3466         if (usbd_transfer_setup_sub_malloc(
3467             parm, &pc, sizeof(struct xhci_td),
3468             XHCI_TD_ALIGN, ntd)) {
3469                 parm->err = USB_ERR_NOMEM;
3470                 return;
3471         }
3472         if (parm->buf) {
3473                 for (n = 0; n != ntd; n++) {
3474                         struct xhci_td *td;
3475
3476                         usbd_get_page(pc + n, 0, &page_info);
3477
3478                         td = page_info.buffer;
3479
3480                         /* init TD */
3481                         td->td_self = page_info.physaddr;
3482                         td->obj_next = last_obj;
3483                         td->page_cache = pc + n;
3484
3485                         last_obj = td;
3486
3487                         usb_pc_cpu_flush(pc + n);
3488                 }
3489         }
3490         xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3491
3492         if (!xfer->flags_int.curr_dma_set) {
3493                 xfer->flags_int.curr_dma_set = 1;
3494                 goto alloc_dma_set;
3495         }
3496 }
3497
3498 static usb_error_t
3499 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3500 {
3501         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3502         struct usb_page_search buf_inp;
3503         struct usb_device *udev;
3504         struct xhci_endpoint_ext *pepext;
3505         struct usb_endpoint_descriptor *edesc;
3506         struct usb_page_cache *pcinp;
3507         usb_error_t err;
3508         uint8_t index;
3509         uint8_t epno;
3510
3511         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3512             xfer->endpoint->edesc);
3513
3514         udev = xfer->xroot->udev;
3515         index = udev->controller_slot_id;
3516
3517         pcinp = &sc->sc_hw.devs[index].input_pc;
3518
3519         usbd_get_page(pcinp, 0, &buf_inp);
3520
3521         edesc = xfer->endpoint->edesc;
3522
3523         epno = edesc->bEndpointAddress;
3524
3525         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3526                 epno |= UE_DIR_IN;
3527
3528         epno = XHCI_EPNO2EPID(epno);
3529
3530         if (epno == 0)
3531                 return (USB_ERR_NO_PIPE);               /* invalid */
3532
3533         XHCI_CMD_LOCK(sc);
3534
3535         /* configure endpoint */
3536
3537         err = xhci_configure_endpoint_by_xfer(xfer);
3538
3539         if (err != 0) {
3540                 XHCI_CMD_UNLOCK(sc);
3541                 return (err);
3542         }
3543
3544         /*
3545          * Get the endpoint into the stopped state according to the
3546          * endpoint context state diagram in the XHCI specification:
3547          */
3548
3549         err = xhci_cmd_stop_ep(sc, 0, epno, index);
3550
3551         if (err != 0)
3552                 DPRINTF("Could not stop endpoint %u\n", epno);
3553
3554         err = xhci_cmd_reset_ep(sc, 0, epno, index);
3555
3556         if (err != 0)
3557                 DPRINTF("Could not reset endpoint %u\n", epno);
3558
3559         err = xhci_cmd_set_tr_dequeue_ptr(sc, pepext->physaddr |
3560             XHCI_EPCTX_2_DCS_SET(1), 0, epno, index);
3561
3562         if (err != 0)
3563                 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3564
3565         /*
3566          * Get the endpoint into the running state according to the
3567          * endpoint context state diagram in the XHCI specification:
3568          */
3569
3570         xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3571
3572         err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3573
3574         if (err != 0)
3575                 DPRINTF("Could not configure endpoint %u\n", epno);
3576
3577         err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3578
3579         if (err != 0)
3580                 DPRINTF("Could not configure endpoint %u\n", epno);
3581
3582         XHCI_CMD_UNLOCK(sc);
3583
3584         return (0);
3585 }
3586
3587 static void
3588 xhci_xfer_unsetup(struct usb_xfer *xfer)
3589 {
3590         return;
3591 }
3592
3593 static void
3594 xhci_start_dma_delay(struct usb_xfer *xfer)
3595 {
3596         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3597
3598         /* put transfer on interrupt queue (again) */
3599         usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3600
3601         (void)usb_proc_msignal(&sc->sc_config_proc,
3602             &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3603 }
3604
3605 static void
3606 xhci_configure_msg(struct usb_proc_msg *pm)
3607 {
3608         struct xhci_softc *sc;
3609         struct xhci_endpoint_ext *pepext;
3610         struct usb_xfer *xfer;
3611
3612         sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3613
3614 restart:
3615         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3616
3617                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3618                     xfer->endpoint->edesc);
3619
3620                 if ((pepext->trb_halted != 0) ||
3621                     (pepext->trb_running == 0)) {
3622
3623                         uint8_t i;
3624
3625                         /* clear halted and running */
3626                         pepext->trb_halted = 0;
3627                         pepext->trb_running = 0;
3628
3629                         /* nuke remaining buffered transfers */
3630
3631                         for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
3632                                 /*
3633                                  * NOTE: We need to use the timeout
3634                                  * error code here else existing
3635                                  * isochronous clients can get
3636                                  * confused:
3637                                  */
3638                                 if (pepext->xfer[i] != NULL) {
3639                                         xhci_device_done(pepext->xfer[i],
3640                                             USB_ERR_TIMEOUT);
3641                                 }
3642                         }
3643
3644                         /*
3645                          * NOTE: The USB transfer cannot vanish in
3646                          * this state!
3647                          */
3648
3649                         USB_BUS_UNLOCK(&sc->sc_bus);
3650
3651                         xhci_configure_reset_endpoint(xfer);
3652
3653                         USB_BUS_LOCK(&sc->sc_bus);
3654
3655                         /* check if halted is still cleared */
3656                         if (pepext->trb_halted == 0) {
3657                                 pepext->trb_running = 1;
3658                                 pepext->trb_index = 0;
3659                         }
3660                         goto restart;
3661                 }
3662
3663                 if (xfer->flags_int.did_dma_delay) {
3664
3665                         /* remove transfer from interrupt queue (again) */
3666                         usbd_transfer_dequeue(xfer);
3667
3668                         /* we are finally done */
3669                         usb_dma_delay_done_cb(xfer);
3670
3671                         /* queue changed - restart */
3672                         goto restart;
3673                 }
3674         }
3675
3676         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3677
3678                 /* try to insert xfer on HW queue */
3679                 xhci_transfer_insert(xfer);
3680
3681                 /* try to multi buffer */
3682                 xhci_device_generic_multi_enter(xfer->endpoint, NULL);
3683         }
3684 }
3685
3686 static void
3687 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3688     struct usb_endpoint *ep)
3689 {
3690         struct xhci_endpoint_ext *pepext;
3691
3692         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3693             ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
3694
3695         if (udev->flags.usb_mode != USB_MODE_HOST) {
3696                 /* not supported */
3697                 return;
3698         }
3699         if (udev->parent_hub == NULL) {
3700                 /* root HUB has special endpoint handling */
3701                 return;
3702         }
3703
3704         ep->methods = &xhci_device_generic_methods;
3705
3706         pepext = xhci_get_endpoint_ext(udev, edesc);
3707
3708         USB_BUS_LOCK(udev->bus);
3709         pepext->trb_halted = 1;
3710         pepext->trb_running = 0;
3711         USB_BUS_UNLOCK(udev->bus);
3712 }
3713
3714 static void
3715 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
3716 {
3717
3718 }
3719
3720 static void
3721 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3722 {
3723         struct xhci_endpoint_ext *pepext;
3724
3725         DPRINTF("\n");
3726
3727         if (udev->flags.usb_mode != USB_MODE_HOST) {
3728                 /* not supported */
3729                 return;
3730         }
3731         if (udev->parent_hub == NULL) {
3732                 /* root HUB has special endpoint handling */
3733                 return;
3734         }
3735
3736         pepext = xhci_get_endpoint_ext(udev, ep->edesc);
3737
3738         USB_BUS_LOCK(udev->bus);
3739         pepext->trb_halted = 1;
3740         pepext->trb_running = 0;
3741         USB_BUS_UNLOCK(udev->bus);
3742 }
3743
3744 static usb_error_t
3745 xhci_device_init(struct usb_device *udev)
3746 {
3747         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3748         usb_error_t err;
3749         uint8_t temp;
3750
3751         /* no init for root HUB */
3752         if (udev->parent_hub == NULL)
3753                 return (0);
3754
3755         XHCI_CMD_LOCK(sc);
3756
3757         /* set invalid default */
3758
3759         udev->controller_slot_id = sc->sc_noslot + 1;
3760
3761         /* try to get a new slot ID from the XHCI */
3762
3763         err = xhci_cmd_enable_slot(sc, &temp);
3764
3765         if (err) {
3766                 XHCI_CMD_UNLOCK(sc);
3767                 return (err);
3768         }
3769
3770         if (temp > sc->sc_noslot) {
3771                 XHCI_CMD_UNLOCK(sc);
3772                 return (USB_ERR_BAD_ADDRESS);
3773         }
3774
3775         if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
3776                 DPRINTF("slot %u already allocated.\n", temp);
3777                 XHCI_CMD_UNLOCK(sc);
3778                 return (USB_ERR_BAD_ADDRESS);
3779         }
3780
3781         /* store slot ID for later reference */
3782
3783         udev->controller_slot_id = temp;
3784
3785         /* reset data structure */
3786
3787         memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
3788
3789         /* set mark slot allocated */
3790
3791         sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
3792
3793         err = xhci_alloc_device_ext(udev);
3794
3795         XHCI_CMD_UNLOCK(sc);
3796
3797         /* get device into default state */
3798
3799         if (err == 0)
3800                 err = xhci_set_address(udev, NULL, 0);
3801
3802         return (err);
3803 }
3804
3805 static void
3806 xhci_device_uninit(struct usb_device *udev)
3807 {
3808         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3809         uint8_t index;
3810
3811         /* no init for root HUB */
3812         if (udev->parent_hub == NULL)
3813                 return;
3814
3815         XHCI_CMD_LOCK(sc);
3816
3817         index = udev->controller_slot_id;
3818
3819         if (index <= sc->sc_noslot) {
3820                 xhci_cmd_disable_slot(sc, index);
3821                 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
3822
3823                 /* free device extension */
3824                 xhci_free_device_ext(udev);
3825         }
3826
3827         XHCI_CMD_UNLOCK(sc);
3828 }
3829
3830 static void
3831 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
3832 {
3833         /*
3834          * Wait until the hardware has finished any possible use of
3835          * the transfer descriptor(s)
3836          */
3837         *pus = 2048;                    /* microseconds */
3838 }
3839
3840 static void
3841 xhci_device_resume(struct usb_device *udev)
3842 {
3843         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3844         uint8_t index;
3845         uint8_t n;
3846         uint8_t p;
3847
3848         DPRINTF("\n");
3849
3850         /* check for root HUB */
3851         if (udev->parent_hub == NULL)
3852                 return;
3853
3854         index = udev->controller_slot_id;
3855
3856         XHCI_CMD_LOCK(sc);
3857
3858         /* blindly resume all endpoints */
3859
3860         USB_BUS_LOCK(udev->bus);
3861
3862         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
3863                 for (p = 0; p != 1 /*XHCI_MAX_STREAMS*/; p++) {
3864                         XWRITE4(sc, door, XHCI_DOORBELL(index),
3865                             n | XHCI_DB_SID_SET(p));
3866                 }
3867         }
3868
3869         USB_BUS_UNLOCK(udev->bus);
3870
3871         XHCI_CMD_UNLOCK(sc);
3872 }
3873
3874 static void
3875 xhci_device_suspend(struct usb_device *udev)
3876 {
3877         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3878         uint8_t index;
3879         uint8_t n;
3880         usb_error_t err;
3881
3882         DPRINTF("\n");
3883
3884         /* check for root HUB */
3885         if (udev->parent_hub == NULL)
3886                 return;
3887
3888         index = udev->controller_slot_id;
3889
3890         XHCI_CMD_LOCK(sc);
3891
3892         /* blindly suspend all endpoints */
3893
3894         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
3895                 err = xhci_cmd_stop_ep(sc, 1, n, index);
3896                 if (err != 0) {
3897                         DPRINTF("Failed to suspend endpoint "
3898                             "%u on slot %u (ignored).\n", n, index);
3899                 }
3900         }
3901
3902         XHCI_CMD_UNLOCK(sc);
3903 }
3904
3905 static void
3906 xhci_set_hw_power(struct usb_bus *bus)
3907 {
3908         DPRINTF("\n");
3909 }
3910
3911 static void
3912 xhci_device_state_change(struct usb_device *udev)
3913 {
3914         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3915         struct usb_page_search buf_inp;
3916         usb_error_t err;
3917         uint8_t index;
3918
3919         /* check for root HUB */
3920         if (udev->parent_hub == NULL)
3921                 return;
3922
3923         index = udev->controller_slot_id;
3924
3925         DPRINTF("\n");
3926
3927         if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
3928                 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
3929                     &sc->sc_hw.devs[index].tt);
3930                 if (err != 0)
3931                         sc->sc_hw.devs[index].nports = 0;
3932         }
3933
3934         XHCI_CMD_LOCK(sc);
3935
3936         switch (usb_get_device_state(udev)) {
3937         case USB_STATE_POWERED:
3938                 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
3939                         break;
3940
3941                 /* set default state */
3942                 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
3943
3944                 /* reset number of contexts */
3945                 sc->sc_hw.devs[index].context_num = 0;
3946
3947                 err = xhci_cmd_reset_dev(sc, index);
3948
3949                 if (err != 0) {
3950                         DPRINTF("Device reset failed "
3951                             "for slot %u.\n", index);
3952                 }
3953                 break;
3954
3955         case USB_STATE_ADDRESSED:
3956                 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
3957                         break;
3958
3959                 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
3960
3961                 err = xhci_cmd_configure_ep(sc, 0, 1, index);
3962
3963                 if (err) {
3964                         DPRINTF("Failed to deconfigure "
3965                             "slot %u.\n", index);
3966                 }
3967                 break;
3968
3969         case USB_STATE_CONFIGURED:
3970                 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
3971                         break;
3972
3973                 /* set configured state */
3974                 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
3975
3976                 /* reset number of contexts */
3977                 sc->sc_hw.devs[index].context_num = 0;
3978
3979                 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
3980
3981                 xhci_configure_mask(udev, 3, 0);
3982
3983                 err = xhci_configure_device(udev);
3984                 if (err != 0) {
3985                         DPRINTF("Could not configure device "
3986                             "at slot %u.\n", index);
3987                 }
3988
3989                 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3990                 if (err != 0) {
3991                         DPRINTF("Could not evaluate device "
3992                             "context at slot %u.\n", index);
3993                 }
3994                 break;
3995
3996         default:
3997                 break;
3998         }
3999         XHCI_CMD_UNLOCK(sc);
4000 }
4001
4002 struct usb_bus_methods xhci_bus_methods = {
4003         .endpoint_init = xhci_ep_init,
4004         .endpoint_uninit = xhci_ep_uninit,
4005         .xfer_setup = xhci_xfer_setup,
4006         .xfer_unsetup = xhci_xfer_unsetup,
4007         .get_dma_delay = xhci_get_dma_delay,
4008         .device_init = xhci_device_init,
4009         .device_uninit = xhci_device_uninit,
4010         .device_resume = xhci_device_resume,
4011         .device_suspend = xhci_device_suspend,
4012         .set_hw_power = xhci_set_hw_power,
4013         .roothub_exec = xhci_roothub_exec,
4014         .xfer_poll = xhci_do_poll,
4015         .start_dma_delay = xhci_start_dma_delay,
4016         .set_address = xhci_set_address,
4017         .clear_stall = xhci_ep_clear_stall,
4018         .device_state_change = xhci_device_state_change,
4019         .set_hw_power_sleep = xhci_set_hw_power_sleep,
4020 };