sys/dev/usb/controller/xhci.c

   1 /*-
   2  * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  */
  25
  26 /*
  27  * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
  28  *
  29  * The XHCI 1.0 spec can be found at
  30  * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
  31  * and the USB 3.0 spec at
  32  * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
  33  */
  34
  35 /*
  36  * A few words about the design implementation: This driver emulates
  37  * the concept about TDs which is found in EHCI specification. This
  38  * way we avoid too much diveration among USB drivers.
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include <sys/stdint.h>
  45 #include <sys/stddef.h>
  46 #include <sys/param.h>
  47 #include <sys/queue.h>
  48 #include <sys/types.h>
  49 #include <sys/systm.h>
  50 #include <sys/kernel.h>
  51 #include <sys/bus.h>
  52 #include <sys/module.h>
  53 #include <sys/lock.h>
  54 #include <sys/mutex.h>
  55 #include <sys/condvar.h>
  56 #include <sys/sysctl.h>
  57 #include <sys/sx.h>
  58 #include <sys/unistd.h>
  59 #include <sys/callout.h>
  60 #include <sys/malloc.h>
  61 #include <sys/priv.h>
  62
  63 #include <dev/usb/usb.h>
  64 #include <dev/usb/usbdi.h>
  65
  66 #define USB_DEBUG_VAR xhcidebug
  67
  68 #include <dev/usb/usb_core.h>
  69 #include <dev/usb/usb_debug.h>
  70 #include <dev/usb/usb_busdma.h>
  71 #include <dev/usb/usb_process.h>
  72 #include <dev/usb/usb_transfer.h>
  73 #include <dev/usb/usb_device.h>
  74 #include <dev/usb/usb_hub.h>
  75 #include <dev/usb/usb_util.h>
  76
  77 #include <dev/usb/usb_controller.h>
  78 #include <dev/usb/usb_bus.h>
  79 #include <dev/usb/controller/xhci.h>
  80 #include <dev/usb/controller/xhcireg.h>
  81
  82 #define XHCI_BUS2SC(bus) \
  83    ((struct xhci_softc *)(((uint8_t *)(bus)) - \
  84     ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
  85
  86 #ifdef USB_DEBUG
  87 static int xhcidebug;
  88 static int xhciroute;
  89
  90 SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
  91 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
  92     &xhcidebug, 0, "Debug level");
  93 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
  94 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN,
  95     &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller");
  96 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
  97 #else
  98 #define xhciroute 0
  99 #endif
 100
 101 #define XHCI_INTR_ENDPT 1
 102
 103 struct xhci_std_temp {
 104         struct xhci_softc       *sc;
 105         struct usb_page_cache   *pc;
 106         struct xhci_td          *td;
 107         struct xhci_td          *td_next;
 108         uint32_t                len;
 109         uint32_t                offset;
 110         uint32_t                max_packet_size;
 111         uint32_t                average;
 112         uint16_t                isoc_delta;
 113         uint16_t                isoc_frame;
 114         uint8_t                 shortpkt;
 115         uint8_t                 multishort;
 116         uint8_t                 last_frame;
 117         uint8_t                 trb_type;
 118         uint8_t                 direction;
 119         uint8_t                 tbc;
 120         uint8_t                 tlbpc;
 121         uint8_t                 step_td;
 122         uint8_t                 do_isoc_sync;
 123 };
 124
 125 static void     xhci_do_poll(struct usb_bus *);
 126 static void     xhci_device_done(struct usb_xfer *, usb_error_t);
 127 static void     xhci_root_intr(struct xhci_softc *);
 128 static void     xhci_free_device_ext(struct usb_device *);
 129 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
 130                     struct usb_endpoint_descriptor *);
 131 static usb_proc_callback_t xhci_configure_msg;
 132 static usb_error_t xhci_configure_device(struct usb_device *);
 133 static usb_error_t xhci_configure_endpoint(struct usb_device *,
 134                     struct usb_endpoint_descriptor *, uint64_t, uint16_t,
 135                     uint8_t, uint8_t, uint8_t, uint16_t, uint16_t);
 136 static usb_error_t xhci_configure_mask(struct usb_device *,
 137                     uint32_t, uint8_t);
 138 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
 139                     uint64_t, uint8_t);
 140 static void xhci_endpoint_doorbell(struct usb_xfer *);
 141 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
 142 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
 143 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
 144 #ifdef USB_DEBUG
 145 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
 146 #endif
 147
 148 extern struct usb_bus_methods xhci_bus_methods;
 149
 150 #ifdef USB_DEBUG
 151 static void
 152 xhci_dump_trb(struct xhci_trb *trb)
 153 {
 154         DPRINTFN(5, "trb = %p\n", trb);
 155         DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
 156         DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
 157         DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
 158 }
 159
 160 static void
 161 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
 162 {
 163         DPRINTFN(5, "pep = %p\n", pep);
 164         DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
 165         DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
 166         DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
 167         DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
 168         DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
 169         DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
 170         DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
 171 }
 172
 173 static void
 174 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
 175 {
 176         DPRINTFN(5, "psl = %p\n", psl);
 177         DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
 178         DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
 179         DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
 180         DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
 181 }
 182 #endif
 183
 184 static void
 185 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
 186 {
 187         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 188         uint8_t i;
 189
 190         cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
 191            sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
 192
 193         cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
 194            sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
 195
 196         for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) {
 197                 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
 198                     XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
 199         }
 200 }
 201
 202 static void
 203 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
 204 {
 205         if (sc->sc_ctx_is_64_byte) {
 206                 uint32_t offset;
 207                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 208                 /* all contexts are initially 32-bytes */
 209                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 210                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 211         }
 212         *ptr = htole32(val);
 213 }
 214
 215 static uint32_t
 216 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
 217 {
 218         if (sc->sc_ctx_is_64_byte) {
 219                 uint32_t offset;
 220                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 221                 /* all contexts are initially 32-bytes */
 222                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 223                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 224         }
 225         return (le32toh(*ptr));
 226 }
 227
 228 static void
 229 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
 230 {
 231         if (sc->sc_ctx_is_64_byte) {
 232                 uint32_t offset;
 233                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 234                 /* all contexts are initially 32-bytes */
 235                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 236                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 237         }
 238         *ptr = htole64(val);
 239 }
 240
 241 #ifdef USB_DEBUG
 242 static uint64_t
 243 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
 244 {
 245         if (sc->sc_ctx_is_64_byte) {
 246                 uint32_t offset;
 247                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 248                 /* all contexts are initially 32-bytes */
 249                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 250                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 251         }
 252         return (le64toh(*ptr));
 253 }
 254 #endif
 255
 256 static int
 257 xhci_reset_command_queue_locked(struct xhci_softc *sc)
 258 {
 259         struct usb_page_search buf_res;
 260         struct xhci_hw_root *phwr;
 261         uint64_t addr;
 262         uint32_t temp;
 263
 264         DPRINTF("\n");
 265
 266         temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 267         if (temp & XHCI_CRCR_LO_CRR) {
 268                 DPRINTF("Command ring running\n");
 269                 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
 270
 271                 /*
 272                  * Try to abort the last command as per section
 273                  * 4.6.1.2 "Aborting a Command" of the XHCI
 274                  * specification:
 275                  */
 276
 277                 /* stop and cancel */
 278                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
 279                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 280
 281                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
 282                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 283
 284                 /* wait 250ms */
 285                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
 286
 287                 /* check if command ring is still running */
 288                 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 289                 if (temp & XHCI_CRCR_LO_CRR) {
 290                         DPRINTF("Comand ring still running\n");
 291                         return (USB_ERR_IOERROR);
 292                 }
 293         }
 294
 295         /* reset command ring */
 296         sc->sc_command_ccs = 1;
 297         sc->sc_command_idx = 0;
 298
 299         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 300
 301         /* setup command ring control base address */
 302         addr = buf_res.physaddr;
 303         phwr = buf_res.buffer;
 304         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 305
 306         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 307
 308         memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
 309         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 310
 311         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
 312
 313         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 314         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 315
 316         return (0);
 317 }
 318
 319 usb_error_t
 320 xhci_start_controller(struct xhci_softc *sc)
 321 {
 322         struct usb_page_search buf_res;
 323         struct xhci_hw_root *phwr;
 324         struct xhci_dev_ctx_addr *pdctxa;
 325         uint64_t addr;
 326         uint32_t temp;
 327         uint16_t i;
 328
 329         DPRINTF("\n");
 330
 331         sc->sc_capa_off = 0;
 332         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 333         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
 334         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 335
 336         DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
 337         DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
 338         DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
 339
 340         sc->sc_event_ccs = 1;
 341         sc->sc_event_idx = 0;
 342         sc->sc_command_ccs = 1;
 343         sc->sc_command_idx = 0;
 344
 345         DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
 346
 347         temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
 348
 349         DPRINTF("HCS0 = 0x%08x\n", temp);
 350
 351         if (XHCI_HCS0_CSZ(temp)) {
 352                 sc->sc_ctx_is_64_byte = 1;
 353                 device_printf(sc->sc_bus.parent, "64 byte context size.\n");
 354         } else {
 355                 sc->sc_ctx_is_64_byte = 0;
 356                 device_printf(sc->sc_bus.parent, "32 byte context size.\n");
 357         }
 358
 359         /* Reset controller */
 360         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
 361
 362         for (i = 0; i != 100; i++) {
 363                 usb_pause_mtx(NULL, hz / 100);
 364                 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
 365                     (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
 366                 if (!temp)
 367                         break;
 368         }
 369
 370         if (temp) {
 371                 device_printf(sc->sc_bus.parent, "Controller "
 372                     "reset timeout.\n");
 373                 return (USB_ERR_IOERROR);
 374         }
 375
 376         if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
 377                 device_printf(sc->sc_bus.parent, "Controller does "
 378                     "not support 4K page size.\n");
 379                 return (USB_ERR_IOERROR);
 380         }
 381
 382         temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
 383
 384         i = XHCI_HCS1_N_PORTS(temp);
 385
 386         if (i == 0) {
 387                 device_printf(sc->sc_bus.parent, "Invalid number "
 388                     "of ports: %u\n", i);
 389                 return (USB_ERR_IOERROR);
 390         }
 391
 392         sc->sc_noport = i;
 393         sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
 394
 395         if (sc->sc_noslot > XHCI_MAX_DEVICES)
 396                 sc->sc_noslot = XHCI_MAX_DEVICES;
 397
 398         /* setup number of device slots */
 399
 400         DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
 401             XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
 402
 403         XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
 404
 405         DPRINTF("Max slots: %u\n", sc->sc_noslot);
 406
 407         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 408
 409         sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
 410
 411         if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
 412                 device_printf(sc->sc_bus.parent, "XHCI request "
 413                     "too many scratchpads\n");
 414                 return (USB_ERR_NOMEM);
 415         }
 416
 417         DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
 418
 419         temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
 420
 421         sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
 422             XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
 423
 424         temp = XREAD4(sc, oper, XHCI_USBSTS);
 425
 426         /* clear interrupts */
 427         XWRITE4(sc, oper, XHCI_USBSTS, temp);
 428         /* disable all device notifications */
 429         XWRITE4(sc, oper, XHCI_DNCTRL, 0);
 430
 431         /* setup device context base address */
 432         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
 433         pdctxa = buf_res.buffer;
 434         memset(pdctxa, 0, sizeof(*pdctxa));
 435
 436         addr = buf_res.physaddr;
 437         addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
 438
 439         /* slot 0 points to the table of scratchpad pointers */
 440         pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
 441
 442         for (i = 0; i != sc->sc_noscratch; i++) {
 443                 struct usb_page_search buf_scp;
 444                 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
 445                 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
 446         }
 447
 448         addr = buf_res.physaddr;
 449
 450         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 451         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 452         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 453         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 454
 455         /* Setup event table size */
 456
 457         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 458
 459         DPRINTF("HCS2=0x%08x\n", temp);
 460
 461         temp = XHCI_HCS2_ERST_MAX(temp);
 462         temp = 1U << temp;
 463         if (temp > XHCI_MAX_RSEG)
 464                 temp = XHCI_MAX_RSEG;
 465
 466         sc->sc_erst_max = temp;
 467
 468         DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
 469             XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp);
 470
 471         XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp));
 472
 473         /* Setup interrupt rate */
 474         XWRITE4(sc, runt, XHCI_IMOD(0), XHCI_IMOD_DEFAULT);
 475
 476         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 477
 478         phwr = buf_res.buffer;
 479         addr = buf_res.physaddr;
 480         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
 481
 482         /* reset hardware root structure */
 483         memset(phwr, 0, sizeof(*phwr));
 484
 485         phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
 486         phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
 487
 488         DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
 489
 490         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
 491         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
 492
 493         addr = (uint64_t)buf_res.physaddr;
 494
 495         DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
 496
 497         XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
 498         XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
 499
 500         /* Setup interrupter registers */
 501
 502         temp = XREAD4(sc, runt, XHCI_IMAN(0));
 503         temp |= XHCI_IMAN_INTR_ENA;
 504         XWRITE4(sc, runt, XHCI_IMAN(0), temp);
 505
 506         /* setup command ring control base address */
 507         addr = buf_res.physaddr;
 508         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 509
 510         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 511
 512         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 513         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 514
 515         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 516
 517         usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 518
 519         /* Go! */
 520         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
 521             XHCI_CMD_INTE | XHCI_CMD_HSEE);
 522
 523         for (i = 0; i != 100; i++) {
 524                 usb_pause_mtx(NULL, hz / 100);
 525                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 526                 if (!temp)
 527                         break;
 528         }
 529         if (temp) {
 530                 XWRITE4(sc, oper, XHCI_USBCMD, 0);
 531                 device_printf(sc->sc_bus.parent, "Run timeout.\n");
 532                 return (USB_ERR_IOERROR);
 533         }
 534
 535         /* catch any lost interrupts */
 536         xhci_do_poll(&sc->sc_bus);
 537
 538         if (sc->sc_port_route != NULL) {
 539                 /* Route all ports to the XHCI by default */
 540                 sc->sc_port_route(sc->sc_bus.parent,
 541                     ~xhciroute, xhciroute);
 542         }
 543         return (0);
 544 }
 545
 546 usb_error_t
 547 xhci_halt_controller(struct xhci_softc *sc)
 548 {
 549         uint32_t temp;
 550         uint16_t i;
 551
 552         DPRINTF("\n");
 553
 554         sc->sc_capa_off = 0;
 555         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 556         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
 557         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 558
 559         /* Halt controller */
 560         XWRITE4(sc, oper, XHCI_USBCMD, 0);
 561
 562         for (i = 0; i != 100; i++) {
 563                 usb_pause_mtx(NULL, hz / 100);
 564                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 565                 if (temp)
 566                         break;
 567         }
 568
 569         if (!temp) {
 570                 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
 571                 return (USB_ERR_IOERROR);
 572         }
 573         return (0);
 574 }
 575
 576 usb_error_t
 577 xhci_init(struct xhci_softc *sc, device_t self)
 578 {
 579         /* initialise some bus fields */
 580         sc->sc_bus.parent = self;
 581
 582         /* set the bus revision */
 583         sc->sc_bus.usbrev = USB_REV_3_0;
 584
 585         /* set up the bus struct */
 586         sc->sc_bus.methods = &xhci_bus_methods;
 587
 588         /* setup devices array */
 589         sc->sc_bus.devices = sc->sc_devices;
 590         sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
 591
 592         /* setup command queue mutex and condition varible */
 593         cv_init(&sc->sc_cmd_cv, "CMDQ");
 594         sx_init(&sc->sc_cmd_sx, "CMDQ lock");
 595
 596         /* get all DMA memory */
 597         if (usb_bus_mem_alloc_all(&sc->sc_bus,
 598             USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
 599                 return (ENOMEM);
 600         }
 601
 602         sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
 603         sc->sc_config_msg[0].bus = &sc->sc_bus;
 604         sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
 605         sc->sc_config_msg[1].bus = &sc->sc_bus;
 606
 607         if (usb_proc_create(&sc->sc_config_proc,
 608             &sc->sc_bus.bus_mtx, device_get_nameunit(self), USB_PRI_MED)) {
 609                 printf("WARNING: Creation of XHCI configure "
 610                     "callback process failed.\n");
 611         }
 612         return (0);
 613 }
 614
 615 void
 616 xhci_uninit(struct xhci_softc *sc)
 617 {
 618         usb_proc_free(&sc->sc_config_proc);
 619
 620         usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 621
 622         cv_destroy(&sc->sc_cmd_cv);
 623         sx_destroy(&sc->sc_cmd_sx);
 624 }
 625
 626 static void
 627 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
 628 {
 629         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 630
 631         switch (state) {
 632         case USB_HW_POWER_SUSPEND:
 633                 DPRINTF("Stopping the XHCI\n");
 634                 xhci_halt_controller(sc);
 635                 break;
 636         case USB_HW_POWER_SHUTDOWN:
 637                 DPRINTF("Stopping the XHCI\n");
 638                 xhci_halt_controller(sc);
 639                 break;
 640         case USB_HW_POWER_RESUME:
 641                 DPRINTF("Starting the XHCI\n");
 642                 xhci_start_controller(sc);
 643                 break;
 644         default:
 645                 break;
 646         }
 647 }
 648
 649 static usb_error_t
 650 xhci_generic_done_sub(struct usb_xfer *xfer)
 651 {
 652         struct xhci_td *td;
 653         struct xhci_td *td_alt_next;
 654         uint32_t len;
 655         uint8_t status;
 656
 657         td = xfer->td_transfer_cache;
 658         td_alt_next = td->alt_next;
 659
 660         if (xfer->aframes != xfer->nframes)
 661                 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
 662
 663         while (1) {
 664
 665                 usb_pc_cpu_invalidate(td->page_cache);
 666
 667                 status = td->status;
 668                 len = td->remainder;
 669
 670                 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
 671                     xfer, (unsigned int)xfer->aframes,
 672                     (unsigned int)xfer->nframes,
 673                     (unsigned int)len, (unsigned int)td->len,
 674                     (unsigned int)status);
 675
 676                 /*
 677                  * Verify the status length and
 678                  * add the length to "frlengths[]":
 679                  */
 680                 if (len > td->len) {
 681                         /* should not happen */
 682                         DPRINTF("Invalid status length, "
 683                             "0x%04x/0x%04x bytes\n", len, td->len);
 684                         status = XHCI_TRB_ERROR_LENGTH;
 685                 } else if (xfer->aframes != xfer->nframes) {
 686                         xfer->frlengths[xfer->aframes] += td->len - len;
 687                 }
 688                 /* Check for last transfer */
 689                 if (((void *)td) == xfer->td_transfer_last) {
 690                         td = NULL;
 691                         break;
 692                 }
 693                 /* Check for transfer error */
 694                 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
 695                     status != XHCI_TRB_ERROR_SUCCESS) {
 696                         /* the transfer is finished */
 697                         td = NULL;
 698                         break;
 699                 }
 700                 /* Check for short transfer */
 701                 if (len > 0) {
 702                         if (xfer->flags_int.short_frames_ok ||
 703                             xfer->flags_int.isochronous_xfr ||
 704                             xfer->flags_int.control_xfr) {
 705                                 /* follow alt next */
 706                                 td = td->alt_next;
 707                         } else {
 708                                 /* the transfer is finished */
 709                                 td = NULL;
 710                         }
 711                         break;
 712                 }
 713                 td = td->obj_next;
 714
 715                 if (td->alt_next != td_alt_next) {
 716                         /* this USB frame is complete */
 717                         break;
 718                 }
 719         }
 720
 721         /* update transfer cache */
 722
 723         xfer->td_transfer_cache = td;
 724
 725         return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
 726             (status != XHCI_TRB_ERROR_SHORT_PKT &&
 727             status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
 728             USB_ERR_NORMAL_COMPLETION);
 729 }
 730
 731 static void
 732 xhci_generic_done(struct usb_xfer *xfer)
 733 {
 734         usb_error_t err = 0;
 735
 736         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
 737             xfer, xfer->endpoint);
 738
 739         /* reset scanner */
 740
 741         xfer->td_transfer_cache = xfer->td_transfer_first;
 742
 743         if (xfer->flags_int.control_xfr) {
 744
 745                 if (xfer->flags_int.control_hdr)
 746                         err = xhci_generic_done_sub(xfer);
 747
 748                 xfer->aframes = 1;
 749
 750                 if (xfer->td_transfer_cache == NULL)
 751                         goto done;
 752         }
 753
 754         while (xfer->aframes != xfer->nframes) {
 755
 756                 err = xhci_generic_done_sub(xfer);
 757                 xfer->aframes++;
 758
 759                 if (xfer->td_transfer_cache == NULL)
 760                         goto done;
 761         }
 762
 763         if (xfer->flags_int.control_xfr &&
 764             !xfer->flags_int.control_act)
 765                 err = xhci_generic_done_sub(xfer);
 766 done:
 767         /* transfer is complete */
 768         xhci_device_done(xfer, err);
 769 }
 770
 771 static void
 772 xhci_activate_transfer(struct usb_xfer *xfer)
 773 {
 774         struct xhci_td *td;
 775
 776         td = xfer->td_transfer_cache;
 777
 778         usb_pc_cpu_invalidate(td->page_cache);
 779
 780         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 781
 782                 /* activate the transfer */
 783
 784                 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
 785                 usb_pc_cpu_flush(td->page_cache);
 786
 787                 xhci_endpoint_doorbell(xfer);
 788         }
 789 }
 790
 791 static void
 792 xhci_skip_transfer(struct usb_xfer *xfer)
 793 {
 794         struct xhci_td *td;
 795         struct xhci_td *td_last;
 796
 797         td = xfer->td_transfer_cache;
 798         td_last = xfer->td_transfer_last;
 799
 800         td = td->alt_next;
 801
 802         usb_pc_cpu_invalidate(td->page_cache);
 803
 804         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 805
 806                 usb_pc_cpu_invalidate(td_last->page_cache);
 807
 808                 /* copy LINK TRB to current waiting location */
 809
 810                 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
 811                 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
 812                 usb_pc_cpu_flush(td->page_cache);
 813
 814                 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
 815                 usb_pc_cpu_flush(td->page_cache);
 816
 817                 xhci_endpoint_doorbell(xfer);
 818         }
 819 }
 820
 821 /*------------------------------------------------------------------------*
 822  *      xhci_check_transfer
 823  *------------------------------------------------------------------------*/
 824 static void
 825 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
 826 {
 827         int64_t offset;
 828         uint64_t td_event;
 829         uint32_t temp;
 830         uint32_t remainder;
 831         uint8_t status;
 832         uint8_t halted;
 833         uint8_t epno;
 834         uint8_t index;
 835         uint8_t i;
 836
 837         /* decode TRB */
 838         td_event = le64toh(trb->qwTrb0);
 839         temp = le32toh(trb->dwTrb2);
 840
 841         remainder = XHCI_TRB_2_REM_GET(temp);
 842         status = XHCI_TRB_2_ERROR_GET(temp);
 843
 844         temp = le32toh(trb->dwTrb3);
 845         epno = XHCI_TRB_3_EP_GET(temp);
 846         index = XHCI_TRB_3_SLOT_GET(temp);
 847
 848         /* check if error means halted */
 849         halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
 850             status != XHCI_TRB_ERROR_SUCCESS);
 851
 852         DPRINTF("slot=%u epno=%u remainder=%u status=%u\n",
 853             index, epno, remainder, status);
 854
 855         if (index > sc->sc_noslot) {
 856                 DPRINTF("Invalid slot.\n");
 857                 return;
 858         }
 859
 860         if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
 861                 DPRINTF("Invalid endpoint.\n");
 862                 return;
 863         }
 864
 865         /* try to find the USB transfer that generated the event */
 866         for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
 867                 struct usb_xfer *xfer;
 868                 struct xhci_td *td;
 869                 struct xhci_endpoint_ext *pepext;
 870
 871                 pepext = &sc->sc_hw.devs[index].endp[epno];
 872
 873                 xfer = pepext->xfer[i];
 874                 if (xfer == NULL)
 875                         continue;
 876
 877                 td = xfer->td_transfer_cache;
 878
 879                 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
 880                         (long long)td_event,
 881                         (long long)td->td_self,
 882                         (long long)td->td_self + sizeof(td->td_trb));
 883
 884                 /*
 885                  * NOTE: Some XHCI implementations might not trigger
 886                  * an event on the last LINK TRB so we need to
 887                  * consider both the last and second last event
 888                  * address as conditions for a successful transfer.
 889                  *
 890                  * NOTE: We assume that the XHCI will only trigger one
 891                  * event per chain of TRBs.
 892                  */
 893
 894                 offset = td_event - td->td_self;
 895
 896                 if (offset >= 0 &&
 897                     offset < (int64_t)sizeof(td->td_trb)) {
 898
 899                         usb_pc_cpu_invalidate(td->page_cache);
 900
 901                         /* compute rest of remainder, if any */
 902                         for (i = (offset / 16) + 1; i < td->ntrb; i++) {
 903                                 temp = le32toh(td->td_trb[i].dwTrb2);
 904                                 remainder += XHCI_TRB_2_BYTES_GET(temp);
 905                         }
 906
 907                         DPRINTFN(5, "New remainder: %u\n", remainder);
 908
 909                         /* clear isochronous transfer errors */
 910                         if (xfer->flags_int.isochronous_xfr) {
 911                                 if (halted) {
 912                                         halted = 0;
 913                                         status = XHCI_TRB_ERROR_SUCCESS;
 914                                         remainder = td->len;
 915                                 }
 916                         }
 917
 918                         /* "td->remainder" is verified later */
 919                         td->remainder = remainder;
 920                         td->status = status;
 921
 922                         usb_pc_cpu_flush(td->page_cache);
 923
 924                         /*
 925                          * 1) Last transfer descriptor makes the
 926                          * transfer done
 927                          */
 928                         if (((void *)td) == xfer->td_transfer_last) {
 929                                 DPRINTF("TD is last\n");
 930                                 xhci_generic_done(xfer);
 931                                 break;
 932                         }
 933
 934                         /*
 935                          * 2) Any kind of error makes the transfer
 936                          * done
 937                          */
 938                         if (halted) {
 939                                 DPRINTF("TD has I/O error\n");
 940                                 xhci_generic_done(xfer);
 941                                 break;
 942                         }
 943
 944                         /*
 945                          * 3) If there is no alternate next transfer,
 946                          * a short packet also makes the transfer done
 947                          */
 948                         if (td->remainder > 0) {
 949                                 if (td->alt_next == NULL) {
 950                                         DPRINTF(
 951                                             "short TD has no alternate next\n");
 952                                         xhci_generic_done(xfer);
 953                                         break;
 954                                 }
 955                                 DPRINTF("TD has short pkt\n");
 956                                 if (xfer->flags_int.short_frames_ok ||
 957                                     xfer->flags_int.isochronous_xfr ||
 958                                     xfer->flags_int.control_xfr) {
 959                                         /* follow the alt next */
 960                                         xfer->td_transfer_cache = td->alt_next;
 961                                         xhci_activate_transfer(xfer);
 962                                         break;
 963                                 }
 964                                 xhci_skip_transfer(xfer);
 965                                 xhci_generic_done(xfer);
 966                                 break;
 967                         }
 968
 969                         /*
 970                          * 4) Transfer complete - go to next TD
 971                          */
 972                         DPRINTF("Following next TD\n");
 973                         xfer->td_transfer_cache = td->obj_next;
 974                         xhci_activate_transfer(xfer);
 975                         break;          /* there should only be one match */
 976                 }
 977         }
 978 }
 979
 980 static int
 981 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
 982 {
 983         if (sc->sc_cmd_addr == trb->qwTrb0) {
 984                 DPRINTF("Received command event\n");
 985                 sc->sc_cmd_result[0] = trb->dwTrb2;
 986                 sc->sc_cmd_result[1] = trb->dwTrb3;
 987                 cv_signal(&sc->sc_cmd_cv);
 988                 return (1);     /* command match */
 989         }
 990         return (0);
 991 }
 992
 993 static int
 994 xhci_interrupt_poll(struct xhci_softc *sc)
 995 {
 996         struct usb_page_search buf_res;
 997         struct xhci_hw_root *phwr;
 998         uint64_t addr;
 999         uint32_t temp;
1000         int retval = 0;
1001         uint16_t i;
1002         uint8_t event;
1003         uint8_t j;
1004         uint8_t k;
1005         uint8_t t;
1006
1007         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1008
1009         phwr = buf_res.buffer;
1010
1011         /* Receive any events */
1012
1013         usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1014
1015         i = sc->sc_event_idx;
1016         j = sc->sc_event_ccs;
1017         t = 2;
1018
1019         while (1) {
1020
1021                 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1022
1023                 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1024
1025                 if (j != k)
1026                         break;
1027
1028                 event = XHCI_TRB_3_TYPE_GET(temp);
1029
1030                 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1031                     i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1032                     (long)le32toh(phwr->hwr_events[i].dwTrb2),
1033                     (long)le32toh(phwr->hwr_events[i].dwTrb3));
1034
1035                 switch (event) {
1036                 case XHCI_TRB_EVENT_TRANSFER:
1037                         xhci_check_transfer(sc, &phwr->hwr_events[i]);
1038                         break;
1039                 case XHCI_TRB_EVENT_CMD_COMPLETE:
1040                         retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1041                         break;
1042                 default:
1043                         DPRINTF("Unhandled event = %u\n", event);
1044                         break;
1045                 }
1046
1047                 i++;
1048
1049                 if (i == XHCI_MAX_EVENTS) {
1050                         i = 0;
1051                         j ^= 1;
1052
1053                         /* check for timeout */
1054                         if (!--t)
1055                                 break;
1056                 }
1057         }
1058
1059         sc->sc_event_idx = i;
1060         sc->sc_event_ccs = j;
1061
1062         /*
1063          * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1064          * latched. That means to activate the register we need to
1065          * write both the low and high double word of the 64-bit
1066          * register.
1067          */
1068
1069         addr = (uint32_t)buf_res.physaddr;
1070         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1071
1072         /* try to clear busy bit */
1073         addr |= XHCI_ERDP_LO_BUSY;
1074
1075         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1076         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1077
1078         return (retval);
1079 }
1080
1081 static usb_error_t
1082 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1083     uint16_t timeout_ms)
1084 {
1085         struct usb_page_search buf_res;
1086         struct xhci_hw_root *phwr;
1087         uint64_t addr;
1088         uint32_t temp;
1089         uint8_t i;
1090         uint8_t j;
1091         uint8_t timeout = 0;
1092         int err;
1093
1094         XHCI_CMD_ASSERT_LOCKED(sc);
1095
1096         /* get hardware root structure */
1097
1098         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1099
1100         phwr = buf_res.buffer;
1101
1102         /* Queue command */
1103
1104         USB_BUS_LOCK(&sc->sc_bus);
1105 retry:
1106         i = sc->sc_command_idx;
1107         j = sc->sc_command_ccs;
1108
1109         DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1110             i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1111             (long long)le64toh(trb->qwTrb0),
1112             (long)le32toh(trb->dwTrb2),
1113             (long)le32toh(trb->dwTrb3));
1114
1115         phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1116         phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1117
1118         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1119
1120         temp = trb->dwTrb3;
1121
1122         if (j)
1123                 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1124         else
1125                 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1126
1127         temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1128
1129         phwr->hwr_commands[i].dwTrb3 = temp;
1130
1131         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1132
1133         addr = buf_res.physaddr;
1134         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1135
1136         sc->sc_cmd_addr = htole64(addr);
1137
1138         i++;
1139
1140         if (i == (XHCI_MAX_COMMANDS - 1)) {
1141
1142                 if (j) {
1143                         temp = htole32(XHCI_TRB_3_TC_BIT |
1144                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1145                             XHCI_TRB_3_CYCLE_BIT);
1146                 } else {
1147                         temp = htole32(XHCI_TRB_3_TC_BIT |
1148                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1149                 }
1150
1151                 phwr->hwr_commands[i].dwTrb3 = temp;
1152
1153                 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1154
1155                 i = 0;
1156                 j ^= 1;
1157         }
1158
1159         sc->sc_command_idx = i;
1160         sc->sc_command_ccs = j;
1161
1162         XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1163
1164         err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1165             USB_MS_TO_TICKS(timeout_ms));
1166
1167         /*
1168          * In some error cases event interrupts are not generated.
1169          * Poll one time to see if the command has completed.
1170          */
1171         if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1172                 DPRINTF("Command was completed when polling\n");
1173                 err = 0;
1174         }
1175         if (err != 0) {
1176                 DPRINTF("Command timeout!\n");
1177                 /*
1178                  * After some weeks of continuous operation, it has
1179                  * been observed that the ASMedia Technology, ASM1042
1180                  * SuperSpeed USB Host Controller can suddenly stop
1181                  * accepting commands via the command queue. Try to
1182                  * first reset the command queue. If that fails do a
1183                  * host controller reset.
1184                  */
1185                 if (timeout == 0 &&
1186                     xhci_reset_command_queue_locked(sc) == 0) {
1187                         timeout = 1;
1188                         goto retry;
1189                 } else {
1190                         DPRINTF("Controller reset!\n");
1191                         usb_bus_reset_async_locked(&sc->sc_bus);
1192                 }
1193                 err = USB_ERR_TIMEOUT;
1194                 trb->dwTrb2 = 0;
1195                 trb->dwTrb3 = 0;
1196         } else {
1197                 temp = le32toh(sc->sc_cmd_result[0]);
1198                 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1199                         err = USB_ERR_IOERROR;
1200
1201                 trb->dwTrb2 = sc->sc_cmd_result[0];
1202                 trb->dwTrb3 = sc->sc_cmd_result[1];
1203         }
1204
1205         USB_BUS_UNLOCK(&sc->sc_bus);
1206
1207         return (err);
1208 }
1209
1210 #if 0
1211 static usb_error_t
1212 xhci_cmd_nop(struct xhci_softc *sc)
1213 {
1214         struct xhci_trb trb;
1215         uint32_t temp;
1216
1217         DPRINTF("\n");
1218
1219         trb.qwTrb0 = 0;
1220         trb.dwTrb2 = 0;
1221         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1222
1223         trb.dwTrb3 = htole32(temp);
1224
1225         return (xhci_do_command(sc, &trb, 100 /* ms */));
1226 }
1227 #endif
1228
1229 static usb_error_t
1230 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1231 {
1232         struct xhci_trb trb;
1233         uint32_t temp;
1234         usb_error_t err;
1235
1236         DPRINTF("\n");
1237
1238         trb.qwTrb0 = 0;
1239         trb.dwTrb2 = 0;
1240         trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1241
1242         err = xhci_do_command(sc, &trb, 100 /* ms */);
1243         if (err)
1244                 goto done;
1245
1246         temp = le32toh(trb.dwTrb3);
1247
1248         *pslot = XHCI_TRB_3_SLOT_GET(temp);
1249
1250 done:
1251         return (err);
1252 }
1253
1254 static usb_error_t
1255 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1256 {
1257         struct xhci_trb trb;
1258         uint32_t temp;
1259
1260         DPRINTF("\n");
1261
1262         trb.qwTrb0 = 0;
1263         trb.dwTrb2 = 0;
1264         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1265             XHCI_TRB_3_SLOT_SET(slot_id);
1266
1267         trb.dwTrb3 = htole32(temp);
1268
1269         return (xhci_do_command(sc, &trb, 100 /* ms */));
1270 }
1271
1272 static usb_error_t
1273 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1274     uint8_t bsr, uint8_t slot_id)
1275 {
1276         struct xhci_trb trb;
1277         uint32_t temp;
1278
1279         DPRINTF("\n");
1280
1281         trb.qwTrb0 = htole64(input_ctx);
1282         trb.dwTrb2 = 0;
1283         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1284             XHCI_TRB_3_SLOT_SET(slot_id);
1285
1286         if (bsr)
1287                 temp |= XHCI_TRB_3_BSR_BIT;
1288
1289         trb.dwTrb3 = htole32(temp);
1290
1291         return (xhci_do_command(sc, &trb, 500 /* ms */));
1292 }
1293
1294 static usb_error_t
1295 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1296 {
1297         struct usb_page_search buf_inp;
1298         struct usb_page_search buf_dev;
1299         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1300         struct xhci_hw_dev *hdev;
1301         struct xhci_dev_ctx *pdev;
1302         struct xhci_endpoint_ext *pepext;
1303         uint32_t temp;
1304         uint16_t mps;
1305         usb_error_t err;
1306         uint8_t index;
1307
1308         /* the root HUB case is not handled here */
1309         if (udev->parent_hub == NULL)
1310                 return (USB_ERR_INVAL);
1311
1312         index = udev->controller_slot_id;
1313
1314         hdev =  &sc->sc_hw.devs[index];
1315
1316         if (mtx != NULL)
1317                 mtx_unlock(mtx);
1318
1319         XHCI_CMD_LOCK(sc);
1320
1321         switch (hdev->state) {
1322         case XHCI_ST_DEFAULT:
1323         case XHCI_ST_ENABLED:
1324
1325                 hdev->state = XHCI_ST_ENABLED;
1326
1327                 /* set configure mask to slot and EP0 */
1328                 xhci_configure_mask(udev, 3, 0);
1329
1330                 /* configure input slot context structure */
1331                 err = xhci_configure_device(udev);
1332
1333                 if (err != 0) {
1334                         DPRINTF("Could not configure device\n");
1335                         break;
1336                 }
1337
1338                 /* configure input endpoint context structure */
1339                 switch (udev->speed) {
1340                 case USB_SPEED_LOW:
1341                 case USB_SPEED_FULL:
1342                         mps = 8;
1343                         break;
1344                 case USB_SPEED_HIGH:
1345                         mps = 64;
1346                         break;
1347                 default:
1348                         mps = 512;
1349                         break;
1350                 }
1351
1352                 pepext = xhci_get_endpoint_ext(udev,
1353                     &udev->ctrl_ep_desc);
1354                 err = xhci_configure_endpoint(udev,
1355                     &udev->ctrl_ep_desc, pepext->physaddr,
1356                     0, 1, 1, 0, mps, mps);
1357
1358                 if (err != 0) {
1359                         DPRINTF("Could not configure default endpoint\n");
1360                         break;
1361                 }
1362
1363                 /* execute set address command */
1364                 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1365
1366                 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1367                     (address == 0), index);
1368
1369                 if (err != 0) {
1370                         temp = le32toh(sc->sc_cmd_result[0]);
1371                         if (address == 0 && sc->sc_port_route != NULL &&
1372                             XHCI_TRB_2_ERROR_GET(temp) ==
1373                             XHCI_TRB_ERROR_PARAMETER) {
1374                                 /* LynxPoint XHCI - ports are not switchable */
1375                                 /* Un-route all ports from the XHCI */
1376                                 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1377                         }
1378                         DPRINTF("Could not set address "
1379                             "for slot %u.\n", index);
1380                         if (address != 0)
1381                                 break;
1382                 }
1383
1384                 /* update device address to new value */
1385
1386                 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1387                 pdev = buf_dev.buffer;
1388                 usb_pc_cpu_invalidate(&hdev->device_pc);
1389
1390                 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1391                 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1392
1393                 /* update device state to new value */
1394
1395                 if (address != 0)
1396                         hdev->state = XHCI_ST_ADDRESSED;
1397                 else
1398                         hdev->state = XHCI_ST_DEFAULT;
1399                 break;
1400
1401         default:
1402                 DPRINTF("Wrong state for set address.\n");
1403                 err = USB_ERR_IOERROR;
1404                 break;
1405         }
1406         XHCI_CMD_UNLOCK(sc);
1407
1408         if (mtx != NULL)
1409                 mtx_lock(mtx);
1410
1411         return (err);
1412 }
1413
1414 static usb_error_t
1415 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1416     uint8_t deconfigure, uint8_t slot_id)
1417 {
1418         struct xhci_trb trb;
1419         uint32_t temp;
1420
1421         DPRINTF("\n");
1422
1423         trb.qwTrb0 = htole64(input_ctx);
1424         trb.dwTrb2 = 0;
1425         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1426             XHCI_TRB_3_SLOT_SET(slot_id);
1427
1428         if (deconfigure)
1429                 temp |= XHCI_TRB_3_DCEP_BIT;
1430
1431         trb.dwTrb3 = htole32(temp);
1432
1433         return (xhci_do_command(sc, &trb, 100 /* ms */));
1434 }
1435
1436 static usb_error_t
1437 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1438     uint8_t slot_id)
1439 {
1440         struct xhci_trb trb;
1441         uint32_t temp;
1442
1443         DPRINTF("\n");
1444
1445         trb.qwTrb0 = htole64(input_ctx);
1446         trb.dwTrb2 = 0;
1447         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1448             XHCI_TRB_3_SLOT_SET(slot_id);
1449         trb.dwTrb3 = htole32(temp);
1450
1451         return (xhci_do_command(sc, &trb, 100 /* ms */));
1452 }
1453
1454 static usb_error_t
1455 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1456     uint8_t ep_id, uint8_t slot_id)
1457 {
1458         struct xhci_trb trb;
1459         uint32_t temp;
1460
1461         DPRINTF("\n");
1462
1463         trb.qwTrb0 = 0;
1464         trb.dwTrb2 = 0;
1465         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1466             XHCI_TRB_3_SLOT_SET(slot_id) |
1467             XHCI_TRB_3_EP_SET(ep_id);
1468
1469         if (preserve)
1470                 temp |= XHCI_TRB_3_PRSV_BIT;
1471
1472         trb.dwTrb3 = htole32(temp);
1473
1474         return (xhci_do_command(sc, &trb, 100 /* ms */));
1475 }
1476
1477 static usb_error_t
1478 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1479     uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1480 {
1481         struct xhci_trb trb;
1482         uint32_t temp;
1483
1484         DPRINTF("\n");
1485
1486         trb.qwTrb0 = htole64(dequeue_ptr);
1487
1488         temp = XHCI_TRB_2_STREAM_SET(stream_id);
1489         trb.dwTrb2 = htole32(temp);
1490
1491         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1492             XHCI_TRB_3_SLOT_SET(slot_id) |
1493             XHCI_TRB_3_EP_SET(ep_id);
1494         trb.dwTrb3 = htole32(temp);
1495
1496         return (xhci_do_command(sc, &trb, 100 /* ms */));
1497 }
1498
1499 static usb_error_t
1500 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1501     uint8_t ep_id, uint8_t slot_id)
1502 {
1503         struct xhci_trb trb;
1504         uint32_t temp;
1505
1506         DPRINTF("\n");
1507
1508         trb.qwTrb0 = 0;
1509         trb.dwTrb2 = 0;
1510         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1511             XHCI_TRB_3_SLOT_SET(slot_id) |
1512             XHCI_TRB_3_EP_SET(ep_id);
1513
1514         if (suspend)
1515                 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1516
1517         trb.dwTrb3 = htole32(temp);
1518
1519         return (xhci_do_command(sc, &trb, 100 /* ms */));
1520 }
1521
1522 static usb_error_t
1523 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1524 {
1525         struct xhci_trb trb;
1526         uint32_t temp;
1527
1528         DPRINTF("\n");
1529
1530         trb.qwTrb0 = 0;
1531         trb.dwTrb2 = 0;
1532         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1533             XHCI_TRB_3_SLOT_SET(slot_id);
1534
1535         trb.dwTrb3 = htole32(temp);
1536
1537         return (xhci_do_command(sc, &trb, 100 /* ms */));
1538 }
1539
1540 /*------------------------------------------------------------------------*
1541  *      xhci_interrupt - XHCI interrupt handler
1542  *------------------------------------------------------------------------*/
1543 void
1544 xhci_interrupt(struct xhci_softc *sc)
1545 {
1546         uint32_t status;
1547         uint32_t temp;
1548
1549         USB_BUS_LOCK(&sc->sc_bus);
1550
1551         status = XREAD4(sc, oper, XHCI_USBSTS);
1552
1553         /* acknowledge interrupts, if any */
1554         if (status != 0) {
1555                 XWRITE4(sc, oper, XHCI_USBSTS, status);
1556                 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1557         }
1558
1559         temp = XREAD4(sc, runt, XHCI_IMAN(0));
1560
1561         /* force clearing of pending interrupts */
1562         if (temp & XHCI_IMAN_INTR_PEND)
1563                 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1564
1565         /* check for event(s) */
1566         xhci_interrupt_poll(sc);
1567
1568         if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1569             XHCI_STS_HSE | XHCI_STS_HCE)) {
1570
1571                 if (status & XHCI_STS_PCD) {
1572                         xhci_root_intr(sc);
1573                 }
1574
1575                 if (status & XHCI_STS_HCH) {
1576                         printf("%s: host controller halted\n",
1577                             __FUNCTION__);
1578                 }
1579
1580                 if (status & XHCI_STS_HSE) {
1581                         printf("%s: host system error\n",
1582                             __FUNCTION__);
1583                 }
1584
1585                 if (status & XHCI_STS_HCE) {
1586                         printf("%s: host controller error\n",
1587                            __FUNCTION__);
1588                 }
1589         }
1590         USB_BUS_UNLOCK(&sc->sc_bus);
1591 }
1592
1593 /*------------------------------------------------------------------------*
1594  *      xhci_timeout - XHCI timeout handler
1595  *------------------------------------------------------------------------*/
1596 static void
1597 xhci_timeout(void *arg)
1598 {
1599         struct usb_xfer *xfer = arg;
1600
1601         DPRINTF("xfer=%p\n", xfer);
1602
1603         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1604
1605         /* transfer is transferred */
1606         xhci_device_done(xfer, USB_ERR_TIMEOUT);
1607 }
1608
1609 static void
1610 xhci_do_poll(struct usb_bus *bus)
1611 {
1612         struct xhci_softc *sc = XHCI_BUS2SC(bus);
1613
1614         USB_BUS_LOCK(&sc->sc_bus);
1615         xhci_interrupt_poll(sc);
1616         USB_BUS_UNLOCK(&sc->sc_bus);
1617 }
1618
1619 static void
1620 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1621 {
1622         struct usb_page_search buf_res;
1623         struct xhci_td *td;
1624         struct xhci_td *td_next;
1625         struct xhci_td *td_alt_next;
1626         struct xhci_td *td_first;
1627         uint32_t buf_offset;
1628         uint32_t average;
1629         uint32_t len_old;
1630         uint32_t npkt_off;
1631         uint32_t dword;
1632         uint8_t shortpkt_old;
1633         uint8_t precompute;
1634         uint8_t x;
1635
1636         td_alt_next = NULL;
1637         buf_offset = 0;
1638         shortpkt_old = temp->shortpkt;
1639         len_old = temp->len;
1640         npkt_off = 0;
1641         precompute = 1;
1642
1643 restart:
1644
1645         td = temp->td;
1646         td_next = td_first = temp->td_next;
1647
1648         while (1) {
1649
1650                 if (temp->len == 0) {
1651
1652                         if (temp->shortpkt)
1653                                 break;
1654
1655                         /* send a Zero Length Packet, ZLP, last */
1656
1657                         temp->shortpkt = 1;
1658                         average = 0;
1659
1660                 } else {
1661
1662                         average = temp->average;
1663
1664                         if (temp->len < average) {
1665                                 if (temp->len % temp->max_packet_size) {
1666                                         temp->shortpkt = 1;
1667                                 }
1668                                 average = temp->len;
1669                         }
1670                 }
1671
1672                 if (td_next == NULL)
1673                         panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1674
1675                 /* get next TD */
1676
1677                 td = td_next;
1678                 td_next = td->obj_next;
1679
1680                 /* check if we are pre-computing */
1681
1682                 if (precompute) {
1683
1684                         /* update remaining length */
1685
1686                         temp->len -= average;
1687
1688                         continue;
1689                 }
1690                 /* fill out current TD */
1691
1692                 td->len = average;
1693                 td->remainder = 0;
1694                 td->status = 0;
1695
1696                 /* update remaining length */
1697
1698                 temp->len -= average;
1699
1700                 /* reset TRB index */
1701
1702                 x = 0;
1703
1704                 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1705                         /* immediate data */
1706
1707                         if (average > 8)
1708                                 average = 8;
1709
1710                         td->td_trb[0].qwTrb0 = 0;
1711
1712                         usbd_copy_out(temp->pc, temp->offset + buf_offset,
1713                            (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1714                            average);
1715
1716                         dword = XHCI_TRB_2_BYTES_SET(8) |
1717                             XHCI_TRB_2_TDSZ_SET(0) |
1718                             XHCI_TRB_2_IRQ_SET(0);
1719
1720                         td->td_trb[0].dwTrb2 = htole32(dword);
1721
1722                         dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1723                           XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1724
1725                         /* check wLength */
1726                         if (td->td_trb[0].qwTrb0 &
1727                            htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1728                                 if (td->td_trb[0].qwTrb0 &
1729                                     htole64(XHCI_TRB_0_DIR_IN_MASK))
1730                                         dword |= XHCI_TRB_3_TRT_IN;
1731                                 else
1732                                         dword |= XHCI_TRB_3_TRT_OUT;
1733                         }
1734
1735                         td->td_trb[0].dwTrb3 = htole32(dword);
1736 #ifdef USB_DEBUG
1737                         xhci_dump_trb(&td->td_trb[x]);
1738 #endif
1739                         x++;
1740
1741                 } else do {
1742
1743                         uint32_t npkt;
1744
1745                         /* fill out buffer pointers */
1746
1747                         if (average == 0) {
1748                                 memset(&buf_res, 0, sizeof(buf_res));
1749                         } else {
1750                                 usbd_get_page(temp->pc, temp->offset +
1751                                     buf_offset, &buf_res);
1752
1753                                 /* get length to end of page */
1754                                 if (buf_res.length > average)
1755                                         buf_res.length = average;
1756
1757                                 /* check for maximum length */
1758                                 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1759                                         buf_res.length = XHCI_TD_PAGE_SIZE;
1760
1761                                 npkt_off += buf_res.length;
1762                         }
1763
1764                         /* setup npkt */
1765                         npkt = (len_old - npkt_off + temp->max_packet_size - 1) /
1766                             temp->max_packet_size;
1767
1768                         if (npkt == 0)
1769                                 npkt = 1;
1770                         else if (npkt > 31)
1771                                 npkt = 31;
1772
1773                         /* fill out TRB's */
1774                         td->td_trb[x].qwTrb0 =
1775                             htole64((uint64_t)buf_res.physaddr);
1776
1777                         dword =
1778                           XHCI_TRB_2_BYTES_SET(buf_res.length) |
1779                           XHCI_TRB_2_TDSZ_SET(npkt) |
1780                           XHCI_TRB_2_IRQ_SET(0);
1781
1782                         td->td_trb[x].dwTrb2 = htole32(dword);
1783
1784                         switch (temp->trb_type) {
1785                         case XHCI_TRB_TYPE_ISOCH:
1786                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1787                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1788                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1789                                 if (td != td_first) {
1790                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1791                                 } else if (temp->do_isoc_sync != 0) {
1792                                         temp->do_isoc_sync = 0;
1793                                         /* wait until "isoc_frame" */
1794                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1795                                             XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1796                                 } else {
1797                                         /* start data transfer at next interval */
1798                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1799                                             XHCI_TRB_3_ISO_SIA_BIT;
1800                                 }
1801                                 if (temp->direction == UE_DIR_IN)
1802                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1803                                 break;
1804                         case XHCI_TRB_TYPE_DATA_STAGE:
1805                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1806                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) |
1807                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1808                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1809                                 if (temp->direction == UE_DIR_IN)
1810                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1811                                 break;
1812                         case XHCI_TRB_TYPE_STATUS_STAGE:
1813                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1814                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) |
1815                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1816                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1817                                 if (temp->direction == UE_DIR_IN)
1818                                         dword |= XHCI_TRB_3_DIR_IN;
1819                                 break;
1820                         default:        /* XHCI_TRB_TYPE_NORMAL */
1821                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1822                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) |
1823                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1824                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1825                                 if (temp->direction == UE_DIR_IN)
1826                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1827                                 break;
1828                         }
1829                         td->td_trb[x].dwTrb3 = htole32(dword);
1830
1831                         average -= buf_res.length;
1832                         buf_offset += buf_res.length;
1833 #ifdef USB_DEBUG
1834                         xhci_dump_trb(&td->td_trb[x]);
1835 #endif
1836                         x++;
1837
1838                 } while (average != 0);
1839
1840                 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1841
1842                 /* store number of data TRB's */
1843
1844                 td->ntrb = x;
1845
1846                 DPRINTF("NTRB=%u\n", x);
1847
1848                 /* fill out link TRB */
1849
1850                 if (td_next != NULL) {
1851                         /* link the current TD with the next one */
1852                         td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1853                         DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1854                 } else {
1855                         /* this field will get updated later */
1856                         DPRINTF("NOLINK\n");
1857                 }
1858
1859                 dword = XHCI_TRB_2_IRQ_SET(0);
1860
1861                 td->td_trb[x].dwTrb2 = htole32(dword);
1862
1863                 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1864                     XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1865                     /*
1866                      * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1867                      * frame only receives a single short packet event
1868                      * by setting the CHAIN bit in the LINK field. In
1869                      * addition some XHCI controllers have problems
1870                      * sending a ZLP unless the CHAIN-BIT is set in
1871                      * the LINK TRB.
1872                      */
1873                     XHCI_TRB_3_CHAIN_BIT;
1874
1875                 td->td_trb[x].dwTrb3 = htole32(dword);
1876
1877                 td->alt_next = td_alt_next;
1878 #ifdef USB_DEBUG
1879                 xhci_dump_trb(&td->td_trb[x]);
1880 #endif
1881                 usb_pc_cpu_flush(td->page_cache);
1882         }
1883
1884         if (precompute) {
1885                 precompute = 0;
1886
1887                 /* setup alt next pointer, if any */
1888                 if (temp->last_frame) {
1889                         td_alt_next = NULL;
1890                 } else {
1891                         /* we use this field internally */
1892                         td_alt_next = td_next;
1893                 }
1894
1895                 /* restore */
1896                 temp->shortpkt = shortpkt_old;
1897                 temp->len = len_old;
1898                 goto restart;
1899         }
1900
1901         /*
1902          * Remove cycle bit from the first TRB if we are
1903          * stepping them:
1904          */
1905         if (temp->step_td != 0) {
1906                 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1907                 usb_pc_cpu_flush(td_first->page_cache);
1908         }
1909
1910         /* clear TD SIZE to zero, hence this is the last TRB */
1911         /* remove chain bit because this is the last data TRB in the chain */
1912         td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1913         td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1914         /* remove CHAIN-BIT from last LINK TRB */
1915         td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1916
1917         usb_pc_cpu_flush(td->page_cache);
1918
1919         temp->td = td;
1920         temp->td_next = td_next;
1921 }
1922
1923 static void
1924 xhci_setup_generic_chain(struct usb_xfer *xfer)
1925 {
1926         struct xhci_std_temp temp;
1927         struct xhci_td *td;
1928         uint32_t x;
1929         uint32_t y;
1930         uint8_t mult;
1931
1932         temp.do_isoc_sync = 0;
1933         temp.step_td = 0;
1934         temp.tbc = 0;
1935         temp.tlbpc = 0;
1936         temp.average = xfer->max_hc_frame_size;
1937         temp.max_packet_size = xfer->max_packet_size;
1938         temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
1939         temp.pc = NULL;
1940         temp.last_frame = 0;
1941         temp.offset = 0;
1942         temp.multishort = xfer->flags_int.isochronous_xfr ||
1943             xfer->flags_int.control_xfr ||
1944             xfer->flags_int.short_frames_ok;
1945
1946         /* toggle the DMA set we are using */
1947         xfer->flags_int.curr_dma_set ^= 1;
1948
1949         /* get next DMA set */
1950         td = xfer->td_start[xfer->flags_int.curr_dma_set];
1951
1952         temp.td = NULL;
1953         temp.td_next = td;
1954
1955         xfer->td_transfer_first = td;
1956         xfer->td_transfer_cache = td;
1957
1958         if (xfer->flags_int.isochronous_xfr) {
1959                 uint8_t shift;
1960
1961                 /* compute multiplier for ISOCHRONOUS transfers */
1962                 mult = xfer->endpoint->ecomp ?
1963                     (xfer->endpoint->ecomp->bmAttributes & 3) : 0;
1964                 /* check for USB 2.0 multiplier */
1965                 if (mult == 0) {
1966                         mult = (xfer->endpoint->edesc->
1967                             wMaxPacketSize[1] >> 3) & 3;
1968                 }
1969                 /* range check */
1970                 if (mult > 2)
1971                         mult = 3;
1972                 else
1973                         mult++;
1974
1975                 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
1976
1977                 DPRINTF("MFINDEX=0x%08x\n", x);
1978
1979                 switch (usbd_get_speed(xfer->xroot->udev)) {
1980                 case USB_SPEED_FULL:
1981                         shift = 3;
1982                         temp.isoc_delta = 8;    /* 1ms */
1983                         x += temp.isoc_delta - 1;
1984                         x &= ~(temp.isoc_delta - 1);
1985                         break;
1986                 default:
1987                         shift = usbd_xfer_get_fps_shift(xfer);
1988                         temp.isoc_delta = 1U << shift;
1989                         x += temp.isoc_delta - 1;
1990                         x &= ~(temp.isoc_delta - 1);
1991                         /* simple frame load balancing */
1992                         x += xfer->endpoint->usb_uframe;
1993                         break;
1994                 }
1995
1996                 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
1997
1998                 if ((xfer->endpoint->is_synced == 0) ||
1999                     (y < (xfer->nframes << shift)) ||
2000                     (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
2001                         /*
2002                          * If there is data underflow or the pipe
2003                          * queue is empty we schedule the transfer a
2004                          * few frames ahead of the current frame
2005                          * position. Else two isochronous transfers
2006                          * might overlap.
2007                          */
2008                         xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2009                         xfer->endpoint->is_synced = 1;
2010                         temp.do_isoc_sync = 1;
2011
2012                         DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2013                 }
2014
2015                 /* compute isochronous completion time */
2016
2017                 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2018
2019                 xfer->isoc_time_complete =
2020                     usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2021                     (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2022
2023                 x = 0;
2024                 temp.isoc_frame = xfer->endpoint->isoc_next;
2025                 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2026
2027                 xfer->endpoint->isoc_next += xfer->nframes << shift;
2028
2029         } else if (xfer->flags_int.control_xfr) {
2030
2031                 /* check if we should prepend a setup message */
2032
2033                 if (xfer->flags_int.control_hdr) {
2034
2035                         temp.len = xfer->frlengths[0];
2036                         temp.pc = xfer->frbuffers + 0;
2037                         temp.shortpkt = temp.len ? 1 : 0;
2038                         temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2039                         temp.direction = 0;
2040
2041                         /* check for last frame */
2042                         if (xfer->nframes == 1) {
2043                                 /* no STATUS stage yet, SETUP is last */
2044                                 if (xfer->flags_int.control_act)
2045                                         temp.last_frame = 1;
2046                         }
2047
2048                         xhci_setup_generic_chain_sub(&temp);
2049                 }
2050                 x = 1;
2051                 mult = 1;
2052                 temp.isoc_delta = 0;
2053                 temp.isoc_frame = 0;
2054                 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE;
2055         } else {
2056                 x = 0;
2057                 mult = 1;
2058                 temp.isoc_delta = 0;
2059                 temp.isoc_frame = 0;
2060                 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2061         }
2062
2063         if (x != xfer->nframes) {
2064                 /* setup page_cache pointer */
2065                 temp.pc = xfer->frbuffers + x;
2066                 /* set endpoint direction */
2067                 temp.direction = UE_GET_DIR(xfer->endpointno);
2068         }
2069
2070         while (x != xfer->nframes) {
2071
2072                 /* DATA0 / DATA1 message */
2073
2074                 temp.len = xfer->frlengths[x];
2075                 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2076                     x != 0 && temp.multishort == 0);
2077
2078                 x++;
2079
2080                 if (x == xfer->nframes) {
2081                         if (xfer->flags_int.control_xfr) {
2082                                 /* no STATUS stage yet, DATA is last */
2083                                 if (xfer->flags_int.control_act)
2084                                         temp.last_frame = 1;
2085                         } else {
2086                                 temp.last_frame = 1;
2087                         }
2088                 }
2089                 if (temp.len == 0) {
2090
2091                         /* make sure that we send an USB packet */
2092
2093                         temp.shortpkt = 0;
2094
2095                         temp.tbc = 0;
2096                         temp.tlbpc = mult - 1;
2097
2098                 } else if (xfer->flags_int.isochronous_xfr) {
2099
2100                         uint8_t tdpc;
2101
2102                         /*
2103                          * Isochronous transfers don't have short
2104                          * packet termination:
2105                          */
2106
2107                         temp.shortpkt = 1;
2108
2109                         /* isochronous transfers have a transfer limit */
2110
2111                         if (temp.len > xfer->max_frame_size)
2112                                 temp.len = xfer->max_frame_size;
2113
2114                         /* compute TD packet count */
2115                         tdpc = (temp.len + xfer->max_packet_size - 1) /
2116                             xfer->max_packet_size;
2117
2118                         temp.tbc = ((tdpc + mult - 1) / mult) - 1;
2119                         temp.tlbpc = (tdpc % mult);
2120
2121                         if (temp.tlbpc == 0)
2122                                 temp.tlbpc = mult - 1;
2123                         else
2124                                 temp.tlbpc--;
2125                 } else {
2126
2127                         /* regular data transfer */
2128
2129                         temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2130                 }
2131
2132                 xhci_setup_generic_chain_sub(&temp);
2133
2134                 if (xfer->flags_int.isochronous_xfr) {
2135                         temp.offset += xfer->frlengths[x - 1];
2136                         temp.isoc_frame += temp.isoc_delta;
2137                 } else {
2138                         /* get next Page Cache pointer */
2139                         temp.pc = xfer->frbuffers + x;
2140                 }
2141         }
2142
2143         /* check if we should append a status stage */
2144
2145         if (xfer->flags_int.control_xfr &&
2146             !xfer->flags_int.control_act) {
2147
2148                 /*
2149                  * Send a DATA1 message and invert the current
2150                  * endpoint direction.
2151                  */
2152                 temp.step_td = (xfer->nframes != 0);
2153                 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2154                 temp.len = 0;
2155                 temp.pc = NULL;
2156                 temp.shortpkt = 0;
2157                 temp.last_frame = 1;
2158                 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2159
2160                 xhci_setup_generic_chain_sub(&temp);
2161         }
2162
2163         td = temp.td;
2164
2165         /* must have at least one frame! */
2166
2167         xfer->td_transfer_last = td;
2168
2169         DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2170 }
2171
2172 static void
2173 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2174 {
2175         struct usb_page_search buf_res;
2176         struct xhci_dev_ctx_addr *pdctxa;
2177
2178         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2179
2180         pdctxa = buf_res.buffer;
2181
2182         DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2183
2184         pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2185
2186         usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2187 }
2188
2189 static usb_error_t
2190 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2191 {
2192         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2193         struct usb_page_search buf_inp;
2194         struct xhci_input_dev_ctx *pinp;
2195         uint32_t temp;
2196         uint8_t index;
2197         uint8_t x;
2198
2199         index = udev->controller_slot_id;
2200
2201         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2202
2203         pinp = buf_inp.buffer;
2204
2205         if (drop) {
2206                 mask &= XHCI_INCTX_NON_CTRL_MASK;
2207                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2208                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2209         } else {
2210                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0);
2211                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2212
2213                 /* find most significant set bit */
2214                 for (x = 31; x != 1; x--) {
2215                         if (mask & (1 << x))
2216                                 break;
2217                 }
2218
2219                 /* adjust */
2220                 x--;
2221
2222                 /* figure out maximum */
2223                 if (x > sc->sc_hw.devs[index].context_num) {
2224                         sc->sc_hw.devs[index].context_num = x;
2225                         temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2226                         temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2227                         temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2228                         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2229                 }
2230         }
2231         return (0);
2232 }
2233
2234 static usb_error_t
2235 xhci_configure_endpoint(struct usb_device *udev,
2236     struct usb_endpoint_descriptor *edesc, uint64_t ring_addr,
2237     uint16_t interval, uint8_t max_packet_count, uint8_t mult,
2238     uint8_t fps_shift, uint16_t max_packet_size, uint16_t max_frame_size)
2239 {
2240         struct usb_page_search buf_inp;
2241         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2242         struct xhci_input_dev_ctx *pinp;
2243         uint32_t temp;
2244         uint8_t index;
2245         uint8_t epno;
2246         uint8_t type;
2247
2248         index = udev->controller_slot_id;
2249
2250         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2251
2252         pinp = buf_inp.buffer;
2253
2254         epno = edesc->bEndpointAddress;
2255         type = edesc->bmAttributes & UE_XFERTYPE;
2256
2257         if (type == UE_CONTROL)
2258                 epno |= UE_DIR_IN;
2259
2260         epno = XHCI_EPNO2EPID(epno);
2261
2262         if (epno == 0)
2263                 return (USB_ERR_NO_PIPE);               /* invalid */
2264
2265         if (max_packet_count == 0)
2266                 return (USB_ERR_BAD_BUFSIZE);
2267
2268         max_packet_count--;
2269
2270         if (mult == 0)
2271                 return (USB_ERR_BAD_BUFSIZE);
2272
2273         temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2274             XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2275             XHCI_EPCTX_0_LSA_SET(0);
2276
2277         switch (udev->speed) {
2278         case USB_SPEED_FULL:
2279         case USB_SPEED_LOW:
2280                 /* 1ms -> 125us */
2281                 fps_shift += 3;
2282                 break;
2283         default:
2284                 break;
2285         }
2286
2287         switch (type) {
2288         case UE_INTERRUPT:
2289                 if (fps_shift > 3)
2290                         fps_shift--;
2291                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2292                 break;
2293         case UE_ISOCHRONOUS:
2294                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2295
2296                 switch (udev->speed) {
2297                 case USB_SPEED_SUPER:
2298                         if (mult > 3)
2299                                 mult = 3;
2300                         temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2301                         max_packet_count /= mult;
2302                         break;
2303                 default:
2304                         break;
2305                 }
2306                 break;
2307         default:
2308                 break;
2309         }
2310
2311         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2312
2313         temp =
2314             XHCI_EPCTX_1_HID_SET(0) |
2315             XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2316             XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2317
2318         if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) {
2319                 if (type != UE_ISOCHRONOUS)
2320                         temp |= XHCI_EPCTX_1_CERR_SET(3);
2321         }
2322
2323         switch (type) {
2324         case UE_CONTROL:
2325                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2326                 break;
2327         case UE_ISOCHRONOUS:
2328                 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2329                 break;
2330         case UE_BULK:
2331                 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2332                 break;
2333         default:
2334                 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2335                 break;
2336         }
2337
2338         /* check for IN direction */
2339         if (epno & 1)
2340                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2341
2342         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2343
2344         ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2345
2346         xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2347
2348         switch (edesc->bmAttributes & UE_XFERTYPE) {
2349         case UE_INTERRUPT:
2350         case UE_ISOCHRONOUS:
2351                 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2352                     XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2353                     max_frame_size));
2354                 break;
2355         case UE_CONTROL:
2356                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2357                 break;
2358         default:
2359                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2360                 break;
2361         }
2362
2363         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2364
2365 #ifdef USB_DEBUG
2366         xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2367 #endif
2368         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2369
2370         return (0);             /* success */
2371 }
2372
2373 static usb_error_t
2374 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2375 {
2376         struct xhci_endpoint_ext *pepext;
2377         struct usb_endpoint_ss_comp_descriptor *ecomp;
2378
2379         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2380             xfer->endpoint->edesc);
2381
2382         ecomp = xfer->endpoint->ecomp;
2383
2384         pepext->trb[0].dwTrb3 = 0;      /* halt any transfers */
2385         usb_pc_cpu_flush(pepext->page_cache);
2386
2387         return (xhci_configure_endpoint(xfer->xroot->udev,
2388             xfer->endpoint->edesc, pepext->physaddr,
2389             xfer->interval, xfer->max_packet_count,
2390             (ecomp != NULL) ? (ecomp->bmAttributes & 3) + 1 : 1,
2391             usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2392             xfer->max_frame_size));
2393 }
2394
2395 static usb_error_t
2396 xhci_configure_device(struct usb_device *udev)
2397 {
2398         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2399         struct usb_page_search buf_inp;
2400         struct usb_page_cache *pcinp;
2401         struct xhci_input_dev_ctx *pinp;
2402         struct usb_device *hubdev;
2403         uint32_t temp;
2404         uint32_t route;
2405         uint32_t rh_port;
2406         uint8_t is_hub;
2407         uint8_t index;
2408         uint8_t depth;
2409
2410         index = udev->controller_slot_id;
2411
2412         DPRINTF("index=%u\n", index);
2413
2414         pcinp = &sc->sc_hw.devs[index].input_pc;
2415
2416         usbd_get_page(pcinp, 0, &buf_inp);
2417
2418         pinp = buf_inp.buffer;
2419
2420         rh_port = 0;
2421         route = 0;
2422
2423         /* figure out route string and root HUB port number */
2424
2425         for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2426
2427                 if (hubdev->parent_hub == NULL)
2428                         break;
2429
2430                 depth = hubdev->parent_hub->depth;
2431
2432                 /*
2433                  * NOTE: HS/FS/LS devices and the SS root HUB can have
2434                  * more than 15 ports
2435                  */
2436
2437                 rh_port = hubdev->port_no;
2438
2439                 if (depth == 0)
2440                         break;
2441
2442                 if (rh_port > 15)
2443                         rh_port = 15;
2444
2445                 if (depth < 6)
2446                         route |= rh_port << (4 * (depth - 1));
2447         }
2448
2449         DPRINTF("Route=0x%08x\n", route);
2450
2451         temp = XHCI_SCTX_0_ROUTE_SET(route) |
2452             XHCI_SCTX_0_CTX_NUM_SET(
2453             sc->sc_hw.devs[index].context_num + 1);
2454
2455         switch (udev->speed) {
2456         case USB_SPEED_LOW:
2457                 temp |= XHCI_SCTX_0_SPEED_SET(2);
2458                 if (udev->parent_hs_hub != NULL &&
2459                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2460                     UDPROTO_HSHUBMTT) {
2461                         DPRINTF("Device inherits MTT\n");
2462                         temp |= XHCI_SCTX_0_MTT_SET(1);
2463                 }
2464                 break;
2465         case USB_SPEED_HIGH:
2466                 temp |= XHCI_SCTX_0_SPEED_SET(3);
2467                 if (sc->sc_hw.devs[index].nports != 0 &&
2468                     udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2469                         DPRINTF("HUB supports MTT\n");
2470                         temp |= XHCI_SCTX_0_MTT_SET(1);
2471                 }
2472                 break;
2473         case USB_SPEED_FULL:
2474                 temp |= XHCI_SCTX_0_SPEED_SET(1);
2475                 if (udev->parent_hs_hub != NULL &&
2476                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2477                     UDPROTO_HSHUBMTT) {
2478                         DPRINTF("Device inherits MTT\n");
2479                         temp |= XHCI_SCTX_0_MTT_SET(1);
2480                 }
2481                 break;
2482         default:
2483                 temp |= XHCI_SCTX_0_SPEED_SET(4);
2484                 break;
2485         }
2486
2487         is_hub = sc->sc_hw.devs[index].nports != 0 &&
2488             (udev->speed == USB_SPEED_SUPER ||
2489             udev->speed == USB_SPEED_HIGH);
2490
2491         if (is_hub)
2492                 temp |= XHCI_SCTX_0_HUB_SET(1);
2493
2494         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2495
2496         temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2497
2498         if (is_hub) {
2499                 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2500                     sc->sc_hw.devs[index].nports);
2501         }
2502
2503         switch (udev->speed) {
2504         case USB_SPEED_SUPER:
2505                 switch (sc->sc_hw.devs[index].state) {
2506                 case XHCI_ST_ADDRESSED:
2507                 case XHCI_ST_CONFIGURED:
2508                         /* enable power save */
2509                         temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2510                         break;
2511                 default:
2512                         /* disable power save */
2513                         break;
2514                 }
2515                 break;
2516         default:
2517                 break;
2518         }
2519
2520         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2521
2522         temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2523
2524         if (is_hub) {
2525                 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2526                     sc->sc_hw.devs[index].tt);
2527         }
2528
2529         hubdev = udev->parent_hs_hub;
2530
2531         /* check if we should activate the transaction translator */
2532         switch (udev->speed) {
2533         case USB_SPEED_FULL:
2534         case USB_SPEED_LOW:
2535                 if (hubdev != NULL) {
2536                         temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2537                             hubdev->controller_slot_id);
2538                         temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2539                             udev->hs_port_no);
2540                 }
2541                 break;
2542         default:
2543                 break;
2544         }
2545
2546         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2547
2548         /*
2549          * These fields should be initialized to zero, according to
2550          * XHCI section 6.2.2 - slot context:
2551          */
2552         temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2553             XHCI_SCTX_3_SLOT_STATE_SET(0);
2554
2555         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2556
2557 #ifdef USB_DEBUG
2558         xhci_dump_device(sc, &pinp->ctx_slot);
2559 #endif
2560         usb_pc_cpu_flush(pcinp);
2561
2562         return (0);             /* success */
2563 }
2564
2565 static usb_error_t
2566 xhci_alloc_device_ext(struct usb_device *udev)
2567 {
2568         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2569         struct usb_page_search buf_dev;
2570         struct usb_page_search buf_ep;
2571         struct xhci_trb *trb;
2572         struct usb_page_cache *pc;
2573         struct usb_page *pg;
2574         uint64_t addr;
2575         uint8_t index;
2576         uint8_t i;
2577
2578         index = udev->controller_slot_id;
2579
2580         pc = &sc->sc_hw.devs[index].device_pc;
2581         pg = &sc->sc_hw.devs[index].device_pg;
2582
2583         /* need to initialize the page cache */
2584         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2585
2586         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2587             (2 * sizeof(struct xhci_dev_ctx)) :
2588             sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2589                 goto error;
2590
2591         usbd_get_page(pc, 0, &buf_dev);
2592
2593         pc = &sc->sc_hw.devs[index].input_pc;
2594         pg = &sc->sc_hw.devs[index].input_pg;
2595
2596         /* need to initialize the page cache */
2597         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2598
2599         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2600             (2 * sizeof(struct xhci_input_dev_ctx)) :
2601             sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2602                 goto error;
2603         }
2604
2605         pc = &sc->sc_hw.devs[index].endpoint_pc;
2606         pg = &sc->sc_hw.devs[index].endpoint_pg;
2607
2608         /* need to initialize the page cache */
2609         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2610
2611         if (usb_pc_alloc_mem(pc, pg,
2612             sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) {
2613                 goto error;
2614         }
2615
2616         /* initialise all endpoint LINK TRBs */
2617
2618         for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2619
2620                 /* lookup endpoint TRB ring */
2621                 usbd_get_page(pc, (uintptr_t)&
2622                     ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep);
2623
2624                 /* get TRB pointer */
2625                 trb = buf_ep.buffer;
2626                 trb += XHCI_MAX_TRANSFERS - 1;
2627
2628                 /* get TRB start address */
2629                 addr = buf_ep.physaddr;
2630
2631                 /* create LINK TRB */
2632                 trb->qwTrb0 = htole64(addr);
2633                 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2634                 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2635                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2636         }
2637
2638         usb_pc_cpu_flush(pc);
2639
2640         xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2641
2642         return (0);
2643
2644 error:
2645         xhci_free_device_ext(udev);
2646
2647         return (USB_ERR_NOMEM);
2648 }
2649
2650 static void
2651 xhci_free_device_ext(struct usb_device *udev)
2652 {
2653         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2654         uint8_t index;
2655
2656         index = udev->controller_slot_id;
2657         xhci_set_slot_pointer(sc, index, 0);
2658
2659         usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2660         usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2661         usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc);
2662 }
2663
2664 static struct xhci_endpoint_ext *
2665 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2666 {
2667         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2668         struct xhci_endpoint_ext *pepext;
2669         struct usb_page_cache *pc;
2670         struct usb_page_search buf_ep;
2671         uint8_t epno;
2672         uint8_t index;
2673
2674         epno = edesc->bEndpointAddress;
2675         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2676                 epno |= UE_DIR_IN;
2677
2678         epno = XHCI_EPNO2EPID(epno);
2679
2680         index = udev->controller_slot_id;
2681
2682         pc = &sc->sc_hw.devs[index].endpoint_pc;
2683
2684         usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->trb[epno][0], &buf_ep);
2685
2686         pepext = &sc->sc_hw.devs[index].endp[epno];
2687         pepext->page_cache = pc;
2688         pepext->trb = buf_ep.buffer;
2689         pepext->physaddr = buf_ep.physaddr;
2690
2691         return (pepext);
2692 }
2693
2694 static void
2695 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2696 {
2697         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2698         uint8_t epno;
2699         uint8_t index;
2700
2701         epno = xfer->endpointno;
2702         if (xfer->flags_int.control_xfr)
2703                 epno |= UE_DIR_IN;
2704
2705         epno = XHCI_EPNO2EPID(epno);
2706         index = xfer->xroot->udev->controller_slot_id;
2707
2708         if (xfer->xroot->udev->flags.self_suspended == 0) {
2709                 XWRITE4(sc, door, XHCI_DOORBELL(index),
2710                     epno | XHCI_DB_SID_SET(/*xfer->stream_id*/ 0));
2711         }
2712 }
2713
2714 static void
2715 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2716 {
2717         struct xhci_endpoint_ext *pepext;
2718
2719         if (xfer->flags_int.bandwidth_reclaimed) {
2720                 xfer->flags_int.bandwidth_reclaimed = 0;
2721
2722                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2723                     xfer->endpoint->edesc);
2724
2725                 pepext->trb_used--;
2726
2727                 pepext->xfer[xfer->qh_pos] = NULL;
2728
2729                 if (error && pepext->trb_running != 0) {
2730                         pepext->trb_halted = 1;
2731                         pepext->trb_running = 0;
2732                 }
2733         }
2734 }
2735
2736 static usb_error_t
2737 xhci_transfer_insert(struct usb_xfer *xfer)
2738 {
2739         struct xhci_td *td_first;
2740         struct xhci_td *td_last;
2741         struct xhci_trb *trb_link;
2742         struct xhci_endpoint_ext *pepext;
2743         uint64_t addr;
2744         uint8_t i;
2745         uint8_t inext;
2746         uint8_t trb_limit;
2747
2748         DPRINTFN(8, "\n");
2749
2750         /* check if already inserted */
2751         if (xfer->flags_int.bandwidth_reclaimed) {
2752                 DPRINTFN(8, "Already in schedule\n");
2753                 return (0);
2754         }
2755
2756         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2757             xfer->endpoint->edesc);
2758
2759         td_first = xfer->td_transfer_first;
2760         td_last = xfer->td_transfer_last;
2761         addr = pepext->physaddr;
2762
2763         switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2764         case UE_CONTROL:
2765         case UE_INTERRUPT:
2766                 /* single buffered */
2767                 trb_limit = 1;
2768                 break;
2769         default:
2770                 /* multi buffered */
2771                 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2772                 break;
2773         }
2774
2775         if (pepext->trb_used >= trb_limit) {
2776                 DPRINTFN(8, "Too many TDs queued.\n");
2777                 return (USB_ERR_NOMEM);
2778         }
2779
2780         /* check for stopped condition, after putting transfer on interrupt queue */
2781         if (pepext->trb_running == 0) {
2782                 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2783
2784                 DPRINTFN(8, "Not running\n");
2785
2786                 /* start configuration */
2787                 (void)usb_proc_msignal(&sc->sc_config_proc,
2788                     &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2789                 return (0);
2790         }
2791
2792         pepext->trb_used++;
2793
2794         /* get current TRB index */
2795         i = pepext->trb_index;
2796
2797         /* get next TRB index */
2798         inext = (i + 1);
2799
2800         /* the last entry of the ring is a hardcoded link TRB */
2801         if (inext >= (XHCI_MAX_TRANSFERS - 1))
2802                 inext = 0;
2803
2804         /* compute terminating return address */
2805         addr += inext * sizeof(struct xhci_trb);
2806
2807         /* compute link TRB pointer */
2808         trb_link = td_last->td_trb + td_last->ntrb;
2809
2810         /* update next pointer of last link TRB */
2811         trb_link->qwTrb0 = htole64(addr);
2812         trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2813         trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2814             XHCI_TRB_3_CYCLE_BIT |
2815             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2816
2817 #ifdef USB_DEBUG
2818         xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2819 #endif
2820         usb_pc_cpu_flush(td_last->page_cache);
2821
2822         /* write ahead chain end marker */
2823
2824         pepext->trb[inext].qwTrb0 = 0;
2825         pepext->trb[inext].dwTrb2 = 0;
2826         pepext->trb[inext].dwTrb3 = 0;
2827
2828         /* update next pointer of link TRB */
2829
2830         pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2831         pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2832
2833 #ifdef USB_DEBUG
2834         xhci_dump_trb(&pepext->trb[i]);
2835 #endif
2836         usb_pc_cpu_flush(pepext->page_cache);
2837
2838         /* toggle cycle bit which activates the transfer chain */
2839
2840         pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2841             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2842
2843         usb_pc_cpu_flush(pepext->page_cache);
2844
2845         DPRINTF("qh_pos = %u\n", i);
2846
2847         pepext->xfer[i] = xfer;
2848
2849         xfer->qh_pos = i;
2850
2851         xfer->flags_int.bandwidth_reclaimed = 1;
2852
2853         pepext->trb_index = inext;
2854
2855         xhci_endpoint_doorbell(xfer);
2856
2857         return (0);
2858 }
2859
2860 static void
2861 xhci_root_intr(struct xhci_softc *sc)
2862 {
2863         uint16_t i;
2864
2865         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2866
2867         /* clear any old interrupt data */
2868         memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2869
2870         for (i = 1; i <= sc->sc_noport; i++) {
2871                 /* pick out CHANGE bits from the status register */
2872                 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
2873                     XHCI_PS_CSC | XHCI_PS_PEC |
2874                     XHCI_PS_OCC | XHCI_PS_WRC |
2875                     XHCI_PS_PRC | XHCI_PS_PLC |
2876                     XHCI_PS_CEC)) {
2877                         sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2878                         DPRINTF("port %d changed\n", i);
2879                 }
2880         }
2881         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2882             sizeof(sc->sc_hub_idata));
2883 }
2884
2885 /*------------------------------------------------------------------------*
2886  *      xhci_device_done - XHCI done handler
2887  *
2888  * NOTE: This function can be called two times in a row on
2889  * the same USB transfer. From close and from interrupt.
2890  *------------------------------------------------------------------------*/
2891 static void
2892 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
2893 {
2894         DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2895             xfer, xfer->endpoint, error);
2896
2897         /* remove transfer from HW queue */
2898         xhci_transfer_remove(xfer, error);
2899
2900         /* dequeue transfer and start next transfer */
2901         usbd_transfer_done(xfer, error);
2902 }
2903
2904 /*------------------------------------------------------------------------*
2905  * XHCI data transfer support (generic type)
2906  *------------------------------------------------------------------------*/
2907 static void
2908 xhci_device_generic_open(struct usb_xfer *xfer)
2909 {
2910         if (xfer->flags_int.isochronous_xfr) {
2911                 switch (xfer->xroot->udev->speed) {
2912                 case USB_SPEED_FULL:
2913                         break;
2914                 default:
2915                         usb_hs_bandwidth_alloc(xfer);
2916                         break;
2917                 }
2918         }
2919 }
2920
2921 static void
2922 xhci_device_generic_close(struct usb_xfer *xfer)
2923 {
2924         DPRINTF("\n");
2925
2926         xhci_device_done(xfer, USB_ERR_CANCELLED);
2927
2928         if (xfer->flags_int.isochronous_xfr) {
2929                 switch (xfer->xroot->udev->speed) {
2930                 case USB_SPEED_FULL:
2931                         break;
2932                 default:
2933                         usb_hs_bandwidth_free(xfer);
2934                         break;
2935                 }
2936         }
2937 }
2938
2939 static void
2940 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
2941     struct usb_xfer *enter_xfer)
2942 {
2943         struct usb_xfer *xfer;
2944
2945         /* check if there is a current transfer */
2946         xfer = ep->endpoint_q.curr;
2947         if (xfer == NULL)
2948                 return;
2949
2950         /*
2951          * Check if the current transfer is started and then pickup
2952          * the next one, if any. Else wait for next start event due to
2953          * block on failure feature.
2954          */
2955         if (!xfer->flags_int.bandwidth_reclaimed)
2956                 return;
2957
2958         xfer = TAILQ_FIRST(&ep->endpoint_q.head);
2959         if (xfer == NULL) {
2960                 /*
2961                  * In case of enter we have to consider that the
2962                  * transfer is queued by the USB core after the enter
2963                  * method is called.
2964                  */
2965                 xfer = enter_xfer;
2966
2967                 if (xfer == NULL)
2968                         return;
2969         }
2970
2971         /* try to multi buffer */
2972         xhci_transfer_insert(xfer);
2973 }
2974
2975 static void
2976 xhci_device_generic_enter(struct usb_xfer *xfer)
2977 {
2978         DPRINTF("\n");
2979
2980         /* setup TD's and QH */
2981         xhci_setup_generic_chain(xfer);
2982
2983         xhci_device_generic_multi_enter(xfer->endpoint, xfer);
2984 }
2985
2986 static void
2987 xhci_device_generic_start(struct usb_xfer *xfer)
2988 {
2989         DPRINTF("\n");
2990
2991         /* try to insert xfer on HW queue */
2992         xhci_transfer_insert(xfer);
2993
2994         /* try to multi buffer */
2995         xhci_device_generic_multi_enter(xfer->endpoint, NULL);
2996
2997         /* add transfer last on interrupt queue */
2998         usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
2999
3000         /* start timeout, if any */
3001         if (xfer->timeout != 0)
3002                 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3003 }
3004
3005 struct usb_pipe_methods xhci_device_generic_methods =
3006 {
3007         .open = xhci_device_generic_open,
3008         .close = xhci_device_generic_close,
3009         .enter = xhci_device_generic_enter,
3010         .start = xhci_device_generic_start,
3011 };
3012
3013 /*------------------------------------------------------------------------*
3014  * xhci root HUB support
3015  *------------------------------------------------------------------------*
3016  * Simulate a hardware HUB by handling all the necessary requests.
3017  *------------------------------------------------------------------------*/
3018
3019 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3020
3021 static const
3022 struct usb_device_descriptor xhci_devd =
3023 {
3024         .bLength = sizeof(xhci_devd),
3025         .bDescriptorType = UDESC_DEVICE,        /* type */
3026         HSETW(.bcdUSB, 0x0300),                 /* USB version */
3027         .bDeviceClass = UDCLASS_HUB,            /* class */
3028         .bDeviceSubClass = UDSUBCLASS_HUB,      /* subclass */
3029         .bDeviceProtocol = UDPROTO_SSHUB,       /* protocol */
3030         .bMaxPacketSize = 9,                    /* max packet size */
3031         HSETW(.idVendor, 0x0000),               /* vendor */
3032         HSETW(.idProduct, 0x0000),              /* product */
3033         HSETW(.bcdDevice, 0x0100),              /* device version */
3034         .iManufacturer = 1,
3035         .iProduct = 2,
3036         .iSerialNumber = 0,
3037         .bNumConfigurations = 1,                /* # of configurations */
3038 };
3039
3040 static const
3041 struct xhci_bos_desc xhci_bosd = {
3042         .bosd = {
3043                 .bLength = sizeof(xhci_bosd.bosd),
3044                 .bDescriptorType = UDESC_BOS,
3045                 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3046                 .bNumDeviceCaps = 3,
3047         },
3048         .usb2extd = {
3049                 .bLength = sizeof(xhci_bosd.usb2extd),
3050                 .bDescriptorType = 1,
3051                 .bDevCapabilityType = 2,
3052                 .bmAttributes[0] = 2,
3053         },
3054         .usbdcd = {
3055                 .bLength = sizeof(xhci_bosd.usbdcd),
3056                 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3057                 .bDevCapabilityType = 3,
3058                 .bmAttributes = 0, /* XXX */
3059                 HSETW(.wSpeedsSupported, 0x000C),
3060                 .bFunctionalitySupport = 8,
3061                 .bU1DevExitLat = 255,   /* dummy - not used */
3062                 .wU2DevExitLat = { 0x00, 0x08 },
3063         },
3064         .cidd = {
3065                 .bLength = sizeof(xhci_bosd.cidd),
3066                 .bDescriptorType = 1,
3067                 .bDevCapabilityType = 4,
3068                 .bReserved = 0,
3069                 .bContainerID = 0, /* XXX */
3070         },
3071 };
3072
3073 static const
3074 struct xhci_config_desc xhci_confd = {
3075         .confd = {
3076                 .bLength = sizeof(xhci_confd.confd),
3077                 .bDescriptorType = UDESC_CONFIG,
3078                 .wTotalLength[0] = sizeof(xhci_confd),
3079                 .bNumInterface = 1,
3080                 .bConfigurationValue = 1,
3081                 .iConfiguration = 0,
3082                 .bmAttributes = UC_SELF_POWERED,
3083                 .bMaxPower = 0          /* max power */
3084         },
3085         .ifcd = {
3086                 .bLength = sizeof(xhci_confd.ifcd),
3087                 .bDescriptorType = UDESC_INTERFACE,
3088                 .bNumEndpoints = 1,
3089                 .bInterfaceClass = UICLASS_HUB,
3090                 .bInterfaceSubClass = UISUBCLASS_HUB,
3091                 .bInterfaceProtocol = 0,
3092         },
3093         .endpd = {
3094                 .bLength = sizeof(xhci_confd.endpd),
3095                 .bDescriptorType = UDESC_ENDPOINT,
3096                 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3097                 .bmAttributes = UE_INTERRUPT,
3098                 .wMaxPacketSize[0] = 2,         /* max 15 ports */
3099                 .bInterval = 255,
3100         },
3101         .endpcd = {
3102                 .bLength = sizeof(xhci_confd.endpcd),
3103                 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3104                 .bMaxBurst = 0,
3105                 .bmAttributes = 0,
3106         },
3107 };
3108
3109 static const
3110 struct usb_hub_ss_descriptor xhci_hubd = {
3111         .bLength = sizeof(xhci_hubd),
3112         .bDescriptorType = UDESC_SS_HUB,
3113 };
3114
3115 static usb_error_t
3116 xhci_roothub_exec(struct usb_device *udev,
3117     struct usb_device_request *req, const void **pptr, uint16_t *plength)
3118 {
3119         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3120         const char *str_ptr;
3121         const void *ptr;
3122         uint32_t port;
3123         uint32_t v;
3124         uint16_t len;
3125         uint16_t i;
3126         uint16_t value;
3127         uint16_t index;
3128         uint8_t j;
3129         usb_error_t err;
3130
3131         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3132
3133         /* buffer reset */
3134         ptr = (const void *)&sc->sc_hub_desc;
3135         len = 0;
3136         err = 0;
3137
3138         value = UGETW(req->wValue);
3139         index = UGETW(req->wIndex);
3140
3141         DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3142             "wValue=0x%04x wIndex=0x%04x\n",
3143             req->bmRequestType, req->bRequest,
3144             UGETW(req->wLength), value, index);
3145
3146 #define C(x,y) ((x) | ((y) << 8))
3147         switch (C(req->bRequest, req->bmRequestType)) {
3148         case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3149         case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3150         case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3151                 /*
3152                  * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3153                  * for the integrated root hub.
3154                  */
3155                 break;
3156         case C(UR_GET_CONFIG, UT_READ_DEVICE):
3157                 len = 1;
3158                 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3159                 break;
3160         case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3161                 switch (value >> 8) {
3162                 case UDESC_DEVICE:
3163                         if ((value & 0xff) != 0) {
3164                                 err = USB_ERR_IOERROR;
3165                                 goto done;
3166                         }
3167                         len = sizeof(xhci_devd);
3168                         ptr = (const void *)&xhci_devd;
3169                         break;
3170
3171                 case UDESC_BOS:
3172                         if ((value & 0xff) != 0) {
3173                                 err = USB_ERR_IOERROR;
3174                                 goto done;
3175                         }
3176                         len = sizeof(xhci_bosd);
3177                         ptr = (const void *)&xhci_bosd;
3178                         break;
3179
3180                 case UDESC_CONFIG:
3181                         if ((value & 0xff) != 0) {
3182                                 err = USB_ERR_IOERROR;
3183                                 goto done;
3184                         }
3185                         len = sizeof(xhci_confd);
3186                         ptr = (const void *)&xhci_confd;
3187                         break;
3188
3189                 case UDESC_STRING:
3190                         switch (value & 0xff) {
3191                         case 0: /* Language table */
3192                                 str_ptr = "\001";
3193                                 break;
3194
3195                         case 1: /* Vendor */
3196                                 str_ptr = sc->sc_vendor;
3197                                 break;
3198
3199                         case 2: /* Product */
3200                                 str_ptr = "XHCI root HUB";
3201                                 break;
3202
3203                         default:
3204                                 str_ptr = "";
3205                                 break;
3206                         }
3207
3208                         len = usb_make_str_desc(
3209                             sc->sc_hub_desc.temp,
3210                             sizeof(sc->sc_hub_desc.temp),
3211                             str_ptr);
3212                         break;
3213
3214                 default:
3215                         err = USB_ERR_IOERROR;
3216                         goto done;
3217                 }
3218                 break;
3219         case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3220                 len = 1;
3221                 sc->sc_hub_desc.temp[0] = 0;
3222                 break;
3223         case C(UR_GET_STATUS, UT_READ_DEVICE):
3224                 len = 2;
3225                 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3226                 break;
3227         case C(UR_GET_STATUS, UT_READ_INTERFACE):
3228         case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3229                 len = 2;
3230                 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3231                 break;
3232         case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3233                 if (value >= XHCI_MAX_DEVICES) {
3234                         err = USB_ERR_IOERROR;
3235                         goto done;
3236                 }
3237                 break;
3238         case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3239                 if (value != 0 && value != 1) {
3240                         err = USB_ERR_IOERROR;
3241                         goto done;
3242                 }
3243                 sc->sc_conf = value;
3244                 break;
3245         case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3246                 break;
3247         case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3248         case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3249         case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3250                 err = USB_ERR_IOERROR;
3251                 goto done;
3252         case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3253                 break;
3254         case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3255                 break;
3256                 /* Hub requests */
3257         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3258                 break;
3259         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3260                 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3261
3262                 if ((index < 1) ||
3263                     (index > sc->sc_noport)) {
3264                         err = USB_ERR_IOERROR;
3265                         goto done;
3266                 }
3267                 port = XHCI_PORTSC(index);
3268
3269                 v = XREAD4(sc, oper, port);
3270                 i = XHCI_PS_PLS_GET(v);
3271                 v &= ~XHCI_PS_CLEAR;
3272
3273                 switch (value) {
3274                 case UHF_C_BH_PORT_RESET:
3275                         XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3276                         break;
3277                 case UHF_C_PORT_CONFIG_ERROR:
3278                         XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3279                         break;
3280                 case UHF_C_PORT_SUSPEND:
3281                 case UHF_C_PORT_LINK_STATE:
3282                         XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3283                         break;
3284                 case UHF_C_PORT_CONNECTION:
3285                         XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3286                         break;
3287                 case UHF_C_PORT_ENABLE:
3288                         XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3289                         break;
3290                 case UHF_C_PORT_OVER_CURRENT:
3291                         XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3292                         break;
3293                 case UHF_C_PORT_RESET:
3294                         XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3295                         break;
3296                 case UHF_PORT_ENABLE:
3297                         XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3298                         break;
3299                 case UHF_PORT_POWER:
3300                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3301                         break;
3302                 case UHF_PORT_INDICATOR:
3303                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3304                         break;
3305                 case UHF_PORT_SUSPEND:
3306
3307                         /* U3 -> U15 */
3308                         if (i == 3) {
3309                                 XWRITE4(sc, oper, port, v |
3310                                     XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3311                         }
3312
3313                         /* wait 20ms for resume sequence to complete */
3314                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3315
3316                         /* U0 */
3317                         XWRITE4(sc, oper, port, v |
3318                             XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3319                         break;
3320                 default:
3321                         err = USB_ERR_IOERROR;
3322                         goto done;
3323                 }
3324                 break;
3325
3326         case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3327                 if ((value & 0xff) != 0) {
3328                         err = USB_ERR_IOERROR;
3329                         goto done;
3330                 }
3331
3332                 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3333
3334                 sc->sc_hub_desc.hubd = xhci_hubd;
3335
3336                 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3337
3338                 if (XHCI_HCS0_PPC(v))
3339                         i = UHD_PWR_INDIVIDUAL;
3340                 else
3341                         i = UHD_PWR_GANGED;
3342
3343                 if (XHCI_HCS0_PIND(v))
3344                         i |= UHD_PORT_IND;
3345
3346                 i |= UHD_OC_INDIVIDUAL;
3347
3348                 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3349
3350                 /* see XHCI section 5.4.9: */
3351                 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3352
3353                 for (j = 1; j <= sc->sc_noport; j++) {
3354
3355                         v = XREAD4(sc, oper, XHCI_PORTSC(j));
3356                         if (v & XHCI_PS_DR) {
3357                                 sc->sc_hub_desc.hubd.
3358                                     DeviceRemovable[j / 8] |= 1U << (j % 8);
3359                         }
3360                 }
3361                 len = sc->sc_hub_desc.hubd.bLength;
3362                 break;
3363
3364         case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3365                 len = 16;
3366                 memset(sc->sc_hub_desc.temp, 0, 16);
3367                 break;
3368
3369         case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3370                 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3371
3372                 if ((index < 1) ||
3373                     (index > sc->sc_noport)) {
3374                         err = USB_ERR_IOERROR;
3375                         goto done;
3376                 }
3377
3378                 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3379
3380                 DPRINTFN(9, "port status=0x%08x\n", v);
3381
3382                 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3383
3384                 switch (XHCI_PS_SPEED_GET(v)) {
3385                 case 3:
3386                         i |= UPS_HIGH_SPEED;
3387                         break;
3388                 case 2:
3389                         i |= UPS_LOW_SPEED;
3390                         break;
3391                 case 1:
3392                         /* FULL speed */
3393                         break;
3394                 default:
3395                         i |= UPS_OTHER_SPEED;
3396                         break;
3397                 }
3398
3399                 if (v & XHCI_PS_CCS)
3400                         i |= UPS_CURRENT_CONNECT_STATUS;
3401                 if (v & XHCI_PS_PED)
3402                         i |= UPS_PORT_ENABLED;
3403                 if (v & XHCI_PS_OCA)
3404                         i |= UPS_OVERCURRENT_INDICATOR;
3405                 if (v & XHCI_PS_PR)
3406                         i |= UPS_RESET;
3407                 if (v & XHCI_PS_PP) {
3408                         /*
3409                          * The USB 3.0 RH is using the
3410                          * USB 2.0's power bit
3411                          */
3412                         i |= UPS_PORT_POWER;
3413                 }
3414                 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3415
3416                 i = 0;
3417                 if (v & XHCI_PS_CSC)
3418                         i |= UPS_C_CONNECT_STATUS;
3419                 if (v & XHCI_PS_PEC)
3420                         i |= UPS_C_PORT_ENABLED;
3421                 if (v & XHCI_PS_OCC)
3422                         i |= UPS_C_OVERCURRENT_INDICATOR;
3423                 if (v & XHCI_PS_WRC)
3424                         i |= UPS_C_BH_PORT_RESET;
3425                 if (v & XHCI_PS_PRC)
3426                         i |= UPS_C_PORT_RESET;
3427                 if (v & XHCI_PS_PLC)
3428                         i |= UPS_C_PORT_LINK_STATE;
3429                 if (v & XHCI_PS_CEC)
3430                         i |= UPS_C_PORT_CONFIG_ERROR;
3431
3432                 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3433                 len = sizeof(sc->sc_hub_desc.ps);
3434                 break;
3435
3436         case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3437                 err = USB_ERR_IOERROR;
3438                 goto done;
3439
3440         case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3441                 break;
3442
3443         case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3444
3445                 i = index >> 8;
3446                 index &= 0x00FF;
3447
3448                 if ((index < 1) ||
3449                     (index > sc->sc_noport)) {
3450                         err = USB_ERR_IOERROR;
3451                         goto done;
3452                 }
3453
3454                 port = XHCI_PORTSC(index);
3455                 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3456
3457                 switch (value) {
3458                 case UHF_PORT_U1_TIMEOUT:
3459                         if (XHCI_PS_SPEED_GET(v) != 4) {
3460                                 err = USB_ERR_IOERROR;
3461                                 goto done;
3462                         }
3463                         port = XHCI_PORTPMSC(index);
3464                         v = XREAD4(sc, oper, port);
3465                         v &= ~XHCI_PM3_U1TO_SET(0xFF);
3466                         v |= XHCI_PM3_U1TO_SET(i);
3467                         XWRITE4(sc, oper, port, v);
3468                         break;
3469                 case UHF_PORT_U2_TIMEOUT:
3470                         if (XHCI_PS_SPEED_GET(v) != 4) {
3471                                 err = USB_ERR_IOERROR;
3472                                 goto done;
3473                         }
3474                         port = XHCI_PORTPMSC(index);
3475                         v = XREAD4(sc, oper, port);
3476                         v &= ~XHCI_PM3_U2TO_SET(0xFF);
3477                         v |= XHCI_PM3_U2TO_SET(i);
3478                         XWRITE4(sc, oper, port, v);
3479                         break;
3480                 case UHF_BH_PORT_RESET:
3481                         XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3482                         break;
3483                 case UHF_PORT_LINK_STATE:
3484                         XWRITE4(sc, oper, port, v |
3485                             XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3486                         /* 4ms settle time */
3487                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3488                         break;
3489                 case UHF_PORT_ENABLE:
3490                         DPRINTFN(3, "set port enable %d\n", index);
3491                         break;
3492                 case UHF_PORT_SUSPEND:
3493                         DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3494                         j = XHCI_PS_SPEED_GET(v);
3495                         if ((j < 1) || (j > 3)) {
3496                                 /* non-supported speed */
3497                                 err = USB_ERR_IOERROR;
3498                                 goto done;
3499                         }
3500                         XWRITE4(sc, oper, port, v |
3501                             XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3502                         break;
3503                 case UHF_PORT_RESET:
3504                         DPRINTFN(6, "reset port %d\n", index);
3505                         XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3506                         break;
3507                 case UHF_PORT_POWER:
3508                         DPRINTFN(3, "set port power %d\n", index);
3509                         XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3510                         break;
3511                 case UHF_PORT_TEST:
3512                         DPRINTFN(3, "set port test %d\n", index);
3513                         break;
3514                 case UHF_PORT_INDICATOR:
3515                         DPRINTFN(3, "set port indicator %d\n", index);
3516
3517                         v &= ~XHCI_PS_PIC_SET(3);
3518                         v |= XHCI_PS_PIC_SET(1);
3519
3520                         XWRITE4(sc, oper, port, v);
3521                         break;
3522                 default:
3523                         err = USB_ERR_IOERROR;
3524                         goto done;
3525                 }
3526                 break;
3527
3528         case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3529         case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3530         case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3531         case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3532                 break;
3533         default:
3534                 err = USB_ERR_IOERROR;
3535                 goto done;
3536         }
3537 done:
3538         *plength = len;
3539         *pptr = ptr;
3540         return (err);
3541 }
3542
3543 static void
3544 xhci_xfer_setup(struct usb_setup_params *parm)
3545 {
3546         struct usb_page_search page_info;
3547         struct usb_page_cache *pc;
3548         struct xhci_softc *sc;
3549         struct usb_xfer *xfer;
3550         void *last_obj;
3551         uint32_t ntd;
3552         uint32_t n;
3553
3554         sc = XHCI_BUS2SC(parm->udev->bus);
3555         xfer = parm->curr_xfer;
3556
3557         /*
3558          * The proof for the "ntd" formula is illustrated like this:
3559          *
3560          * +------------------------------------+
3561          * |                                    |
3562          * |         |remainder ->              |
3563          * |   +-----+---+                      |
3564          * |   | xxx | x | frm 0                |
3565          * |   +-----+---++                     |
3566          * |   | xxx | xx | frm 1               |
3567          * |   +-----+----+                     |
3568          * |            ...                     |
3569          * +------------------------------------+
3570          *
3571          * "xxx" means a completely full USB transfer descriptor
3572          *
3573          * "x" and "xx" means a short USB packet
3574          *
3575          * For the remainder of an USB transfer modulo
3576          * "max_data_length" we need two USB transfer descriptors.
3577          * One to transfer the remaining data and one to finalise with
3578          * a zero length packet in case the "force_short_xfer" flag is
3579          * set. We only need two USB transfer descriptors in the case
3580          * where the transfer length of the first one is a factor of
3581          * "max_frame_size". The rest of the needed USB transfer
3582          * descriptors is given by the buffer size divided by the
3583          * maximum data payload.
3584          */
3585         parm->hc_max_packet_size = 0x400;
3586         parm->hc_max_packet_count = 16 * 3;
3587         parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3588
3589         xfer->flags_int.bdma_enable = 1;
3590
3591         usbd_transfer_setup_sub(parm);
3592
3593         if (xfer->flags_int.isochronous_xfr) {
3594                 ntd = ((1 * xfer->nframes)
3595                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3596         } else if (xfer->flags_int.control_xfr) {
3597                 ntd = ((2 * xfer->nframes) + 1  /* STATUS */
3598                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3599         } else {
3600                 ntd = ((2 * xfer->nframes)
3601                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3602         }
3603
3604 alloc_dma_set:
3605
3606         if (parm->err)
3607                 return;
3608
3609         /*
3610          * Allocate queue heads and transfer descriptors
3611          */
3612         last_obj = NULL;
3613
3614         if (usbd_transfer_setup_sub_malloc(
3615             parm, &pc, sizeof(struct xhci_td),
3616             XHCI_TD_ALIGN, ntd)) {
3617                 parm->err = USB_ERR_NOMEM;
3618                 return;
3619         }
3620         if (parm->buf) {
3621                 for (n = 0; n != ntd; n++) {
3622                         struct xhci_td *td;
3623
3624                         usbd_get_page(pc + n, 0, &page_info);
3625
3626                         td = page_info.buffer;
3627
3628                         /* init TD */
3629                         td->td_self = page_info.physaddr;
3630                         td->obj_next = last_obj;
3631                         td->page_cache = pc + n;
3632
3633                         last_obj = td;
3634
3635                         usb_pc_cpu_flush(pc + n);
3636                 }
3637         }
3638         xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3639
3640         if (!xfer->flags_int.curr_dma_set) {
3641                 xfer->flags_int.curr_dma_set = 1;
3642                 goto alloc_dma_set;
3643         }
3644 }
3645
3646 static usb_error_t
3647 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3648 {
3649         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3650         struct usb_page_search buf_inp;
3651         struct usb_device *udev;
3652         struct xhci_endpoint_ext *pepext;
3653         struct usb_endpoint_descriptor *edesc;
3654         struct usb_page_cache *pcinp;
3655         usb_error_t err;
3656         uint8_t index;
3657         uint8_t epno;
3658
3659         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3660             xfer->endpoint->edesc);
3661
3662         udev = xfer->xroot->udev;
3663         index = udev->controller_slot_id;
3664
3665         pcinp = &sc->sc_hw.devs[index].input_pc;
3666
3667         usbd_get_page(pcinp, 0, &buf_inp);
3668
3669         edesc = xfer->endpoint->edesc;
3670
3671         epno = edesc->bEndpointAddress;
3672
3673         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3674                 epno |= UE_DIR_IN;
3675
3676         epno = XHCI_EPNO2EPID(epno);
3677
3678         if (epno == 0)
3679                 return (USB_ERR_NO_PIPE);               /* invalid */
3680
3681         XHCI_CMD_LOCK(sc);
3682
3683         /* configure endpoint */
3684
3685         err = xhci_configure_endpoint_by_xfer(xfer);
3686
3687         if (err != 0) {
3688                 XHCI_CMD_UNLOCK(sc);
3689                 return (err);
3690         }
3691
3692         /*
3693          * Get the endpoint into the stopped state according to the
3694          * endpoint context state diagram in the XHCI specification:
3695          */
3696
3697         err = xhci_cmd_stop_ep(sc, 0, epno, index);
3698
3699         if (err != 0)
3700                 DPRINTF("Could not stop endpoint %u\n", epno);
3701
3702         err = xhci_cmd_reset_ep(sc, 0, epno, index);
3703
3704         if (err != 0)
3705                 DPRINTF("Could not reset endpoint %u\n", epno);
3706
3707         err = xhci_cmd_set_tr_dequeue_ptr(sc, pepext->physaddr |
3708             XHCI_EPCTX_2_DCS_SET(1), 0, epno, index);
3709
3710         if (err != 0)
3711                 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3712
3713         /*
3714          * Get the endpoint into the running state according to the
3715          * endpoint context state diagram in the XHCI specification:
3716          */
3717
3718         xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3719
3720         err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3721
3722         if (err != 0)
3723                 DPRINTF("Could not configure endpoint %u\n", epno);
3724
3725         err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3726
3727         if (err != 0)
3728                 DPRINTF("Could not configure endpoint %u\n", epno);
3729
3730         XHCI_CMD_UNLOCK(sc);
3731
3732         return (0);
3733 }
3734
3735 static void
3736 xhci_xfer_unsetup(struct usb_xfer *xfer)
3737 {
3738         return;
3739 }
3740
3741 static void
3742 xhci_start_dma_delay(struct usb_xfer *xfer)
3743 {
3744         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3745
3746         /* put transfer on interrupt queue (again) */
3747         usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3748
3749         (void)usb_proc_msignal(&sc->sc_config_proc,
3750             &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3751 }
3752
3753 static void
3754 xhci_configure_msg(struct usb_proc_msg *pm)
3755 {
3756         struct xhci_softc *sc;
3757         struct xhci_endpoint_ext *pepext;
3758         struct usb_xfer *xfer;
3759
3760         sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3761
3762 restart:
3763         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3764
3765                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3766                     xfer->endpoint->edesc);
3767
3768                 if ((pepext->trb_halted != 0) ||
3769                     (pepext->trb_running == 0)) {
3770
3771                         uint8_t i;
3772
3773                         /* clear halted and running */
3774                         pepext->trb_halted = 0;
3775                         pepext->trb_running = 0;
3776
3777                         /* nuke remaining buffered transfers */
3778
3779                         for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
3780                                 /*
3781                                  * NOTE: We need to use the timeout
3782                                  * error code here else existing
3783                                  * isochronous clients can get
3784                                  * confused:
3785                                  */
3786                                 if (pepext->xfer[i] != NULL) {
3787                                         xhci_device_done(pepext->xfer[i],
3788                                             USB_ERR_TIMEOUT);
3789                                 }
3790                         }
3791
3792                         /*
3793                          * NOTE: The USB transfer cannot vanish in
3794                          * this state!
3795                          */
3796
3797                         USB_BUS_UNLOCK(&sc->sc_bus);
3798
3799                         xhci_configure_reset_endpoint(xfer);
3800
3801                         USB_BUS_LOCK(&sc->sc_bus);
3802
3803                         /* check if halted is still cleared */
3804                         if (pepext->trb_halted == 0) {
3805                                 pepext->trb_running = 1;
3806                                 pepext->trb_index = 0;
3807                         }
3808                         goto restart;
3809                 }
3810
3811                 if (xfer->flags_int.did_dma_delay) {
3812
3813                         /* remove transfer from interrupt queue (again) */
3814                         usbd_transfer_dequeue(xfer);
3815
3816                         /* we are finally done */
3817                         usb_dma_delay_done_cb(xfer);
3818
3819                         /* queue changed - restart */
3820                         goto restart;
3821                 }
3822         }
3823
3824         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3825
3826                 /* try to insert xfer on HW queue */
3827                 xhci_transfer_insert(xfer);
3828
3829                 /* try to multi buffer */
3830                 xhci_device_generic_multi_enter(xfer->endpoint, NULL);
3831         }
3832 }
3833
3834 static void
3835 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3836     struct usb_endpoint *ep)
3837 {
3838         struct xhci_endpoint_ext *pepext;
3839
3840         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3841             ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
3842
3843         if (udev->flags.usb_mode != USB_MODE_HOST) {
3844                 /* not supported */
3845                 return;
3846         }
3847         if (udev->parent_hub == NULL) {
3848                 /* root HUB has special endpoint handling */
3849                 return;
3850         }
3851
3852         ep->methods = &xhci_device_generic_methods;
3853
3854         pepext = xhci_get_endpoint_ext(udev, edesc);
3855
3856         USB_BUS_LOCK(udev->bus);
3857         pepext->trb_halted = 1;
3858         pepext->trb_running = 0;
3859         USB_BUS_UNLOCK(udev->bus);
3860 }
3861
3862 static void
3863 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
3864 {
3865
3866 }
3867
3868 static void
3869 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3870 {
3871         struct xhci_endpoint_ext *pepext;
3872
3873         DPRINTF("\n");
3874
3875         if (udev->flags.usb_mode != USB_MODE_HOST) {
3876                 /* not supported */
3877                 return;
3878         }
3879         if (udev->parent_hub == NULL) {
3880                 /* root HUB has special endpoint handling */
3881                 return;
3882         }
3883
3884         pepext = xhci_get_endpoint_ext(udev, ep->edesc);
3885
3886         USB_BUS_LOCK(udev->bus);
3887         pepext->trb_halted = 1;
3888         pepext->trb_running = 0;
3889         USB_BUS_UNLOCK(udev->bus);
3890 }
3891
3892 static usb_error_t
3893 xhci_device_init(struct usb_device *udev)
3894 {
3895         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3896         usb_error_t err;
3897         uint8_t temp;
3898
3899         /* no init for root HUB */
3900         if (udev->parent_hub == NULL)
3901                 return (0);
3902
3903         XHCI_CMD_LOCK(sc);
3904
3905         /* set invalid default */
3906
3907         udev->controller_slot_id = sc->sc_noslot + 1;
3908
3909         /* try to get a new slot ID from the XHCI */
3910
3911         err = xhci_cmd_enable_slot(sc, &temp);
3912
3913         if (err) {
3914                 XHCI_CMD_UNLOCK(sc);
3915                 return (err);
3916         }
3917
3918         if (temp > sc->sc_noslot) {
3919                 XHCI_CMD_UNLOCK(sc);
3920                 return (USB_ERR_BAD_ADDRESS);
3921         }
3922
3923         if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
3924                 DPRINTF("slot %u already allocated.\n", temp);
3925                 XHCI_CMD_UNLOCK(sc);
3926                 return (USB_ERR_BAD_ADDRESS);
3927         }
3928
3929         /* store slot ID for later reference */
3930
3931         udev->controller_slot_id = temp;
3932
3933         /* reset data structure */
3934
3935         memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
3936
3937         /* set mark slot allocated */
3938
3939         sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
3940
3941         err = xhci_alloc_device_ext(udev);
3942
3943         XHCI_CMD_UNLOCK(sc);
3944
3945         /* get device into default state */
3946
3947         if (err == 0)
3948                 err = xhci_set_address(udev, NULL, 0);
3949
3950         return (err);
3951 }
3952
3953 static void
3954 xhci_device_uninit(struct usb_device *udev)
3955 {
3956         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3957         uint8_t index;
3958
3959         /* no init for root HUB */
3960         if (udev->parent_hub == NULL)
3961                 return;
3962
3963         XHCI_CMD_LOCK(sc);
3964
3965         index = udev->controller_slot_id;
3966
3967         if (index <= sc->sc_noslot) {
3968                 xhci_cmd_disable_slot(sc, index);
3969                 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
3970
3971                 /* free device extension */
3972                 xhci_free_device_ext(udev);
3973         }
3974
3975         XHCI_CMD_UNLOCK(sc);
3976 }
3977
3978 static void
3979 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
3980 {
3981         /*
3982          * Wait until the hardware has finished any possible use of
3983          * the transfer descriptor(s)
3984          */
3985         *pus = 2048;                    /* microseconds */
3986 }
3987
3988 static void
3989 xhci_device_resume(struct usb_device *udev)
3990 {
3991         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3992         uint8_t index;
3993         uint8_t n;
3994         uint8_t p;
3995
3996         DPRINTF("\n");
3997
3998         /* check for root HUB */
3999         if (udev->parent_hub == NULL)
4000                 return;
4001
4002         index = udev->controller_slot_id;
4003
4004         XHCI_CMD_LOCK(sc);
4005
4006         /* blindly resume all endpoints */
4007
4008         USB_BUS_LOCK(udev->bus);
4009
4010         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4011                 for (p = 0; p != 1 /*XHCI_MAX_STREAMS*/; p++) {
4012                         XWRITE4(sc, door, XHCI_DOORBELL(index),
4013                             n | XHCI_DB_SID_SET(p));
4014                 }
4015         }
4016
4017         USB_BUS_UNLOCK(udev->bus);
4018
4019         XHCI_CMD_UNLOCK(sc);
4020 }
4021
4022 static void
4023 xhci_device_suspend(struct usb_device *udev)
4024 {
4025         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4026         uint8_t index;
4027         uint8_t n;
4028         usb_error_t err;
4029
4030         DPRINTF("\n");
4031
4032         /* check for root HUB */
4033         if (udev->parent_hub == NULL)
4034                 return;
4035
4036         index = udev->controller_slot_id;
4037
4038         XHCI_CMD_LOCK(sc);
4039
4040         /* blindly suspend all endpoints */
4041
4042         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4043                 err = xhci_cmd_stop_ep(sc, 1, n, index);
4044                 if (err != 0) {
4045                         DPRINTF("Failed to suspend endpoint "
4046                             "%u on slot %u (ignored).\n", n, index);
4047                 }
4048         }
4049
4050         XHCI_CMD_UNLOCK(sc);
4051 }
4052
4053 static void
4054 xhci_set_hw_power(struct usb_bus *bus)
4055 {
4056         DPRINTF("\n");
4057 }
4058
4059 static void
4060 xhci_device_state_change(struct usb_device *udev)
4061 {
4062         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4063         struct usb_page_search buf_inp;
4064         usb_error_t err;
4065         uint8_t index;
4066
4067         /* check for root HUB */
4068         if (udev->parent_hub == NULL)
4069                 return;
4070
4071         index = udev->controller_slot_id;
4072
4073         DPRINTF("\n");
4074
4075         if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4076                 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4077                     &sc->sc_hw.devs[index].tt);
4078                 if (err != 0)
4079                         sc->sc_hw.devs[index].nports = 0;
4080         }
4081
4082         XHCI_CMD_LOCK(sc);
4083
4084         switch (usb_get_device_state(udev)) {
4085         case USB_STATE_POWERED:
4086                 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4087                         break;
4088
4089                 /* set default state */
4090                 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4091
4092                 /* reset number of contexts */
4093                 sc->sc_hw.devs[index].context_num = 0;
4094
4095                 err = xhci_cmd_reset_dev(sc, index);
4096
4097                 if (err != 0) {
4098                         DPRINTF("Device reset failed "
4099                             "for slot %u.\n", index);
4100                 }
4101                 break;
4102
4103         case USB_STATE_ADDRESSED:
4104                 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4105                         break;
4106
4107                 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4108
4109                 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4110
4111                 if (err) {
4112                         DPRINTF("Failed to deconfigure "
4113                             "slot %u.\n", index);
4114                 }
4115                 break;
4116
4117         case USB_STATE_CONFIGURED:
4118                 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4119                         break;
4120
4121                 /* set configured state */
4122                 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4123
4124                 /* reset number of contexts */
4125                 sc->sc_hw.devs[index].context_num = 0;
4126
4127                 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4128
4129                 xhci_configure_mask(udev, 3, 0);
4130
4131                 err = xhci_configure_device(udev);
4132                 if (err != 0) {
4133                         DPRINTF("Could not configure device "
4134                             "at slot %u.\n", index);
4135                 }
4136
4137                 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4138                 if (err != 0) {
4139                         DPRINTF("Could not evaluate device "
4140                             "context at slot %u.\n", index);
4141                 }
4142                 break;
4143
4144         default:
4145                 break;
4146         }
4147         XHCI_CMD_UNLOCK(sc);
4148 }
4149
4150 struct usb_bus_methods xhci_bus_methods = {
4151         .endpoint_init = xhci_ep_init,
4152         .endpoint_uninit = xhci_ep_uninit,
4153         .xfer_setup = xhci_xfer_setup,
4154         .xfer_unsetup = xhci_xfer_unsetup,
4155         .get_dma_delay = xhci_get_dma_delay,
4156         .device_init = xhci_device_init,
4157         .device_uninit = xhci_device_uninit,
4158         .device_resume = xhci_device_resume,
4159         .device_suspend = xhci_device_suspend,
4160         .set_hw_power = xhci_set_hw_power,
4161         .roothub_exec = xhci_roothub_exec,
4162         .xfer_poll = xhci_do_poll,
4163         .start_dma_delay = xhci_start_dma_delay,
4164         .set_address = xhci_set_address,
4165         .clear_stall = xhci_ep_clear_stall,
4166         .device_state_change = xhci_device_state_change,
4167         .set_hw_power_sleep = xhci_set_hw_power_sleep,
4168 };