sys/dev/usb/controller/xhci.c

   1 /*-
   2  * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  */
  25
  26 /*
  27  * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
  28  *
  29  * The XHCI 1.0 spec can be found at
  30  * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
  31  * and the USB 3.0 spec at
  32  * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
  33  */
  34
  35 /*
  36  * A few words about the design implementation: This driver emulates
  37  * the concept about TDs which is found in EHCI specification. This
  38  * way we avoid too much diveration among USB drivers.
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include <sys/stdint.h>
  45 #include <sys/stddef.h>
  46 #include <sys/param.h>
  47 #include <sys/queue.h>
  48 #include <sys/types.h>
  49 #include <sys/systm.h>
  50 #include <sys/kernel.h>
  51 #include <sys/bus.h>
  52 #include <sys/module.h>
  53 #include <sys/lock.h>
  54 #include <sys/mutex.h>
  55 #include <sys/condvar.h>
  56 #include <sys/sysctl.h>
  57 #include <sys/sx.h>
  58 #include <sys/unistd.h>
  59 #include <sys/callout.h>
  60 #include <sys/malloc.h>
  61 #include <sys/priv.h>
  62
  63 #include <dev/usb/usb.h>
  64 #include <dev/usb/usbdi.h>
  65
  66 #define USB_DEBUG_VAR xhcidebug
  67
  68 #include <dev/usb/usb_core.h>
  69 #include <dev/usb/usb_debug.h>
  70 #include <dev/usb/usb_busdma.h>
  71 #include <dev/usb/usb_process.h>
  72 #include <dev/usb/usb_transfer.h>
  73 #include <dev/usb/usb_device.h>
  74 #include <dev/usb/usb_hub.h>
  75 #include <dev/usb/usb_util.h>
  76
  77 #include <dev/usb/usb_controller.h>
  78 #include <dev/usb/usb_bus.h>
  79 #include <dev/usb/controller/xhci.h>
  80 #include <dev/usb/controller/xhcireg.h>
  81
  82 #define XHCI_BUS2SC(bus) \
  83    ((struct xhci_softc *)(((uint8_t *)(bus)) - \
  84     ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
  85
  86 #ifdef USB_DEBUG
  87 static int xhcidebug;
  88 static int xhciroute;
  89
  90 SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
  91 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
  92     &xhcidebug, 0, "Debug level");
  93 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
  94 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN,
  95     &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller");
  96 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
  97 #else
  98 #define xhciroute 0
  99 #endif
 100
 101 #define XHCI_INTR_ENDPT 1
 102
 103 struct xhci_std_temp {
 104         struct xhci_softc       *sc;
 105         struct usb_page_cache   *pc;
 106         struct xhci_td          *td;
 107         struct xhci_td          *td_next;
 108         uint32_t                len;
 109         uint32_t                offset;
 110         uint32_t                max_packet_size;
 111         uint32_t                average;
 112         uint16_t                isoc_delta;
 113         uint16_t                isoc_frame;
 114         uint8_t                 shortpkt;
 115         uint8_t                 multishort;
 116         uint8_t                 last_frame;
 117         uint8_t                 trb_type;
 118         uint8_t                 direction;
 119         uint8_t                 tbc;
 120         uint8_t                 tlbpc;
 121         uint8_t                 step_td;
 122         uint8_t                 do_isoc_sync;
 123 };
 124
 125 static void     xhci_do_poll(struct usb_bus *);
 126 static void     xhci_device_done(struct usb_xfer *, usb_error_t);
 127 static void     xhci_root_intr(struct xhci_softc *);
 128 static void     xhci_free_device_ext(struct usb_device *);
 129 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
 130                     struct usb_endpoint_descriptor *);
 131 static usb_proc_callback_t xhci_configure_msg;
 132 static usb_error_t xhci_configure_device(struct usb_device *);
 133 static usb_error_t xhci_configure_endpoint(struct usb_device *,
 134                     struct usb_endpoint_descriptor *, uint64_t, uint16_t,
 135                     uint8_t, uint8_t, uint8_t, uint16_t, uint16_t);
 136 static usb_error_t xhci_configure_mask(struct usb_device *,
 137                     uint32_t, uint8_t);
 138 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
 139                     uint64_t, uint8_t);
 140 static void xhci_endpoint_doorbell(struct usb_xfer *);
 141 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
 142 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
 143 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
 144 #ifdef USB_DEBUG
 145 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
 146 #endif
 147
 148 extern struct usb_bus_methods xhci_bus_methods;
 149
 150 #ifdef USB_DEBUG
 151 static void
 152 xhci_dump_trb(struct xhci_trb *trb)
 153 {
 154         DPRINTFN(5, "trb = %p\n", trb);
 155         DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
 156         DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
 157         DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
 158 }
 159
 160 static void
 161 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
 162 {
 163         DPRINTFN(5, "pep = %p\n", pep);
 164         DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
 165         DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
 166         DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
 167         DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
 168         DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
 169         DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
 170         DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
 171 }
 172
 173 static void
 174 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
 175 {
 176         DPRINTFN(5, "psl = %p\n", psl);
 177         DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
 178         DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
 179         DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
 180         DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
 181 }
 182 #endif
 183
 184 static void
 185 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
 186 {
 187         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 188         uint8_t i;
 189
 190         cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
 191            sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
 192
 193         cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
 194            sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
 195
 196         for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) {
 197                 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
 198                     XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
 199         }
 200 }
 201
 202 static void
 203 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
 204 {
 205         if (sc->sc_ctx_is_64_byte) {
 206                 uint32_t offset;
 207                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 208                 /* all contexts are initially 32-bytes */
 209                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 210                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 211         }
 212         *ptr = htole32(val);
 213 }
 214
 215 static uint32_t
 216 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
 217 {
 218         if (sc->sc_ctx_is_64_byte) {
 219                 uint32_t offset;
 220                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 221                 /* all contexts are initially 32-bytes */
 222                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 223                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 224         }
 225         return (le32toh(*ptr));
 226 }
 227
 228 static void
 229 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
 230 {
 231         if (sc->sc_ctx_is_64_byte) {
 232                 uint32_t offset;
 233                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 234                 /* all contexts are initially 32-bytes */
 235                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 236                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 237         }
 238         *ptr = htole64(val);
 239 }
 240
 241 #ifdef USB_DEBUG
 242 static uint64_t
 243 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
 244 {
 245         if (sc->sc_ctx_is_64_byte) {
 246                 uint32_t offset;
 247                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 248                 /* all contexts are initially 32-bytes */
 249                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 250                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 251         }
 252         return (le64toh(*ptr));
 253 }
 254 #endif
 255
 256 static int
 257 xhci_reset_command_queue_locked(struct xhci_softc *sc)
 258 {
 259         struct usb_page_search buf_res;
 260         struct xhci_hw_root *phwr;
 261         uint64_t addr;
 262         uint32_t temp;
 263
 264         DPRINTF("\n");
 265
 266         temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 267         if (temp & XHCI_CRCR_LO_CRR) {
 268                 DPRINTF("Command ring running\n");
 269                 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
 270
 271                 /*
 272                  * Try to abort the last command as per section
 273                  * 4.6.1.2 "Aborting a Command" of the XHCI
 274                  * specification:
 275                  */
 276
 277                 /* stop and cancel */
 278                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
 279                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 280
 281                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
 282                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 283
 284                 /* wait 250ms */
 285                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
 286
 287                 /* check if command ring is still running */
 288                 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 289                 if (temp & XHCI_CRCR_LO_CRR) {
 290                         DPRINTF("Comand ring still running\n");
 291                         return (USB_ERR_IOERROR);
 292                 }
 293         }
 294
 295         /* reset command ring */
 296         sc->sc_command_ccs = 1;
 297         sc->sc_command_idx = 0;
 298
 299         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 300
 301         /* setup command ring control base address */
 302         addr = buf_res.physaddr;
 303         phwr = buf_res.buffer;
 304         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 305
 306         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 307
 308         memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
 309         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 310
 311         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
 312
 313         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 314         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 315
 316         return (0);
 317 }
 318
 319 usb_error_t
 320 xhci_start_controller(struct xhci_softc *sc)
 321 {
 322         struct usb_page_search buf_res;
 323         struct xhci_hw_root *phwr;
 324         struct xhci_dev_ctx_addr *pdctxa;
 325         uint64_t addr;
 326         uint32_t temp;
 327         uint16_t i;
 328
 329         DPRINTF("\n");
 330
 331         sc->sc_capa_off = 0;
 332         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 333         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
 334         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 335
 336         DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
 337         DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
 338         DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
 339
 340         sc->sc_event_ccs = 1;
 341         sc->sc_event_idx = 0;
 342         sc->sc_command_ccs = 1;
 343         sc->sc_command_idx = 0;
 344
 345         DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
 346
 347         temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
 348
 349         DPRINTF("HCS0 = 0x%08x\n", temp);
 350
 351         if (XHCI_HCS0_CSZ(temp)) {
 352                 sc->sc_ctx_is_64_byte = 1;
 353                 device_printf(sc->sc_bus.parent, "64 byte context size.\n");
 354         } else {
 355                 sc->sc_ctx_is_64_byte = 0;
 356                 device_printf(sc->sc_bus.parent, "32 byte context size.\n");
 357         }
 358
 359         /* Reset controller */
 360         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
 361
 362         for (i = 0; i != 100; i++) {
 363                 usb_pause_mtx(NULL, hz / 100);
 364                 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
 365                     (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
 366                 if (!temp)
 367                         break;
 368         }
 369
 370         if (temp) {
 371                 device_printf(sc->sc_bus.parent, "Controller "
 372                     "reset timeout.\n");
 373                 return (USB_ERR_IOERROR);
 374         }
 375
 376         if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
 377                 device_printf(sc->sc_bus.parent, "Controller does "
 378                     "not support 4K page size.\n");
 379                 return (USB_ERR_IOERROR);
 380         }
 381
 382         temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
 383
 384         i = XHCI_HCS1_N_PORTS(temp);
 385
 386         if (i == 0) {
 387                 device_printf(sc->sc_bus.parent, "Invalid number "
 388                     "of ports: %u\n", i);
 389                 return (USB_ERR_IOERROR);
 390         }
 391
 392         sc->sc_noport = i;
 393         sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
 394
 395         if (sc->sc_noslot > XHCI_MAX_DEVICES)
 396                 sc->sc_noslot = XHCI_MAX_DEVICES;
 397
 398         /* setup number of device slots */
 399
 400         DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
 401             XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
 402
 403         XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
 404
 405         DPRINTF("Max slots: %u\n", sc->sc_noslot);
 406
 407         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 408
 409         sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
 410
 411         if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
 412                 device_printf(sc->sc_bus.parent, "XHCI request "
 413                     "too many scratchpads\n");
 414                 return (USB_ERR_NOMEM);
 415         }
 416
 417         DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
 418
 419         temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
 420
 421         sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
 422             XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
 423
 424         temp = XREAD4(sc, oper, XHCI_USBSTS);
 425
 426         /* clear interrupts */
 427         XWRITE4(sc, oper, XHCI_USBSTS, temp);
 428         /* disable all device notifications */
 429         XWRITE4(sc, oper, XHCI_DNCTRL, 0);
 430
 431         /* setup device context base address */
 432         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
 433         pdctxa = buf_res.buffer;
 434         memset(pdctxa, 0, sizeof(*pdctxa));
 435
 436         addr = buf_res.physaddr;
 437         addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
 438
 439         /* slot 0 points to the table of scratchpad pointers */
 440         pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
 441
 442         for (i = 0; i != sc->sc_noscratch; i++) {
 443                 struct usb_page_search buf_scp;
 444                 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
 445                 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
 446         }
 447
 448         addr = buf_res.physaddr;
 449
 450         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 451         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 452         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 453         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 454
 455         /* Setup event table size */
 456
 457         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 458
 459         DPRINTF("HCS2=0x%08x\n", temp);
 460
 461         temp = XHCI_HCS2_ERST_MAX(temp);
 462         temp = 1U << temp;
 463         if (temp > XHCI_MAX_RSEG)
 464                 temp = XHCI_MAX_RSEG;
 465
 466         sc->sc_erst_max = temp;
 467
 468         DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
 469             XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp);
 470
 471         XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp));
 472
 473         /* Check if we should use the default IMOD value */
 474         if (sc->sc_imod_default == 0)
 475                 sc->sc_imod_default = XHCI_IMOD_DEFAULT;
 476
 477         /* Setup interrupt rate */
 478         XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default);
 479
 480         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 481
 482         phwr = buf_res.buffer;
 483         addr = buf_res.physaddr;
 484         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
 485
 486         /* reset hardware root structure */
 487         memset(phwr, 0, sizeof(*phwr));
 488
 489         phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
 490         phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
 491
 492         DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
 493
 494         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
 495         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
 496
 497         addr = (uint64_t)buf_res.physaddr;
 498
 499         DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
 500
 501         XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
 502         XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
 503
 504         /* Setup interrupter registers */
 505
 506         temp = XREAD4(sc, runt, XHCI_IMAN(0));
 507         temp |= XHCI_IMAN_INTR_ENA;
 508         XWRITE4(sc, runt, XHCI_IMAN(0), temp);
 509
 510         /* setup command ring control base address */
 511         addr = buf_res.physaddr;
 512         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 513
 514         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 515
 516         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 517         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 518
 519         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 520
 521         usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 522
 523         /* Go! */
 524         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
 525             XHCI_CMD_INTE | XHCI_CMD_HSEE);
 526
 527         for (i = 0; i != 100; i++) {
 528                 usb_pause_mtx(NULL, hz / 100);
 529                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 530                 if (!temp)
 531                         break;
 532         }
 533         if (temp) {
 534                 XWRITE4(sc, oper, XHCI_USBCMD, 0);
 535                 device_printf(sc->sc_bus.parent, "Run timeout.\n");
 536                 return (USB_ERR_IOERROR);
 537         }
 538
 539         /* catch any lost interrupts */
 540         xhci_do_poll(&sc->sc_bus);
 541
 542         if (sc->sc_port_route != NULL) {
 543                 /* Route all ports to the XHCI by default */
 544                 sc->sc_port_route(sc->sc_bus.parent,
 545                     ~xhciroute, xhciroute);
 546         }
 547         return (0);
 548 }
 549
 550 usb_error_t
 551 xhci_halt_controller(struct xhci_softc *sc)
 552 {
 553         uint32_t temp;
 554         uint16_t i;
 555
 556         DPRINTF("\n");
 557
 558         sc->sc_capa_off = 0;
 559         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 560         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
 561         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 562
 563         /* Halt controller */
 564         XWRITE4(sc, oper, XHCI_USBCMD, 0);
 565
 566         for (i = 0; i != 100; i++) {
 567                 usb_pause_mtx(NULL, hz / 100);
 568                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 569                 if (temp)
 570                         break;
 571         }
 572
 573         if (!temp) {
 574                 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
 575                 return (USB_ERR_IOERROR);
 576         }
 577         return (0);
 578 }
 579
 580 usb_error_t
 581 xhci_init(struct xhci_softc *sc, device_t self)
 582 {
 583         /* initialise some bus fields */
 584         sc->sc_bus.parent = self;
 585
 586         /* set the bus revision */
 587         sc->sc_bus.usbrev = USB_REV_3_0;
 588
 589         /* set up the bus struct */
 590         sc->sc_bus.methods = &xhci_bus_methods;
 591
 592         /* setup devices array */
 593         sc->sc_bus.devices = sc->sc_devices;
 594         sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
 595
 596         /* setup command queue mutex and condition varible */
 597         cv_init(&sc->sc_cmd_cv, "CMDQ");
 598         sx_init(&sc->sc_cmd_sx, "CMDQ lock");
 599
 600         /* get all DMA memory */
 601         if (usb_bus_mem_alloc_all(&sc->sc_bus,
 602             USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
 603                 return (ENOMEM);
 604         }
 605
 606         sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
 607         sc->sc_config_msg[0].bus = &sc->sc_bus;
 608         sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
 609         sc->sc_config_msg[1].bus = &sc->sc_bus;
 610
 611         if (usb_proc_create(&sc->sc_config_proc,
 612             &sc->sc_bus.bus_mtx, device_get_nameunit(self), USB_PRI_MED)) {
 613                 printf("WARNING: Creation of XHCI configure "
 614                     "callback process failed.\n");
 615         }
 616         return (0);
 617 }
 618
 619 void
 620 xhci_uninit(struct xhci_softc *sc)
 621 {
 622         usb_proc_free(&sc->sc_config_proc);
 623
 624         usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 625
 626         cv_destroy(&sc->sc_cmd_cv);
 627         sx_destroy(&sc->sc_cmd_sx);
 628 }
 629
 630 static void
 631 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
 632 {
 633         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 634
 635         switch (state) {
 636         case USB_HW_POWER_SUSPEND:
 637                 DPRINTF("Stopping the XHCI\n");
 638                 xhci_halt_controller(sc);
 639                 break;
 640         case USB_HW_POWER_SHUTDOWN:
 641                 DPRINTF("Stopping the XHCI\n");
 642                 xhci_halt_controller(sc);
 643                 break;
 644         case USB_HW_POWER_RESUME:
 645                 DPRINTF("Starting the XHCI\n");
 646                 xhci_start_controller(sc);
 647                 break;
 648         default:
 649                 break;
 650         }
 651 }
 652
 653 static usb_error_t
 654 xhci_generic_done_sub(struct usb_xfer *xfer)
 655 {
 656         struct xhci_td *td;
 657         struct xhci_td *td_alt_next;
 658         uint32_t len;
 659         uint8_t status;
 660
 661         td = xfer->td_transfer_cache;
 662         td_alt_next = td->alt_next;
 663
 664         if (xfer->aframes != xfer->nframes)
 665                 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
 666
 667         while (1) {
 668
 669                 usb_pc_cpu_invalidate(td->page_cache);
 670
 671                 status = td->status;
 672                 len = td->remainder;
 673
 674                 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
 675                     xfer, (unsigned int)xfer->aframes,
 676                     (unsigned int)xfer->nframes,
 677                     (unsigned int)len, (unsigned int)td->len,
 678                     (unsigned int)status);
 679
 680                 /*
 681                  * Verify the status length and
 682                  * add the length to "frlengths[]":
 683                  */
 684                 if (len > td->len) {
 685                         /* should not happen */
 686                         DPRINTF("Invalid status length, "
 687                             "0x%04x/0x%04x bytes\n", len, td->len);
 688                         status = XHCI_TRB_ERROR_LENGTH;
 689                 } else if (xfer->aframes != xfer->nframes) {
 690                         xfer->frlengths[xfer->aframes] += td->len - len;
 691                 }
 692                 /* Check for last transfer */
 693                 if (((void *)td) == xfer->td_transfer_last) {
 694                         td = NULL;
 695                         break;
 696                 }
 697                 /* Check for transfer error */
 698                 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
 699                     status != XHCI_TRB_ERROR_SUCCESS) {
 700                         /* the transfer is finished */
 701                         td = NULL;
 702                         break;
 703                 }
 704                 /* Check for short transfer */
 705                 if (len > 0) {
 706                         if (xfer->flags_int.short_frames_ok ||
 707                             xfer->flags_int.isochronous_xfr ||
 708                             xfer->flags_int.control_xfr) {
 709                                 /* follow alt next */
 710                                 td = td->alt_next;
 711                         } else {
 712                                 /* the transfer is finished */
 713                                 td = NULL;
 714                         }
 715                         break;
 716                 }
 717                 td = td->obj_next;
 718
 719                 if (td->alt_next != td_alt_next) {
 720                         /* this USB frame is complete */
 721                         break;
 722                 }
 723         }
 724
 725         /* update transfer cache */
 726
 727         xfer->td_transfer_cache = td;
 728
 729         return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
 730             (status != XHCI_TRB_ERROR_SHORT_PKT &&
 731             status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
 732             USB_ERR_NORMAL_COMPLETION);
 733 }
 734
 735 static void
 736 xhci_generic_done(struct usb_xfer *xfer)
 737 {
 738         usb_error_t err = 0;
 739
 740         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
 741             xfer, xfer->endpoint);
 742
 743         /* reset scanner */
 744
 745         xfer->td_transfer_cache = xfer->td_transfer_first;
 746
 747         if (xfer->flags_int.control_xfr) {
 748
 749                 if (xfer->flags_int.control_hdr)
 750                         err = xhci_generic_done_sub(xfer);
 751
 752                 xfer->aframes = 1;
 753
 754                 if (xfer->td_transfer_cache == NULL)
 755                         goto done;
 756         }
 757
 758         while (xfer->aframes != xfer->nframes) {
 759
 760                 err = xhci_generic_done_sub(xfer);
 761                 xfer->aframes++;
 762
 763                 if (xfer->td_transfer_cache == NULL)
 764                         goto done;
 765         }
 766
 767         if (xfer->flags_int.control_xfr &&
 768             !xfer->flags_int.control_act)
 769                 err = xhci_generic_done_sub(xfer);
 770 done:
 771         /* transfer is complete */
 772         xhci_device_done(xfer, err);
 773 }
 774
 775 static void
 776 xhci_activate_transfer(struct usb_xfer *xfer)
 777 {
 778         struct xhci_td *td;
 779
 780         td = xfer->td_transfer_cache;
 781
 782         usb_pc_cpu_invalidate(td->page_cache);
 783
 784         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 785
 786                 /* activate the transfer */
 787
 788                 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
 789                 usb_pc_cpu_flush(td->page_cache);
 790
 791                 xhci_endpoint_doorbell(xfer);
 792         }
 793 }
 794
 795 static void
 796 xhci_skip_transfer(struct usb_xfer *xfer)
 797 {
 798         struct xhci_td *td;
 799         struct xhci_td *td_last;
 800
 801         td = xfer->td_transfer_cache;
 802         td_last = xfer->td_transfer_last;
 803
 804         td = td->alt_next;
 805
 806         usb_pc_cpu_invalidate(td->page_cache);
 807
 808         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 809
 810                 usb_pc_cpu_invalidate(td_last->page_cache);
 811
 812                 /* copy LINK TRB to current waiting location */
 813
 814                 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
 815                 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
 816                 usb_pc_cpu_flush(td->page_cache);
 817
 818                 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
 819                 usb_pc_cpu_flush(td->page_cache);
 820
 821                 xhci_endpoint_doorbell(xfer);
 822         }
 823 }
 824
 825 /*------------------------------------------------------------------------*
 826  *      xhci_check_transfer
 827  *------------------------------------------------------------------------*/
 828 static void
 829 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
 830 {
 831         int64_t offset;
 832         uint64_t td_event;
 833         uint32_t temp;
 834         uint32_t remainder;
 835         uint8_t status;
 836         uint8_t halted;
 837         uint8_t epno;
 838         uint8_t index;
 839         uint8_t i;
 840
 841         /* decode TRB */
 842         td_event = le64toh(trb->qwTrb0);
 843         temp = le32toh(trb->dwTrb2);
 844
 845         remainder = XHCI_TRB_2_REM_GET(temp);
 846         status = XHCI_TRB_2_ERROR_GET(temp);
 847
 848         temp = le32toh(trb->dwTrb3);
 849         epno = XHCI_TRB_3_EP_GET(temp);
 850         index = XHCI_TRB_3_SLOT_GET(temp);
 851
 852         /* check if error means halted */
 853         halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
 854             status != XHCI_TRB_ERROR_SUCCESS);
 855
 856         DPRINTF("slot=%u epno=%u remainder=%u status=%u\n",
 857             index, epno, remainder, status);
 858
 859         if (index > sc->sc_noslot) {
 860                 DPRINTF("Invalid slot.\n");
 861                 return;
 862         }
 863
 864         if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
 865                 DPRINTF("Invalid endpoint.\n");
 866                 return;
 867         }
 868
 869         /* try to find the USB transfer that generated the event */
 870         for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
 871                 struct usb_xfer *xfer;
 872                 struct xhci_td *td;
 873                 struct xhci_endpoint_ext *pepext;
 874
 875                 pepext = &sc->sc_hw.devs[index].endp[epno];
 876
 877                 xfer = pepext->xfer[i];
 878                 if (xfer == NULL)
 879                         continue;
 880
 881                 td = xfer->td_transfer_cache;
 882
 883                 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
 884                         (long long)td_event,
 885                         (long long)td->td_self,
 886                         (long long)td->td_self + sizeof(td->td_trb));
 887
 888                 /*
 889                  * NOTE: Some XHCI implementations might not trigger
 890                  * an event on the last LINK TRB so we need to
 891                  * consider both the last and second last event
 892                  * address as conditions for a successful transfer.
 893                  *
 894                  * NOTE: We assume that the XHCI will only trigger one
 895                  * event per chain of TRBs.
 896                  */
 897
 898                 offset = td_event - td->td_self;
 899
 900                 if (offset >= 0 &&
 901                     offset < (int64_t)sizeof(td->td_trb)) {
 902
 903                         usb_pc_cpu_invalidate(td->page_cache);
 904
 905                         /* compute rest of remainder, if any */
 906                         for (i = (offset / 16) + 1; i < td->ntrb; i++) {
 907                                 temp = le32toh(td->td_trb[i].dwTrb2);
 908                                 remainder += XHCI_TRB_2_BYTES_GET(temp);
 909                         }
 910
 911                         DPRINTFN(5, "New remainder: %u\n", remainder);
 912
 913                         /* clear isochronous transfer errors */
 914                         if (xfer->flags_int.isochronous_xfr) {
 915                                 if (halted) {
 916                                         halted = 0;
 917                                         status = XHCI_TRB_ERROR_SUCCESS;
 918                                         remainder = td->len;
 919                                 }
 920                         }
 921
 922                         /* "td->remainder" is verified later */
 923                         td->remainder = remainder;
 924                         td->status = status;
 925
 926                         usb_pc_cpu_flush(td->page_cache);
 927
 928                         /*
 929                          * 1) Last transfer descriptor makes the
 930                          * transfer done
 931                          */
 932                         if (((void *)td) == xfer->td_transfer_last) {
 933                                 DPRINTF("TD is last\n");
 934                                 xhci_generic_done(xfer);
 935                                 break;
 936                         }
 937
 938                         /*
 939                          * 2) Any kind of error makes the transfer
 940                          * done
 941                          */
 942                         if (halted) {
 943                                 DPRINTF("TD has I/O error\n");
 944                                 xhci_generic_done(xfer);
 945                                 break;
 946                         }
 947
 948                         /*
 949                          * 3) If there is no alternate next transfer,
 950                          * a short packet also makes the transfer done
 951                          */
 952                         if (td->remainder > 0) {
 953                                 if (td->alt_next == NULL) {
 954                                         DPRINTF(
 955                                             "short TD has no alternate next\n");
 956                                         xhci_generic_done(xfer);
 957                                         break;
 958                                 }
 959                                 DPRINTF("TD has short pkt\n");
 960                                 if (xfer->flags_int.short_frames_ok ||
 961                                     xfer->flags_int.isochronous_xfr ||
 962                                     xfer->flags_int.control_xfr) {
 963                                         /* follow the alt next */
 964                                         xfer->td_transfer_cache = td->alt_next;
 965                                         xhci_activate_transfer(xfer);
 966                                         break;
 967                                 }
 968                                 xhci_skip_transfer(xfer);
 969                                 xhci_generic_done(xfer);
 970                                 break;
 971                         }
 972
 973                         /*
 974                          * 4) Transfer complete - go to next TD
 975                          */
 976                         DPRINTF("Following next TD\n");
 977                         xfer->td_transfer_cache = td->obj_next;
 978                         xhci_activate_transfer(xfer);
 979                         break;          /* there should only be one match */
 980                 }
 981         }
 982 }
 983
 984 static int
 985 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
 986 {
 987         if (sc->sc_cmd_addr == trb->qwTrb0) {
 988                 DPRINTF("Received command event\n");
 989                 sc->sc_cmd_result[0] = trb->dwTrb2;
 990                 sc->sc_cmd_result[1] = trb->dwTrb3;
 991                 cv_signal(&sc->sc_cmd_cv);
 992                 return (1);     /* command match */
 993         }
 994         return (0);
 995 }
 996
 997 static int
 998 xhci_interrupt_poll(struct xhci_softc *sc)
 999 {
1000         struct usb_page_search buf_res;
1001         struct xhci_hw_root *phwr;
1002         uint64_t addr;
1003         uint32_t temp;
1004         int retval = 0;
1005         uint16_t i;
1006         uint8_t event;
1007         uint8_t j;
1008         uint8_t k;
1009         uint8_t t;
1010
1011         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1012
1013         phwr = buf_res.buffer;
1014
1015         /* Receive any events */
1016
1017         usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1018
1019         i = sc->sc_event_idx;
1020         j = sc->sc_event_ccs;
1021         t = 2;
1022
1023         while (1) {
1024
1025                 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1026
1027                 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1028
1029                 if (j != k)
1030                         break;
1031
1032                 event = XHCI_TRB_3_TYPE_GET(temp);
1033
1034                 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1035                     i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1036                     (long)le32toh(phwr->hwr_events[i].dwTrb2),
1037                     (long)le32toh(phwr->hwr_events[i].dwTrb3));
1038
1039                 switch (event) {
1040                 case XHCI_TRB_EVENT_TRANSFER:
1041                         xhci_check_transfer(sc, &phwr->hwr_events[i]);
1042                         break;
1043                 case XHCI_TRB_EVENT_CMD_COMPLETE:
1044                         retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1045                         break;
1046                 default:
1047                         DPRINTF("Unhandled event = %u\n", event);
1048                         break;
1049                 }
1050
1051                 i++;
1052
1053                 if (i == XHCI_MAX_EVENTS) {
1054                         i = 0;
1055                         j ^= 1;
1056
1057                         /* check for timeout */
1058                         if (!--t)
1059                                 break;
1060                 }
1061         }
1062
1063         sc->sc_event_idx = i;
1064         sc->sc_event_ccs = j;
1065
1066         /*
1067          * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1068          * latched. That means to activate the register we need to
1069          * write both the low and high double word of the 64-bit
1070          * register.
1071          */
1072
1073         addr = (uint32_t)buf_res.physaddr;
1074         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1075
1076         /* try to clear busy bit */
1077         addr |= XHCI_ERDP_LO_BUSY;
1078
1079         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1080         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1081
1082         return (retval);
1083 }
1084
1085 static usb_error_t
1086 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1087     uint16_t timeout_ms)
1088 {
1089         struct usb_page_search buf_res;
1090         struct xhci_hw_root *phwr;
1091         uint64_t addr;
1092         uint32_t temp;
1093         uint8_t i;
1094         uint8_t j;
1095         uint8_t timeout = 0;
1096         int err;
1097
1098         XHCI_CMD_ASSERT_LOCKED(sc);
1099
1100         /* get hardware root structure */
1101
1102         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1103
1104         phwr = buf_res.buffer;
1105
1106         /* Queue command */
1107
1108         USB_BUS_LOCK(&sc->sc_bus);
1109 retry:
1110         i = sc->sc_command_idx;
1111         j = sc->sc_command_ccs;
1112
1113         DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1114             i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1115             (long long)le64toh(trb->qwTrb0),
1116             (long)le32toh(trb->dwTrb2),
1117             (long)le32toh(trb->dwTrb3));
1118
1119         phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1120         phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1121
1122         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1123
1124         temp = trb->dwTrb3;
1125
1126         if (j)
1127                 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1128         else
1129                 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1130
1131         temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1132
1133         phwr->hwr_commands[i].dwTrb3 = temp;
1134
1135         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1136
1137         addr = buf_res.physaddr;
1138         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1139
1140         sc->sc_cmd_addr = htole64(addr);
1141
1142         i++;
1143
1144         if (i == (XHCI_MAX_COMMANDS - 1)) {
1145
1146                 if (j) {
1147                         temp = htole32(XHCI_TRB_3_TC_BIT |
1148                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1149                             XHCI_TRB_3_CYCLE_BIT);
1150                 } else {
1151                         temp = htole32(XHCI_TRB_3_TC_BIT |
1152                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1153                 }
1154
1155                 phwr->hwr_commands[i].dwTrb3 = temp;
1156
1157                 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1158
1159                 i = 0;
1160                 j ^= 1;
1161         }
1162
1163         sc->sc_command_idx = i;
1164         sc->sc_command_ccs = j;
1165
1166         XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1167
1168         err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1169             USB_MS_TO_TICKS(timeout_ms));
1170
1171         /*
1172          * In some error cases event interrupts are not generated.
1173          * Poll one time to see if the command has completed.
1174          */
1175         if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1176                 DPRINTF("Command was completed when polling\n");
1177                 err = 0;
1178         }
1179         if (err != 0) {
1180                 DPRINTF("Command timeout!\n");
1181                 /*
1182                  * After some weeks of continuous operation, it has
1183                  * been observed that the ASMedia Technology, ASM1042
1184                  * SuperSpeed USB Host Controller can suddenly stop
1185                  * accepting commands via the command queue. Try to
1186                  * first reset the command queue. If that fails do a
1187                  * host controller reset.
1188                  */
1189                 if (timeout == 0 &&
1190                     xhci_reset_command_queue_locked(sc) == 0) {
1191                         temp = le32toh(trb->dwTrb3);
1192
1193                         /*
1194                          * Avoid infinite XHCI reset loops if the set
1195                          * address command fails to respond due to a
1196                          * non-enumerating device:
1197                          */
1198                         if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE &&
1199                             (temp & XHCI_TRB_3_BSR_BIT) == 0) {
1200                                 DPRINTF("Set address timeout\n");
1201                         } else {
1202                                 timeout = 1;
1203                                 goto retry;
1204                         }
1205                 } else {
1206                         DPRINTF("Controller reset!\n");
1207                         usb_bus_reset_async_locked(&sc->sc_bus);
1208                 }
1209                 err = USB_ERR_TIMEOUT;
1210                 trb->dwTrb2 = 0;
1211                 trb->dwTrb3 = 0;
1212         } else {
1213                 temp = le32toh(sc->sc_cmd_result[0]);
1214                 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1215                         err = USB_ERR_IOERROR;
1216
1217                 trb->dwTrb2 = sc->sc_cmd_result[0];
1218                 trb->dwTrb3 = sc->sc_cmd_result[1];
1219         }
1220
1221         USB_BUS_UNLOCK(&sc->sc_bus);
1222
1223         return (err);
1224 }
1225
1226 #if 0
1227 static usb_error_t
1228 xhci_cmd_nop(struct xhci_softc *sc)
1229 {
1230         struct xhci_trb trb;
1231         uint32_t temp;
1232
1233         DPRINTF("\n");
1234
1235         trb.qwTrb0 = 0;
1236         trb.dwTrb2 = 0;
1237         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1238
1239         trb.dwTrb3 = htole32(temp);
1240
1241         return (xhci_do_command(sc, &trb, 100 /* ms */));
1242 }
1243 #endif
1244
1245 static usb_error_t
1246 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1247 {
1248         struct xhci_trb trb;
1249         uint32_t temp;
1250         usb_error_t err;
1251
1252         DPRINTF("\n");
1253
1254         trb.qwTrb0 = 0;
1255         trb.dwTrb2 = 0;
1256         trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1257
1258         err = xhci_do_command(sc, &trb, 100 /* ms */);
1259         if (err)
1260                 goto done;
1261
1262         temp = le32toh(trb.dwTrb3);
1263
1264         *pslot = XHCI_TRB_3_SLOT_GET(temp);
1265
1266 done:
1267         return (err);
1268 }
1269
1270 static usb_error_t
1271 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1272 {
1273         struct xhci_trb trb;
1274         uint32_t temp;
1275
1276         DPRINTF("\n");
1277
1278         trb.qwTrb0 = 0;
1279         trb.dwTrb2 = 0;
1280         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1281             XHCI_TRB_3_SLOT_SET(slot_id);
1282
1283         trb.dwTrb3 = htole32(temp);
1284
1285         return (xhci_do_command(sc, &trb, 100 /* ms */));
1286 }
1287
1288 static usb_error_t
1289 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1290     uint8_t bsr, uint8_t slot_id)
1291 {
1292         struct xhci_trb trb;
1293         uint32_t temp;
1294
1295         DPRINTF("\n");
1296
1297         trb.qwTrb0 = htole64(input_ctx);
1298         trb.dwTrb2 = 0;
1299         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1300             XHCI_TRB_3_SLOT_SET(slot_id);
1301
1302         if (bsr)
1303                 temp |= XHCI_TRB_3_BSR_BIT;
1304
1305         trb.dwTrb3 = htole32(temp);
1306
1307         return (xhci_do_command(sc, &trb, 500 /* ms */));
1308 }
1309
1310 static usb_error_t
1311 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1312 {
1313         struct usb_page_search buf_inp;
1314         struct usb_page_search buf_dev;
1315         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1316         struct xhci_hw_dev *hdev;
1317         struct xhci_dev_ctx *pdev;
1318         struct xhci_endpoint_ext *pepext;
1319         uint32_t temp;
1320         uint16_t mps;
1321         usb_error_t err;
1322         uint8_t index;
1323
1324         /* the root HUB case is not handled here */
1325         if (udev->parent_hub == NULL)
1326                 return (USB_ERR_INVAL);
1327
1328         index = udev->controller_slot_id;
1329
1330         hdev =  &sc->sc_hw.devs[index];
1331
1332         if (mtx != NULL)
1333                 mtx_unlock(mtx);
1334
1335         XHCI_CMD_LOCK(sc);
1336
1337         switch (hdev->state) {
1338         case XHCI_ST_DEFAULT:
1339         case XHCI_ST_ENABLED:
1340
1341                 hdev->state = XHCI_ST_ENABLED;
1342
1343                 /* set configure mask to slot and EP0 */
1344                 xhci_configure_mask(udev, 3, 0);
1345
1346                 /* configure input slot context structure */
1347                 err = xhci_configure_device(udev);
1348
1349                 if (err != 0) {
1350                         DPRINTF("Could not configure device\n");
1351                         break;
1352                 }
1353
1354                 /* configure input endpoint context structure */
1355                 switch (udev->speed) {
1356                 case USB_SPEED_LOW:
1357                 case USB_SPEED_FULL:
1358                         mps = 8;
1359                         break;
1360                 case USB_SPEED_HIGH:
1361                         mps = 64;
1362                         break;
1363                 default:
1364                         mps = 512;
1365                         break;
1366                 }
1367
1368                 pepext = xhci_get_endpoint_ext(udev,
1369                     &udev->ctrl_ep_desc);
1370                 err = xhci_configure_endpoint(udev,
1371                     &udev->ctrl_ep_desc, pepext->physaddr,
1372                     0, 1, 1, 0, mps, mps);
1373
1374                 if (err != 0) {
1375                         DPRINTF("Could not configure default endpoint\n");
1376                         break;
1377                 }
1378
1379                 /* execute set address command */
1380                 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1381
1382                 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1383                     (address == 0), index);
1384
1385                 if (err != 0) {
1386                         temp = le32toh(sc->sc_cmd_result[0]);
1387                         if (address == 0 && sc->sc_port_route != NULL &&
1388                             XHCI_TRB_2_ERROR_GET(temp) ==
1389                             XHCI_TRB_ERROR_PARAMETER) {
1390                                 /* LynxPoint XHCI - ports are not switchable */
1391                                 /* Un-route all ports from the XHCI */
1392                                 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1393                         }
1394                         DPRINTF("Could not set address "
1395                             "for slot %u.\n", index);
1396                         if (address != 0)
1397                                 break;
1398                 }
1399
1400                 /* update device address to new value */
1401
1402                 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1403                 pdev = buf_dev.buffer;
1404                 usb_pc_cpu_invalidate(&hdev->device_pc);
1405
1406                 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1407                 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1408
1409                 /* update device state to new value */
1410
1411                 if (address != 0)
1412                         hdev->state = XHCI_ST_ADDRESSED;
1413                 else
1414                         hdev->state = XHCI_ST_DEFAULT;
1415                 break;
1416
1417         default:
1418                 DPRINTF("Wrong state for set address.\n");
1419                 err = USB_ERR_IOERROR;
1420                 break;
1421         }
1422         XHCI_CMD_UNLOCK(sc);
1423
1424         if (mtx != NULL)
1425                 mtx_lock(mtx);
1426
1427         return (err);
1428 }
1429
1430 static usb_error_t
1431 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1432     uint8_t deconfigure, uint8_t slot_id)
1433 {
1434         struct xhci_trb trb;
1435         uint32_t temp;
1436
1437         DPRINTF("\n");
1438
1439         trb.qwTrb0 = htole64(input_ctx);
1440         trb.dwTrb2 = 0;
1441         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1442             XHCI_TRB_3_SLOT_SET(slot_id);
1443
1444         if (deconfigure)
1445                 temp |= XHCI_TRB_3_DCEP_BIT;
1446
1447         trb.dwTrb3 = htole32(temp);
1448
1449         return (xhci_do_command(sc, &trb, 100 /* ms */));
1450 }
1451
1452 static usb_error_t
1453 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1454     uint8_t slot_id)
1455 {
1456         struct xhci_trb trb;
1457         uint32_t temp;
1458
1459         DPRINTF("\n");
1460
1461         trb.qwTrb0 = htole64(input_ctx);
1462         trb.dwTrb2 = 0;
1463         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1464             XHCI_TRB_3_SLOT_SET(slot_id);
1465         trb.dwTrb3 = htole32(temp);
1466
1467         return (xhci_do_command(sc, &trb, 100 /* ms */));
1468 }
1469
1470 static usb_error_t
1471 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1472     uint8_t ep_id, uint8_t slot_id)
1473 {
1474         struct xhci_trb trb;
1475         uint32_t temp;
1476
1477         DPRINTF("\n");
1478
1479         trb.qwTrb0 = 0;
1480         trb.dwTrb2 = 0;
1481         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1482             XHCI_TRB_3_SLOT_SET(slot_id) |
1483             XHCI_TRB_3_EP_SET(ep_id);
1484
1485         if (preserve)
1486                 temp |= XHCI_TRB_3_PRSV_BIT;
1487
1488         trb.dwTrb3 = htole32(temp);
1489
1490         return (xhci_do_command(sc, &trb, 100 /* ms */));
1491 }
1492
1493 static usb_error_t
1494 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1495     uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1496 {
1497         struct xhci_trb trb;
1498         uint32_t temp;
1499
1500         DPRINTF("\n");
1501
1502         trb.qwTrb0 = htole64(dequeue_ptr);
1503
1504         temp = XHCI_TRB_2_STREAM_SET(stream_id);
1505         trb.dwTrb2 = htole32(temp);
1506
1507         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1508             XHCI_TRB_3_SLOT_SET(slot_id) |
1509             XHCI_TRB_3_EP_SET(ep_id);
1510         trb.dwTrb3 = htole32(temp);
1511
1512         return (xhci_do_command(sc, &trb, 100 /* ms */));
1513 }
1514
1515 static usb_error_t
1516 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1517     uint8_t ep_id, uint8_t slot_id)
1518 {
1519         struct xhci_trb trb;
1520         uint32_t temp;
1521
1522         DPRINTF("\n");
1523
1524         trb.qwTrb0 = 0;
1525         trb.dwTrb2 = 0;
1526         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1527             XHCI_TRB_3_SLOT_SET(slot_id) |
1528             XHCI_TRB_3_EP_SET(ep_id);
1529
1530         if (suspend)
1531                 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1532
1533         trb.dwTrb3 = htole32(temp);
1534
1535         return (xhci_do_command(sc, &trb, 100 /* ms */));
1536 }
1537
1538 static usb_error_t
1539 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1540 {
1541         struct xhci_trb trb;
1542         uint32_t temp;
1543
1544         DPRINTF("\n");
1545
1546         trb.qwTrb0 = 0;
1547         trb.dwTrb2 = 0;
1548         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1549             XHCI_TRB_3_SLOT_SET(slot_id);
1550
1551         trb.dwTrb3 = htole32(temp);
1552
1553         return (xhci_do_command(sc, &trb, 100 /* ms */));
1554 }
1555
1556 /*------------------------------------------------------------------------*
1557  *      xhci_interrupt - XHCI interrupt handler
1558  *------------------------------------------------------------------------*/
1559 void
1560 xhci_interrupt(struct xhci_softc *sc)
1561 {
1562         uint32_t status;
1563         uint32_t temp;
1564
1565         USB_BUS_LOCK(&sc->sc_bus);
1566
1567         status = XREAD4(sc, oper, XHCI_USBSTS);
1568
1569         /* acknowledge interrupts, if any */
1570         if (status != 0) {
1571                 XWRITE4(sc, oper, XHCI_USBSTS, status);
1572                 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1573         }
1574
1575         temp = XREAD4(sc, runt, XHCI_IMAN(0));
1576
1577         /* force clearing of pending interrupts */
1578         if (temp & XHCI_IMAN_INTR_PEND)
1579                 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1580
1581         /* check for event(s) */
1582         xhci_interrupt_poll(sc);
1583
1584         if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1585             XHCI_STS_HSE | XHCI_STS_HCE)) {
1586
1587                 if (status & XHCI_STS_PCD) {
1588                         xhci_root_intr(sc);
1589                 }
1590
1591                 if (status & XHCI_STS_HCH) {
1592                         printf("%s: host controller halted\n",
1593                             __FUNCTION__);
1594                 }
1595
1596                 if (status & XHCI_STS_HSE) {
1597                         printf("%s: host system error\n",
1598                             __FUNCTION__);
1599                 }
1600
1601                 if (status & XHCI_STS_HCE) {
1602                         printf("%s: host controller error\n",
1603                            __FUNCTION__);
1604                 }
1605         }
1606         USB_BUS_UNLOCK(&sc->sc_bus);
1607 }
1608
1609 /*------------------------------------------------------------------------*
1610  *      xhci_timeout - XHCI timeout handler
1611  *------------------------------------------------------------------------*/
1612 static void
1613 xhci_timeout(void *arg)
1614 {
1615         struct usb_xfer *xfer = arg;
1616
1617         DPRINTF("xfer=%p\n", xfer);
1618
1619         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1620
1621         /* transfer is transferred */
1622         xhci_device_done(xfer, USB_ERR_TIMEOUT);
1623 }
1624
1625 static void
1626 xhci_do_poll(struct usb_bus *bus)
1627 {
1628         struct xhci_softc *sc = XHCI_BUS2SC(bus);
1629
1630         USB_BUS_LOCK(&sc->sc_bus);
1631         xhci_interrupt_poll(sc);
1632         USB_BUS_UNLOCK(&sc->sc_bus);
1633 }
1634
1635 static void
1636 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1637 {
1638         struct usb_page_search buf_res;
1639         struct xhci_td *td;
1640         struct xhci_td *td_next;
1641         struct xhci_td *td_alt_next;
1642         struct xhci_td *td_first;
1643         uint32_t buf_offset;
1644         uint32_t average;
1645         uint32_t len_old;
1646         uint32_t npkt_off;
1647         uint32_t dword;
1648         uint8_t shortpkt_old;
1649         uint8_t precompute;
1650         uint8_t x;
1651
1652         td_alt_next = NULL;
1653         buf_offset = 0;
1654         shortpkt_old = temp->shortpkt;
1655         len_old = temp->len;
1656         npkt_off = 0;
1657         precompute = 1;
1658
1659 restart:
1660
1661         td = temp->td;
1662         td_next = td_first = temp->td_next;
1663
1664         while (1) {
1665
1666                 if (temp->len == 0) {
1667
1668                         if (temp->shortpkt)
1669                                 break;
1670
1671                         /* send a Zero Length Packet, ZLP, last */
1672
1673                         temp->shortpkt = 1;
1674                         average = 0;
1675
1676                 } else {
1677
1678                         average = temp->average;
1679
1680                         if (temp->len < average) {
1681                                 if (temp->len % temp->max_packet_size) {
1682                                         temp->shortpkt = 1;
1683                                 }
1684                                 average = temp->len;
1685                         }
1686                 }
1687
1688                 if (td_next == NULL)
1689                         panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1690
1691                 /* get next TD */
1692
1693                 td = td_next;
1694                 td_next = td->obj_next;
1695
1696                 /* check if we are pre-computing */
1697
1698                 if (precompute) {
1699
1700                         /* update remaining length */
1701
1702                         temp->len -= average;
1703
1704                         continue;
1705                 }
1706                 /* fill out current TD */
1707
1708                 td->len = average;
1709                 td->remainder = 0;
1710                 td->status = 0;
1711
1712                 /* update remaining length */
1713
1714                 temp->len -= average;
1715
1716                 /* reset TRB index */
1717
1718                 x = 0;
1719
1720                 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1721                         /* immediate data */
1722
1723                         if (average > 8)
1724                                 average = 8;
1725
1726                         td->td_trb[0].qwTrb0 = 0;
1727
1728                         usbd_copy_out(temp->pc, temp->offset + buf_offset,
1729                            (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1730                            average);
1731
1732                         dword = XHCI_TRB_2_BYTES_SET(8) |
1733                             XHCI_TRB_2_TDSZ_SET(0) |
1734                             XHCI_TRB_2_IRQ_SET(0);
1735
1736                         td->td_trb[0].dwTrb2 = htole32(dword);
1737
1738                         dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1739                           XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1740
1741                         /* check wLength */
1742                         if (td->td_trb[0].qwTrb0 &
1743                            htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1744                                 if (td->td_trb[0].qwTrb0 &
1745                                     htole64(XHCI_TRB_0_DIR_IN_MASK))
1746                                         dword |= XHCI_TRB_3_TRT_IN;
1747                                 else
1748                                         dword |= XHCI_TRB_3_TRT_OUT;
1749                         }
1750
1751                         td->td_trb[0].dwTrb3 = htole32(dword);
1752 #ifdef USB_DEBUG
1753                         xhci_dump_trb(&td->td_trb[x]);
1754 #endif
1755                         x++;
1756
1757                 } else do {
1758
1759                         uint32_t npkt;
1760
1761                         /* fill out buffer pointers */
1762
1763                         if (average == 0) {
1764                                 memset(&buf_res, 0, sizeof(buf_res));
1765                         } else {
1766                                 usbd_get_page(temp->pc, temp->offset +
1767                                     buf_offset, &buf_res);
1768
1769                                 /* get length to end of page */
1770                                 if (buf_res.length > average)
1771                                         buf_res.length = average;
1772
1773                                 /* check for maximum length */
1774                                 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1775                                         buf_res.length = XHCI_TD_PAGE_SIZE;
1776
1777                                 npkt_off += buf_res.length;
1778                         }
1779
1780                         /* setup npkt */
1781                         npkt = (len_old - npkt_off + temp->max_packet_size - 1) /
1782                             temp->max_packet_size;
1783
1784                         if (npkt == 0)
1785                                 npkt = 1;
1786                         else if (npkt > 31)
1787                                 npkt = 31;
1788
1789                         /* fill out TRB's */
1790                         td->td_trb[x].qwTrb0 =
1791                             htole64((uint64_t)buf_res.physaddr);
1792
1793                         dword =
1794                           XHCI_TRB_2_BYTES_SET(buf_res.length) |
1795                           XHCI_TRB_2_TDSZ_SET(npkt) |
1796                           XHCI_TRB_2_IRQ_SET(0);
1797
1798                         td->td_trb[x].dwTrb2 = htole32(dword);
1799
1800                         switch (temp->trb_type) {
1801                         case XHCI_TRB_TYPE_ISOCH:
1802                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1803                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1804                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1805                                 if (td != td_first) {
1806                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1807                                 } else if (temp->do_isoc_sync != 0) {
1808                                         temp->do_isoc_sync = 0;
1809                                         /* wait until "isoc_frame" */
1810                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1811                                             XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1812                                 } else {
1813                                         /* start data transfer at next interval */
1814                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1815                                             XHCI_TRB_3_ISO_SIA_BIT;
1816                                 }
1817                                 if (temp->direction == UE_DIR_IN)
1818                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1819                                 break;
1820                         case XHCI_TRB_TYPE_DATA_STAGE:
1821                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1822                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) |
1823                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1824                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1825                                 if (temp->direction == UE_DIR_IN)
1826                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1827                                 break;
1828                         case XHCI_TRB_TYPE_STATUS_STAGE:
1829                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1830                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) |
1831                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1832                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1833                                 if (temp->direction == UE_DIR_IN)
1834                                         dword |= XHCI_TRB_3_DIR_IN;
1835                                 break;
1836                         default:        /* XHCI_TRB_TYPE_NORMAL */
1837                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1838                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) |
1839                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1840                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1841                                 if (temp->direction == UE_DIR_IN)
1842                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1843                                 break;
1844                         }
1845                         td->td_trb[x].dwTrb3 = htole32(dword);
1846
1847                         average -= buf_res.length;
1848                         buf_offset += buf_res.length;
1849 #ifdef USB_DEBUG
1850                         xhci_dump_trb(&td->td_trb[x]);
1851 #endif
1852                         x++;
1853
1854                 } while (average != 0);
1855
1856                 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1857
1858                 /* store number of data TRB's */
1859
1860                 td->ntrb = x;
1861
1862                 DPRINTF("NTRB=%u\n", x);
1863
1864                 /* fill out link TRB */
1865
1866                 if (td_next != NULL) {
1867                         /* link the current TD with the next one */
1868                         td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1869                         DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1870                 } else {
1871                         /* this field will get updated later */
1872                         DPRINTF("NOLINK\n");
1873                 }
1874
1875                 dword = XHCI_TRB_2_IRQ_SET(0);
1876
1877                 td->td_trb[x].dwTrb2 = htole32(dword);
1878
1879                 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1880                     XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1881                     /*
1882                      * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1883                      * frame only receives a single short packet event
1884                      * by setting the CHAIN bit in the LINK field. In
1885                      * addition some XHCI controllers have problems
1886                      * sending a ZLP unless the CHAIN-BIT is set in
1887                      * the LINK TRB.
1888                      */
1889                     XHCI_TRB_3_CHAIN_BIT;
1890
1891                 td->td_trb[x].dwTrb3 = htole32(dword);
1892
1893                 td->alt_next = td_alt_next;
1894 #ifdef USB_DEBUG
1895                 xhci_dump_trb(&td->td_trb[x]);
1896 #endif
1897                 usb_pc_cpu_flush(td->page_cache);
1898         }
1899
1900         if (precompute) {
1901                 precompute = 0;
1902
1903                 /* setup alt next pointer, if any */
1904                 if (temp->last_frame) {
1905                         td_alt_next = NULL;
1906                 } else {
1907                         /* we use this field internally */
1908                         td_alt_next = td_next;
1909                 }
1910
1911                 /* restore */
1912                 temp->shortpkt = shortpkt_old;
1913                 temp->len = len_old;
1914                 goto restart;
1915         }
1916
1917         /*
1918          * Remove cycle bit from the first TRB if we are
1919          * stepping them:
1920          */
1921         if (temp->step_td != 0) {
1922                 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1923                 usb_pc_cpu_flush(td_first->page_cache);
1924         }
1925
1926         /* clear TD SIZE to zero, hence this is the last TRB */
1927         /* remove chain bit because this is the last data TRB in the chain */
1928         td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1929         td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1930         /* remove CHAIN-BIT from last LINK TRB */
1931         td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1932
1933         usb_pc_cpu_flush(td->page_cache);
1934
1935         temp->td = td;
1936         temp->td_next = td_next;
1937 }
1938
1939 static void
1940 xhci_setup_generic_chain(struct usb_xfer *xfer)
1941 {
1942         struct xhci_std_temp temp;
1943         struct xhci_td *td;
1944         uint32_t x;
1945         uint32_t y;
1946         uint8_t mult;
1947
1948         temp.do_isoc_sync = 0;
1949         temp.step_td = 0;
1950         temp.tbc = 0;
1951         temp.tlbpc = 0;
1952         temp.average = xfer->max_hc_frame_size;
1953         temp.max_packet_size = xfer->max_packet_size;
1954         temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
1955         temp.pc = NULL;
1956         temp.last_frame = 0;
1957         temp.offset = 0;
1958         temp.multishort = xfer->flags_int.isochronous_xfr ||
1959             xfer->flags_int.control_xfr ||
1960             xfer->flags_int.short_frames_ok;
1961
1962         /* toggle the DMA set we are using */
1963         xfer->flags_int.curr_dma_set ^= 1;
1964
1965         /* get next DMA set */
1966         td = xfer->td_start[xfer->flags_int.curr_dma_set];
1967
1968         temp.td = NULL;
1969         temp.td_next = td;
1970
1971         xfer->td_transfer_first = td;
1972         xfer->td_transfer_cache = td;
1973
1974         if (xfer->flags_int.isochronous_xfr) {
1975                 uint8_t shift;
1976
1977                 /* compute multiplier for ISOCHRONOUS transfers */
1978                 mult = xfer->endpoint->ecomp ?
1979                     (xfer->endpoint->ecomp->bmAttributes & 3) : 0;
1980                 /* check for USB 2.0 multiplier */
1981                 if (mult == 0) {
1982                         mult = (xfer->endpoint->edesc->
1983                             wMaxPacketSize[1] >> 3) & 3;
1984                 }
1985                 /* range check */
1986                 if (mult > 2)
1987                         mult = 3;
1988                 else
1989                         mult++;
1990
1991                 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
1992
1993                 DPRINTF("MFINDEX=0x%08x\n", x);
1994
1995                 switch (usbd_get_speed(xfer->xroot->udev)) {
1996                 case USB_SPEED_FULL:
1997                         shift = 3;
1998                         temp.isoc_delta = 8;    /* 1ms */
1999                         x += temp.isoc_delta - 1;
2000                         x &= ~(temp.isoc_delta - 1);
2001                         break;
2002                 default:
2003                         shift = usbd_xfer_get_fps_shift(xfer);
2004                         temp.isoc_delta = 1U << shift;
2005                         x += temp.isoc_delta - 1;
2006                         x &= ~(temp.isoc_delta - 1);
2007                         /* simple frame load balancing */
2008                         x += xfer->endpoint->usb_uframe;
2009                         break;
2010                 }
2011
2012                 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
2013
2014                 if ((xfer->endpoint->is_synced == 0) ||
2015                     (y < (xfer->nframes << shift)) ||
2016                     (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
2017                         /*
2018                          * If there is data underflow or the pipe
2019                          * queue is empty we schedule the transfer a
2020                          * few frames ahead of the current frame
2021                          * position. Else two isochronous transfers
2022                          * might overlap.
2023                          */
2024                         xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2025                         xfer->endpoint->is_synced = 1;
2026                         temp.do_isoc_sync = 1;
2027
2028                         DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2029                 }
2030
2031                 /* compute isochronous completion time */
2032
2033                 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2034
2035                 xfer->isoc_time_complete =
2036                     usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2037                     (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2038
2039                 x = 0;
2040                 temp.isoc_frame = xfer->endpoint->isoc_next;
2041                 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2042
2043                 xfer->endpoint->isoc_next += xfer->nframes << shift;
2044
2045         } else if (xfer->flags_int.control_xfr) {
2046
2047                 /* check if we should prepend a setup message */
2048
2049                 if (xfer->flags_int.control_hdr) {
2050
2051                         temp.len = xfer->frlengths[0];
2052                         temp.pc = xfer->frbuffers + 0;
2053                         temp.shortpkt = temp.len ? 1 : 0;
2054                         temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2055                         temp.direction = 0;
2056
2057                         /* check for last frame */
2058                         if (xfer->nframes == 1) {
2059                                 /* no STATUS stage yet, SETUP is last */
2060                                 if (xfer->flags_int.control_act)
2061                                         temp.last_frame = 1;
2062                         }
2063
2064                         xhci_setup_generic_chain_sub(&temp);
2065                 }
2066                 x = 1;
2067                 mult = 1;
2068                 temp.isoc_delta = 0;
2069                 temp.isoc_frame = 0;
2070                 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE;
2071         } else {
2072                 x = 0;
2073                 mult = 1;
2074                 temp.isoc_delta = 0;
2075                 temp.isoc_frame = 0;
2076                 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2077         }
2078
2079         if (x != xfer->nframes) {
2080                 /* setup page_cache pointer */
2081                 temp.pc = xfer->frbuffers + x;
2082                 /* set endpoint direction */
2083                 temp.direction = UE_GET_DIR(xfer->endpointno);
2084         }
2085
2086         while (x != xfer->nframes) {
2087
2088                 /* DATA0 / DATA1 message */
2089
2090                 temp.len = xfer->frlengths[x];
2091                 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2092                     x != 0 && temp.multishort == 0);
2093
2094                 x++;
2095
2096                 if (x == xfer->nframes) {
2097                         if (xfer->flags_int.control_xfr) {
2098                                 /* no STATUS stage yet, DATA is last */
2099                                 if (xfer->flags_int.control_act)
2100                                         temp.last_frame = 1;
2101                         } else {
2102                                 temp.last_frame = 1;
2103                         }
2104                 }
2105                 if (temp.len == 0) {
2106
2107                         /* make sure that we send an USB packet */
2108
2109                         temp.shortpkt = 0;
2110
2111                         temp.tbc = 0;
2112                         temp.tlbpc = mult - 1;
2113
2114                 } else if (xfer->flags_int.isochronous_xfr) {
2115
2116                         uint8_t tdpc;
2117
2118                         /*
2119                          * Isochronous transfers don't have short
2120                          * packet termination:
2121                          */
2122
2123                         temp.shortpkt = 1;
2124
2125                         /* isochronous transfers have a transfer limit */
2126
2127                         if (temp.len > xfer->max_frame_size)
2128                                 temp.len = xfer->max_frame_size;
2129
2130                         /* compute TD packet count */
2131                         tdpc = (temp.len + xfer->max_packet_size - 1) /
2132                             xfer->max_packet_size;
2133
2134                         temp.tbc = ((tdpc + mult - 1) / mult) - 1;
2135                         temp.tlbpc = (tdpc % mult);
2136
2137                         if (temp.tlbpc == 0)
2138                                 temp.tlbpc = mult - 1;
2139                         else
2140                                 temp.tlbpc--;
2141                 } else {
2142
2143                         /* regular data transfer */
2144
2145                         temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2146                 }
2147
2148                 xhci_setup_generic_chain_sub(&temp);
2149
2150                 if (xfer->flags_int.isochronous_xfr) {
2151                         temp.offset += xfer->frlengths[x - 1];
2152                         temp.isoc_frame += temp.isoc_delta;
2153                 } else {
2154                         /* get next Page Cache pointer */
2155                         temp.pc = xfer->frbuffers + x;
2156                 }
2157         }
2158
2159         /* check if we should append a status stage */
2160
2161         if (xfer->flags_int.control_xfr &&
2162             !xfer->flags_int.control_act) {
2163
2164                 /*
2165                  * Send a DATA1 message and invert the current
2166                  * endpoint direction.
2167                  */
2168                 temp.step_td = (xfer->nframes != 0);
2169                 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2170                 temp.len = 0;
2171                 temp.pc = NULL;
2172                 temp.shortpkt = 0;
2173                 temp.last_frame = 1;
2174                 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2175
2176                 xhci_setup_generic_chain_sub(&temp);
2177         }
2178
2179         td = temp.td;
2180
2181         /* must have at least one frame! */
2182
2183         xfer->td_transfer_last = td;
2184
2185         DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2186 }
2187
2188 static void
2189 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2190 {
2191         struct usb_page_search buf_res;
2192         struct xhci_dev_ctx_addr *pdctxa;
2193
2194         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2195
2196         pdctxa = buf_res.buffer;
2197
2198         DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2199
2200         pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2201
2202         usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2203 }
2204
2205 static usb_error_t
2206 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2207 {
2208         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2209         struct usb_page_search buf_inp;
2210         struct xhci_input_dev_ctx *pinp;
2211         uint32_t temp;
2212         uint8_t index;
2213         uint8_t x;
2214
2215         index = udev->controller_slot_id;
2216
2217         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2218
2219         pinp = buf_inp.buffer;
2220
2221         if (drop) {
2222                 mask &= XHCI_INCTX_NON_CTRL_MASK;
2223                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2224                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2225         } else {
2226                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0);
2227                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2228
2229                 /* find most significant set bit */
2230                 for (x = 31; x != 1; x--) {
2231                         if (mask & (1 << x))
2232                                 break;
2233                 }
2234
2235                 /* adjust */
2236                 x--;
2237
2238                 /* figure out maximum */
2239                 if (x > sc->sc_hw.devs[index].context_num) {
2240                         sc->sc_hw.devs[index].context_num = x;
2241                         temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2242                         temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2243                         temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2244                         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2245                 }
2246         }
2247         return (0);
2248 }
2249
2250 static usb_error_t
2251 xhci_configure_endpoint(struct usb_device *udev,
2252     struct usb_endpoint_descriptor *edesc, uint64_t ring_addr,
2253     uint16_t interval, uint8_t max_packet_count, uint8_t mult,
2254     uint8_t fps_shift, uint16_t max_packet_size, uint16_t max_frame_size)
2255 {
2256         struct usb_page_search buf_inp;
2257         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2258         struct xhci_input_dev_ctx *pinp;
2259         uint32_t temp;
2260         uint8_t index;
2261         uint8_t epno;
2262         uint8_t type;
2263
2264         index = udev->controller_slot_id;
2265
2266         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2267
2268         pinp = buf_inp.buffer;
2269
2270         epno = edesc->bEndpointAddress;
2271         type = edesc->bmAttributes & UE_XFERTYPE;
2272
2273         if (type == UE_CONTROL)
2274                 epno |= UE_DIR_IN;
2275
2276         epno = XHCI_EPNO2EPID(epno);
2277
2278         if (epno == 0)
2279                 return (USB_ERR_NO_PIPE);               /* invalid */
2280
2281         if (max_packet_count == 0)
2282                 return (USB_ERR_BAD_BUFSIZE);
2283
2284         max_packet_count--;
2285
2286         if (mult == 0)
2287                 return (USB_ERR_BAD_BUFSIZE);
2288
2289         temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2290             XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2291             XHCI_EPCTX_0_LSA_SET(0);
2292
2293         switch (udev->speed) {
2294         case USB_SPEED_FULL:
2295         case USB_SPEED_LOW:
2296                 /* 1ms -> 125us */
2297                 fps_shift += 3;
2298                 break;
2299         default:
2300                 break;
2301         }
2302
2303         switch (type) {
2304         case UE_INTERRUPT:
2305                 if (fps_shift > 3)
2306                         fps_shift--;
2307                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2308                 break;
2309         case UE_ISOCHRONOUS:
2310                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2311
2312                 switch (udev->speed) {
2313                 case USB_SPEED_SUPER:
2314                         if (mult > 3)
2315                                 mult = 3;
2316                         temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2317                         max_packet_count /= mult;
2318                         break;
2319                 default:
2320                         break;
2321                 }
2322                 break;
2323         default:
2324                 break;
2325         }
2326
2327         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2328
2329         temp =
2330             XHCI_EPCTX_1_HID_SET(0) |
2331             XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2332             XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2333
2334         if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) {
2335                 if (type != UE_ISOCHRONOUS)
2336                         temp |= XHCI_EPCTX_1_CERR_SET(3);
2337         }
2338
2339         switch (type) {
2340         case UE_CONTROL:
2341                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2342                 break;
2343         case UE_ISOCHRONOUS:
2344                 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2345                 break;
2346         case UE_BULK:
2347                 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2348                 break;
2349         default:
2350                 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2351                 break;
2352         }
2353
2354         /* check for IN direction */
2355         if (epno & 1)
2356                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2357
2358         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2359
2360         ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2361
2362         xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2363
2364         switch (edesc->bmAttributes & UE_XFERTYPE) {
2365         case UE_INTERRUPT:
2366         case UE_ISOCHRONOUS:
2367                 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2368                     XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2369                     max_frame_size));
2370                 break;
2371         case UE_CONTROL:
2372                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2373                 break;
2374         default:
2375                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2376                 break;
2377         }
2378
2379         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2380
2381 #ifdef USB_DEBUG
2382         xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2383 #endif
2384         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2385
2386         return (0);             /* success */
2387 }
2388
2389 static usb_error_t
2390 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2391 {
2392         struct xhci_endpoint_ext *pepext;
2393         struct usb_endpoint_ss_comp_descriptor *ecomp;
2394
2395         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2396             xfer->endpoint->edesc);
2397
2398         ecomp = xfer->endpoint->ecomp;
2399
2400         pepext->trb[0].dwTrb3 = 0;      /* halt any transfers */
2401         usb_pc_cpu_flush(pepext->page_cache);
2402
2403         return (xhci_configure_endpoint(xfer->xroot->udev,
2404             xfer->endpoint->edesc, pepext->physaddr,
2405             xfer->interval, xfer->max_packet_count,
2406             (ecomp != NULL) ? (ecomp->bmAttributes & 3) + 1 : 1,
2407             usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2408             xfer->max_frame_size));
2409 }
2410
2411 static usb_error_t
2412 xhci_configure_device(struct usb_device *udev)
2413 {
2414         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2415         struct usb_page_search buf_inp;
2416         struct usb_page_cache *pcinp;
2417         struct xhci_input_dev_ctx *pinp;
2418         struct usb_device *hubdev;
2419         uint32_t temp;
2420         uint32_t route;
2421         uint32_t rh_port;
2422         uint8_t is_hub;
2423         uint8_t index;
2424         uint8_t depth;
2425
2426         index = udev->controller_slot_id;
2427
2428         DPRINTF("index=%u\n", index);
2429
2430         pcinp = &sc->sc_hw.devs[index].input_pc;
2431
2432         usbd_get_page(pcinp, 0, &buf_inp);
2433
2434         pinp = buf_inp.buffer;
2435
2436         rh_port = 0;
2437         route = 0;
2438
2439         /* figure out route string and root HUB port number */
2440
2441         for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2442
2443                 if (hubdev->parent_hub == NULL)
2444                         break;
2445
2446                 depth = hubdev->parent_hub->depth;
2447
2448                 /*
2449                  * NOTE: HS/FS/LS devices and the SS root HUB can have
2450                  * more than 15 ports
2451                  */
2452
2453                 rh_port = hubdev->port_no;
2454
2455                 if (depth == 0)
2456                         break;
2457
2458                 if (rh_port > 15)
2459                         rh_port = 15;
2460
2461                 if (depth < 6)
2462                         route |= rh_port << (4 * (depth - 1));
2463         }
2464
2465         DPRINTF("Route=0x%08x\n", route);
2466
2467         temp = XHCI_SCTX_0_ROUTE_SET(route) |
2468             XHCI_SCTX_0_CTX_NUM_SET(
2469             sc->sc_hw.devs[index].context_num + 1);
2470
2471         switch (udev->speed) {
2472         case USB_SPEED_LOW:
2473                 temp |= XHCI_SCTX_0_SPEED_SET(2);
2474                 if (udev->parent_hs_hub != NULL &&
2475                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2476                     UDPROTO_HSHUBMTT) {
2477                         DPRINTF("Device inherits MTT\n");
2478                         temp |= XHCI_SCTX_0_MTT_SET(1);
2479                 }
2480                 break;
2481         case USB_SPEED_HIGH:
2482                 temp |= XHCI_SCTX_0_SPEED_SET(3);
2483                 if (sc->sc_hw.devs[index].nports != 0 &&
2484                     udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2485                         DPRINTF("HUB supports MTT\n");
2486                         temp |= XHCI_SCTX_0_MTT_SET(1);
2487                 }
2488                 break;
2489         case USB_SPEED_FULL:
2490                 temp |= XHCI_SCTX_0_SPEED_SET(1);
2491                 if (udev->parent_hs_hub != NULL &&
2492                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2493                     UDPROTO_HSHUBMTT) {
2494                         DPRINTF("Device inherits MTT\n");
2495                         temp |= XHCI_SCTX_0_MTT_SET(1);
2496                 }
2497                 break;
2498         default:
2499                 temp |= XHCI_SCTX_0_SPEED_SET(4);
2500                 break;
2501         }
2502
2503         is_hub = sc->sc_hw.devs[index].nports != 0 &&
2504             (udev->speed == USB_SPEED_SUPER ||
2505             udev->speed == USB_SPEED_HIGH);
2506
2507         if (is_hub)
2508                 temp |= XHCI_SCTX_0_HUB_SET(1);
2509
2510         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2511
2512         temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2513
2514         if (is_hub) {
2515                 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2516                     sc->sc_hw.devs[index].nports);
2517         }
2518
2519         switch (udev->speed) {
2520         case USB_SPEED_SUPER:
2521                 switch (sc->sc_hw.devs[index].state) {
2522                 case XHCI_ST_ADDRESSED:
2523                 case XHCI_ST_CONFIGURED:
2524                         /* enable power save */
2525                         temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2526                         break;
2527                 default:
2528                         /* disable power save */
2529                         break;
2530                 }
2531                 break;
2532         default:
2533                 break;
2534         }
2535
2536         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2537
2538         temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2539
2540         if (is_hub) {
2541                 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2542                     sc->sc_hw.devs[index].tt);
2543         }
2544
2545         hubdev = udev->parent_hs_hub;
2546
2547         /* check if we should activate the transaction translator */
2548         switch (udev->speed) {
2549         case USB_SPEED_FULL:
2550         case USB_SPEED_LOW:
2551                 if (hubdev != NULL) {
2552                         temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2553                             hubdev->controller_slot_id);
2554                         temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2555                             udev->hs_port_no);
2556                 }
2557                 break;
2558         default:
2559                 break;
2560         }
2561
2562         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2563
2564         /*
2565          * These fields should be initialized to zero, according to
2566          * XHCI section 6.2.2 - slot context:
2567          */
2568         temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2569             XHCI_SCTX_3_SLOT_STATE_SET(0);
2570
2571         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2572
2573 #ifdef USB_DEBUG
2574         xhci_dump_device(sc, &pinp->ctx_slot);
2575 #endif
2576         usb_pc_cpu_flush(pcinp);
2577
2578         return (0);             /* success */
2579 }
2580
2581 static usb_error_t
2582 xhci_alloc_device_ext(struct usb_device *udev)
2583 {
2584         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2585         struct usb_page_search buf_dev;
2586         struct usb_page_search buf_ep;
2587         struct xhci_trb *trb;
2588         struct usb_page_cache *pc;
2589         struct usb_page *pg;
2590         uint64_t addr;
2591         uint8_t index;
2592         uint8_t i;
2593
2594         index = udev->controller_slot_id;
2595
2596         pc = &sc->sc_hw.devs[index].device_pc;
2597         pg = &sc->sc_hw.devs[index].device_pg;
2598
2599         /* need to initialize the page cache */
2600         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2601
2602         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2603             (2 * sizeof(struct xhci_dev_ctx)) :
2604             sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2605                 goto error;
2606
2607         usbd_get_page(pc, 0, &buf_dev);
2608
2609         pc = &sc->sc_hw.devs[index].input_pc;
2610         pg = &sc->sc_hw.devs[index].input_pg;
2611
2612         /* need to initialize the page cache */
2613         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2614
2615         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2616             (2 * sizeof(struct xhci_input_dev_ctx)) :
2617             sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2618                 goto error;
2619         }
2620
2621         pc = &sc->sc_hw.devs[index].endpoint_pc;
2622         pg = &sc->sc_hw.devs[index].endpoint_pg;
2623
2624         /* need to initialize the page cache */
2625         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2626
2627         if (usb_pc_alloc_mem(pc, pg,
2628             sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) {
2629                 goto error;
2630         }
2631
2632         /* initialise all endpoint LINK TRBs */
2633
2634         for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2635
2636                 /* lookup endpoint TRB ring */
2637                 usbd_get_page(pc, (uintptr_t)&
2638                     ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep);
2639
2640                 /* get TRB pointer */
2641                 trb = buf_ep.buffer;
2642                 trb += XHCI_MAX_TRANSFERS - 1;
2643
2644                 /* get TRB start address */
2645                 addr = buf_ep.physaddr;
2646
2647                 /* create LINK TRB */
2648                 trb->qwTrb0 = htole64(addr);
2649                 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2650                 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2651                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2652         }
2653
2654         usb_pc_cpu_flush(pc);
2655
2656         xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2657
2658         return (0);
2659
2660 error:
2661         xhci_free_device_ext(udev);
2662
2663         return (USB_ERR_NOMEM);
2664 }
2665
2666 static void
2667 xhci_free_device_ext(struct usb_device *udev)
2668 {
2669         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2670         uint8_t index;
2671
2672         index = udev->controller_slot_id;
2673         xhci_set_slot_pointer(sc, index, 0);
2674
2675         usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2676         usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2677         usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc);
2678 }
2679
2680 static struct xhci_endpoint_ext *
2681 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2682 {
2683         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2684         struct xhci_endpoint_ext *pepext;
2685         struct usb_page_cache *pc;
2686         struct usb_page_search buf_ep;
2687         uint8_t epno;
2688         uint8_t index;
2689
2690         epno = edesc->bEndpointAddress;
2691         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2692                 epno |= UE_DIR_IN;
2693
2694         epno = XHCI_EPNO2EPID(epno);
2695
2696         index = udev->controller_slot_id;
2697
2698         pc = &sc->sc_hw.devs[index].endpoint_pc;
2699
2700         usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->trb[epno][0], &buf_ep);
2701
2702         pepext = &sc->sc_hw.devs[index].endp[epno];
2703         pepext->page_cache = pc;
2704         pepext->trb = buf_ep.buffer;
2705         pepext->physaddr = buf_ep.physaddr;
2706
2707         return (pepext);
2708 }
2709
2710 static void
2711 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2712 {
2713         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2714         uint8_t epno;
2715         uint8_t index;
2716
2717         epno = xfer->endpointno;
2718         if (xfer->flags_int.control_xfr)
2719                 epno |= UE_DIR_IN;
2720
2721         epno = XHCI_EPNO2EPID(epno);
2722         index = xfer->xroot->udev->controller_slot_id;
2723
2724         if (xfer->xroot->udev->flags.self_suspended == 0) {
2725                 XWRITE4(sc, door, XHCI_DOORBELL(index),
2726                     epno | XHCI_DB_SID_SET(/*xfer->stream_id*/ 0));
2727         }
2728 }
2729
2730 static void
2731 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2732 {
2733         struct xhci_endpoint_ext *pepext;
2734
2735         if (xfer->flags_int.bandwidth_reclaimed) {
2736                 xfer->flags_int.bandwidth_reclaimed = 0;
2737
2738                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2739                     xfer->endpoint->edesc);
2740
2741                 pepext->trb_used--;
2742
2743                 pepext->xfer[xfer->qh_pos] = NULL;
2744
2745                 if (error && pepext->trb_running != 0) {
2746                         pepext->trb_halted = 1;
2747                         pepext->trb_running = 0;
2748                 }
2749         }
2750 }
2751
2752 static usb_error_t
2753 xhci_transfer_insert(struct usb_xfer *xfer)
2754 {
2755         struct xhci_td *td_first;
2756         struct xhci_td *td_last;
2757         struct xhci_trb *trb_link;
2758         struct xhci_endpoint_ext *pepext;
2759         uint64_t addr;
2760         uint8_t i;
2761         uint8_t inext;
2762         uint8_t trb_limit;
2763
2764         DPRINTFN(8, "\n");
2765
2766         /* check if already inserted */
2767         if (xfer->flags_int.bandwidth_reclaimed) {
2768                 DPRINTFN(8, "Already in schedule\n");
2769                 return (0);
2770         }
2771
2772         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2773             xfer->endpoint->edesc);
2774
2775         td_first = xfer->td_transfer_first;
2776         td_last = xfer->td_transfer_last;
2777         addr = pepext->physaddr;
2778
2779         switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2780         case UE_CONTROL:
2781         case UE_INTERRUPT:
2782                 /* single buffered */
2783                 trb_limit = 1;
2784                 break;
2785         default:
2786                 /* multi buffered */
2787                 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2788                 break;
2789         }
2790
2791         if (pepext->trb_used >= trb_limit) {
2792                 DPRINTFN(8, "Too many TDs queued.\n");
2793                 return (USB_ERR_NOMEM);
2794         }
2795
2796         /* check for stopped condition, after putting transfer on interrupt queue */
2797         if (pepext->trb_running == 0) {
2798                 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2799
2800                 DPRINTFN(8, "Not running\n");
2801
2802                 /* start configuration */
2803                 (void)usb_proc_msignal(&sc->sc_config_proc,
2804                     &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2805                 return (0);
2806         }
2807
2808         pepext->trb_used++;
2809
2810         /* get current TRB index */
2811         i = pepext->trb_index;
2812
2813         /* get next TRB index */
2814         inext = (i + 1);
2815
2816         /* the last entry of the ring is a hardcoded link TRB */
2817         if (inext >= (XHCI_MAX_TRANSFERS - 1))
2818                 inext = 0;
2819
2820         /* compute terminating return address */
2821         addr += inext * sizeof(struct xhci_trb);
2822
2823         /* compute link TRB pointer */
2824         trb_link = td_last->td_trb + td_last->ntrb;
2825
2826         /* update next pointer of last link TRB */
2827         trb_link->qwTrb0 = htole64(addr);
2828         trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2829         trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2830             XHCI_TRB_3_CYCLE_BIT |
2831             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2832
2833 #ifdef USB_DEBUG
2834         xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2835 #endif
2836         usb_pc_cpu_flush(td_last->page_cache);
2837
2838         /* write ahead chain end marker */
2839
2840         pepext->trb[inext].qwTrb0 = 0;
2841         pepext->trb[inext].dwTrb2 = 0;
2842         pepext->trb[inext].dwTrb3 = 0;
2843
2844         /* update next pointer of link TRB */
2845
2846         pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2847         pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2848
2849 #ifdef USB_DEBUG
2850         xhci_dump_trb(&pepext->trb[i]);
2851 #endif
2852         usb_pc_cpu_flush(pepext->page_cache);
2853
2854         /* toggle cycle bit which activates the transfer chain */
2855
2856         pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2857             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2858
2859         usb_pc_cpu_flush(pepext->page_cache);
2860
2861         DPRINTF("qh_pos = %u\n", i);
2862
2863         pepext->xfer[i] = xfer;
2864
2865         xfer->qh_pos = i;
2866
2867         xfer->flags_int.bandwidth_reclaimed = 1;
2868
2869         pepext->trb_index = inext;
2870
2871         xhci_endpoint_doorbell(xfer);
2872
2873         return (0);
2874 }
2875
2876 static void
2877 xhci_root_intr(struct xhci_softc *sc)
2878 {
2879         uint16_t i;
2880
2881         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2882
2883         /* clear any old interrupt data */
2884         memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2885
2886         for (i = 1; i <= sc->sc_noport; i++) {
2887                 /* pick out CHANGE bits from the status register */
2888                 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
2889                     XHCI_PS_CSC | XHCI_PS_PEC |
2890                     XHCI_PS_OCC | XHCI_PS_WRC |
2891                     XHCI_PS_PRC | XHCI_PS_PLC |
2892                     XHCI_PS_CEC)) {
2893                         sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2894                         DPRINTF("port %d changed\n", i);
2895                 }
2896         }
2897         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2898             sizeof(sc->sc_hub_idata));
2899 }
2900
2901 /*------------------------------------------------------------------------*
2902  *      xhci_device_done - XHCI done handler
2903  *
2904  * NOTE: This function can be called two times in a row on
2905  * the same USB transfer. From close and from interrupt.
2906  *------------------------------------------------------------------------*/
2907 static void
2908 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
2909 {
2910         DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2911             xfer, xfer->endpoint, error);
2912
2913         /* remove transfer from HW queue */
2914         xhci_transfer_remove(xfer, error);
2915
2916         /* dequeue transfer and start next transfer */
2917         usbd_transfer_done(xfer, error);
2918 }
2919
2920 /*------------------------------------------------------------------------*
2921  * XHCI data transfer support (generic type)
2922  *------------------------------------------------------------------------*/
2923 static void
2924 xhci_device_generic_open(struct usb_xfer *xfer)
2925 {
2926         if (xfer->flags_int.isochronous_xfr) {
2927                 switch (xfer->xroot->udev->speed) {
2928                 case USB_SPEED_FULL:
2929                         break;
2930                 default:
2931                         usb_hs_bandwidth_alloc(xfer);
2932                         break;
2933                 }
2934         }
2935 }
2936
2937 static void
2938 xhci_device_generic_close(struct usb_xfer *xfer)
2939 {
2940         DPRINTF("\n");
2941
2942         xhci_device_done(xfer, USB_ERR_CANCELLED);
2943
2944         if (xfer->flags_int.isochronous_xfr) {
2945                 switch (xfer->xroot->udev->speed) {
2946                 case USB_SPEED_FULL:
2947                         break;
2948                 default:
2949                         usb_hs_bandwidth_free(xfer);
2950                         break;
2951                 }
2952         }
2953 }
2954
2955 static void
2956 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
2957     struct usb_xfer *enter_xfer)
2958 {
2959         struct usb_xfer *xfer;
2960
2961         /* check if there is a current transfer */
2962         xfer = ep->endpoint_q.curr;
2963         if (xfer == NULL)
2964                 return;
2965
2966         /*
2967          * Check if the current transfer is started and then pickup
2968          * the next one, if any. Else wait for next start event due to
2969          * block on failure feature.
2970          */
2971         if (!xfer->flags_int.bandwidth_reclaimed)
2972                 return;
2973
2974         xfer = TAILQ_FIRST(&ep->endpoint_q.head);
2975         if (xfer == NULL) {
2976                 /*
2977                  * In case of enter we have to consider that the
2978                  * transfer is queued by the USB core after the enter
2979                  * method is called.
2980                  */
2981                 xfer = enter_xfer;
2982
2983                 if (xfer == NULL)
2984                         return;
2985         }
2986
2987         /* try to multi buffer */
2988         xhci_transfer_insert(xfer);
2989 }
2990
2991 static void
2992 xhci_device_generic_enter(struct usb_xfer *xfer)
2993 {
2994         DPRINTF("\n");
2995
2996         /* setup TD's and QH */
2997         xhci_setup_generic_chain(xfer);
2998
2999         xhci_device_generic_multi_enter(xfer->endpoint, xfer);
3000 }
3001
3002 static void
3003 xhci_device_generic_start(struct usb_xfer *xfer)
3004 {
3005         DPRINTF("\n");
3006
3007         /* try to insert xfer on HW queue */
3008         xhci_transfer_insert(xfer);
3009
3010         /* try to multi buffer */
3011         xhci_device_generic_multi_enter(xfer->endpoint, NULL);
3012
3013         /* add transfer last on interrupt queue */
3014         usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3015
3016         /* start timeout, if any */
3017         if (xfer->timeout != 0)
3018                 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3019 }
3020
3021 struct usb_pipe_methods xhci_device_generic_methods =
3022 {
3023         .open = xhci_device_generic_open,
3024         .close = xhci_device_generic_close,
3025         .enter = xhci_device_generic_enter,
3026         .start = xhci_device_generic_start,
3027 };
3028
3029 /*------------------------------------------------------------------------*
3030  * xhci root HUB support
3031  *------------------------------------------------------------------------*
3032  * Simulate a hardware HUB by handling all the necessary requests.
3033  *------------------------------------------------------------------------*/
3034
3035 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3036
3037 static const
3038 struct usb_device_descriptor xhci_devd =
3039 {
3040         .bLength = sizeof(xhci_devd),
3041         .bDescriptorType = UDESC_DEVICE,        /* type */
3042         HSETW(.bcdUSB, 0x0300),                 /* USB version */
3043         .bDeviceClass = UDCLASS_HUB,            /* class */
3044         .bDeviceSubClass = UDSUBCLASS_HUB,      /* subclass */
3045         .bDeviceProtocol = UDPROTO_SSHUB,       /* protocol */
3046         .bMaxPacketSize = 9,                    /* max packet size */
3047         HSETW(.idVendor, 0x0000),               /* vendor */
3048         HSETW(.idProduct, 0x0000),              /* product */
3049         HSETW(.bcdDevice, 0x0100),              /* device version */
3050         .iManufacturer = 1,
3051         .iProduct = 2,
3052         .iSerialNumber = 0,
3053         .bNumConfigurations = 1,                /* # of configurations */
3054 };
3055
3056 static const
3057 struct xhci_bos_desc xhci_bosd = {
3058         .bosd = {
3059                 .bLength = sizeof(xhci_bosd.bosd),
3060                 .bDescriptorType = UDESC_BOS,
3061                 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3062                 .bNumDeviceCaps = 3,
3063         },
3064         .usb2extd = {
3065                 .bLength = sizeof(xhci_bosd.usb2extd),
3066                 .bDescriptorType = 1,
3067                 .bDevCapabilityType = 2,
3068                 .bmAttributes[0] = 2,
3069         },
3070         .usbdcd = {
3071                 .bLength = sizeof(xhci_bosd.usbdcd),
3072                 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3073                 .bDevCapabilityType = 3,
3074                 .bmAttributes = 0, /* XXX */
3075                 HSETW(.wSpeedsSupported, 0x000C),
3076                 .bFunctionalitySupport = 8,
3077                 .bU1DevExitLat = 255,   /* dummy - not used */
3078                 .wU2DevExitLat = { 0x00, 0x08 },
3079         },
3080         .cidd = {
3081                 .bLength = sizeof(xhci_bosd.cidd),
3082                 .bDescriptorType = 1,
3083                 .bDevCapabilityType = 4,
3084                 .bReserved = 0,
3085                 .bContainerID = 0, /* XXX */
3086         },
3087 };
3088
3089 static const
3090 struct xhci_config_desc xhci_confd = {
3091         .confd = {
3092                 .bLength = sizeof(xhci_confd.confd),
3093                 .bDescriptorType = UDESC_CONFIG,
3094                 .wTotalLength[0] = sizeof(xhci_confd),
3095                 .bNumInterface = 1,
3096                 .bConfigurationValue = 1,
3097                 .iConfiguration = 0,
3098                 .bmAttributes = UC_SELF_POWERED,
3099                 .bMaxPower = 0          /* max power */
3100         },
3101         .ifcd = {
3102                 .bLength = sizeof(xhci_confd.ifcd),
3103                 .bDescriptorType = UDESC_INTERFACE,
3104                 .bNumEndpoints = 1,
3105                 .bInterfaceClass = UICLASS_HUB,
3106                 .bInterfaceSubClass = UISUBCLASS_HUB,
3107                 .bInterfaceProtocol = 0,
3108         },
3109         .endpd = {
3110                 .bLength = sizeof(xhci_confd.endpd),
3111                 .bDescriptorType = UDESC_ENDPOINT,
3112                 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3113                 .bmAttributes = UE_INTERRUPT,
3114                 .wMaxPacketSize[0] = 2,         /* max 15 ports */
3115                 .bInterval = 255,
3116         },
3117         .endpcd = {
3118                 .bLength = sizeof(xhci_confd.endpcd),
3119                 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3120                 .bMaxBurst = 0,
3121                 .bmAttributes = 0,
3122         },
3123 };
3124
3125 static const
3126 struct usb_hub_ss_descriptor xhci_hubd = {
3127         .bLength = sizeof(xhci_hubd),
3128         .bDescriptorType = UDESC_SS_HUB,
3129 };
3130
3131 static usb_error_t
3132 xhci_roothub_exec(struct usb_device *udev,
3133     struct usb_device_request *req, const void **pptr, uint16_t *plength)
3134 {
3135         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3136         const char *str_ptr;
3137         const void *ptr;
3138         uint32_t port;
3139         uint32_t v;
3140         uint16_t len;
3141         uint16_t i;
3142         uint16_t value;
3143         uint16_t index;
3144         uint8_t j;
3145         usb_error_t err;
3146
3147         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3148
3149         /* buffer reset */
3150         ptr = (const void *)&sc->sc_hub_desc;
3151         len = 0;
3152         err = 0;
3153
3154         value = UGETW(req->wValue);
3155         index = UGETW(req->wIndex);
3156
3157         DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3158             "wValue=0x%04x wIndex=0x%04x\n",
3159             req->bmRequestType, req->bRequest,
3160             UGETW(req->wLength), value, index);
3161
3162 #define C(x,y) ((x) | ((y) << 8))
3163         switch (C(req->bRequest, req->bmRequestType)) {
3164         case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3165         case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3166         case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3167                 /*
3168                  * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3169                  * for the integrated root hub.
3170                  */
3171                 break;
3172         case C(UR_GET_CONFIG, UT_READ_DEVICE):
3173                 len = 1;
3174                 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3175                 break;
3176         case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3177                 switch (value >> 8) {
3178                 case UDESC_DEVICE:
3179                         if ((value & 0xff) != 0) {
3180                                 err = USB_ERR_IOERROR;
3181                                 goto done;
3182                         }
3183                         len = sizeof(xhci_devd);
3184                         ptr = (const void *)&xhci_devd;
3185                         break;
3186
3187                 case UDESC_BOS:
3188                         if ((value & 0xff) != 0) {
3189                                 err = USB_ERR_IOERROR;
3190                                 goto done;
3191                         }
3192                         len = sizeof(xhci_bosd);
3193                         ptr = (const void *)&xhci_bosd;
3194                         break;
3195
3196                 case UDESC_CONFIG:
3197                         if ((value & 0xff) != 0) {
3198                                 err = USB_ERR_IOERROR;
3199                                 goto done;
3200                         }
3201                         len = sizeof(xhci_confd);
3202                         ptr = (const void *)&xhci_confd;
3203                         break;
3204
3205                 case UDESC_STRING:
3206                         switch (value & 0xff) {
3207                         case 0: /* Language table */
3208                                 str_ptr = "\001";
3209                                 break;
3210
3211                         case 1: /* Vendor */
3212                                 str_ptr = sc->sc_vendor;
3213                                 break;
3214
3215                         case 2: /* Product */
3216                                 str_ptr = "XHCI root HUB";
3217                                 break;
3218
3219                         default:
3220                                 str_ptr = "";
3221                                 break;
3222                         }
3223
3224                         len = usb_make_str_desc(
3225                             sc->sc_hub_desc.temp,
3226                             sizeof(sc->sc_hub_desc.temp),
3227                             str_ptr);
3228                         break;
3229
3230                 default:
3231                         err = USB_ERR_IOERROR;
3232                         goto done;
3233                 }
3234                 break;
3235         case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3236                 len = 1;
3237                 sc->sc_hub_desc.temp[0] = 0;
3238                 break;
3239         case C(UR_GET_STATUS, UT_READ_DEVICE):
3240                 len = 2;
3241                 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3242                 break;
3243         case C(UR_GET_STATUS, UT_READ_INTERFACE):
3244         case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3245                 len = 2;
3246                 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3247                 break;
3248         case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3249                 if (value >= XHCI_MAX_DEVICES) {
3250                         err = USB_ERR_IOERROR;
3251                         goto done;
3252                 }
3253                 break;
3254         case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3255                 if (value != 0 && value != 1) {
3256                         err = USB_ERR_IOERROR;
3257                         goto done;
3258                 }
3259                 sc->sc_conf = value;
3260                 break;
3261         case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3262                 break;
3263         case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3264         case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3265         case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3266                 err = USB_ERR_IOERROR;
3267                 goto done;
3268         case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3269                 break;
3270         case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3271                 break;
3272                 /* Hub requests */
3273         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3274                 break;
3275         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3276                 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3277
3278                 if ((index < 1) ||
3279                     (index > sc->sc_noport)) {
3280                         err = USB_ERR_IOERROR;
3281                         goto done;
3282                 }
3283                 port = XHCI_PORTSC(index);
3284
3285                 v = XREAD4(sc, oper, port);
3286                 i = XHCI_PS_PLS_GET(v);
3287                 v &= ~XHCI_PS_CLEAR;
3288
3289                 switch (value) {
3290                 case UHF_C_BH_PORT_RESET:
3291                         XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3292                         break;
3293                 case UHF_C_PORT_CONFIG_ERROR:
3294                         XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3295                         break;
3296                 case UHF_C_PORT_SUSPEND:
3297                 case UHF_C_PORT_LINK_STATE:
3298                         XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3299                         break;
3300                 case UHF_C_PORT_CONNECTION:
3301                         XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3302                         break;
3303                 case UHF_C_PORT_ENABLE:
3304                         XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3305                         break;
3306                 case UHF_C_PORT_OVER_CURRENT:
3307                         XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3308                         break;
3309                 case UHF_C_PORT_RESET:
3310                         XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3311                         break;
3312                 case UHF_PORT_ENABLE:
3313                         XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3314                         break;
3315                 case UHF_PORT_POWER:
3316                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3317                         break;
3318                 case UHF_PORT_INDICATOR:
3319                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3320                         break;
3321                 case UHF_PORT_SUSPEND:
3322
3323                         /* U3 -> U15 */
3324                         if (i == 3) {
3325                                 XWRITE4(sc, oper, port, v |
3326                                     XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3327                         }
3328
3329                         /* wait 20ms for resume sequence to complete */
3330                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3331
3332                         /* U0 */
3333                         XWRITE4(sc, oper, port, v |
3334                             XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3335                         break;
3336                 default:
3337                         err = USB_ERR_IOERROR;
3338                         goto done;
3339                 }
3340                 break;
3341
3342         case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3343                 if ((value & 0xff) != 0) {
3344                         err = USB_ERR_IOERROR;
3345                         goto done;
3346                 }
3347
3348                 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3349
3350                 sc->sc_hub_desc.hubd = xhci_hubd;
3351
3352                 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3353
3354                 if (XHCI_HCS0_PPC(v))
3355                         i = UHD_PWR_INDIVIDUAL;
3356                 else
3357                         i = UHD_PWR_GANGED;
3358
3359                 if (XHCI_HCS0_PIND(v))
3360                         i |= UHD_PORT_IND;
3361
3362                 i |= UHD_OC_INDIVIDUAL;
3363
3364                 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3365
3366                 /* see XHCI section 5.4.9: */
3367                 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3368
3369                 for (j = 1; j <= sc->sc_noport; j++) {
3370
3371                         v = XREAD4(sc, oper, XHCI_PORTSC(j));
3372                         if (v & XHCI_PS_DR) {
3373                                 sc->sc_hub_desc.hubd.
3374                                     DeviceRemovable[j / 8] |= 1U << (j % 8);
3375                         }
3376                 }
3377                 len = sc->sc_hub_desc.hubd.bLength;
3378                 break;
3379
3380         case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3381                 len = 16;
3382                 memset(sc->sc_hub_desc.temp, 0, 16);
3383                 break;
3384
3385         case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3386                 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3387
3388                 if ((index < 1) ||
3389                     (index > sc->sc_noport)) {
3390                         err = USB_ERR_IOERROR;
3391                         goto done;
3392                 }
3393
3394                 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3395
3396                 DPRINTFN(9, "port status=0x%08x\n", v);
3397
3398                 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3399
3400                 switch (XHCI_PS_SPEED_GET(v)) {
3401                 case 3:
3402                         i |= UPS_HIGH_SPEED;
3403                         break;
3404                 case 2:
3405                         i |= UPS_LOW_SPEED;
3406                         break;
3407                 case 1:
3408                         /* FULL speed */
3409                         break;
3410                 default:
3411                         i |= UPS_OTHER_SPEED;
3412                         break;
3413                 }
3414
3415                 if (v & XHCI_PS_CCS)
3416                         i |= UPS_CURRENT_CONNECT_STATUS;
3417                 if (v & XHCI_PS_PED)
3418                         i |= UPS_PORT_ENABLED;
3419                 if (v & XHCI_PS_OCA)
3420                         i |= UPS_OVERCURRENT_INDICATOR;
3421                 if (v & XHCI_PS_PR)
3422                         i |= UPS_RESET;
3423                 if (v & XHCI_PS_PP) {
3424                         /*
3425                          * The USB 3.0 RH is using the
3426                          * USB 2.0's power bit
3427                          */
3428                         i |= UPS_PORT_POWER;
3429                 }
3430                 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3431
3432                 i = 0;
3433                 if (v & XHCI_PS_CSC)
3434                         i |= UPS_C_CONNECT_STATUS;
3435                 if (v & XHCI_PS_PEC)
3436                         i |= UPS_C_PORT_ENABLED;
3437                 if (v & XHCI_PS_OCC)
3438                         i |= UPS_C_OVERCURRENT_INDICATOR;
3439                 if (v & XHCI_PS_WRC)
3440                         i |= UPS_C_BH_PORT_RESET;
3441                 if (v & XHCI_PS_PRC)
3442                         i |= UPS_C_PORT_RESET;
3443                 if (v & XHCI_PS_PLC)
3444                         i |= UPS_C_PORT_LINK_STATE;
3445                 if (v & XHCI_PS_CEC)
3446                         i |= UPS_C_PORT_CONFIG_ERROR;
3447
3448                 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3449                 len = sizeof(sc->sc_hub_desc.ps);
3450                 break;
3451
3452         case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3453                 err = USB_ERR_IOERROR;
3454                 goto done;
3455
3456         case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3457                 break;
3458
3459         case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3460
3461                 i = index >> 8;
3462                 index &= 0x00FF;
3463
3464                 if ((index < 1) ||
3465                     (index > sc->sc_noport)) {
3466                         err = USB_ERR_IOERROR;
3467                         goto done;
3468                 }
3469
3470                 port = XHCI_PORTSC(index);
3471                 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3472
3473                 switch (value) {
3474                 case UHF_PORT_U1_TIMEOUT:
3475                         if (XHCI_PS_SPEED_GET(v) != 4) {
3476                                 err = USB_ERR_IOERROR;
3477                                 goto done;
3478                         }
3479                         port = XHCI_PORTPMSC(index);
3480                         v = XREAD4(sc, oper, port);
3481                         v &= ~XHCI_PM3_U1TO_SET(0xFF);
3482                         v |= XHCI_PM3_U1TO_SET(i);
3483                         XWRITE4(sc, oper, port, v);
3484                         break;
3485                 case UHF_PORT_U2_TIMEOUT:
3486                         if (XHCI_PS_SPEED_GET(v) != 4) {
3487                                 err = USB_ERR_IOERROR;
3488                                 goto done;
3489                         }
3490                         port = XHCI_PORTPMSC(index);
3491                         v = XREAD4(sc, oper, port);
3492                         v &= ~XHCI_PM3_U2TO_SET(0xFF);
3493                         v |= XHCI_PM3_U2TO_SET(i);
3494                         XWRITE4(sc, oper, port, v);
3495                         break;
3496                 case UHF_BH_PORT_RESET:
3497                         XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3498                         break;
3499                 case UHF_PORT_LINK_STATE:
3500                         XWRITE4(sc, oper, port, v |
3501                             XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3502                         /* 4ms settle time */
3503                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3504                         break;
3505                 case UHF_PORT_ENABLE:
3506                         DPRINTFN(3, "set port enable %d\n", index);
3507                         break;
3508                 case UHF_PORT_SUSPEND:
3509                         DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3510                         j = XHCI_PS_SPEED_GET(v);
3511                         if ((j < 1) || (j > 3)) {
3512                                 /* non-supported speed */
3513                                 err = USB_ERR_IOERROR;
3514                                 goto done;
3515                         }
3516                         XWRITE4(sc, oper, port, v |
3517                             XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3518                         break;
3519                 case UHF_PORT_RESET:
3520                         DPRINTFN(6, "reset port %d\n", index);
3521                         XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3522                         break;
3523                 case UHF_PORT_POWER:
3524                         DPRINTFN(3, "set port power %d\n", index);
3525                         XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3526                         break;
3527                 case UHF_PORT_TEST:
3528                         DPRINTFN(3, "set port test %d\n", index);
3529                         break;
3530                 case UHF_PORT_INDICATOR:
3531                         DPRINTFN(3, "set port indicator %d\n", index);
3532
3533                         v &= ~XHCI_PS_PIC_SET(3);
3534                         v |= XHCI_PS_PIC_SET(1);
3535
3536                         XWRITE4(sc, oper, port, v);
3537                         break;
3538                 default:
3539                         err = USB_ERR_IOERROR;
3540                         goto done;
3541                 }
3542                 break;
3543
3544         case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3545         case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3546         case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3547         case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3548                 break;
3549         default:
3550                 err = USB_ERR_IOERROR;
3551                 goto done;
3552         }
3553 done:
3554         *plength = len;
3555         *pptr = ptr;
3556         return (err);
3557 }
3558
3559 static void
3560 xhci_xfer_setup(struct usb_setup_params *parm)
3561 {
3562         struct usb_page_search page_info;
3563         struct usb_page_cache *pc;
3564         struct xhci_softc *sc;
3565         struct usb_xfer *xfer;
3566         void *last_obj;
3567         uint32_t ntd;
3568         uint32_t n;
3569
3570         sc = XHCI_BUS2SC(parm->udev->bus);
3571         xfer = parm->curr_xfer;
3572
3573         /*
3574          * The proof for the "ntd" formula is illustrated like this:
3575          *
3576          * +------------------------------------+
3577          * |                                    |
3578          * |         |remainder ->              |
3579          * |   +-----+---+                      |
3580          * |   | xxx | x | frm 0                |
3581          * |   +-----+---++                     |
3582          * |   | xxx | xx | frm 1               |
3583          * |   +-----+----+                     |
3584          * |            ...                     |
3585          * +------------------------------------+
3586          *
3587          * "xxx" means a completely full USB transfer descriptor
3588          *
3589          * "x" and "xx" means a short USB packet
3590          *
3591          * For the remainder of an USB transfer modulo
3592          * "max_data_length" we need two USB transfer descriptors.
3593          * One to transfer the remaining data and one to finalise with
3594          * a zero length packet in case the "force_short_xfer" flag is
3595          * set. We only need two USB transfer descriptors in the case
3596          * where the transfer length of the first one is a factor of
3597          * "max_frame_size". The rest of the needed USB transfer
3598          * descriptors is given by the buffer size divided by the
3599          * maximum data payload.
3600          */
3601         parm->hc_max_packet_size = 0x400;
3602         parm->hc_max_packet_count = 16 * 3;
3603         parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3604
3605         xfer->flags_int.bdma_enable = 1;
3606
3607         usbd_transfer_setup_sub(parm);
3608
3609         if (xfer->flags_int.isochronous_xfr) {
3610                 ntd = ((1 * xfer->nframes)
3611                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3612         } else if (xfer->flags_int.control_xfr) {
3613                 ntd = ((2 * xfer->nframes) + 1  /* STATUS */
3614                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3615         } else {
3616                 ntd = ((2 * xfer->nframes)
3617                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3618         }
3619
3620 alloc_dma_set:
3621
3622         if (parm->err)
3623                 return;
3624
3625         /*
3626          * Allocate queue heads and transfer descriptors
3627          */
3628         last_obj = NULL;
3629
3630         if (usbd_transfer_setup_sub_malloc(
3631             parm, &pc, sizeof(struct xhci_td),
3632             XHCI_TD_ALIGN, ntd)) {
3633                 parm->err = USB_ERR_NOMEM;
3634                 return;
3635         }
3636         if (parm->buf) {
3637                 for (n = 0; n != ntd; n++) {
3638                         struct xhci_td *td;
3639
3640                         usbd_get_page(pc + n, 0, &page_info);
3641
3642                         td = page_info.buffer;
3643
3644                         /* init TD */
3645                         td->td_self = page_info.physaddr;
3646                         td->obj_next = last_obj;
3647                         td->page_cache = pc + n;
3648
3649                         last_obj = td;
3650
3651                         usb_pc_cpu_flush(pc + n);
3652                 }
3653         }
3654         xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3655
3656         if (!xfer->flags_int.curr_dma_set) {
3657                 xfer->flags_int.curr_dma_set = 1;
3658                 goto alloc_dma_set;
3659         }
3660 }
3661
3662 static usb_error_t
3663 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3664 {
3665         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3666         struct usb_page_search buf_inp;
3667         struct usb_device *udev;
3668         struct xhci_endpoint_ext *pepext;
3669         struct usb_endpoint_descriptor *edesc;
3670         struct usb_page_cache *pcinp;
3671         usb_error_t err;
3672         uint8_t index;
3673         uint8_t epno;
3674
3675         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3676             xfer->endpoint->edesc);
3677
3678         udev = xfer->xroot->udev;
3679         index = udev->controller_slot_id;
3680
3681         pcinp = &sc->sc_hw.devs[index].input_pc;
3682
3683         usbd_get_page(pcinp, 0, &buf_inp);
3684
3685         edesc = xfer->endpoint->edesc;
3686
3687         epno = edesc->bEndpointAddress;
3688
3689         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3690                 epno |= UE_DIR_IN;
3691
3692         epno = XHCI_EPNO2EPID(epno);
3693
3694         if (epno == 0)
3695                 return (USB_ERR_NO_PIPE);               /* invalid */
3696
3697         XHCI_CMD_LOCK(sc);
3698
3699         /* configure endpoint */
3700
3701         err = xhci_configure_endpoint_by_xfer(xfer);
3702
3703         if (err != 0) {
3704                 XHCI_CMD_UNLOCK(sc);
3705                 return (err);
3706         }
3707
3708         /*
3709          * Get the endpoint into the stopped state according to the
3710          * endpoint context state diagram in the XHCI specification:
3711          */
3712
3713         err = xhci_cmd_stop_ep(sc, 0, epno, index);
3714
3715         if (err != 0)
3716                 DPRINTF("Could not stop endpoint %u\n", epno);
3717
3718         err = xhci_cmd_reset_ep(sc, 0, epno, index);
3719
3720         if (err != 0)
3721                 DPRINTF("Could not reset endpoint %u\n", epno);
3722
3723         err = xhci_cmd_set_tr_dequeue_ptr(sc, pepext->physaddr |
3724             XHCI_EPCTX_2_DCS_SET(1), 0, epno, index);
3725
3726         if (err != 0)
3727                 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3728
3729         /*
3730          * Get the endpoint into the running state according to the
3731          * endpoint context state diagram in the XHCI specification:
3732          */
3733
3734         xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3735
3736         err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3737
3738         if (err != 0)
3739                 DPRINTF("Could not configure endpoint %u\n", epno);
3740
3741         err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3742
3743         if (err != 0)
3744                 DPRINTF("Could not configure endpoint %u\n", epno);
3745
3746         XHCI_CMD_UNLOCK(sc);
3747
3748         return (0);
3749 }
3750
3751 static void
3752 xhci_xfer_unsetup(struct usb_xfer *xfer)
3753 {
3754         return;
3755 }
3756
3757 static void
3758 xhci_start_dma_delay(struct usb_xfer *xfer)
3759 {
3760         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3761
3762         /* put transfer on interrupt queue (again) */
3763         usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3764
3765         (void)usb_proc_msignal(&sc->sc_config_proc,
3766             &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3767 }
3768
3769 static void
3770 xhci_configure_msg(struct usb_proc_msg *pm)
3771 {
3772         struct xhci_softc *sc;
3773         struct xhci_endpoint_ext *pepext;
3774         struct usb_xfer *xfer;
3775
3776         sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3777
3778 restart:
3779         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3780
3781                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3782                     xfer->endpoint->edesc);
3783
3784                 if ((pepext->trb_halted != 0) ||
3785                     (pepext->trb_running == 0)) {
3786
3787                         uint8_t i;
3788
3789                         /* clear halted and running */
3790                         pepext->trb_halted = 0;
3791                         pepext->trb_running = 0;
3792
3793                         /* nuke remaining buffered transfers */
3794
3795                         for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
3796                                 /*
3797                                  * NOTE: We need to use the timeout
3798                                  * error code here else existing
3799                                  * isochronous clients can get
3800                                  * confused:
3801                                  */
3802                                 if (pepext->xfer[i] != NULL) {
3803                                         xhci_device_done(pepext->xfer[i],
3804                                             USB_ERR_TIMEOUT);
3805                                 }
3806                         }
3807
3808                         /*
3809                          * NOTE: The USB transfer cannot vanish in
3810                          * this state!
3811                          */
3812
3813                         USB_BUS_UNLOCK(&sc->sc_bus);
3814
3815                         xhci_configure_reset_endpoint(xfer);
3816
3817                         USB_BUS_LOCK(&sc->sc_bus);
3818
3819                         /* check if halted is still cleared */
3820                         if (pepext->trb_halted == 0) {
3821                                 pepext->trb_running = 1;
3822                                 pepext->trb_index = 0;
3823                         }
3824                         goto restart;
3825                 }
3826
3827                 if (xfer->flags_int.did_dma_delay) {
3828
3829                         /* remove transfer from interrupt queue (again) */
3830                         usbd_transfer_dequeue(xfer);
3831
3832                         /* we are finally done */
3833                         usb_dma_delay_done_cb(xfer);
3834
3835                         /* queue changed - restart */
3836                         goto restart;
3837                 }
3838         }
3839
3840         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3841
3842                 /* try to insert xfer on HW queue */
3843                 xhci_transfer_insert(xfer);
3844
3845                 /* try to multi buffer */
3846                 xhci_device_generic_multi_enter(xfer->endpoint, NULL);
3847         }
3848 }
3849
3850 static void
3851 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3852     struct usb_endpoint *ep)
3853 {
3854         struct xhci_endpoint_ext *pepext;
3855
3856         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3857             ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
3858
3859         if (udev->flags.usb_mode != USB_MODE_HOST) {
3860                 /* not supported */
3861                 return;
3862         }
3863         if (udev->parent_hub == NULL) {
3864                 /* root HUB has special endpoint handling */
3865                 return;
3866         }
3867
3868         ep->methods = &xhci_device_generic_methods;
3869
3870         pepext = xhci_get_endpoint_ext(udev, edesc);
3871
3872         USB_BUS_LOCK(udev->bus);
3873         pepext->trb_halted = 1;
3874         pepext->trb_running = 0;
3875         USB_BUS_UNLOCK(udev->bus);
3876 }
3877
3878 static void
3879 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
3880 {
3881
3882 }
3883
3884 static void
3885 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3886 {
3887         struct xhci_endpoint_ext *pepext;
3888
3889         DPRINTF("\n");
3890
3891         if (udev->flags.usb_mode != USB_MODE_HOST) {
3892                 /* not supported */
3893                 return;
3894         }
3895         if (udev->parent_hub == NULL) {
3896                 /* root HUB has special endpoint handling */
3897                 return;
3898         }
3899
3900         pepext = xhci_get_endpoint_ext(udev, ep->edesc);
3901
3902         USB_BUS_LOCK(udev->bus);
3903         pepext->trb_halted = 1;
3904         pepext->trb_running = 0;
3905         USB_BUS_UNLOCK(udev->bus);
3906 }
3907
3908 static usb_error_t
3909 xhci_device_init(struct usb_device *udev)
3910 {
3911         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3912         usb_error_t err;
3913         uint8_t temp;
3914
3915         /* no init for root HUB */
3916         if (udev->parent_hub == NULL)
3917                 return (0);
3918
3919         XHCI_CMD_LOCK(sc);
3920
3921         /* set invalid default */
3922
3923         udev->controller_slot_id = sc->sc_noslot + 1;
3924
3925         /* try to get a new slot ID from the XHCI */
3926
3927         err = xhci_cmd_enable_slot(sc, &temp);
3928
3929         if (err) {
3930                 XHCI_CMD_UNLOCK(sc);
3931                 return (err);
3932         }
3933
3934         if (temp > sc->sc_noslot) {
3935                 XHCI_CMD_UNLOCK(sc);
3936                 return (USB_ERR_BAD_ADDRESS);
3937         }
3938
3939         if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
3940                 DPRINTF("slot %u already allocated.\n", temp);
3941                 XHCI_CMD_UNLOCK(sc);
3942                 return (USB_ERR_BAD_ADDRESS);
3943         }
3944
3945         /* store slot ID for later reference */
3946
3947         udev->controller_slot_id = temp;
3948
3949         /* reset data structure */
3950
3951         memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
3952
3953         /* set mark slot allocated */
3954
3955         sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
3956
3957         err = xhci_alloc_device_ext(udev);
3958
3959         XHCI_CMD_UNLOCK(sc);
3960
3961         /* get device into default state */
3962
3963         if (err == 0)
3964                 err = xhci_set_address(udev, NULL, 0);
3965
3966         return (err);
3967 }
3968
3969 static void
3970 xhci_device_uninit(struct usb_device *udev)
3971 {
3972         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3973         uint8_t index;
3974
3975         /* no init for root HUB */
3976         if (udev->parent_hub == NULL)
3977                 return;
3978
3979         XHCI_CMD_LOCK(sc);
3980
3981         index = udev->controller_slot_id;
3982
3983         if (index <= sc->sc_noslot) {
3984                 xhci_cmd_disable_slot(sc, index);
3985                 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
3986
3987                 /* free device extension */
3988                 xhci_free_device_ext(udev);
3989         }
3990
3991         XHCI_CMD_UNLOCK(sc);
3992 }
3993
3994 static void
3995 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
3996 {
3997         /*
3998          * Wait until the hardware has finished any possible use of
3999          * the transfer descriptor(s)
4000          */
4001         *pus = 2048;                    /* microseconds */
4002 }
4003
4004 static void
4005 xhci_device_resume(struct usb_device *udev)
4006 {
4007         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4008         uint8_t index;
4009         uint8_t n;
4010         uint8_t p;
4011
4012         DPRINTF("\n");
4013
4014         /* check for root HUB */
4015         if (udev->parent_hub == NULL)
4016                 return;
4017
4018         index = udev->controller_slot_id;
4019
4020         XHCI_CMD_LOCK(sc);
4021
4022         /* blindly resume all endpoints */
4023
4024         USB_BUS_LOCK(udev->bus);
4025
4026         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4027                 for (p = 0; p != 1 /*XHCI_MAX_STREAMS*/; p++) {
4028                         XWRITE4(sc, door, XHCI_DOORBELL(index),
4029                             n | XHCI_DB_SID_SET(p));
4030                 }
4031         }
4032
4033         USB_BUS_UNLOCK(udev->bus);
4034
4035         XHCI_CMD_UNLOCK(sc);
4036 }
4037
4038 static void
4039 xhci_device_suspend(struct usb_device *udev)
4040 {
4041         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4042         uint8_t index;
4043         uint8_t n;
4044         usb_error_t err;
4045
4046         DPRINTF("\n");
4047
4048         /* check for root HUB */
4049         if (udev->parent_hub == NULL)
4050                 return;
4051
4052         index = udev->controller_slot_id;
4053
4054         XHCI_CMD_LOCK(sc);
4055
4056         /* blindly suspend all endpoints */
4057
4058         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4059                 err = xhci_cmd_stop_ep(sc, 1, n, index);
4060                 if (err != 0) {
4061                         DPRINTF("Failed to suspend endpoint "
4062                             "%u on slot %u (ignored).\n", n, index);
4063                 }
4064         }
4065
4066         XHCI_CMD_UNLOCK(sc);
4067 }
4068
4069 static void
4070 xhci_set_hw_power(struct usb_bus *bus)
4071 {
4072         DPRINTF("\n");
4073 }
4074
4075 static void
4076 xhci_device_state_change(struct usb_device *udev)
4077 {
4078         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4079         struct usb_page_search buf_inp;
4080         usb_error_t err;
4081         uint8_t index;
4082
4083         /* check for root HUB */
4084         if (udev->parent_hub == NULL)
4085                 return;
4086
4087         index = udev->controller_slot_id;
4088
4089         DPRINTF("\n");
4090
4091         if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4092                 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4093                     &sc->sc_hw.devs[index].tt);
4094                 if (err != 0)
4095                         sc->sc_hw.devs[index].nports = 0;
4096         }
4097
4098         XHCI_CMD_LOCK(sc);
4099
4100         switch (usb_get_device_state(udev)) {
4101         case USB_STATE_POWERED:
4102                 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4103                         break;
4104
4105                 /* set default state */
4106                 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4107
4108                 /* reset number of contexts */
4109                 sc->sc_hw.devs[index].context_num = 0;
4110
4111                 err = xhci_cmd_reset_dev(sc, index);
4112
4113                 if (err != 0) {
4114                         DPRINTF("Device reset failed "
4115                             "for slot %u.\n", index);
4116                 }
4117                 break;
4118
4119         case USB_STATE_ADDRESSED:
4120                 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4121                         break;
4122
4123                 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4124
4125                 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4126
4127                 if (err) {
4128                         DPRINTF("Failed to deconfigure "
4129                             "slot %u.\n", index);
4130                 }
4131                 break;
4132
4133         case USB_STATE_CONFIGURED:
4134                 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4135                         break;
4136
4137                 /* set configured state */
4138                 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4139
4140                 /* reset number of contexts */
4141                 sc->sc_hw.devs[index].context_num = 0;
4142
4143                 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4144
4145                 xhci_configure_mask(udev, 3, 0);
4146
4147                 err = xhci_configure_device(udev);
4148                 if (err != 0) {
4149                         DPRINTF("Could not configure device "
4150                             "at slot %u.\n", index);
4151                 }
4152
4153                 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4154                 if (err != 0) {
4155                         DPRINTF("Could not evaluate device "
4156                             "context at slot %u.\n", index);
4157                 }
4158                 break;
4159
4160         default:
4161                 break;
4162         }
4163         XHCI_CMD_UNLOCK(sc);
4164 }
4165
4166 struct usb_bus_methods xhci_bus_methods = {
4167         .endpoint_init = xhci_ep_init,
4168         .endpoint_uninit = xhci_ep_uninit,
4169         .xfer_setup = xhci_xfer_setup,
4170         .xfer_unsetup = xhci_xfer_unsetup,
4171         .get_dma_delay = xhci_get_dma_delay,
4172         .device_init = xhci_device_init,
4173         .device_uninit = xhci_device_uninit,
4174         .device_resume = xhci_device_resume,
4175         .device_suspend = xhci_device_suspend,
4176         .set_hw_power = xhci_set_hw_power,
4177         .roothub_exec = xhci_roothub_exec,
4178         .xfer_poll = xhci_do_poll,
4179         .start_dma_delay = xhci_start_dma_delay,
4180         .set_address = xhci_set_address,
4181         .clear_stall = xhci_ep_clear_stall,
4182         .device_state_change = xhci_device_state_change,
4183         .set_hw_power_sleep = xhci_set_hw_power_sleep,
4184 };