2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
29 #include <sys/stdint.h>
30 #include <sys/stddef.h>
31 #include <sys/param.h>
32 #include <sys/queue.h>
33 #include <sys/types.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
37 #include <sys/module.h>
39 #include <sys/mutex.h>
40 #include <sys/condvar.h>
41 #include <sys/sysctl.h>
43 #include <sys/unistd.h>
44 #include <sys/callout.h>
45 #include <sys/malloc.h>
48 #include <dev/usb/usb.h>
49 #include <dev/usb/usbdi.h>
51 #include <dev/usb/usb_core.h>
52 #include <dev/usb/usb_busdma.h>
53 #include <dev/usb/usb_process.h>
54 #include <dev/usb/usb_util.h>
56 #include <dev/usb/usb_controller.h>
57 #include <dev/usb/usb_bus.h>
58 #include <dev/usb/usb_pci.h>
59 #include <dev/usb/controller/xhci.h>
60 #include <dev/usb/controller/xhcireg.h>
63 static device_probe_t xhci_pci_probe;
64 static device_attach_t xhci_pci_attach;
65 static device_detach_t xhci_pci_detach;
66 static usb_take_controller_t xhci_pci_take_controller;
68 static device_method_t xhci_device_methods[] = {
69 /* device interface */
70 DEVMETHOD(device_probe, xhci_pci_probe),
71 DEVMETHOD(device_attach, xhci_pci_attach),
72 DEVMETHOD(device_detach, xhci_pci_detach),
73 DEVMETHOD(device_suspend, bus_generic_suspend),
74 DEVMETHOD(device_resume, bus_generic_resume),
75 DEVMETHOD(device_shutdown, bus_generic_shutdown),
76 DEVMETHOD(usb_take_controller, xhci_pci_take_controller),
81 static driver_t xhci_driver = {
83 .methods = xhci_device_methods,
84 .size = sizeof(struct xhci_softc),
87 static devclass_t xhci_devclass;
89 DRIVER_MODULE(xhci, pci, xhci_driver, xhci_devclass, 0, 0);
90 MODULE_DEPEND(xhci, usb, 1, 1, 1);
94 xhci_pci_match(device_t self)
96 uint32_t device_id = pci_get_devid(self);
100 return ("NEC uPD720200 USB 3.0 controller");
103 return ("ASMedia ASM1042 USB 3.0 controller");
106 return ("Intel Intel BayTrail USB 3.0 controller");
109 return ("Intel Panther Point USB 3.0 controller");
111 return ("Intel Lynx Point USB 3.0 controller");
117 if ((pci_get_class(self) == PCIC_SERIALBUS)
118 && (pci_get_subclass(self) == PCIS_SERIALBUS_USB)
119 && (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) {
120 return ("XHCI (generic) USB 3.0 controller");
122 return (NULL); /* dunno */
126 xhci_pci_probe(device_t self)
128 const char *desc = xhci_pci_match(self);
131 device_set_desc(self, desc);
138 static int xhci_use_msi = 1;
139 TUNABLE_INT("hw.usb.xhci.msi", &xhci_use_msi);
142 xhci_interrupt_poll(void *_sc)
144 struct xhci_softc *sc = _sc;
145 USB_BUS_UNLOCK(&sc->sc_bus);
147 USB_BUS_LOCK(&sc->sc_bus);
148 usb_callout_reset(&sc->sc_callout, 1, (void *)&xhci_interrupt_poll, sc);
152 xhci_pci_port_route(device_t self, uint32_t set, uint32_t clear)
158 temp = pci_read_config(self, PCI_XHCI_INTEL_USB3_PSSEN, 4) |
159 pci_read_config(self, PCI_XHCI_INTEL_XUSB2PR, 4);
164 /* Don't set bits which the hardware doesn't support */
165 usb3_mask = pci_read_config(self, PCI_XHCI_INTEL_USB3PRM, 4);
166 usb2_mask = pci_read_config(self, PCI_XHCI_INTEL_USB2PRM, 4);
168 pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp & usb3_mask, 4);
169 pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp & usb2_mask, 4);
171 device_printf(self, "Port routing mask set to 0x%08x\n", temp);
177 xhci_pci_attach(device_t self)
179 struct xhci_softc *sc = device_get_softc(self);
182 /* XXX check for 64-bit capability */
184 if (xhci_init(sc, self)) {
185 device_printf(self, "Could not initialize softc\n");
189 pci_enable_busmaster(self);
191 rid = PCI_XHCI_CBMEM;
192 sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid,
194 if (!sc->sc_io_res) {
195 device_printf(self, "Could not map memory\n");
198 sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
199 sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
200 sc->sc_io_size = rman_get_size(sc->sc_io_res);
202 usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_mtx, 0);
207 if (pci_alloc_msi(self, &count) == 0) {
209 device_printf(self, "MSI enabled\n");
213 sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
214 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
215 if (sc->sc_irq_res == NULL) {
216 pci_release_msi(self);
217 device_printf(self, "Could not allocate IRQ\n");
219 sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
220 if (sc->sc_bus.bdev == NULL) {
221 device_printf(self, "Could not add USB device\n");
224 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
226 sprintf(sc->sc_vendor, "0x%04x", pci_get_vendor(self));
228 if (sc->sc_irq_res != NULL) {
229 err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
230 NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl);
232 bus_release_resource(self, SYS_RES_IRQ,
233 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
234 sc->sc_irq_res = NULL;
235 pci_release_msi(self);
236 device_printf(self, "Could not setup IRQ, err=%d\n", err);
237 sc->sc_intr_hdl = NULL;
240 if (sc->sc_irq_res == NULL || sc->sc_intr_hdl == NULL) {
241 if (xhci_use_polling() != 0) {
242 device_printf(self, "Interrupt polling at %dHz\n", hz);
243 USB_BUS_LOCK(&sc->sc_bus);
244 xhci_interrupt_poll(sc);
245 USB_BUS_UNLOCK(&sc->sc_bus);
250 /* On Intel chipsets reroute ports from EHCI to XHCI controller. */
251 switch (pci_get_devid(self)) {
252 case 0x0f358086: /* BayTrail */
253 case 0x9c318086: /* Panther Point */
254 case 0x1e318086: /* Panther Point */
255 case 0x8c318086: /* Lynx Point */
256 case 0x8cb18086: /* Wildcat Point */
257 sc->sc_port_route = &xhci_pci_port_route;
258 sc->sc_imod_default = XHCI_IMOD_DEFAULT_LP;
264 if (sc->sc_irq_res == NULL || sc->sc_intr_hdl == NULL ||
265 xhci_use_polling() != 0) {
266 device_printf(self, "Interrupt polling at %dHz\n", hz);
267 USB_BUS_LOCK(&sc->sc_bus);
268 xhci_interrupt_poll(sc);
269 USB_BUS_UNLOCK(&sc->sc_bus);
272 xhci_pci_take_controller(self);
274 err = xhci_halt_controller(sc);
277 err = xhci_start_controller(sc);
280 err = device_probe_and_attach(sc->sc_bus.bdev);
283 device_printf(self, "XHCI halt/start/probe failed err=%d\n", err);
289 xhci_pci_detach(self);
294 xhci_pci_detach(device_t self)
296 struct xhci_softc *sc = device_get_softc(self);
298 /* during module unload there are lots of children leftover */
299 device_delete_all_children(self);
302 usb_callout_drain(&sc->sc_callout);
303 xhci_halt_controller(sc);
306 pci_disable_busmaster(self);
308 if (sc->sc_irq_res && sc->sc_intr_hdl) {
309 bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl);
310 sc->sc_intr_hdl = NULL;
312 if (sc->sc_irq_res) {
313 bus_release_resource(self, SYS_RES_IRQ,
314 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
315 sc->sc_irq_res = NULL;
316 pci_release_msi(self);
319 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM,
321 sc->sc_io_res = NULL;
330 xhci_pci_take_controller(device_t self)
332 struct xhci_softc *sc = device_get_softc(self);
339 cparams = XREAD4(sc, capa, XHCI_HCSPARAMS0);
343 /* Synchronise with the BIOS if it owns the controller. */
344 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec);
345 eecp += XHCI_XECP_NEXT(eec) << 2) {
346 eec = XREAD4(sc, capa, eecp);
348 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY)
350 bios_sem = XREAD1(sc, capa, eecp +
354 device_printf(sc->sc_bus.bdev, "waiting for BIOS "
355 "to give up control\n");
356 XWRITE1(sc, capa, eecp +
357 XHCI_XECP_OS_SEM, 1);
360 bios_sem = XREAD1(sc, capa, eecp +
366 device_printf(sc->sc_bus.bdev,
367 "timed out waiting for BIOS\n");
370 usb_pause_mtx(NULL, hz / 100); /* wait 10ms */