2 * Copyright (c) 2008 Weongyo Jeong <weongyo@FreeBSD.org>
4 * Permission to use, copy, modify, and distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <sys/cdefs.h>
18 __FBSDID("$FreeBSD$");
19 #include <sys/param.h>
20 #include <sys/sockio.h>
21 #include <sys/sysctl.h>
23 #include <sys/mutex.h>
25 #include <sys/kernel.h>
26 #include <sys/socket.h>
27 #include <sys/systm.h>
28 #include <sys/malloc.h>
29 #include <sys/module.h>
31 #include <sys/endian.h>
34 #include <machine/bus.h>
35 #include <machine/resource.h>
39 #include <net/if_arp.h>
40 #include <net/ethernet.h>
41 #include <net/if_dl.h>
42 #include <net/if_media.h>
43 #include <net/if_types.h>
46 #include <netinet/in.h>
47 #include <netinet/in_systm.h>
48 #include <netinet/in_var.h>
49 #include <netinet/if_ether.h>
50 #include <netinet/ip.h>
53 #include <net80211/ieee80211_var.h>
54 #include <net80211/ieee80211_regdomain.h>
55 #include <net80211/ieee80211_radiotap.h>
57 #include <dev/usb/usb.h>
58 #include <dev/usb/usbdi.h>
61 #include <dev/usb/wlan/if_urtwreg.h>
62 #include <dev/usb/wlan/if_urtwvar.h>
64 SYSCTL_NODE(_hw_usb, OID_AUTO, urtw, CTLFLAG_RW, 0, "USB Realtek 8187L");
67 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, debug, CTLFLAG_RW, &urtw_debug, 0,
68 "control debugging printfs");
69 TUNABLE_INT("hw.usb.urtw.debug", &urtw_debug);
71 URTW_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
72 URTW_DEBUG_RECV = 0x00000002, /* basic recv operation */
73 URTW_DEBUG_RESET = 0x00000004, /* reset processing */
74 URTW_DEBUG_TX_PROC = 0x00000008, /* tx ISR proc */
75 URTW_DEBUG_RX_PROC = 0x00000010, /* rx ISR proc */
76 URTW_DEBUG_STATE = 0x00000020, /* 802.11 state transitions */
77 URTW_DEBUG_STAT = 0x00000040, /* statistic */
78 URTW_DEBUG_INIT = 0x00000080, /* initialization of dev */
79 URTW_DEBUG_ANY = 0xffffffff
81 #define DPRINTF(sc, m, fmt, ...) do { \
82 if (sc->sc_debug & (m)) \
83 printf(fmt, __VA_ARGS__); \
86 #define DPRINTF(sc, m, fmt, ...) do { \
90 static int urtw_preamble_mode = URTW_PREAMBLE_MODE_LONG;
91 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, preamble_mode, CTLFLAG_RW,
92 &urtw_preamble_mode, 0, "set the preable mode (long or short)");
93 TUNABLE_INT("hw.usb.urtw.preamble_mode", &urtw_preamble_mode);
95 /* recognized device vendors/products */
96 #define urtw_lookup(v, p) \
97 ((const struct urtw_type *)usb_lookup(urtw_devs, v, p))
98 #define URTW_DEV_B(v,p) \
99 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187B) }
100 #define URTW_DEV_L(v,p) \
101 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187L) }
102 #define URTW_REV_RTL8187B 0
103 #define URTW_REV_RTL8187L 1
104 static const struct usb_device_id urtw_devs[] = {
105 { USB_VPI(USB_VENDOR_BELKIN, 0x705e, URTW_REV_RTL8187B) },
106 { USB_VPI(USB_VENDOR_REALTEK, 0x8189, URTW_REV_RTL8187B) },
107 { USB_VPI(USB_VENDOR_REALTEK, 0x8197, URTW_REV_RTL8187B) },
108 { USB_VPI(USB_VENDOR_REALTEK, 0x8198, URTW_REV_RTL8187B) },
109 { USB_VPI(USB_VENDOR_NETGEAR, 0x4260, URTW_REV_RTL8187B) },
110 { USB_VPI(0x1b75, 0x8187, URTW_REV_RTL8187L) },
111 { USB_VPI(USB_VENDOR_ASUS, 0x171d, URTW_REV_RTL8187L) },
112 { USB_VPI(USB_VENDOR_DICKSMITH, 0x9401, URTW_REV_RTL8187L) },
113 { USB_VPI(USB_VENDOR_HP, 0xca02, URTW_REV_RTL8187L) },
114 { USB_VPI(USB_VENDOR_LOGITEC, 0x010c, URTW_REV_RTL8187L) },
115 { USB_VPI(USB_VENDOR_NETGEAR, 0x6100, URTW_REV_RTL8187L) },
116 URTW_DEV_L(NETGEAR, WG111V2),
117 URTW_DEV_L(REALTEK, RTL8187),
118 { USB_VPI(USB_VENDOR_SITECOMEU, 0x000d, URTW_REV_RTL8187L) },
119 { USB_VPI(USB_VENDOR_SITECOMEU, 0x0028, URTW_REV_RTL8187B) },
120 { USB_VPI(USB_VENDOR_SPHAIRON, 0x0150, URTW_REV_RTL8187L) },
121 { USB_VPI(USB_VENDOR_SURECOM, 0x11f2, URTW_REV_RTL8187L) },
122 { USB_VPI(USB_VENDOR_QCOM, 0x6232, URTW_REV_RTL8187L) },
127 #define urtw_read8_m(sc, val, data) do { \
128 error = urtw_read8_c(sc, val, data); \
132 #define urtw_write8_m(sc, val, data) do { \
133 error = urtw_write8_c(sc, val, data); \
137 #define urtw_read16_m(sc, val, data) do { \
138 error = urtw_read16_c(sc, val, data); \
142 #define urtw_write16_m(sc, val, data) do { \
143 error = urtw_write16_c(sc, val, data); \
147 #define urtw_read32_m(sc, val, data) do { \
148 error = urtw_read32_c(sc, val, data); \
152 #define urtw_write32_m(sc, val, data) do { \
153 error = urtw_write32_c(sc, val, data); \
157 #define urtw_8187_write_phy_ofdm(sc, val, data) do { \
158 error = urtw_8187_write_phy_ofdm_c(sc, val, data); \
162 #define urtw_8187_write_phy_cck(sc, val, data) do { \
163 error = urtw_8187_write_phy_cck_c(sc, val, data); \
167 #define urtw_8225_write(sc, val, data) do { \
168 error = urtw_8225_write_c(sc, val, data); \
178 static uint8_t urtw_8225_agc[] = {
179 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9d, 0x9c, 0x9b,
180 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90,
181 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85,
182 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a,
183 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f,
184 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24,
185 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19,
186 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e,
187 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03,
188 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
189 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
190 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01
193 static uint8_t urtw_8225z2_agc[] = {
194 0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57, 0x55, 0x53, 0x51,
195 0x4f, 0x4d, 0x4b, 0x49, 0x47, 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b,
196 0x39, 0x37, 0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27, 0x25,
197 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f,
198 0x0d, 0x0b, 0x09, 0x07, 0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
199 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x19, 0x19,
200 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x20, 0x21, 0x22, 0x23,
201 0x24, 0x25, 0x26, 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x2a, 0x2a,
202 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d, 0x2d, 0x2d, 0x2d,
203 0x2e, 0x2e, 0x2e, 0x2e, 0x2f, 0x2f, 0x2f, 0x30, 0x30, 0x31, 0x31,
204 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31,
205 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31
208 static uint32_t urtw_8225_channel[] = {
209 0x0000, /* dummy channel 0 */
226 static uint8_t urtw_8225_gain[] = {
227 0x23, 0x88, 0x7c, 0xa5, /* -82dbm */
228 0x23, 0x88, 0x7c, 0xb5, /* -82dbm */
229 0x23, 0x88, 0x7c, 0xc5, /* -82dbm */
230 0x33, 0x80, 0x79, 0xc5, /* -78dbm */
231 0x43, 0x78, 0x76, 0xc5, /* -74dbm */
232 0x53, 0x60, 0x73, 0xc5, /* -70dbm */
233 0x63, 0x58, 0x70, 0xc5, /* -66dbm */
236 static struct urtw_pair urtw_8225_rf_part1[] = {
237 { 0x00, 0x0067 }, { 0x01, 0x0fe0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
238 { 0x04, 0x0486 }, { 0x05, 0x0bc0 }, { 0x06, 0x0ae6 }, { 0x07, 0x082a },
239 { 0x08, 0x001f }, { 0x09, 0x0334 }, { 0x0a, 0x0fd4 }, { 0x0b, 0x0391 },
240 { 0x0c, 0x0050 }, { 0x0d, 0x06db }, { 0x0e, 0x0029 }, { 0x0f, 0x0914 },
243 static struct urtw_pair urtw_8225_rf_part2[] = {
244 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 },
245 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 },
246 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x09 }, { 0x0b, 0x80 },
247 { 0x0c, 0x01 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, { 0x10, 0x84 },
248 { 0x11, 0x06 }, { 0x12, 0x20 }, { 0x13, 0x20 }, { 0x14, 0x00 },
249 { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, { 0x18, 0xef },
250 { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x76 }, { 0x1c, 0x04 },
251 { 0x1e, 0x95 }, { 0x1f, 0x75 }, { 0x20, 0x1f }, { 0x21, 0x27 },
252 { 0x22, 0x16 }, { 0x24, 0x46 }, { 0x25, 0x20 }, { 0x26, 0x90 },
256 static struct urtw_pair urtw_8225_rf_part3[] = {
257 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 },
258 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x10, 0x9b },
259 { 0x11, 0x88 }, { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 },
260 { 0x1a, 0xa0 }, { 0x1b, 0x08 }, { 0x40, 0x86 }, { 0x41, 0x8d },
261 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x1f }, { 0x45, 0x1e },
262 { 0x46, 0x1a }, { 0x47, 0x15 }, { 0x48, 0x10 }, { 0x49, 0x0a },
263 { 0x4a, 0x05 }, { 0x4b, 0x02 }, { 0x4c, 0x05 }
266 static uint16_t urtw_8225_rxgain[] = {
267 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
268 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
269 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
270 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
271 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
272 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
273 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
274 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
275 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
276 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
277 0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3,
278 0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb
281 static uint8_t urtw_8225_threshold[] = {
282 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd,
285 static uint8_t urtw_8225_tx_gain_cck_ofdm[] = {
286 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e
289 static uint8_t urtw_8225_txpwr_cck[] = {
290 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02,
291 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02,
292 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02,
293 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02,
294 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03,
295 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03
298 static uint8_t urtw_8225_txpwr_cck_ch14[] = {
299 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00,
300 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00,
301 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00,
302 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00,
303 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00,
304 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00
307 static uint8_t urtw_8225_txpwr_ofdm[]={
308 0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4
311 static uint8_t urtw_8225v2_gain_bg[]={
312 0x23, 0x15, 0xa5, /* -82-1dbm */
313 0x23, 0x15, 0xb5, /* -82-2dbm */
314 0x23, 0x15, 0xc5, /* -82-3dbm */
315 0x33, 0x15, 0xc5, /* -78dbm */
316 0x43, 0x15, 0xc5, /* -74dbm */
317 0x53, 0x15, 0xc5, /* -70dbm */
318 0x63, 0x15, 0xc5, /* -66dbm */
321 static struct urtw_pair urtw_8225v2_rf_part1[] = {
322 { 0x00, 0x02bf }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
323 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a },
324 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb },
325 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }
328 static struct urtw_pair urtw_8225v2b_rf_part1[] = {
329 { 0x00, 0x00b7 }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
330 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a },
331 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb },
332 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }
335 static struct urtw_pair urtw_8225v2_rf_part2[] = {
336 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 },
337 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 },
338 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x08 }, { 0x0b, 0x80 },
339 { 0x0c, 0x01 }, { 0x0d, 0x43 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 },
340 { 0x10, 0x84 }, { 0x11, 0x07 }, { 0x12, 0x20 }, { 0x13, 0x20 },
341 { 0x14, 0x00 }, { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 },
342 { 0x18, 0xef }, { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x15 },
343 { 0x1c, 0x04 }, { 0x1d, 0xc5 }, { 0x1e, 0x95 }, { 0x1f, 0x75 },
344 { 0x20, 0x1f }, { 0x21, 0x17 }, { 0x22, 0x16 }, { 0x23, 0x80 },
345 { 0x24, 0x46 }, { 0x25, 0x00 }, { 0x26, 0x90 }, { 0x27, 0x88 }
348 static struct urtw_pair urtw_8225v2b_rf_part2[] = {
349 { 0x00, 0x10 }, { 0x01, 0x0d }, { 0x02, 0x01 }, { 0x03, 0x00 },
350 { 0x04, 0x14 }, { 0x05, 0xfb }, { 0x06, 0xfb }, { 0x07, 0x60 },
351 { 0x08, 0x00 }, { 0x09, 0x60 }, { 0x0a, 0x00 }, { 0x0b, 0x00 },
352 { 0x0c, 0x00 }, { 0x0d, 0x5c }, { 0x0e, 0x00 }, { 0x0f, 0x00 },
353 { 0x10, 0x40 }, { 0x11, 0x00 }, { 0x12, 0x40 }, { 0x13, 0x00 },
354 { 0x14, 0x00 }, { 0x15, 0x00 }, { 0x16, 0xa8 }, { 0x17, 0x26 },
355 { 0x18, 0x32 }, { 0x19, 0x33 }, { 0x1a, 0x07 }, { 0x1b, 0xa5 },
356 { 0x1c, 0x6f }, { 0x1d, 0x55 }, { 0x1e, 0xc8 }, { 0x1f, 0xb3 },
357 { 0x20, 0x0a }, { 0x21, 0xe1 }, { 0x22, 0x2C }, { 0x23, 0x8a },
358 { 0x24, 0x86 }, { 0x25, 0x83 }, { 0x26, 0x34 }, { 0x27, 0x0f },
359 { 0x28, 0x4f }, { 0x29, 0x24 }, { 0x2a, 0x6f }, { 0x2b, 0xc2 },
360 { 0x2c, 0x6b }, { 0x2d, 0x40 }, { 0x2e, 0x80 }, { 0x2f, 0x00 },
361 { 0x30, 0xc0 }, { 0x31, 0xc1 }, { 0x32, 0x58 }, { 0x33, 0xf1 },
362 { 0x34, 0x00 }, { 0x35, 0xe4 }, { 0x36, 0x90 }, { 0x37, 0x3e },
363 { 0x38, 0x6d }, { 0x39, 0x3c }, { 0x3a, 0xfb }, { 0x3b, 0x07 }
366 static struct urtw_pair urtw_8225v2_rf_part3[] = {
367 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 },
368 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x09, 0x11 },
369 { 0x0a, 0x17 }, { 0x0b, 0x11 }, { 0x10, 0x9b }, { 0x11, 0x88 },
370 { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, { 0x1a, 0xa0 },
371 { 0x1b, 0x08 }, { 0x1d, 0x00 }, { 0x40, 0x86 }, { 0x41, 0x9d },
372 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x36 }, { 0x45, 0x35 },
373 { 0x46, 0x2e }, { 0x47, 0x25 }, { 0x48, 0x1c }, { 0x49, 0x12 },
374 { 0x4a, 0x09 }, { 0x4b, 0x04 }, { 0x4c, 0x05 }
377 static uint16_t urtw_8225v2_rxgain[] = {
378 0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0008, 0x0009,
379 0x000a, 0x000b, 0x0102, 0x0103, 0x0104, 0x0105, 0x0140, 0x0141,
380 0x0142, 0x0143, 0x0144, 0x0145, 0x0180, 0x0181, 0x0182, 0x0183,
381 0x0184, 0x0185, 0x0188, 0x0189, 0x018a, 0x018b, 0x0243, 0x0244,
382 0x0245, 0x0280, 0x0281, 0x0282, 0x0283, 0x0284, 0x0285, 0x0288,
383 0x0289, 0x028a, 0x028b, 0x028c, 0x0342, 0x0343, 0x0344, 0x0345,
384 0x0380, 0x0381, 0x0382, 0x0383, 0x0384, 0x0385, 0x0388, 0x0389,
385 0x038a, 0x038b, 0x038c, 0x038d, 0x0390, 0x0391, 0x0392, 0x0393,
386 0x0394, 0x0395, 0x0398, 0x0399, 0x039a, 0x039b, 0x039c, 0x039d,
387 0x03a0, 0x03a1, 0x03a2, 0x03a3, 0x03a4, 0x03a5, 0x03a8, 0x03a9,
388 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
389 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
392 static uint16_t urtw_8225v2b_rxgain[] = {
393 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
394 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
395 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
396 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
397 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
398 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
399 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
400 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
401 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
402 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
403 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
404 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
407 static uint8_t urtw_8225v2_tx_gain_cck_ofdm[] = {
408 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
409 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b,
410 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11,
411 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
412 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d,
413 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23,
416 static uint8_t urtw_8225v2_txpwr_cck[] = {
417 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04
420 static uint8_t urtw_8225v2_txpwr_cck_ch14[] = {
421 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00
424 static uint8_t urtw_8225v2b_txpwr_cck[] = {
425 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04,
426 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03,
427 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03,
428 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03
431 static uint8_t urtw_8225v2b_txpwr_cck_ch14[] = {
432 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00,
433 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00,
434 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00,
435 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00
438 static struct urtw_pair urtw_ratetable[] = {
439 { 2, 0 }, { 4, 1 }, { 11, 2 }, { 12, 4 }, { 18, 5 },
440 { 22, 3 }, { 24, 6 }, { 36, 7 }, { 48, 8 }, { 72, 9 },
441 { 96, 10 }, { 108, 11 }
444 static const uint8_t urtw_8187b_reg_table[][3] = {
445 { 0xf0, 0x32, 0 }, { 0xf1, 0x32, 0 }, { 0xf2, 0x00, 0 },
446 { 0xf3, 0x00, 0 }, { 0xf4, 0x32, 0 }, { 0xf5, 0x43, 0 },
447 { 0xf6, 0x00, 0 }, { 0xf7, 0x00, 0 }, { 0xf8, 0x46, 0 },
448 { 0xf9, 0xa4, 0 }, { 0xfa, 0x00, 0 }, { 0xfb, 0x00, 0 },
449 { 0xfc, 0x96, 0 }, { 0xfd, 0xa4, 0 }, { 0xfe, 0x00, 0 },
450 { 0xff, 0x00, 0 }, { 0x58, 0x4b, 1 }, { 0x59, 0x00, 1 },
451 { 0x5a, 0x4b, 1 }, { 0x5b, 0x00, 1 }, { 0x60, 0x4b, 1 },
452 { 0x61, 0x09, 1 }, { 0x62, 0x4b, 1 }, { 0x63, 0x09, 1 },
453 { 0xce, 0x0f, 1 }, { 0xcf, 0x00, 1 }, { 0xe0, 0xff, 1 },
454 { 0xe1, 0x0f, 1 }, { 0xe2, 0x00, 1 }, { 0xf0, 0x4e, 1 },
455 { 0xf1, 0x01, 1 }, { 0xf2, 0x02, 1 }, { 0xf3, 0x03, 1 },
456 { 0xf4, 0x04, 1 }, { 0xf5, 0x05, 1 }, { 0xf6, 0x06, 1 },
457 { 0xf7, 0x07, 1 }, { 0xf8, 0x08, 1 }, { 0x4e, 0x00, 2 },
458 { 0x0c, 0x04, 2 }, { 0x21, 0x61, 2 }, { 0x22, 0x68, 2 },
459 { 0x23, 0x6f, 2 }, { 0x24, 0x76, 2 }, { 0x25, 0x7d, 2 },
460 { 0x26, 0x84, 2 }, { 0x27, 0x8d, 2 }, { 0x4d, 0x08, 2 },
461 { 0x50, 0x05, 2 }, { 0x51, 0xf5, 2 }, { 0x52, 0x04, 2 },
462 { 0x53, 0xa0, 2 }, { 0x54, 0x1f, 2 }, { 0x55, 0x23, 2 },
463 { 0x56, 0x45, 2 }, { 0x57, 0x67, 2 }, { 0x58, 0x08, 2 },
464 { 0x59, 0x08, 2 }, { 0x5a, 0x08, 2 }, { 0x5b, 0x08, 2 },
465 { 0x60, 0x08, 2 }, { 0x61, 0x08, 2 }, { 0x62, 0x08, 2 },
466 { 0x63, 0x08, 2 }, { 0x64, 0xcf, 2 }, { 0x72, 0x56, 2 },
467 { 0x73, 0x9a, 2 }, { 0x34, 0xf0, 0 }, { 0x35, 0x0f, 0 },
468 { 0x5b, 0x40, 0 }, { 0x84, 0x88, 0 }, { 0x85, 0x24, 0 },
469 { 0x88, 0x54, 0 }, { 0x8b, 0xb8, 0 }, { 0x8c, 0x07, 0 },
470 { 0x8d, 0x00, 0 }, { 0x94, 0x1b, 0 }, { 0x95, 0x12, 0 },
471 { 0x96, 0x00, 0 }, { 0x97, 0x06, 0 }, { 0x9d, 0x1a, 0 },
472 { 0x9f, 0x10, 0 }, { 0xb4, 0x22, 0 }, { 0xbe, 0x80, 0 },
473 { 0xdb, 0x00, 0 }, { 0xee, 0x00, 0 }, { 0x91, 0x03, 0 },
474 { 0x4c, 0x00, 2 }, { 0x9f, 0x00, 3 }, { 0x8c, 0x01, 0 },
475 { 0x8d, 0x10, 0 }, { 0x8e, 0x08, 0 }, { 0x8f, 0x00, 0 }
478 static usb_callback_t urtw_bulk_rx_callback;
479 static usb_callback_t urtw_bulk_tx_callback;
481 static const struct usb_config urtw_8187b_usbconfig[URTW_8187B_N_XFERS] = {
482 [URTW_8187B_BULK_RX] = {
485 .direction = UE_DIR_IN,
492 .callback = urtw_bulk_rx_callback
494 [URTW_8187B_BULK_TX_BE] = {
496 .endpoint = URTW_8187B_TXPIPE_BE,
497 .direction = UE_DIR_OUT,
498 .bufsize = URTW_TX_MAXSIZE,
501 .force_short_xfer = 1,
504 .callback = urtw_bulk_tx_callback,
505 .timeout = URTW_DATA_TIMEOUT
507 [URTW_8187B_BULK_TX_BK] = {
509 .endpoint = URTW_8187B_TXPIPE_BK,
510 .direction = UE_DIR_OUT,
511 .bufsize = URTW_TX_MAXSIZE,
514 .force_short_xfer = 1,
517 .callback = urtw_bulk_tx_callback,
518 .timeout = URTW_DATA_TIMEOUT
520 [URTW_8187B_BULK_TX_VI] = {
522 .endpoint = URTW_8187B_TXPIPE_VI,
523 .direction = UE_DIR_OUT,
524 .bufsize = URTW_TX_MAXSIZE,
527 .force_short_xfer = 1,
530 .callback = urtw_bulk_tx_callback,
531 .timeout = URTW_DATA_TIMEOUT
533 [URTW_8187B_BULK_TX_VO] = {
535 .endpoint = URTW_8187B_TXPIPE_VO,
536 .direction = UE_DIR_OUT,
537 .bufsize = URTW_TX_MAXSIZE,
540 .force_short_xfer = 1,
543 .callback = urtw_bulk_tx_callback,
544 .timeout = URTW_DATA_TIMEOUT
546 [URTW_8187B_BULK_TX_EP12] = {
549 .direction = UE_DIR_OUT,
550 .bufsize = URTW_TX_MAXSIZE,
553 .force_short_xfer = 1,
556 .callback = urtw_bulk_tx_callback,
557 .timeout = URTW_DATA_TIMEOUT
561 static const struct usb_config urtw_8187l_usbconfig[URTW_8187L_N_XFERS] = {
562 [URTW_8187L_BULK_RX] = {
565 .direction = UE_DIR_IN,
572 .callback = urtw_bulk_rx_callback
574 [URTW_8187L_BULK_TX_LOW] = {
577 .direction = UE_DIR_OUT,
578 .bufsize = URTW_TX_MAXSIZE,
581 .force_short_xfer = 1,
584 .callback = urtw_bulk_tx_callback,
585 .timeout = URTW_DATA_TIMEOUT
587 [URTW_8187L_BULK_TX_NORMAL] = {
590 .direction = UE_DIR_OUT,
591 .bufsize = URTW_TX_MAXSIZE,
594 .force_short_xfer = 1,
597 .callback = urtw_bulk_tx_callback,
598 .timeout = URTW_DATA_TIMEOUT
602 static struct ieee80211vap *urtw_vap_create(struct ieee80211com *,
603 const char name[IFNAMSIZ], int unit, int opmode,
604 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN],
605 const uint8_t mac[IEEE80211_ADDR_LEN]);
606 static void urtw_vap_delete(struct ieee80211vap *);
607 static void urtw_init(void *);
608 static void urtw_stop(struct ifnet *, int);
609 static void urtw_stop_locked(struct ifnet *, int);
610 static int urtw_ioctl(struct ifnet *, u_long, caddr_t);
611 static void urtw_start(struct ifnet *);
612 static int urtw_alloc_rx_data_list(struct urtw_softc *);
613 static int urtw_alloc_tx_data_list(struct urtw_softc *);
614 static int urtw_raw_xmit(struct ieee80211_node *, struct mbuf *,
615 const struct ieee80211_bpf_params *);
616 static void urtw_scan_start(struct ieee80211com *);
617 static void urtw_scan_end(struct ieee80211com *);
618 static void urtw_set_channel(struct ieee80211com *);
619 static void urtw_update_mcast(struct ifnet *);
620 static int urtw_tx_start(struct urtw_softc *,
621 struct ieee80211_node *, struct mbuf *,
622 struct urtw_data *, int);
623 static int urtw_newstate(struct ieee80211vap *,
624 enum ieee80211_state, int);
625 static void urtw_led_ch(void *);
626 static void urtw_ledtask(void *, int);
627 static void urtw_watchdog(void *);
628 static void urtw_set_multi(void *);
629 static int urtw_isbmode(uint16_t);
630 static uint16_t urtw_rate2rtl(int);
631 static uint16_t urtw_rtl2rate(int);
632 static usb_error_t urtw_set_rate(struct urtw_softc *);
633 static usb_error_t urtw_update_msr(struct urtw_softc *);
634 static usb_error_t urtw_read8_c(struct urtw_softc *, int, uint8_t *);
635 static usb_error_t urtw_read16_c(struct urtw_softc *, int, uint16_t *);
636 static usb_error_t urtw_read32_c(struct urtw_softc *, int, uint32_t *);
637 static usb_error_t urtw_write8_c(struct urtw_softc *, int, uint8_t);
638 static usb_error_t urtw_write16_c(struct urtw_softc *, int, uint16_t);
639 static usb_error_t urtw_write32_c(struct urtw_softc *, int, uint32_t);
640 static usb_error_t urtw_eprom_cs(struct urtw_softc *, int);
641 static usb_error_t urtw_eprom_ck(struct urtw_softc *);
642 static usb_error_t urtw_eprom_sendbits(struct urtw_softc *, int16_t *,
644 static usb_error_t urtw_eprom_read32(struct urtw_softc *, uint32_t,
646 static usb_error_t urtw_eprom_readbit(struct urtw_softc *, int16_t *);
647 static usb_error_t urtw_eprom_writebit(struct urtw_softc *, int16_t);
648 static usb_error_t urtw_get_macaddr(struct urtw_softc *);
649 static usb_error_t urtw_get_txpwr(struct urtw_softc *);
650 static usb_error_t urtw_get_rfchip(struct urtw_softc *);
651 static usb_error_t urtw_led_init(struct urtw_softc *);
652 static usb_error_t urtw_8185_rf_pins_enable(struct urtw_softc *);
653 static usb_error_t urtw_8185_tx_antenna(struct urtw_softc *, uint8_t);
654 static usb_error_t urtw_8187_write_phy(struct urtw_softc *, uint8_t,
656 static usb_error_t urtw_8187_write_phy_ofdm_c(struct urtw_softc *,
658 static usb_error_t urtw_8187_write_phy_cck_c(struct urtw_softc *, uint8_t,
660 static usb_error_t urtw_8225_setgain(struct urtw_softc *, int16_t);
661 static usb_error_t urtw_8225_usb_init(struct urtw_softc *);
662 static usb_error_t urtw_8225_write_c(struct urtw_softc *, uint8_t,
664 static usb_error_t urtw_8225_write_s16(struct urtw_softc *, uint8_t, int,
666 static usb_error_t urtw_8225_read(struct urtw_softc *, uint8_t,
668 static usb_error_t urtw_8225_rf_init(struct urtw_softc *);
669 static usb_error_t urtw_8225_rf_set_chan(struct urtw_softc *, int);
670 static usb_error_t urtw_8225_rf_set_sens(struct urtw_softc *, int);
671 static usb_error_t urtw_8225_set_txpwrlvl(struct urtw_softc *, int);
672 static usb_error_t urtw_8225_rf_stop(struct urtw_softc *);
673 static usb_error_t urtw_8225v2_rf_init(struct urtw_softc *);
674 static usb_error_t urtw_8225v2_rf_set_chan(struct urtw_softc *, int);
675 static usb_error_t urtw_8225v2_set_txpwrlvl(struct urtw_softc *, int);
676 static usb_error_t urtw_8225v2_setgain(struct urtw_softc *, int16_t);
677 static usb_error_t urtw_8225_isv2(struct urtw_softc *, int *);
678 static usb_error_t urtw_8225v2b_rf_init(struct urtw_softc *);
679 static usb_error_t urtw_8225v2b_rf_set_chan(struct urtw_softc *, int);
680 static usb_error_t urtw_read8e(struct urtw_softc *, int, uint8_t *);
681 static usb_error_t urtw_write8e(struct urtw_softc *, int, uint8_t);
682 static usb_error_t urtw_8180_set_anaparam(struct urtw_softc *, uint32_t);
683 static usb_error_t urtw_8185_set_anaparam2(struct urtw_softc *, uint32_t);
684 static usb_error_t urtw_intr_enable(struct urtw_softc *);
685 static usb_error_t urtw_intr_disable(struct urtw_softc *);
686 static usb_error_t urtw_reset(struct urtw_softc *);
687 static usb_error_t urtw_led_on(struct urtw_softc *, int);
688 static usb_error_t urtw_led_ctl(struct urtw_softc *, int);
689 static usb_error_t urtw_led_blink(struct urtw_softc *);
690 static usb_error_t urtw_led_mode0(struct urtw_softc *, int);
691 static usb_error_t urtw_led_mode1(struct urtw_softc *, int);
692 static usb_error_t urtw_led_mode2(struct urtw_softc *, int);
693 static usb_error_t urtw_led_mode3(struct urtw_softc *, int);
694 static usb_error_t urtw_rx_setconf(struct urtw_softc *);
695 static usb_error_t urtw_rx_enable(struct urtw_softc *);
696 static usb_error_t urtw_tx_enable(struct urtw_softc *sc);
697 static void urtw_free_tx_data_list(struct urtw_softc *);
698 static void urtw_free_rx_data_list(struct urtw_softc *);
699 static void urtw_free_data_list(struct urtw_softc *,
700 struct urtw_data data[], int, int);
701 static usb_error_t urtw_adapter_start(struct urtw_softc *);
702 static usb_error_t urtw_adapter_start_b(struct urtw_softc *);
703 static usb_error_t urtw_set_mode(struct urtw_softc *, uint32_t);
704 static usb_error_t urtw_8187b_cmd_reset(struct urtw_softc *);
705 static usb_error_t urtw_write16_i(struct urtw_softc *, int, uint16_t, int);
706 static usb_error_t urtw_write8_i(struct urtw_softc *, int, uint8_t, int);
707 static usb_error_t urtw_write32_i(struct urtw_softc *, int, uint32_t, int);
708 static usb_error_t urtw_do_request(struct urtw_softc *,
709 struct usb_device_request *, void *);
710 static usb_error_t urtw_8225v2b_set_txpwrlvl(struct urtw_softc *, int);
711 static usb_error_t urtw_led_off(struct urtw_softc *, int);
712 static void urtw_abort_xfers(struct urtw_softc *);
713 static struct urtw_data *
714 urtw_getbuf(struct urtw_softc *sc);
717 urtw_match(device_t dev)
719 struct usb_attach_arg *uaa = device_get_ivars(dev);
721 if (uaa->usb_mode != USB_MODE_HOST)
723 if (uaa->info.bConfigIndex != URTW_CONFIG_INDEX)
725 if (uaa->info.bIfaceIndex != URTW_IFACE_INDEX)
728 return (usbd_lookup_id_by_uaa(urtw_devs, sizeof(urtw_devs), uaa));
732 urtw_attach(device_t dev)
734 const struct usb_config *setup_start;
736 struct urtw_softc *sc = device_get_softc(dev);
737 struct usb_attach_arg *uaa = device_get_ivars(dev);
738 struct ieee80211com *ic;
740 uint8_t bands, iface_index = URTW_IFACE_INDEX; /* XXX */
745 device_set_usb_desc(dev);
748 sc->sc_udev = uaa->device;
749 if (USB_GET_DRIVER_INFO(uaa) == URTW_REV_RTL8187B)
750 sc->sc_flags |= URTW_RTL8187B;
752 sc->sc_debug = urtw_debug;
755 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->sc_dev), MTX_NETWORK_LOCK,
757 usb_callout_init_mtx(&sc->sc_led_ch, &sc->sc_mtx, 0);
758 TASK_INIT(&sc->sc_led_task, 0, urtw_ledtask, sc);
759 callout_init(&sc->sc_watchdog_ch, 0);
761 if (sc->sc_flags & URTW_RTL8187B) {
762 setup_start = urtw_8187b_usbconfig;
763 n_setup = URTW_8187B_N_XFERS;
765 setup_start = urtw_8187l_usbconfig;
766 n_setup = URTW_8187L_N_XFERS;
769 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
770 setup_start, n_setup, sc, &sc->sc_mtx);
772 device_printf(dev, "could not allocate USB transfers, "
773 "err=%s\n", usbd_errstr(error));
780 urtw_read32_m(sc, URTW_RX, &data);
781 sc->sc_epromtype = (data & URTW_RX_9356SEL) ? URTW_EEPROM_93C56 :
784 error = urtw_get_rfchip(sc);
787 error = urtw_get_macaddr(sc);
790 error = urtw_get_txpwr(sc);
793 error = urtw_led_init(sc);
799 sc->sc_rts_retry = URTW_DEFAULT_RTS_RETRY;
800 sc->sc_tx_retry = URTW_DEFAULT_TX_RETRY;
802 sc->sc_preamble_mode = urtw_preamble_mode;
804 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
806 device_printf(sc->sc_dev, "can not allocate ifnet\n");
812 if_initname(ifp, "urtw", device_get_unit(sc->sc_dev));
813 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
814 ifp->if_init = urtw_init;
815 ifp->if_ioctl = urtw_ioctl;
816 ifp->if_start = urtw_start;
817 /* XXX URTW_TX_DATA_LIST_COUNT */
818 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
819 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
820 IFQ_SET_READY(&ifp->if_snd);
824 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
825 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
827 /* set device capabilities */
829 IEEE80211_C_STA | /* station mode */
830 IEEE80211_C_MONITOR | /* monitor mode supported */
831 IEEE80211_C_TXPMGT | /* tx power management */
832 IEEE80211_C_SHPREAMBLE | /* short preamble supported */
833 IEEE80211_C_SHSLOT | /* short slot time supported */
834 IEEE80211_C_BGSCAN | /* capable of bg scanning */
835 IEEE80211_C_WPA; /* 802.11i */
838 setbit(&bands, IEEE80211_MODE_11B);
839 setbit(&bands, IEEE80211_MODE_11G);
840 ieee80211_init_channels(ic, NULL, &bands);
842 ieee80211_ifattach(ic, sc->sc_bssid);
843 ic->ic_raw_xmit = urtw_raw_xmit;
844 ic->ic_scan_start = urtw_scan_start;
845 ic->ic_scan_end = urtw_scan_end;
846 ic->ic_set_channel = urtw_set_channel;
848 ic->ic_vap_create = urtw_vap_create;
849 ic->ic_vap_delete = urtw_vap_delete;
850 ic->ic_update_mcast = urtw_update_mcast;
852 ieee80211_radiotap_attach(ic,
853 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap),
854 URTW_TX_RADIOTAP_PRESENT,
855 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
856 URTW_RX_RADIOTAP_PRESENT);
859 ieee80211_announce(ic);
862 fail: URTW_UNLOCK(sc);
863 fail1: usbd_transfer_unsetup(sc->sc_xfer, (sc->sc_flags & URTW_RTL8187B) ?
864 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS);
870 urtw_detach(device_t dev)
872 struct urtw_softc *sc = device_get_softc(dev);
873 struct ifnet *ifp = sc->sc_ifp;
874 struct ieee80211com *ic = ifp->if_l2com;
876 if (!device_is_attached(dev))
880 ieee80211_draintask(ic, &sc->sc_led_task);
882 usb_callout_drain(&sc->sc_led_ch);
883 callout_drain(&sc->sc_watchdog_ch);
885 usbd_transfer_unsetup(sc->sc_xfer, (sc->sc_flags & URTW_RTL8187B) ?
886 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS);
887 ieee80211_ifdetach(ic);
889 urtw_free_tx_data_list(sc);
890 urtw_free_rx_data_list(sc);
893 mtx_destroy(&sc->sc_mtx);
899 urtw_free_tx_data_list(struct urtw_softc *sc)
902 urtw_free_data_list(sc, sc->sc_tx, URTW_TX_DATA_LIST_COUNT, 0);
906 urtw_free_rx_data_list(struct urtw_softc *sc)
909 urtw_free_data_list(sc, sc->sc_rx, URTW_RX_DATA_LIST_COUNT, 1);
913 urtw_free_data_list(struct urtw_softc *sc, struct urtw_data data[], int ndata,
918 for (i = 0; i < ndata; i++) {
919 struct urtw_data *dp = &data[i];
928 if (dp->buf != NULL) {
929 free(dp->buf, M_USBDEV);
933 if (dp->ni != NULL) {
934 ieee80211_free_node(dp->ni);
940 static struct ieee80211vap *
941 urtw_vap_create(struct ieee80211com *ic,
942 const char name[IFNAMSIZ], int unit, int opmode, int flags,
943 const uint8_t bssid[IEEE80211_ADDR_LEN],
944 const uint8_t mac[IEEE80211_ADDR_LEN])
946 struct urtw_vap *uvp;
947 struct ieee80211vap *vap;
949 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
951 uvp = (struct urtw_vap *) malloc(sizeof(struct urtw_vap),
952 M_80211_VAP, M_NOWAIT | M_ZERO);
956 /* enable s/w bmiss handling for sta mode */
957 ieee80211_vap_setup(ic, vap, name, unit, opmode,
958 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac);
960 /* override state transition machine */
961 uvp->newstate = vap->iv_newstate;
962 vap->iv_newstate = urtw_newstate;
965 ieee80211_vap_attach(vap, ieee80211_media_change,
966 ieee80211_media_status);
967 ic->ic_opmode = opmode;
972 urtw_vap_delete(struct ieee80211vap *vap)
974 struct urtw_vap *uvp = URTW_VAP(vap);
976 ieee80211_vap_detach(vap);
977 free(uvp, M_80211_VAP);
981 urtw_init_locked(void *arg)
984 struct urtw_softc *sc = arg;
985 struct ifnet *ifp = sc->sc_ifp;
988 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
989 urtw_stop_locked(ifp, 0);
991 error = (sc->sc_flags & URTW_RTL8187B) ? urtw_adapter_start_b(sc) :
992 urtw_adapter_start(sc);
996 /* reset softc variables */
999 if (!(sc->sc_flags & URTW_INIT_ONCE)) {
1000 ret = urtw_alloc_rx_data_list(sc);
1003 ret = urtw_alloc_tx_data_list(sc);
1006 sc->sc_flags |= URTW_INIT_ONCE;
1009 error = urtw_rx_enable(sc);
1012 error = urtw_tx_enable(sc);
1016 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1017 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1019 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc);
1025 urtw_init(void *arg)
1027 struct urtw_softc *sc = arg;
1030 urtw_init_locked(arg);
1035 urtw_adapter_start_b(struct urtw_softc *sc)
1037 #define N(a) (sizeof(a) / sizeof((a)[0]))
1042 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1046 urtw_read8_m(sc, URTW_CONFIG3, &data8);
1047 urtw_write8_m(sc, URTW_CONFIG3,
1048 data8 | URTW_CONFIG3_ANAPARAM_WRITE | URTW_CONFIG3_GNT_SELECT);
1049 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8187B_8225_ANAPARAM2_ON);
1050 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_ON);
1051 urtw_write8_m(sc, URTW_ANAPARAM3, URTW_8187B_8225_ANAPARAM3_ON);
1053 urtw_write8_m(sc, 0x61, 0x10);
1054 urtw_read8_m(sc, 0x62, &data8);
1055 urtw_write8_m(sc, 0x62, data8 & ~(1 << 5));
1056 urtw_write8_m(sc, 0x62, data8 | (1 << 5));
1058 urtw_read8_m(sc, URTW_CONFIG3, &data8);
1059 data8 &= ~URTW_CONFIG3_ANAPARAM_WRITE;
1060 urtw_write8_m(sc, URTW_CONFIG3, data8);
1062 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1066 error = urtw_8187b_cmd_reset(sc);
1070 urtw_write16_m(sc, 0x2d, 0xfff);
1071 urtw_read8_m(sc, URTW_CW_CONF, &data8);
1072 urtw_write8_m(sc, URTW_CW_CONF, data8 | URTW_CW_CONF_PERPACKET_RETRY);
1073 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8);
1074 data8 |= URTW_TX_AGC_CTL_PERPACKET_GAIN |
1075 URTW_TX_AGC_CTL_PERPACKET_ANTSEL;
1076 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8);
1078 error = urtw_write16_i(sc, 0xe0, 0xfff, 1);
1082 urtw_read8_m(sc, URTW_RATE_FALLBACK, &data8);
1083 urtw_write8_m(sc, URTW_RATE_FALLBACK, data8 | URTW_RATE_FALLBACK_ENABLE);
1085 urtw_write16_m(sc, URTW_ATIM_WND, 2);
1086 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100);
1087 error = urtw_write16_i(sc, 0xd4, 0xffff, 1);
1091 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1094 urtw_read8_m(sc, URTW_CONFIG1, &data8);
1095 urtw_write8_m(sc, URTW_CONFIG1, (data8 & 0x3f) | 0x80);
1096 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1100 urtw_write8_m(sc, URTW_WPA_CONFIG, 0);
1101 for (i = 0; i < N(urtw_8187b_reg_table); i++) {
1102 error = urtw_write8_i(sc, urtw_8187b_reg_table[i][0],
1103 urtw_8187b_reg_table[i][1], urtw_8187b_reg_table[i][2]);
1108 urtw_write16_m(sc, URTW_TID_AC_MAP, 0xfa50);
1109 urtw_write16_m(sc, URTW_INT_MIG, 0);
1111 error = urtw_write32_i(sc, 0xf0, 0, 1);
1114 error = urtw_write32_i(sc, 0xf4, 0, 1);
1117 error = urtw_write8_i(sc, 0xf8, 0, 1);
1121 urtw_write32_m(sc, URTW_RF_TIMING, 0x00004001);
1123 error = urtw_write16_i(sc, 0x72, 0x569a, 2);
1127 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1130 urtw_read8_m(sc, URTW_CONFIG3, &data8);
1131 urtw_write8_m(sc, URTW_CONFIG3, data8 | URTW_CONFIG3_ANAPARAM_WRITE);
1132 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1136 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0480);
1137 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x2488);
1138 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1fff);
1139 usb_pause_mtx(&sc->sc_mtx, 100);
1141 error = sc->sc_rf_init(sc);
1145 error = urtw_intr_enable(sc);
1149 error = urtw_write8e(sc, 0x41, 0xf4);
1152 error = urtw_write8e(sc, 0x40, 0x00);
1155 error = urtw_write8e(sc, 0x42, 0x00);
1158 error = urtw_write8e(sc, 0x42, 0x01);
1161 error = urtw_write8e(sc, 0x40, 0x0f);
1164 error = urtw_write8e(sc, 0x42, 0x00);
1167 error = urtw_write8e(sc, 0x42, 0x01);
1171 urtw_read8_m(sc, 0xdb, &data8);
1172 urtw_write8_m(sc, 0xdb, data8 | (1 << 2));
1173 error = urtw_write16_i(sc, 0x72, 0x59fa, 3);
1176 error = urtw_write16_i(sc, 0x74, 0x59d2, 3);
1179 error = urtw_write16_i(sc, 0x76, 0x59d2, 3);
1182 error = urtw_write16_i(sc, 0x78, 0x19fa, 3);
1185 error = urtw_write16_i(sc, 0x7a, 0x19fa, 3);
1188 error = urtw_write16_i(sc, 0x7c, 0x00d0, 3);
1191 urtw_write8_m(sc, 0x61, 0);
1192 error = urtw_write8_i(sc, 0x80, 0x0f, 1);
1195 error = urtw_write8_i(sc, 0x83, 0x03, 1);
1198 urtw_write8_m(sc, 0xda, 0x10);
1199 error = urtw_write8_i(sc, 0x4d, 0x08, 2);
1203 urtw_write32_m(sc, URTW_HSSI_PARA, 0x0600321B);
1205 error = urtw_write16_i(sc, 0xec, 0x800, 1);
1215 urtw_adapter_start(struct urtw_softc *sc)
1219 error = urtw_reset(sc);
1223 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 0);
1224 urtw_write8_m(sc, URTW_GPIO, 0);
1227 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4);
1228 error = urtw_led_ctl(sc, URTW_LED_CTL_POWER_ON);
1232 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1235 /* applying MAC address again. */
1236 urtw_write32_m(sc, URTW_MAC0, ((uint32_t *)sc->sc_bssid)[0]);
1237 urtw_write16_m(sc, URTW_MAC4, ((uint32_t *)sc->sc_bssid)[1] & 0xffff);
1238 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1242 error = urtw_update_msr(sc);
1246 urtw_write32_m(sc, URTW_INT_TIMEOUT, 0);
1247 urtw_write8_m(sc, URTW_WPA_CONFIG, 0);
1248 urtw_write8_m(sc, URTW_RATE_FALLBACK, URTW_RATE_FALLBACK_ENABLE | 0x1);
1249 error = urtw_set_rate(sc);
1253 error = sc->sc_rf_init(sc);
1256 if (sc->sc_rf_set_sens != NULL)
1257 sc->sc_rf_set_sens(sc, sc->sc_sens);
1259 /* XXX correct? to call write16 */
1260 urtw_write16_m(sc, URTW_PSR, 1);
1261 urtw_write16_m(sc, URTW_ADDR_MAGIC2, 0x10);
1262 urtw_write8_m(sc, URTW_TALLY_SEL, 0x80);
1263 urtw_write8_m(sc, URTW_ADDR_MAGIC3, 0x60);
1264 /* XXX correct? to call write16 */
1265 urtw_write16_m(sc, URTW_PSR, 0);
1266 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4);
1268 error = urtw_intr_enable(sc);
1277 urtw_set_mode(struct urtw_softc *sc, uint32_t mode)
1282 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
1283 data = (data & ~URTW_EPROM_CMD_MASK) | (mode << URTW_EPROM_CMD_SHIFT);
1284 data = data & ~(URTW_EPROM_CS | URTW_EPROM_CK);
1285 urtw_write8_m(sc, URTW_EPROM_CMD, data);
1291 urtw_8187b_cmd_reset(struct urtw_softc *sc)
1297 /* XXX the code can be duplicate with urtw_reset(). */
1298 urtw_read8_m(sc, URTW_CMD, &data8);
1299 data8 = (data8 & 0x2) | URTW_CMD_RST;
1300 urtw_write8_m(sc, URTW_CMD, data8);
1302 for (i = 0; i < 20; i++) {
1303 usb_pause_mtx(&sc->sc_mtx, 2);
1304 urtw_read8_m(sc, URTW_CMD, &data8);
1305 if (!(data8 & URTW_CMD_RST))
1309 device_printf(sc->sc_dev, "reset timeout\n");
1313 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD);
1317 for (i = 0; i < 20; i++) {
1318 usb_pause_mtx(&sc->sc_mtx, 4);
1319 urtw_read8_m(sc, URTW_EPROM_CMD, &data8);
1320 if (!(data8 & URTW_EPROM_CMD_CONFIG))
1324 device_printf(sc->sc_dev, "eeprom reset timeout\n");
1333 urtw_write16_i(struct urtw_softc *sc, int val, uint16_t data, int idx)
1335 struct usb_device_request req;
1337 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
1338 req.bRequest = URTW_8187_SETREGS_REQ;
1339 USETW(req.wValue, val | 0xff00);
1340 USETW(req.wIndex, idx & 0x3);
1341 USETW(req.wLength, sizeof(uint16_t));
1343 return (urtw_do_request(sc, &req, &data));
1347 urtw_do_request(struct urtw_softc *sc,
1348 struct usb_device_request *req, void *data)
1353 URTW_ASSERT_LOCKED(sc);
1356 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx,
1357 req, data, 0, NULL, 250 /* ms */);
1361 DPRINTF(sc, URTW_DEBUG_INIT,
1362 "Control request failed, %s (retrying)\n",
1364 usb_pause_mtx(&sc->sc_mtx, hz / 100);
1370 urtw_write8_i(struct urtw_softc *sc, int val, uint8_t data, int idx)
1372 struct usb_device_request req;
1374 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
1375 req.bRequest = URTW_8187_SETREGS_REQ;
1376 USETW(req.wValue, val | 0xff00);
1377 USETW(req.wIndex, idx & 0x3);
1378 USETW(req.wLength, sizeof(uint8_t));
1380 return (urtw_do_request(sc, &req, &data));
1384 urtw_write32_i(struct urtw_softc *sc, int val, uint32_t data, int idx)
1386 struct usb_device_request req;
1388 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
1389 req.bRequest = URTW_8187_SETREGS_REQ;
1390 USETW(req.wValue, val | 0xff00);
1391 USETW(req.wIndex, idx & 0x3);
1392 USETW(req.wLength, sizeof(uint32_t));
1394 return (urtw_do_request(sc, &req, &data));
1398 urtw_stop_locked(struct ifnet *ifp, int disable)
1400 struct urtw_softc *sc = ifp->if_softc;
1405 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1407 error = urtw_intr_disable(sc);
1410 urtw_read8_m(sc, URTW_CMD, &data8);
1411 data8 &= ~(URTW_CMD_RX_ENABLE | URTW_CMD_TX_ENABLE);
1412 urtw_write8_m(sc, URTW_CMD, data8);
1414 error = sc->sc_rf_stop(sc);
1418 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1421 urtw_read8_m(sc, URTW_CONFIG4, &data8);
1422 urtw_write8_m(sc, URTW_CONFIG4, data8 | URTW_CONFIG4_VCOOFF);
1423 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1428 device_printf(sc->sc_dev, "failed to stop (%s)\n",
1429 usbd_errstr(error));
1431 usb_callout_stop(&sc->sc_led_ch);
1432 callout_stop(&sc->sc_watchdog_ch);
1434 urtw_abort_xfers(sc);
1438 urtw_stop(struct ifnet *ifp, int disable)
1440 struct urtw_softc *sc = ifp->if_softc;
1443 urtw_stop_locked(ifp, disable);
1448 urtw_abort_xfers(struct urtw_softc *sc)
1452 URTW_ASSERT_LOCKED(sc);
1454 max = (sc->sc_flags & URTW_RTL8187B) ? URTW_8187B_N_XFERS :
1457 /* abort any pending transfers */
1458 for (i = 0; i < max; i++)
1459 usbd_transfer_stop(sc->sc_xfer[i]);
1463 urtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1465 struct urtw_softc *sc = ifp->if_softc;
1466 struct ieee80211com *ic = ifp->if_l2com;
1467 struct ifreq *ifr = (struct ifreq *) data;
1468 int error = 0, startall = 0;
1472 if (ifp->if_flags & IFF_UP) {
1473 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1474 if ((ifp->if_flags ^ sc->sc_if_flags) &
1475 (IFF_ALLMULTI | IFF_PROMISC))
1478 urtw_init(ifp->if_softc);
1482 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1485 sc->sc_if_flags = ifp->if_flags;
1487 ieee80211_start_all(ic);
1490 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
1493 error = ether_ioctl(ifp, cmd, data);
1504 urtw_start(struct ifnet *ifp)
1506 struct urtw_data *bf;
1507 struct urtw_softc *sc = ifp->if_softc;
1508 struct ieee80211_node *ni;
1511 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1516 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1519 bf = urtw_getbuf(sc);
1521 IFQ_DRV_PREPEND(&ifp->if_snd, m);
1525 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
1526 m->m_pkthdr.rcvif = NULL;
1528 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_NORMAL) != 0) {
1530 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next);
1531 ieee80211_free_node(ni);
1541 urtw_alloc_data_list(struct urtw_softc *sc, struct urtw_data data[],
1542 int ndata, int maxsz, int fillmbuf)
1546 for (i = 0; i < ndata; i++) {
1547 struct urtw_data *dp = &data[i];
1551 dp->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1552 if (dp->m == NULL) {
1553 device_printf(sc->sc_dev,
1554 "could not allocate rx mbuf\n");
1558 dp->buf = mtod(dp->m, uint8_t *);
1561 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT);
1562 if (dp->buf == NULL) {
1563 device_printf(sc->sc_dev,
1564 "could not allocate buffer\n");
1568 if (((unsigned long)dp->buf) % 4)
1569 device_printf(sc->sc_dev,
1570 "warn: unaligned buffer %p\n", dp->buf);
1577 fail: urtw_free_data_list(sc, data, ndata, fillmbuf);
1582 urtw_alloc_rx_data_list(struct urtw_softc *sc)
1586 error = urtw_alloc_data_list(sc,
1587 sc->sc_rx, URTW_RX_DATA_LIST_COUNT, MCLBYTES, 1 /* mbufs */);
1591 STAILQ_INIT(&sc->sc_rx_active);
1592 STAILQ_INIT(&sc->sc_rx_inactive);
1594 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++)
1595 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next);
1601 urtw_alloc_tx_data_list(struct urtw_softc *sc)
1605 error = urtw_alloc_data_list(sc,
1606 sc->sc_tx, URTW_TX_DATA_LIST_COUNT, URTW_TX_MAXSIZE,
1611 STAILQ_INIT(&sc->sc_tx_active);
1612 STAILQ_INIT(&sc->sc_tx_inactive);
1613 STAILQ_INIT(&sc->sc_tx_pending);
1615 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++)
1616 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i],
1623 urtw_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1624 const struct ieee80211_bpf_params *params)
1626 struct ieee80211com *ic = ni->ni_ic;
1627 struct ifnet *ifp = ic->ic_ifp;
1628 struct urtw_data *bf;
1629 struct urtw_softc *sc = ifp->if_softc;
1631 /* prevent management frames from being sent if we're not ready */
1632 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1634 ieee80211_free_node(ni);
1638 bf = urtw_getbuf(sc);
1640 ieee80211_free_node(ni);
1643 return (ENOBUFS); /* XXX */
1647 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_LOW) != 0) {
1648 ieee80211_free_node(ni);
1650 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next);
1661 urtw_scan_start(struct ieee80211com *ic)
1664 /* XXX do nothing? */
1668 urtw_scan_end(struct ieee80211com *ic)
1671 /* XXX do nothing? */
1675 urtw_set_channel(struct ieee80211com *ic)
1677 struct urtw_softc *sc = ic->ic_ifp->if_softc;
1678 struct ifnet *ifp = sc->sc_ifp;
1679 uint32_t data, orig;
1683 * if the user set a channel explicitly using ifconfig(8) this function
1684 * can be called earlier than we're expected that in some cases the
1685 * initialization would be failed if setting a channel is called before
1686 * the init have done.
1688 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1691 if (sc->sc_curchan != NULL && sc->sc_curchan == ic->ic_curchan)
1697 * during changing th channel we need to temporarily be disable
1700 urtw_read32_m(sc, URTW_TX_CONF, &orig);
1701 data = orig & ~URTW_TX_LOOPBACK_MASK;
1702 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_MAC);
1704 error = sc->sc_rf_set_chan(sc, ieee80211_chan2ieee(ic, ic->ic_curchan));
1707 usb_pause_mtx(&sc->sc_mtx, 10);
1708 urtw_write32_m(sc, URTW_TX_CONF, orig);
1710 urtw_write16_m(sc, URTW_ATIM_WND, 2);
1711 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100);
1712 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100);
1713 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100);
1718 sc->sc_curchan = ic->ic_curchan;
1721 device_printf(sc->sc_dev, "could not change the channel\n");
1725 urtw_update_mcast(struct ifnet *ifp)
1728 /* XXX do nothing? */
1732 urtw_tx_start(struct urtw_softc *sc, struct ieee80211_node *ni, struct mbuf *m0,
1733 struct urtw_data *data, int prior)
1736 struct ifnet *ifp = sc->sc_ifp;
1737 struct ieee80211_frame *wh = mtod(m0, struct ieee80211_frame *);
1738 struct ieee80211_key *k;
1739 const struct ieee80211_txparam *tp;
1740 struct ieee80211com *ic = ifp->if_l2com;
1741 struct ieee80211vap *vap = ni->ni_vap;
1742 struct urtw_8187b_txhdr *hdr;
1743 struct usb_xfer *rtl8187b_pipes[URTW_8187B_TXPIPE_MAX] = {
1744 sc->sc_xfer[URTW_8187B_BULK_TX_BE],
1745 sc->sc_xfer[URTW_8187B_BULK_TX_BK],
1746 sc->sc_xfer[URTW_8187B_BULK_TX_VI],
1747 sc->sc_xfer[URTW_8187B_BULK_TX_VO]
1749 struct usb_xfer *xfer;
1752 URTW_ASSERT_LOCKED(sc);
1757 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1758 k = ieee80211_crypto_encap(ni, m0);
1760 device_printf(sc->sc_dev,
1761 "ieee80211_crypto_encap returns NULL.\n");
1762 /* XXX we don't expect the fragmented frames */
1767 /* in case packet header moved, reset pointer */
1768 wh = mtod(m0, struct ieee80211_frame *);
1771 if (ieee80211_radiotap_active_vap(vap)) {
1772 struct urtw_tx_radiotap_header *tap = &sc->sc_txtap;
1774 /* XXX Are variables correct? */
1776 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq);
1777 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags);
1779 ieee80211_radiotap_tx(vap, m0);
1782 xferlen = m0->m_pkthdr.len;
1783 xferlen += (sc->sc_flags & URTW_RTL8187B) ? (4 * 8) : (4 * 3);
1784 if ((0 == xferlen % 64) || (0 == xferlen % 512))
1787 bzero(data->buf, URTW_TX_MAXSIZE);
1788 data->buf[0] = m0->m_pkthdr.len & 0xff;
1789 data->buf[1] = (m0->m_pkthdr.len & 0x0f00) >> 8;
1790 data->buf[1] |= (1 << 7);
1792 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
1793 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) &&
1794 (sc->sc_preamble_mode == URTW_PREAMBLE_MODE_SHORT) &&
1795 (sc->sc_currate != 0))
1797 if ((m0->m_pkthdr.len > vap->iv_rtsthreshold) &&
1798 prior == URTW_PRIORITY_LOW) {
1799 device_printf(sc->sc_dev, "TODO tx.\n");
1802 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)
1803 data->buf[2] |= (1 << 1);
1804 /* RTS rate - 10 means we use a basic rate. */
1805 data->buf[2] |= (urtw_rate2rtl(2) << 3);
1807 * XXX currently TX rate control depends on the rate value of
1808 * RX descriptor because I don't know how to we can control TX rate
1809 * in more smart way. Please fix me you find a thing.
1811 data->buf[3] = sc->sc_currate;
1812 if (prior == URTW_PRIORITY_NORMAL) {
1813 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)];
1814 if (IEEE80211_IS_MULTICAST(wh->i_addr1))
1815 data->buf[3] = urtw_rate2rtl(tp->mcastrate);
1816 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
1817 data->buf[3] = urtw_rate2rtl(tp->ucastrate);
1820 if (sc->sc_flags & URTW_RTL8187B) {
1821 hdr = (struct urtw_8187b_txhdr *)data->buf;
1822 hdr->rts_duration = 0;
1824 hdr->retry = 3 | (7 << 4) | 11;
1825 hdr->tx_duration = ieee80211_compute_duration(ic->ic_rt,
1826 m0->m_pkthdr.len + IEEE80211_CRC_LEN,
1827 urtw_rtl2rate(data->buf[3]),
1828 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0);
1829 /* XXX MUST fill another variables like rts_duration, tx_.. */
1830 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)&data->buf[32]);
1832 data->buf[8] = 3; /* CW minimum */
1833 data->buf[8] |= (7 << 4); /* CW maximum */
1834 data->buf[9] |= 11; /* retry limitation */
1835 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)&data->buf[12]);
1838 data->buflen = xferlen;
1842 if (sc->sc_flags & URTW_RTL8187B) {
1843 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
1844 case IEEE80211_FC0_TYPE_CTL:
1845 case IEEE80211_FC0_TYPE_MGT:
1846 xfer = sc->sc_xfer[URTW_8187B_BULK_TX_EP12];
1849 KASSERT(M_WME_GETAC(m0) < URTW_8187B_TXPIPE_MAX,
1850 ("unsupported WME pipe %d", M_WME_GETAC(m0)));
1851 xfer = rtl8187b_pipes[M_WME_GETAC(m0)];
1855 xfer = (prior == URTW_PRIORITY_LOW) ?
1856 sc->sc_xfer[URTW_8187L_BULK_TX_LOW] :
1857 sc->sc_xfer[URTW_8187L_BULK_TX_NORMAL];
1859 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next);
1860 usbd_transfer_start(xfer);
1862 error = urtw_led_ctl(sc, URTW_LED_CTL_TX);
1864 device_printf(sc->sc_dev, "could not control LED (%d)\n",
1870 urtw_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
1872 struct ieee80211_node *ni = vap->iv_bss;
1873 struct ieee80211com *ic = vap->iv_ic;
1874 struct urtw_softc *sc = ic->ic_ifp->if_softc;
1875 struct urtw_vap *uvp = URTW_VAP(vap);
1876 usb_error_t error = 0;
1878 DPRINTF(sc, URTW_DEBUG_STATE, "%s: %s -> %s\n", __func__,
1879 ieee80211_state_name[vap->iv_state],
1880 ieee80211_state_name[nstate]);
1882 sc->sc_state = nstate;
1884 IEEE80211_UNLOCK(ic);
1886 usb_callout_stop(&sc->sc_led_ch);
1887 callout_stop(&sc->sc_watchdog_ch);
1890 case IEEE80211_S_INIT:
1891 case IEEE80211_S_SCAN:
1892 case IEEE80211_S_AUTH:
1893 case IEEE80211_S_ASSOC:
1895 case IEEE80211_S_RUN:
1896 /* setting bssid. */
1897 urtw_write32_m(sc, URTW_BSSID, ((uint32_t *)ni->ni_bssid)[0]);
1898 urtw_write16_m(sc, URTW_BSSID + 4,
1899 ((uint16_t *)ni->ni_bssid)[2]);
1900 urtw_update_msr(sc);
1901 /* XXX maybe the below would be incorrect. */
1902 urtw_write16_m(sc, URTW_ATIM_WND, 2);
1903 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100);
1904 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 0x64);
1905 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100);
1906 error = urtw_led_ctl(sc, URTW_LED_CTL_LINK);
1908 device_printf(sc->sc_dev,
1909 "could not control LED (%d)\n", error);
1917 return (uvp->newstate(vap, nstate, arg));
1921 urtw_watchdog(void *arg)
1923 struct urtw_softc *sc = arg;
1924 struct ifnet *ifp = sc->sc_ifp;
1926 if (sc->sc_txtimer > 0) {
1927 if (--sc->sc_txtimer == 0) {
1928 device_printf(sc->sc_dev, "device timeout\n");
1932 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc);
1937 urtw_set_multi(void *arg)
1939 struct urtw_softc *sc = arg;
1940 struct ifnet *ifp = sc->sc_ifp;
1942 if (!(ifp->if_flags & IFF_UP))
1946 * XXX don't know how to set a device. Lack of docs. Just try to set
1947 * IFF_ALLMULTI flag here.
1949 ifp->if_flags |= IFF_ALLMULTI;
1953 urtw_set_rate(struct urtw_softc *sc)
1955 int i, basic_rate, min_rr_rate, max_rr_rate;
1959 basic_rate = urtw_rate2rtl(48);
1960 min_rr_rate = urtw_rate2rtl(12);
1961 max_rr_rate = urtw_rate2rtl(48);
1963 urtw_write8_m(sc, URTW_RESP_RATE,
1964 max_rr_rate << URTW_RESP_MAX_RATE_SHIFT |
1965 min_rr_rate << URTW_RESP_MIN_RATE_SHIFT);
1967 urtw_read16_m(sc, URTW_BRSR, &data);
1968 data &= ~URTW_BRSR_MBR_8185;
1970 for (i = 0; i <= basic_rate; i++)
1973 urtw_write16_m(sc, URTW_BRSR, data);
1979 urtw_rate2rtl(int rate)
1981 #define N(a) (sizeof(a) / sizeof((a)[0]))
1984 for (i = 0; i < N(urtw_ratetable); i++) {
1985 if (rate == urtw_ratetable[i].reg)
1986 return urtw_ratetable[i].val;
1994 urtw_rtl2rate(int rate)
1996 #define N(a) (sizeof(a) / sizeof((a)[0]))
1999 for (i = 0; i < N(urtw_ratetable); i++) {
2000 if (rate == urtw_ratetable[i].val)
2001 return urtw_ratetable[i].reg;
2009 urtw_update_msr(struct urtw_softc *sc)
2011 struct ifnet *ifp = sc->sc_ifp;
2012 struct ieee80211com *ic = ifp->if_l2com;
2016 urtw_read8_m(sc, URTW_MSR, &data);
2017 data &= ~URTW_MSR_LINK_MASK;
2019 if (sc->sc_state == IEEE80211_S_RUN) {
2020 switch (ic->ic_opmode) {
2021 case IEEE80211_M_STA:
2022 case IEEE80211_M_MONITOR:
2023 data |= URTW_MSR_LINK_STA;
2024 if (sc->sc_flags & URTW_RTL8187B)
2025 data |= URTW_MSR_LINK_ENEDCA;
2027 case IEEE80211_M_IBSS:
2028 data |= URTW_MSR_LINK_ADHOC;
2030 case IEEE80211_M_HOSTAP:
2031 data |= URTW_MSR_LINK_HOSTAP;
2034 panic("unsupported operation mode 0x%x\n",
2039 data |= URTW_MSR_LINK_NONE;
2041 urtw_write8_m(sc, URTW_MSR, data);
2047 urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data)
2049 struct usb_device_request req;
2052 URTW_ASSERT_LOCKED(sc);
2054 req.bmRequestType = UT_READ_VENDOR_DEVICE;
2055 req.bRequest = URTW_8187_GETREGS_REQ;
2056 USETW(req.wValue, val | 0xff00);
2057 USETW(req.wIndex, 0);
2058 USETW(req.wLength, sizeof(uint8_t));
2060 error = urtw_do_request(sc, &req, data);
2065 urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data)
2067 struct usb_device_request req;
2070 URTW_ASSERT_LOCKED(sc);
2072 req.bmRequestType = UT_READ_VENDOR_DEVICE;
2073 req.bRequest = URTW_8187_GETREGS_REQ;
2074 USETW(req.wValue, val | 0xff00);
2075 USETW(req.wIndex, 0);
2076 USETW(req.wLength, sizeof(uint16_t));
2078 error = urtw_do_request(sc, &req, data);
2083 urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data)
2085 struct usb_device_request req;
2088 URTW_ASSERT_LOCKED(sc);
2090 req.bmRequestType = UT_READ_VENDOR_DEVICE;
2091 req.bRequest = URTW_8187_GETREGS_REQ;
2092 USETW(req.wValue, val | 0xff00);
2093 USETW(req.wIndex, 0);
2094 USETW(req.wLength, sizeof(uint32_t));
2096 error = urtw_do_request(sc, &req, data);
2101 urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data)
2103 struct usb_device_request req;
2105 URTW_ASSERT_LOCKED(sc);
2107 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2108 req.bRequest = URTW_8187_SETREGS_REQ;
2109 USETW(req.wValue, val | 0xff00);
2110 USETW(req.wIndex, 0);
2111 USETW(req.wLength, sizeof(uint8_t));
2113 return (urtw_do_request(sc, &req, &data));
2117 urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data)
2119 struct usb_device_request req;
2121 URTW_ASSERT_LOCKED(sc);
2123 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2124 req.bRequest = URTW_8187_SETREGS_REQ;
2125 USETW(req.wValue, val | 0xff00);
2126 USETW(req.wIndex, 0);
2127 USETW(req.wLength, sizeof(uint16_t));
2129 return (urtw_do_request(sc, &req, &data));
2133 urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data)
2135 struct usb_device_request req;
2137 URTW_ASSERT_LOCKED(sc);
2139 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2140 req.bRequest = URTW_8187_SETREGS_REQ;
2141 USETW(req.wValue, val | 0xff00);
2142 USETW(req.wIndex, 0);
2143 USETW(req.wLength, sizeof(uint32_t));
2145 return (urtw_do_request(sc, &req, &data));
2149 urtw_get_macaddr(struct urtw_softc *sc)
2154 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data);
2157 sc->sc_bssid[0] = data & 0xff;
2158 sc->sc_bssid[1] = (data & 0xff00) >> 8;
2159 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data);
2162 sc->sc_bssid[2] = data & 0xff;
2163 sc->sc_bssid[3] = (data & 0xff00) >> 8;
2164 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data);
2167 sc->sc_bssid[4] = data & 0xff;
2168 sc->sc_bssid[5] = (data & 0xff00) >> 8;
2174 urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data)
2176 #define URTW_READCMD_LEN 3
2178 int16_t addrstr[8], data16, readcmd[] = { 1, 1, 0 };
2181 /* NB: make sure the buffer is initialized */
2184 /* enable EPROM programming */
2185 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_PROGRAM_MODE);
2186 DELAY(URTW_EPROM_DELAY);
2188 error = urtw_eprom_cs(sc, URTW_EPROM_ENABLE);
2191 error = urtw_eprom_ck(sc);
2194 error = urtw_eprom_sendbits(sc, readcmd, URTW_READCMD_LEN);
2197 if (sc->sc_epromtype == URTW_EEPROM_93C56) {
2199 addrstr[0] = addr & (1 << 7);
2200 addrstr[1] = addr & (1 << 6);
2201 addrstr[2] = addr & (1 << 5);
2202 addrstr[3] = addr & (1 << 4);
2203 addrstr[4] = addr & (1 << 3);
2204 addrstr[5] = addr & (1 << 2);
2205 addrstr[6] = addr & (1 << 1);
2206 addrstr[7] = addr & (1 << 0);
2209 addrstr[0] = addr & (1 << 5);
2210 addrstr[1] = addr & (1 << 4);
2211 addrstr[2] = addr & (1 << 3);
2212 addrstr[3] = addr & (1 << 2);
2213 addrstr[4] = addr & (1 << 1);
2214 addrstr[5] = addr & (1 << 0);
2216 error = urtw_eprom_sendbits(sc, addrstr, addrlen);
2220 error = urtw_eprom_writebit(sc, 0);
2224 for (i = 0; i < 16; i++) {
2225 error = urtw_eprom_ck(sc);
2228 error = urtw_eprom_readbit(sc, &data16);
2232 (*data) |= (data16 << (15 - i));
2235 error = urtw_eprom_cs(sc, URTW_EPROM_DISABLE);
2238 error = urtw_eprom_ck(sc);
2242 /* now disable EPROM programming */
2243 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_NORMAL_MODE);
2246 #undef URTW_READCMD_LEN
2250 urtw_eprom_cs(struct urtw_softc *sc, int able)
2255 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2256 if (able == URTW_EPROM_ENABLE)
2257 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CS);
2259 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CS);
2260 DELAY(URTW_EPROM_DELAY);
2266 urtw_eprom_ck(struct urtw_softc *sc)
2272 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2273 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK);
2274 DELAY(URTW_EPROM_DELAY);
2276 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2277 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK);
2278 DELAY(URTW_EPROM_DELAY);
2284 urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data)
2289 urtw_read8_m(sc, URTW_EPROM_CMD, &data8);
2290 *data = (data8 & URTW_EPROM_READBIT) ? 1 : 0;
2291 DELAY(URTW_EPROM_DELAY);
2298 urtw_eprom_writebit(struct urtw_softc *sc, int16_t bit)
2303 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2305 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_WRITEBIT);
2307 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_WRITEBIT);
2308 DELAY(URTW_EPROM_DELAY);
2314 urtw_eprom_sendbits(struct urtw_softc *sc, int16_t *buf, int buflen)
2317 usb_error_t error = 0;
2319 for (i = 0; i < buflen; i++) {
2320 error = urtw_eprom_writebit(sc, buf[i]);
2323 error = urtw_eprom_ck(sc);
2333 urtw_get_txpwr(struct urtw_softc *sc)
2339 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data);
2342 sc->sc_txpwr_cck_base = data & 0xf;
2343 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf;
2345 for (i = 1, j = 0; i < 6; i += 2, j++) {
2346 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data);
2349 sc->sc_txpwr_cck[i] = data & 0xf;
2350 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8;
2351 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4;
2352 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12;
2354 for (i = 1, j = 0; i < 4; i += 2, j++) {
2355 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data);
2358 sc->sc_txpwr_cck[i + 6] = data & 0xf;
2359 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8;
2360 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4;
2361 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12;
2363 if (sc->sc_flags & URTW_RTL8187B) {
2364 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2, &data);
2367 sc->sc_txpwr_cck[1 + 6 + 4] = data & 0xf;
2368 sc->sc_txpwr_ofdm[1 + 6 + 4] = (data & 0xf0) >> 4;
2369 error = urtw_eprom_read32(sc, 0x0a, &data);
2372 sc->sc_txpwr_cck[2 + 6 + 4] = data & 0xf;
2373 sc->sc_txpwr_ofdm[2 + 6 + 4] = (data & 0xf0) >> 4;
2374 error = urtw_eprom_read32(sc, 0x1c, &data);
2377 sc->sc_txpwr_cck[3 + 6 + 4] = data & 0xf;
2378 sc->sc_txpwr_cck[3 + 6 + 4 + 1] = (data & 0xf00) >> 8;
2379 sc->sc_txpwr_ofdm[3 + 6 + 4] = (data & 0xf0) >> 4;
2380 sc->sc_txpwr_ofdm[3 + 6 + 4 + 1] = (data & 0xf000) >> 12;
2382 for (i = 1, j = 0; i < 4; i += 2, j++) {
2383 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2 + j,
2387 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf;
2388 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8;
2389 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4;
2390 sc->sc_txpwr_ofdm[i + 6 + 4 + 1] = (data & 0xf000) >> 12;
2399 urtw_get_rfchip(struct urtw_softc *sc)
2406 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data);
2409 switch (data & 0xff) {
2410 case URTW_EPROM_RFCHIPID_RTL8225U:
2411 error = urtw_8225_isv2(sc, &ret);
2415 sc->sc_rf_init = urtw_8225_rf_init;
2416 sc->sc_rf_set_sens = urtw_8225_rf_set_sens;
2417 sc->sc_rf_set_chan = urtw_8225_rf_set_chan;
2418 sc->sc_rf_stop = urtw_8225_rf_stop;
2420 sc->sc_rf_init = urtw_8225v2_rf_init;
2421 sc->sc_rf_set_chan = urtw_8225v2_rf_set_chan;
2422 sc->sc_rf_stop = urtw_8225_rf_stop;
2424 sc->sc_max_sens = URTW_8225_RF_MAX_SENS;
2425 sc->sc_sens = URTW_8225_RF_DEF_SENS;
2427 case URTW_EPROM_RFCHIPID_RTL8225Z2:
2428 sc->sc_rf_init = urtw_8225v2b_rf_init;
2429 sc->sc_rf_set_chan = urtw_8225v2b_rf_set_chan;
2430 sc->sc_max_sens = URTW_8225_RF_MAX_SENS;
2431 sc->sc_sens = URTW_8225_RF_DEF_SENS;
2432 sc->sc_rf_stop = urtw_8225_rf_stop;
2435 panic("unsupported RF chip %d\n", data & 0xff);
2439 if (sc->sc_flags & URTW_RTL8187B) {
2440 urtw_read8_m(sc, 0xe1, &data8);
2441 sc->sc_flags |= (data8 == 0) ? URTW_RTL8187B_REV_B :
2442 (data8 == 1) ? URTW_RTL8187B_REV_D : URTW_RTL8187B_REV_E;
2445 device_printf(sc->sc_dev, "%s rf %s hwrev %s\n",
2446 (sc->sc_flags & URTW_RTL8187B) ? "rtl8187b" : "rtl8187l",
2447 ((data & 0xff) == URTW_EPROM_RFCHIPID_RTL8225U) ? "rtl8225u" :
2449 (sc->sc_flags & URTW_RTL8187B) ? ((data8 == 0) ? "b" :
2450 (data8 == 1) ? "d" : "e") : "none");
2458 urtw_led_init(struct urtw_softc *sc)
2463 urtw_read8_m(sc, URTW_PSR, &sc->sc_psr);
2464 error = urtw_eprom_read32(sc, URTW_EPROM_SWREV, &rev);
2468 switch (rev & URTW_EPROM_CID_MASK) {
2469 case URTW_EPROM_CID_ALPHA0:
2470 sc->sc_strategy = URTW_SW_LED_MODE1;
2472 case URTW_EPROM_CID_SERCOMM_PS:
2473 sc->sc_strategy = URTW_SW_LED_MODE3;
2475 case URTW_EPROM_CID_HW_LED:
2476 sc->sc_strategy = URTW_HW_LED;
2478 case URTW_EPROM_CID_RSVD0:
2479 case URTW_EPROM_CID_RSVD1:
2481 sc->sc_strategy = URTW_SW_LED_MODE0;
2485 sc->sc_gpio_ledpin = URTW_LED_PIN_GPIO0;
2493 urtw_8225_rf_init(struct urtw_softc *sc)
2495 #define N(a) (sizeof(a) / sizeof((a)[0]))
2500 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
2504 error = urtw_8225_usb_init(sc);
2508 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008);
2509 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */
2510 urtw_write16_m(sc, URTW_BRSR, 0xffff);
2511 urtw_write32_m(sc, URTW_RF_PARA, 0x100044);
2513 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2516 urtw_write8_m(sc, URTW_CONFIG3, 0x44);
2517 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2521 error = urtw_8185_rf_pins_enable(sc);
2524 usb_pause_mtx(&sc->sc_mtx, 1000);
2526 for (i = 0; i < N(urtw_8225_rf_part1); i++) {
2527 urtw_8225_write(sc, urtw_8225_rf_part1[i].reg,
2528 urtw_8225_rf_part1[i].val);
2529 usb_pause_mtx(&sc->sc_mtx, 1);
2531 usb_pause_mtx(&sc->sc_mtx, 100);
2533 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1);
2534 usb_pause_mtx(&sc->sc_mtx, 200);
2536 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2);
2537 usb_pause_mtx(&sc->sc_mtx, 200);
2539 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC3);
2541 for (i = 0; i < 95; i++) {
2542 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1));
2543 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, urtw_8225_rxgain[i]);
2547 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC4);
2549 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC5);
2551 for (i = 0; i < 128; i++) {
2552 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]);
2553 usb_pause_mtx(&sc->sc_mtx, 1);
2554 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80);
2555 usb_pause_mtx(&sc->sc_mtx, 1);
2558 for (i = 0; i < N(urtw_8225_rf_part2); i++) {
2559 urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg,
2560 urtw_8225_rf_part2[i].val);
2561 usb_pause_mtx(&sc->sc_mtx, 1);
2564 error = urtw_8225_setgain(sc, 4);
2568 for (i = 0; i < N(urtw_8225_rf_part3); i++) {
2569 urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg,
2570 urtw_8225_rf_part3[i].val);
2571 usb_pause_mtx(&sc->sc_mtx, 1);
2574 urtw_write8_m(sc, URTW_TESTR, 0x0d);
2576 error = urtw_8225_set_txpwrlvl(sc, 1);
2580 urtw_8187_write_phy_cck(sc, 0x10, 0x9b);
2581 usb_pause_mtx(&sc->sc_mtx, 1);
2582 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90);
2583 usb_pause_mtx(&sc->sc_mtx, 1);
2585 /* TX ant A, 0x0 for B */
2586 error = urtw_8185_tx_antenna(sc, 0x3);
2589 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002);
2591 error = urtw_8225_rf_set_chan(sc, 1);
2598 urtw_8185_rf_pins_enable(struct urtw_softc *sc)
2600 usb_error_t error = 0;
2602 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1ff7);
2608 urtw_8185_tx_antenna(struct urtw_softc *sc, uint8_t ant)
2612 urtw_write8_m(sc, URTW_TX_ANTENNA, ant);
2613 usb_pause_mtx(&sc->sc_mtx, 1);
2619 urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2623 return urtw_8187_write_phy(sc, addr, data);
2627 urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2631 return urtw_8187_write_phy(sc, addr, data | 0x10000);
2635 urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2640 phyw = ((data << 8) | (addr | 0x80));
2641 urtw_write8_m(sc, URTW_PHY_MAGIC4, ((phyw & 0xff000000) >> 24));
2642 urtw_write8_m(sc, URTW_PHY_MAGIC3, ((phyw & 0x00ff0000) >> 16));
2643 urtw_write8_m(sc, URTW_PHY_MAGIC2, ((phyw & 0x0000ff00) >> 8));
2644 urtw_write8_m(sc, URTW_PHY_MAGIC1, ((phyw & 0x000000ff)));
2645 usb_pause_mtx(&sc->sc_mtx, 1);
2651 urtw_8225_setgain(struct urtw_softc *sc, int16_t gain)
2655 urtw_8187_write_phy_ofdm(sc, 0x0d, urtw_8225_gain[gain * 4]);
2656 urtw_8187_write_phy_ofdm(sc, 0x1b, urtw_8225_gain[gain * 4 + 2]);
2657 urtw_8187_write_phy_ofdm(sc, 0x1d, urtw_8225_gain[gain * 4 + 3]);
2658 urtw_8187_write_phy_ofdm(sc, 0x23, urtw_8225_gain[gain * 4 + 1]);
2664 urtw_8225_usb_init(struct urtw_softc *sc)
2669 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 0);
2670 urtw_write8_m(sc, URTW_GPIO, 0);
2671 error = urtw_read8e(sc, 0x53, &data);
2674 error = urtw_write8e(sc, 0x53, data | (1 << 7));
2677 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 4);
2678 urtw_write8_m(sc, URTW_GPIO, 0x20);
2679 urtw_write8_m(sc, URTW_GP_ENABLE, 0);
2681 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x80);
2682 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x80);
2683 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x80);
2685 usb_pause_mtx(&sc->sc_mtx, 500);
2691 urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data)
2693 uint16_t d80, d82, d84;
2696 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &d80);
2697 d80 &= URTW_RF_PINS_MAGIC1;
2698 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &d82);
2699 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &d84);
2700 d84 &= URTW_RF_PINS_MAGIC2;
2701 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, d82 | URTW_RF_PINS_MAGIC3);
2702 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84 | URTW_RF_PINS_MAGIC3);
2705 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
2707 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80);
2710 error = urtw_8225_write_s16(sc, addr, 0x8225, &data);
2714 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
2716 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
2717 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84);
2718 usb_pause_mtx(&sc->sc_mtx, 2);
2723 /* XXX why we should allocalte memory buffer instead of using memory stack? */
2725 urtw_8225_write_s16(struct urtw_softc *sc, uint8_t addr, int index,
2730 struct usb_device_request *req;
2731 usb_error_t error = 0;
2734 req = (usb_device_request_t *)malloc(sizeof(usb_device_request_t),
2735 M_80211_VAP, M_NOWAIT | M_ZERO);
2737 device_printf(sc->sc_dev, "could not allocate a memory\n");
2740 buf = (uint8_t *)malloc(2, M_80211_VAP, M_NOWAIT | M_ZERO);
2742 device_printf(sc->sc_dev, "could not allocate a memory\n");
2746 req->bmRequestType = UT_WRITE_VENDOR_DEVICE;
2747 req->bRequest = URTW_8187_SETREGS_REQ;
2748 USETW(req->wValue, addr);
2749 USETW(req->wIndex, index);
2750 USETW(req->wLength, sizeof(uint16_t));
2751 buf[0] = (data16 & 0x00ff);
2752 buf[1] = (data16 & 0xff00) >> 8;
2754 error = urtw_do_request(sc, req, buf);
2756 free(buf, M_80211_VAP);
2757 fail1: free(req, M_80211_VAP);
2758 fail0: return (error);
2762 urtw_8225_rf_set_chan(struct urtw_softc *sc, int chan)
2764 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
2765 struct ieee80211_channel *c = ic->ic_curchan;
2768 error = urtw_8225_set_txpwrlvl(sc, chan);
2771 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]);
2772 usb_pause_mtx(&sc->sc_mtx, 10);
2774 urtw_write8_m(sc, URTW_SIFS, 0x22);
2776 if (sc->sc_state == IEEE80211_S_ASSOC &&
2777 ic->ic_flags & IEEE80211_F_SHSLOT)
2778 urtw_write8_m(sc, URTW_SLOT, 0x9);
2780 urtw_write8_m(sc, URTW_SLOT, 0x14);
2782 if (IEEE80211_IS_CHAN_G(c)) {
2784 urtw_write8_m(sc, URTW_DIFS, 0x14);
2785 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x14);
2786 urtw_write8_m(sc, URTW_CW_VAL, 0x73);
2789 urtw_write8_m(sc, URTW_DIFS, 0x24);
2790 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x24);
2791 urtw_write8_m(sc, URTW_CW_VAL, 0xa5);
2799 urtw_8225_rf_set_sens(struct urtw_softc *sc, int sens)
2803 if (sens < 0 || sens > 6)
2808 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC1);
2811 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC2);
2814 error = urtw_8225_setgain(sc, sens);
2818 urtw_8187_write_phy_cck(sc, 0x41, urtw_8225_threshold[sens]);
2825 urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan)
2828 uint8_t *cck_pwltable;
2829 uint8_t cck_pwrlvl_max, ofdm_pwrlvl_min, ofdm_pwrlvl_max;
2830 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
2831 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
2834 cck_pwrlvl_max = 11;
2835 ofdm_pwrlvl_max = 25; /* 12 -> 25 */
2836 ofdm_pwrlvl_min = 10;
2838 /* CCK power setting */
2839 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl;
2840 idx = cck_pwrlvl % 6;
2841 set = cck_pwrlvl / 6;
2842 cck_pwltable = (chan == 14) ? urtw_8225_txpwr_cck_ch14 :
2843 urtw_8225_txpwr_cck;
2845 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
2846 urtw_8225_tx_gain_cck_ofdm[set] >> 1);
2847 for (i = 0; i < 8; i++) {
2848 urtw_8187_write_phy_cck(sc, 0x44 + i,
2849 cck_pwltable[idx * 8 + i]);
2851 usb_pause_mtx(&sc->sc_mtx, 1);
2853 /* OFDM power setting */
2854 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ?
2855 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min;
2856 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
2858 idx = ofdm_pwrlvl % 6;
2859 set = ofdm_pwrlvl / 6;
2861 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
2864 urtw_8187_write_phy_ofdm(sc, 2, 0x42);
2865 urtw_8187_write_phy_ofdm(sc, 6, 0);
2866 urtw_8187_write_phy_ofdm(sc, 8, 0);
2868 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
2869 urtw_8225_tx_gain_cck_ofdm[set] >> 1);
2870 urtw_8187_write_phy_ofdm(sc, 0x5, urtw_8225_txpwr_ofdm[idx]);
2871 urtw_8187_write_phy_ofdm(sc, 0x7, urtw_8225_txpwr_ofdm[idx]);
2872 usb_pause_mtx(&sc->sc_mtx, 1);
2879 urtw_8225_rf_stop(struct urtw_softc *sc)
2884 urtw_8225_write(sc, 0x4, 0x1f);
2886 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2890 urtw_read8_m(sc, URTW_CONFIG3, &data);
2891 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
2892 if (sc->sc_flags & URTW_RTL8187B) {
2893 urtw_write32_m(sc, URTW_ANAPARAM2,
2894 URTW_8187B_8225_ANAPARAM2_OFF);
2895 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_OFF);
2896 urtw_write32_m(sc, URTW_ANAPARAM3,
2897 URTW_8187B_8225_ANAPARAM3_OFF);
2899 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8225_ANAPARAM2_OFF);
2900 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8225_ANAPARAM_OFF);
2903 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
2904 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2913 urtw_8225v2_rf_init(struct urtw_softc *sc)
2915 #define N(a) (sizeof(a) / sizeof((a)[0]))
2921 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
2925 error = urtw_8225_usb_init(sc);
2929 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008);
2930 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */
2931 urtw_write16_m(sc, URTW_BRSR, 0xffff);
2932 urtw_write32_m(sc, URTW_RF_PARA, 0x100044);
2934 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2937 urtw_write8_m(sc, URTW_CONFIG3, 0x44);
2938 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2942 error = urtw_8185_rf_pins_enable(sc);
2946 usb_pause_mtx(&sc->sc_mtx, 500);
2948 for (i = 0; i < N(urtw_8225v2_rf_part1); i++) {
2949 urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg,
2950 urtw_8225v2_rf_part1[i].val);
2952 usb_pause_mtx(&sc->sc_mtx, 50);
2955 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC1);
2957 for (i = 0; i < 95; i++) {
2958 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1));
2959 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC,
2960 urtw_8225v2_rxgain[i]);
2964 URTW_8225_ADDR_3_MAGIC, URTW_8225_ADDR_3_DATA_MAGIC1);
2966 URTW_8225_ADDR_5_MAGIC, URTW_8225_ADDR_5_DATA_MAGIC1);
2968 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC2);
2970 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1);
2971 usb_pause_mtx(&sc->sc_mtx, 100);
2973 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2);
2974 usb_pause_mtx(&sc->sc_mtx, 100);
2976 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32);
2979 if (data32 != URTW_8225_ADDR_6_DATA_MAGIC1)
2980 device_printf(sc->sc_dev, "expect 0xe6!! (0x%x)\n", data32);
2981 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2)) {
2983 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1);
2984 usb_pause_mtx(&sc->sc_mtx, 100);
2986 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2);
2987 usb_pause_mtx(&sc->sc_mtx, 50);
2988 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32);
2991 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2))
2992 device_printf(sc->sc_dev, "RF calibration failed\n");
2994 usb_pause_mtx(&sc->sc_mtx, 100);
2997 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC6);
2998 for (i = 0; i < 128; i++) {
2999 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]);
3000 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80);
3003 for (i = 0; i < N(urtw_8225v2_rf_part2); i++) {
3004 urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg,
3005 urtw_8225v2_rf_part2[i].val);
3008 error = urtw_8225v2_setgain(sc, 4);
3012 for (i = 0; i < N(urtw_8225v2_rf_part3); i++) {
3013 urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg,
3014 urtw_8225v2_rf_part3[i].val);
3017 urtw_write8_m(sc, URTW_TESTR, 0x0d);
3019 error = urtw_8225v2_set_txpwrlvl(sc, 1);
3023 urtw_8187_write_phy_cck(sc, 0x10, 0x9b);
3024 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90);
3026 /* TX ant A, 0x0 for B */
3027 error = urtw_8185_tx_antenna(sc, 0x3);
3030 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002);
3032 error = urtw_8225_rf_set_chan(sc, 1);
3039 urtw_8225v2_rf_set_chan(struct urtw_softc *sc, int chan)
3041 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
3042 struct ieee80211_channel *c = ic->ic_curchan;
3045 error = urtw_8225v2_set_txpwrlvl(sc, chan);
3049 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]);
3050 usb_pause_mtx(&sc->sc_mtx, 10);
3052 urtw_write8_m(sc, URTW_SIFS, 0x22);
3054 if(sc->sc_state == IEEE80211_S_ASSOC &&
3055 ic->ic_flags & IEEE80211_F_SHSLOT)
3056 urtw_write8_m(sc, URTW_SLOT, 0x9);
3058 urtw_write8_m(sc, URTW_SLOT, 0x14);
3060 if (IEEE80211_IS_CHAN_G(c)) {
3062 urtw_write8_m(sc, URTW_DIFS, 0x14);
3063 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x14);
3064 urtw_write8_m(sc, URTW_CW_VAL, 0x73);
3067 urtw_write8_m(sc, URTW_DIFS, 0x24);
3068 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x24);
3069 urtw_write8_m(sc, URTW_CW_VAL, 0xa5);
3077 urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data)
3081 uint8_t rlen = 12, wlen = 6;
3082 uint16_t o1, o2, o3, tmp;
3083 uint32_t d2w = ((uint32_t)(addr & 0x1f)) << 27;
3084 uint32_t mask = 0x80000000, value = 0;
3087 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &o1);
3088 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &o2);
3089 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &o3);
3090 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2 | URTW_RF_PINS_MAGIC4);
3091 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3 | URTW_RF_PINS_MAGIC4);
3092 o1 &= ~URTW_RF_PINS_MAGIC4;
3093 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN);
3095 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1);
3098 for (i = 0; i < (wlen / 2); i++, mask = mask >> 1) {
3099 bit = ((d2w & mask) != 0) ? 1 : 0;
3101 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1);
3103 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3104 URTW_BB_HOST_BANG_CLK);
3106 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3107 URTW_BB_HOST_BANG_CLK);
3112 bit = ((d2w & mask) != 0) ? 1 : 0;
3113 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3114 URTW_BB_HOST_BANG_CLK);
3116 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3117 URTW_BB_HOST_BANG_CLK);
3119 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1);
3122 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW |
3123 URTW_BB_HOST_BANG_CLK);
3125 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW);
3127 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_RW);
3131 for (i = 0; i < rlen; i++, mask = mask >> 1) {
3132 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3133 o1 | URTW_BB_HOST_BANG_RW);
3135 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3136 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK);
3138 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3139 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK);
3141 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3142 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK);
3145 urtw_read16_m(sc, URTW_RF_PINS_INPUT, &tmp);
3146 value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0);
3147 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3148 o1 | URTW_BB_HOST_BANG_RW);
3152 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN |
3153 URTW_BB_HOST_BANG_RW);
3156 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2);
3157 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3);
3158 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_OUTPUT_MAGIC1);
3168 urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan)
3171 uint8_t *cck_pwrtable;
3172 uint8_t cck_pwrlvl_max = 15, ofdm_pwrlvl_max = 25, ofdm_pwrlvl_min = 10;
3173 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
3174 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
3177 /* CCK power setting */
3178 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl;
3179 cck_pwrlvl += sc->sc_txpwr_cck_base;
3180 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl;
3181 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 :
3182 urtw_8225v2_txpwr_cck;
3184 for (i = 0; i < 8; i++)
3185 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]);
3187 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
3188 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl]);
3189 usb_pause_mtx(&sc->sc_mtx, 1);
3191 /* OFDM power setting */
3192 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ?
3193 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min;
3194 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base;
3195 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
3197 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
3201 urtw_8187_write_phy_ofdm(sc, 2, 0x42);
3202 urtw_8187_write_phy_ofdm(sc, 5, 0x0);
3203 urtw_8187_write_phy_ofdm(sc, 6, 0x40);
3204 urtw_8187_write_phy_ofdm(sc, 7, 0x0);
3205 urtw_8187_write_phy_ofdm(sc, 8, 0x40);
3207 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
3208 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl]);
3209 usb_pause_mtx(&sc->sc_mtx, 1);
3215 urtw_8225v2_setgain(struct urtw_softc *sc, int16_t gain)
3221 gainp = urtw_8225v2_gain_bg;
3222 urtw_8187_write_phy_ofdm(sc, 0x0d, gainp[gain * 3]);
3223 usb_pause_mtx(&sc->sc_mtx, 1);
3224 urtw_8187_write_phy_ofdm(sc, 0x1b, gainp[gain * 3 + 1]);
3225 usb_pause_mtx(&sc->sc_mtx, 1);
3226 urtw_8187_write_phy_ofdm(sc, 0x1d, gainp[gain * 3 + 2]);
3227 usb_pause_mtx(&sc->sc_mtx, 1);
3228 urtw_8187_write_phy_ofdm(sc, 0x21, 0x17);
3229 usb_pause_mtx(&sc->sc_mtx, 1);
3235 urtw_8225_isv2(struct urtw_softc *sc, int *ret)
3242 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_MAGIC5);
3243 urtw_write16_m(sc, URTW_RF_PINS_SELECT, URTW_RF_PINS_MAGIC5);
3244 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, URTW_RF_PINS_MAGIC5);
3245 usb_pause_mtx(&sc->sc_mtx, 500);
3247 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC,
3248 URTW_8225_ADDR_0_DATA_MAGIC1);
3250 error = urtw_8225_read(sc, URTW_8225_ADDR_8_MAGIC, &data);
3253 if (data != URTW_8225_ADDR_8_DATA_MAGIC1)
3256 error = urtw_8225_read(sc, URTW_8225_ADDR_9_MAGIC, &data);
3259 if (data != URTW_8225_ADDR_9_DATA_MAGIC1)
3263 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC,
3264 URTW_8225_ADDR_0_DATA_MAGIC2);
3270 urtw_8225v2b_rf_init(struct urtw_softc *sc)
3272 #define N(a) (sizeof(a) / sizeof((a)[0]))
3276 for (i = 0; i < N(urtw_8225v2b_rf_part1); i++)
3277 urtw_8225_write(sc, urtw_8225v2b_rf_part1[i].reg,
3278 urtw_8225v2b_rf_part1[i].val);
3281 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC1);
3283 for (i = 0; i < N(urtw_8225v2b_rxgain); i++) {
3284 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1));
3285 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC,
3286 urtw_8225v2b_rxgain[i]);
3289 urtw_8225_write(sc, URTW_8225_ADDR_3_MAGIC, 0x080);
3290 urtw_8225_write(sc, URTW_8225_ADDR_5_MAGIC, 0x004);
3291 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x0b7);
3292 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0xc4d);
3293 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0x44d);
3294 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x2bf);
3296 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 0x03);
3297 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 0x07);
3298 urtw_write8_m(sc, URTW_TX_ANTENNA, 0x03);
3300 urtw_8187_write_phy_ofdm(sc, 0x80, 0x12);
3301 for (i = 0; i < N(urtw_8225z2_agc); i++) {
3302 urtw_8187_write_phy_ofdm(sc, 0xf, urtw_8225z2_agc[i]);
3303 urtw_8187_write_phy_ofdm(sc, 0xe, 0x80 + i);
3304 urtw_8187_write_phy_ofdm(sc, 0xe, 0);
3306 urtw_8187_write_phy_ofdm(sc, 0x80, 0x10);
3308 for (i = 0; i < N(urtw_8225v2b_rf_part2); i++)
3309 urtw_8187_write_phy_ofdm(sc, i, urtw_8225v2b_rf_part2[i].val);
3311 urtw_write32_m(sc, 0xf0, (7 << 12) | (3 << 8) | 0x1c);
3312 urtw_write32_m(sc, 0xf4, (7 << 12) | (3 << 8) | 0x1c);
3313 urtw_write32_m(sc, 0xf8, (7 << 12) | (3 << 8) | 0x1c);
3314 urtw_write32_m(sc, 0xfc, (7 << 12) | (3 << 8) | 0x1c);
3315 urtw_write8_m(sc, URTW_ACM_CONTROL, 0);
3317 urtw_8187_write_phy_ofdm(sc, 0x97, 0x46);
3318 urtw_8187_write_phy_ofdm(sc, 0xa4, 0xb6);
3319 urtw_8187_write_phy_ofdm(sc, 0x85, 0xfc);
3320 urtw_8187_write_phy_cck(sc, 0xc1, 0x88);
3327 urtw_8225v2b_rf_set_chan(struct urtw_softc *sc, int chan)
3330 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
3333 error = urtw_8225v2b_set_txpwrlvl(sc, chan);
3337 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]);
3338 usb_pause_mtx(&sc->sc_mtx, 10);
3340 urtw_write8_m(sc, URTW_SIFS, 0xa);
3341 if (ic->ic_flags & IEEE80211_F_SHSLOT) {
3342 urtw_write8_m(sc, URTW_SLOT, 0x9);
3343 urtw_write8_m(sc, URTW_DIFS, 0x1c);
3344 /* In 8187B, BRSR + 1 ==> EIFS register */
3345 urtw_write8_m(sc, URTW_BRSR + 1, 0x53);
3347 ack = 112 + 48 + 0x1c;
3348 ack += (ic->ic_flags & IEEE80211_F_SHPREAMBLE) ?
3350 urtw_write8_m(sc, URTW_CARRIER_SCOUNT,
3353 urtw_write8_m(sc, URTW_SLOT, 0x14);
3354 urtw_write8_m(sc, URTW_DIFS, 0x32);
3355 /* In 8187B, BRSR + 1 ==> EIFS register */
3356 urtw_write8_m(sc, URTW_BRSR + 1, 0x5b);
3358 ack = 112 + 48 + 0x32;
3359 ack += (ic->ic_flags & IEEE80211_F_SHPREAMBLE) ?
3361 urtw_write8_m(sc, URTW_CARRIER_SCOUNT,
3371 urtw_8225v2b_set_txpwrlvl(struct urtw_softc *sc, int chan)
3374 uint8_t *cck_pwrtable;
3375 uint8_t cck_pwrlvl_max = 15;
3376 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
3377 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
3380 /* CCK power setting */
3381 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ?
3382 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? cck_pwrlvl_max : 22) :
3383 (cck_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 0 : 7));
3384 cck_pwrlvl += sc->sc_txpwr_cck_base;
3385 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl;
3386 cck_pwrtable = (chan == 14) ? urtw_8225v2b_txpwr_cck_ch14 :
3387 urtw_8225v2b_txpwr_cck;
3389 if (sc->sc_flags & URTW_RTL8187B_REV_B)
3390 cck_pwrtable += (cck_pwrlvl <= 6) ? 0 :
3391 ((cck_pwrlvl <= 11) ? 8 : 16);
3393 cck_pwrtable += (cck_pwrlvl <= 5) ? 0 :
3394 ((cck_pwrlvl <= 11) ? 8 : ((cck_pwrlvl <= 17) ? 16 : 24));
3396 for (i = 0; i < 8; i++)
3397 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]);
3399 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
3400 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl] << 1);
3401 usb_pause_mtx(&sc->sc_mtx, 1);
3403 /* OFDM power setting */
3404 ofdm_pwrlvl = (ofdm_pwrlvl > 15) ?
3405 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 17 : 25) :
3406 (ofdm_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 2 : 10));
3407 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base;
3408 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
3410 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
3411 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl] << 1);
3413 if (sc->sc_flags & URTW_RTL8187B_REV_B) {
3414 if (ofdm_pwrlvl <= 11) {
3415 urtw_8187_write_phy_ofdm(sc, 0x87, 0x60);
3416 urtw_8187_write_phy_ofdm(sc, 0x89, 0x60);
3418 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c);
3419 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c);
3422 if (ofdm_pwrlvl <= 11) {
3423 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c);
3424 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c);
3425 } else if (ofdm_pwrlvl <= 17) {
3426 urtw_8187_write_phy_ofdm(sc, 0x87, 0x54);
3427 urtw_8187_write_phy_ofdm(sc, 0x89, 0x54);
3429 urtw_8187_write_phy_ofdm(sc, 0x87, 0x50);
3430 urtw_8187_write_phy_ofdm(sc, 0x89, 0x50);
3433 usb_pause_mtx(&sc->sc_mtx, 1);
3439 urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data)
3441 struct usb_device_request req;
3444 req.bmRequestType = UT_READ_VENDOR_DEVICE;
3445 req.bRequest = URTW_8187_GETREGS_REQ;
3446 USETW(req.wValue, val | 0xfe00);
3447 USETW(req.wIndex, 0);
3448 USETW(req.wLength, sizeof(uint8_t));
3450 error = urtw_do_request(sc, &req, data);
3455 urtw_write8e(struct urtw_softc *sc, int val, uint8_t data)
3457 struct usb_device_request req;
3459 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
3460 req.bRequest = URTW_8187_SETREGS_REQ;
3461 USETW(req.wValue, val | 0xfe00);
3462 USETW(req.wIndex, 0);
3463 USETW(req.wLength, sizeof(uint8_t));
3465 return (urtw_do_request(sc, &req, &data));
3469 urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val)
3474 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3478 urtw_read8_m(sc, URTW_CONFIG3, &data);
3479 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
3480 urtw_write32_m(sc, URTW_ANAPARAM, val);
3481 urtw_read8_m(sc, URTW_CONFIG3, &data);
3482 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
3484 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3492 urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val)
3497 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3501 urtw_read8_m(sc, URTW_CONFIG3, &data);
3502 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
3503 urtw_write32_m(sc, URTW_ANAPARAM2, val);
3504 urtw_read8_m(sc, URTW_CONFIG3, &data);
3505 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
3507 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3515 urtw_intr_enable(struct urtw_softc *sc)
3519 urtw_write16_m(sc, URTW_INTR_MASK, 0xffff);
3525 urtw_intr_disable(struct urtw_softc *sc)
3529 urtw_write16_m(sc, URTW_INTR_MASK, 0);
3535 urtw_reset(struct urtw_softc *sc)
3540 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
3543 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
3547 error = urtw_intr_disable(sc);
3550 usb_pause_mtx(&sc->sc_mtx, 100);
3552 error = urtw_write8e(sc, 0x18, 0x10);
3555 error = urtw_write8e(sc, 0x18, 0x11);
3558 error = urtw_write8e(sc, 0x18, 0x00);
3561 usb_pause_mtx(&sc->sc_mtx, 100);
3563 urtw_read8_m(sc, URTW_CMD, &data);
3564 data = (data & 0x2) | URTW_CMD_RST;
3565 urtw_write8_m(sc, URTW_CMD, data);
3566 usb_pause_mtx(&sc->sc_mtx, 100);
3568 urtw_read8_m(sc, URTW_CMD, &data);
3569 if (data & URTW_CMD_RST) {
3570 device_printf(sc->sc_dev, "reset timeout\n");
3574 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD);
3577 usb_pause_mtx(&sc->sc_mtx, 100);
3579 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
3582 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
3590 urtw_led_ctl(struct urtw_softc *sc, int mode)
3592 usb_error_t error = 0;
3594 switch (sc->sc_strategy) {
3595 case URTW_SW_LED_MODE0:
3596 error = urtw_led_mode0(sc, mode);
3598 case URTW_SW_LED_MODE1:
3599 error = urtw_led_mode1(sc, mode);
3601 case URTW_SW_LED_MODE2:
3602 error = urtw_led_mode2(sc, mode);
3604 case URTW_SW_LED_MODE3:
3605 error = urtw_led_mode3(sc, mode);
3608 panic("unsupported LED mode %d\n", sc->sc_strategy);
3616 urtw_led_mode0(struct urtw_softc *sc, int mode)
3620 case URTW_LED_CTL_POWER_ON:
3621 sc->sc_gpio_ledstate = URTW_LED_POWER_ON_BLINK;
3623 case URTW_LED_CTL_TX:
3624 if (sc->sc_gpio_ledinprogress == 1)
3627 sc->sc_gpio_ledstate = URTW_LED_BLINK_NORMAL;
3628 sc->sc_gpio_blinktime = 2;
3630 case URTW_LED_CTL_LINK:
3631 sc->sc_gpio_ledstate = URTW_LED_ON;
3634 panic("unsupported LED mode 0x%x", mode);
3638 switch (sc->sc_gpio_ledstate) {
3640 if (sc->sc_gpio_ledinprogress != 0)
3642 urtw_led_on(sc, URTW_LED_GPIO);
3644 case URTW_LED_BLINK_NORMAL:
3645 if (sc->sc_gpio_ledinprogress != 0)
3647 sc->sc_gpio_ledinprogress = 1;
3648 sc->sc_gpio_blinkstate = (sc->sc_gpio_ledon != 0) ?
3649 URTW_LED_OFF : URTW_LED_ON;
3650 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc);
3652 case URTW_LED_POWER_ON_BLINK:
3653 urtw_led_on(sc, URTW_LED_GPIO);
3654 usb_pause_mtx(&sc->sc_mtx, 100);
3655 urtw_led_off(sc, URTW_LED_GPIO);
3658 panic("unknown LED status 0x%x", sc->sc_gpio_ledstate);
3665 urtw_led_mode1(struct urtw_softc *sc, int mode)
3668 return (USB_ERR_INVAL);
3672 urtw_led_mode2(struct urtw_softc *sc, int mode)
3675 return (USB_ERR_INVAL);
3679 urtw_led_mode3(struct urtw_softc *sc, int mode)
3682 return (USB_ERR_INVAL);
3686 urtw_led_on(struct urtw_softc *sc, int type)
3690 if (type == URTW_LED_GPIO) {
3691 switch (sc->sc_gpio_ledpin) {
3692 case URTW_LED_PIN_GPIO0:
3693 urtw_write8_m(sc, URTW_GPIO, 0x01);
3694 urtw_write8_m(sc, URTW_GP_ENABLE, 0x00);
3697 panic("unsupported LED PIN type 0x%x",
3698 sc->sc_gpio_ledpin);
3702 panic("unsupported LED type 0x%x", type);
3706 sc->sc_gpio_ledon = 1;
3712 urtw_led_off(struct urtw_softc *sc, int type)
3716 if (type == URTW_LED_GPIO) {
3717 switch (sc->sc_gpio_ledpin) {
3718 case URTW_LED_PIN_GPIO0:
3719 urtw_write8_m(sc, URTW_GPIO, URTW_GPIO_DATA_MAGIC1);
3721 URTW_GP_ENABLE, URTW_GP_ENABLE_DATA_MAGIC1);
3724 panic("unsupported LED PIN type 0x%x",
3725 sc->sc_gpio_ledpin);
3729 panic("unsupported LED type 0x%x", type);
3733 sc->sc_gpio_ledon = 0;
3740 urtw_led_ch(void *arg)
3742 struct urtw_softc *sc = arg;
3743 struct ifnet *ifp = sc->sc_ifp;
3744 struct ieee80211com *ic = ifp->if_l2com;
3746 ieee80211_runtask(ic, &sc->sc_led_task);
3750 urtw_ledtask(void *arg, int pending)
3752 struct urtw_softc *sc = arg;
3754 if (sc->sc_strategy != URTW_SW_LED_MODE0)
3755 panic("could not process a LED strategy 0x%x", sc->sc_strategy);
3763 urtw_led_blink(struct urtw_softc *sc)
3768 if (sc->sc_gpio_blinkstate == URTW_LED_ON)
3769 error = urtw_led_on(sc, URTW_LED_GPIO);
3771 error = urtw_led_off(sc, URTW_LED_GPIO);
3772 sc->sc_gpio_blinktime--;
3773 if (sc->sc_gpio_blinktime == 0)
3776 if (sc->sc_gpio_ledstate != URTW_LED_BLINK_NORMAL &&
3777 sc->sc_gpio_ledstate != URTW_LED_BLINK_SLOWLY &&
3778 sc->sc_gpio_ledstate != URTW_LED_BLINK_CM3)
3782 if (sc->sc_gpio_ledstate == URTW_LED_ON &&
3783 sc->sc_gpio_ledon == 0)
3784 error = urtw_led_on(sc, URTW_LED_GPIO);
3785 else if (sc->sc_gpio_ledstate == URTW_LED_OFF &&
3786 sc->sc_gpio_ledon == 1)
3787 error = urtw_led_off(sc, URTW_LED_GPIO);
3789 sc->sc_gpio_blinktime = 0;
3790 sc->sc_gpio_ledinprogress = 0;
3794 sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ?
3795 URTW_LED_ON : URTW_LED_OFF;
3797 switch (sc->sc_gpio_ledstate) {
3798 case URTW_LED_BLINK_NORMAL:
3799 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc);
3802 panic("unknown LED status 0x%x", sc->sc_gpio_ledstate);
3809 urtw_rx_enable(struct urtw_softc *sc)
3814 usbd_transfer_start((sc->sc_flags & URTW_RTL8187B) ?
3815 sc->sc_xfer[URTW_8187B_BULK_RX] : sc->sc_xfer[URTW_8187L_BULK_RX]);
3817 error = urtw_rx_setconf(sc);
3821 urtw_read8_m(sc, URTW_CMD, &data);
3822 urtw_write8_m(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE);
3828 urtw_tx_enable(struct urtw_softc *sc)
3834 if (sc->sc_flags & URTW_RTL8187B) {
3835 urtw_read32_m(sc, URTW_TX_CONF, &data);
3836 data &= ~URTW_TX_LOOPBACK_MASK;
3837 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK);
3838 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK);
3839 data &= ~URTW_TX_SWPLCPLEN;
3840 data |= URTW_TX_HW_SEQNUM | URTW_TX_DISREQQSIZE |
3841 (7 << 8) | /* short retry limit */
3842 (7 << 0) | /* long retry limit */
3843 (7 << 21); /* MAX TX DMA */
3844 urtw_write32_m(sc, URTW_TX_CONF, data);
3846 urtw_read8_m(sc, URTW_CMD, &data8);
3847 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE);
3851 urtw_read8_m(sc, URTW_CW_CONF, &data8);
3852 data8 &= ~(URTW_CW_CONF_PERPACKET_CW | URTW_CW_CONF_PERPACKET_RETRY);
3853 urtw_write8_m(sc, URTW_CW_CONF, data8);
3855 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8);
3856 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_GAIN;
3857 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_ANTSEL;
3858 data8 &= ~URTW_TX_AGC_CTL_FEEDBACK_ANT;
3859 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8);
3861 urtw_read32_m(sc, URTW_TX_CONF, &data);
3862 data &= ~URTW_TX_LOOPBACK_MASK;
3863 data |= URTW_TX_LOOPBACK_NONE;
3864 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK);
3865 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT;
3866 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT;
3867 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK);
3868 data |= URTW_TX_MXDMA_2048 | URTW_TX_CWMIN | URTW_TX_DISCW;
3869 data &= ~URTW_TX_SWPLCPLEN;
3870 data |= URTW_TX_NOICV;
3871 urtw_write32_m(sc, URTW_TX_CONF, data);
3873 urtw_read8_m(sc, URTW_CMD, &data8);
3874 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE);
3880 urtw_rx_setconf(struct urtw_softc *sc)
3882 struct ifnet *ifp = sc->sc_ifp;
3883 struct ieee80211com *ic = ifp->if_l2com;
3887 urtw_read32_m(sc, URTW_RX, &data);
3888 data = data &~ URTW_RX_FILTER_MASK;
3889 if (sc->sc_flags & URTW_RTL8187B) {
3890 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA |
3891 URTW_RX_FILTER_MCAST | URTW_RX_FILTER_BCAST |
3892 URTW_RX_FILTER_NICMAC | URTW_RX_CHECK_BSSID |
3893 URTW_RX_FIFO_THRESHOLD_NONE |
3894 URTW_MAX_RX_DMA_2048 |
3895 URTW_RX_AUTORESETPHY | URTW_RCR_ONLYERLPKT;
3897 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA;
3898 data = data | URTW_RX_FILTER_BCAST | URTW_RX_FILTER_MCAST;
3900 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
3901 data = data | URTW_RX_FILTER_ICVERR;
3902 data = data | URTW_RX_FILTER_PWR;
3904 if (sc->sc_crcmon == 1 && ic->ic_opmode == IEEE80211_M_MONITOR)
3905 data = data | URTW_RX_FILTER_CRCERR;
3907 if (ic->ic_opmode == IEEE80211_M_MONITOR ||
3908 (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC))) {
3909 data = data | URTW_RX_FILTER_ALLMAC;
3911 data = data | URTW_RX_FILTER_NICMAC;
3912 data = data | URTW_RX_CHECK_BSSID;
3915 data = data &~ URTW_RX_FIFO_THRESHOLD_MASK;
3916 data = data | URTW_RX_FIFO_THRESHOLD_NONE |
3917 URTW_RX_AUTORESETPHY;
3918 data = data &~ URTW_MAX_RX_DMA_MASK;
3919 data = data | URTW_MAX_RX_DMA_2048 | URTW_RCR_ONLYERLPKT;
3922 urtw_write32_m(sc, URTW_RX, data);
3927 static struct mbuf *
3928 urtw_rxeof(struct usb_xfer *xfer, struct urtw_data *data, int *rssi_p,
3931 int actlen, flen, len, nf = -95, rssi;
3932 struct ieee80211_frame *wh;
3933 struct mbuf *m, *mnew;
3934 struct urtw_8187b_rxhdr *bhdr;
3935 struct urtw_softc *sc = data->sc;
3936 struct ifnet *ifp = sc->sc_ifp;
3937 struct ieee80211com *ic = ifp->if_l2com;
3938 uint8_t *desc, quality = 0, rate;
3940 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
3942 if (actlen < URTW_MIN_RXBUFSZ) {
3947 if (sc->sc_flags & URTW_RTL8187B) {
3948 len = actlen - (sizeof(struct urtw_8187b_rxhdr));
3949 bhdr = (struct urtw_8187b_rxhdr *)(data->buf + len);
3950 desc = data->buf + len;
3951 flen = ((desc[1] & 0x0f) << 8) + (desc[0] & 0xff);
3952 if (flen > actlen) {
3956 rate = (le32toh(bhdr->flags) >> 20) & 0xf;
3957 rssi = 14 + (bhdr->rssi / 2);
3961 /* 4 dword and 4 byte CRC */
3962 len = actlen - (4 * 4);
3963 desc = data->buf + len;
3964 flen = ((desc[1] & 0x0f) << 8) + (desc[0] & 0xff);
3965 if (flen > actlen) {
3970 rate = (desc[2] & 0xf0) >> 4;
3971 quality = desc[4] & 0xff;
3973 rssi = (desc[6] & 0xfe) >> 1;
3974 if (!urtw_isbmode(rate)) {
3975 rssi = (rssi > 90) ? 90 : ((rssi < 25) ? 25 : rssi);
3976 rssi = ((90 - rssi) * 100) / 65;
3978 rssi = (rssi > 90) ? 95 : ((rssi < 30) ? 30 : rssi);
3979 rssi = ((95 - rssi) * 100) / 65;
3983 mnew = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
3991 data->buf = mtod(mnew, uint8_t *);
3994 m->m_pkthdr.rcvif = ifp;
3995 m->m_pkthdr.len = m->m_len = flen - 4;
3997 if (ieee80211_radiotap_active(ic)) {
3998 struct urtw_rx_radiotap_header *tap = &sc->sc_rxtap;
4000 /* XXX Are variables correct? */
4001 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq);
4002 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags);
4003 tap->wr_dbm_antsignal = (int8_t)rssi;
4006 wh = mtod(m, struct ieee80211_frame *);
4007 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_DATA)
4008 sc->sc_currate = (rate > 0) ? rate : sc->sc_currate;
4010 if ((sc->sc_flags & URTW_RTL8187B) == 0)
4011 nf = (quality > 64) ? 0 : ((64 - quality) * 100) / 64;
4020 urtw_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error)
4022 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4023 struct ifnet *ifp = sc->sc_ifp;
4024 struct ieee80211com *ic = ifp->if_l2com;
4025 struct ieee80211_frame *wh;
4026 struct ieee80211_node *ni;
4027 struct mbuf *m = NULL;
4028 struct urtw_data *data;
4032 URTW_ASSERT_LOCKED(sc);
4034 switch (USB_GET_STATE(xfer)) {
4035 case USB_ST_TRANSFERRED:
4036 data = STAILQ_FIRST(&sc->sc_rx_active);
4039 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
4040 m = urtw_rxeof(xfer, data, &rssi, &nf);
4041 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
4045 data = STAILQ_FIRST(&sc->sc_rx_inactive);
4047 KASSERT(m == NULL, ("mbuf isn't NULL"));
4050 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next);
4051 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next);
4052 usbd_xfer_set_frame_data(xfer, 0, data->buf,
4053 usbd_xfer_max_len(xfer));
4054 usbd_transfer_submit(xfer);
4057 * To avoid LOR we should unlock our private mutex here to call
4058 * ieee80211_input() because here is at the end of a USB
4059 * callback and safe to unlock.
4063 wh = mtod(m, struct ieee80211_frame *);
4064 ni = ieee80211_find_rxnode(ic,
4065 (struct ieee80211_frame_min *)wh);
4067 (void) ieee80211_input(ni, m, rssi, nf);
4068 /* node is no longer needed */
4069 ieee80211_free_node(ni);
4071 (void) ieee80211_input_all(ic, m, rssi, nf);
4077 /* needs it to the inactive queue due to a error. */
4078 data = STAILQ_FIRST(&sc->sc_rx_active);
4080 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
4081 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
4083 if (error != USB_ERR_CANCELLED) {
4084 usbd_xfer_set_stall(xfer);
4093 urtw_txeof(struct usb_xfer *xfer, struct urtw_data *data)
4095 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4096 struct ifnet *ifp = sc->sc_ifp;
4099 URTW_ASSERT_LOCKED(sc);
4102 * Do any tx complete callback. Note this must be done before releasing
4103 * the node reference.
4107 if (m->m_flags & M_TXCB) {
4109 ieee80211_process_callback(data->ni, m, 0);
4115 ieee80211_free_node(data->ni);
4120 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4124 urtw_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error)
4126 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4127 struct ifnet *ifp = sc->sc_ifp;
4128 struct urtw_data *data;
4130 URTW_ASSERT_LOCKED(sc);
4132 switch (USB_GET_STATE(xfer)) {
4133 case USB_ST_TRANSFERRED:
4134 data = STAILQ_FIRST(&sc->sc_tx_active);
4137 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next);
4138 urtw_txeof(xfer, data);
4139 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next);
4143 data = STAILQ_FIRST(&sc->sc_tx_pending);
4145 DPRINTF(sc, URTW_DEBUG_XMIT,
4146 "%s: empty pending queue\n", __func__);
4149 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next);
4150 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next);
4152 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen);
4153 usbd_transfer_submit(xfer);
4160 data = STAILQ_FIRST(&sc->sc_tx_active);
4163 if (data->ni != NULL) {
4164 ieee80211_free_node(data->ni);
4168 if (error != USB_ERR_CANCELLED) {
4169 usbd_xfer_set_stall(xfer);
4176 static struct urtw_data *
4177 _urtw_getbuf(struct urtw_softc *sc)
4179 struct urtw_data *bf;
4181 bf = STAILQ_FIRST(&sc->sc_tx_inactive);
4183 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next);
4187 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: %s\n", __func__,
4188 "out of xmit buffers");
4192 static struct urtw_data *
4193 urtw_getbuf(struct urtw_softc *sc)
4195 struct urtw_data *bf;
4197 URTW_ASSERT_LOCKED(sc);
4199 bf = _urtw_getbuf(sc);
4201 struct ifnet *ifp = sc->sc_ifp;
4203 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: stop queue\n", __func__);
4204 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4210 urtw_isbmode(uint16_t rate)
4213 rate = urtw_rtl2rate(rate);
4215 return ((rate <= 22 && rate != 12 && rate != 18) ||
4216 rate == 44) ? (1) : (0);
4219 static device_method_t urtw_methods[] = {
4220 DEVMETHOD(device_probe, urtw_match),
4221 DEVMETHOD(device_attach, urtw_attach),
4222 DEVMETHOD(device_detach, urtw_detach),
4225 static driver_t urtw_driver = {
4228 sizeof(struct urtw_softc)
4230 static devclass_t urtw_devclass;
4232 DRIVER_MODULE(urtw, uhub, urtw_driver, urtw_devclass, NULL, 0);
4233 MODULE_DEPEND(urtw, wlan, 1, 1, 1);
4234 MODULE_DEPEND(urtw, usb, 1, 1, 1);