2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * VIA Rhine fast ethernet PCI NIC driver
39 * Supports various network adapters based on the VIA Rhine
40 * and Rhine II PCI controllers, including the D-Link DFE530TX.
41 * Datasheets are available at http://www.via.com.tw.
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
49 * The VIA Rhine controllers are similar in some respects to the
50 * the DEC tulip chips, except less complicated. The controller
51 * uses an MII bus and an external physical layer interface. The
52 * receiver has a one entry perfect filter and a 64-bit hash table
53 * multicast filter. Transmit and receive descriptors are similar
56 * Some Rhine chips has a serious flaw in its transmit DMA mechanism:
57 * transmit buffers must be longword aligned. Unfortunately,
58 * FreeBSD doesn't guarantee that mbufs will be filled in starting
59 * at longword boundaries, so we have to do a buffer copy before
63 #ifdef HAVE_KERNEL_OPTION_HEADERS
64 #include "opt_device_polling.h"
67 #include <sys/param.h>
68 #include <sys/systm.h>
70 #include <sys/endian.h>
71 #include <sys/kernel.h>
72 #include <sys/malloc.h>
74 #include <sys/module.h>
76 #include <sys/socket.h>
77 #include <sys/sockio.h>
78 #include <sys/sysctl.h>
79 #include <sys/taskqueue.h>
83 #include <net/ethernet.h>
84 #include <net/if_dl.h>
85 #include <net/if_media.h>
86 #include <net/if_types.h>
87 #include <net/if_vlan_var.h>
89 #include <dev/mii/mii.h>
90 #include <dev/mii/miivar.h>
92 #include <dev/pci/pcireg.h>
93 #include <dev/pci/pcivar.h>
95 #include <machine/bus.h>
97 #include <dev/vr/if_vrreg.h>
99 /* "device miibus" required. See GENERIC if you get errors here. */
100 #include "miibus_if.h"
102 MODULE_DEPEND(vr, pci, 1, 1, 1);
103 MODULE_DEPEND(vr, ether, 1, 1, 1);
104 MODULE_DEPEND(vr, miibus, 1, 1, 1);
106 /* Define to show Rx/Tx error status. */
107 #undef VR_SHOW_ERRORS
108 #define VR_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
111 * Various supported device vendors/types, their names & quirks.
113 #define VR_Q_NEEDALIGN (1<<0)
114 #define VR_Q_CSUM (1<<1)
115 #define VR_Q_CAM (1<<2)
117 static struct vr_type {
123 { VIA_VENDORID, VIA_DEVICEID_RHINE,
125 "VIA VT3043 Rhine I 10/100BaseTX" },
126 { VIA_VENDORID, VIA_DEVICEID_RHINE_II,
128 "VIA VT86C100A Rhine II 10/100BaseTX" },
129 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2,
131 "VIA VT6102 Rhine II 10/100BaseTX" },
132 { VIA_VENDORID, VIA_DEVICEID_RHINE_III,
134 "VIA VT6105 Rhine III 10/100BaseTX" },
135 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M,
137 "VIA VT6105M Rhine III 10/100BaseTX" },
138 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II,
140 "Delta Electronics Rhine II 10/100BaseTX" },
141 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II,
143 "Addtron Technology Rhine II 10/100BaseTX" },
147 static int vr_probe(device_t);
148 static int vr_attach(device_t);
149 static int vr_detach(device_t);
150 static int vr_shutdown(device_t);
151 static int vr_suspend(device_t);
152 static int vr_resume(device_t);
154 static void vr_dmamap_cb(void *, bus_dma_segment_t *, int, int);
155 static int vr_dma_alloc(struct vr_softc *);
156 static void vr_dma_free(struct vr_softc *);
157 static __inline void vr_discard_rxbuf(struct vr_rxdesc *);
158 static int vr_newbuf(struct vr_softc *, int);
160 #ifndef __NO_STRICT_ALIGNMENT
161 static __inline void vr_fixup_rx(struct mbuf *);
163 static int vr_rxeof(struct vr_softc *);
164 static void vr_txeof(struct vr_softc *);
165 static void vr_tick(void *);
166 static int vr_error(struct vr_softc *, uint16_t);
167 static void vr_tx_underrun(struct vr_softc *);
168 static void vr_intr(void *);
169 static void vr_start(struct ifnet *);
170 static void vr_start_locked(struct ifnet *);
171 static int vr_encap(struct vr_softc *, struct mbuf **);
172 static int vr_ioctl(struct ifnet *, u_long, caddr_t);
173 static void vr_init(void *);
174 static void vr_init_locked(struct vr_softc *);
175 static void vr_tx_start(struct vr_softc *);
176 static void vr_rx_start(struct vr_softc *);
177 static int vr_tx_stop(struct vr_softc *);
178 static int vr_rx_stop(struct vr_softc *);
179 static void vr_stop(struct vr_softc *);
180 static void vr_watchdog(struct vr_softc *);
181 static int vr_ifmedia_upd(struct ifnet *);
182 static void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *);
184 static int vr_miibus_readreg(device_t, int, int);
185 static int vr_miibus_writereg(device_t, int, int, int);
186 static void vr_miibus_statchg(device_t);
188 static void vr_link_task(void *, int);
189 static void vr_cam_mask(struct vr_softc *, uint32_t, int);
190 static int vr_cam_data(struct vr_softc *, int, int, uint8_t *);
191 static void vr_set_filter(struct vr_softc *);
192 static void vr_reset(const struct vr_softc *);
193 static int vr_tx_ring_init(struct vr_softc *);
194 static int vr_rx_ring_init(struct vr_softc *);
195 static void vr_setwol(struct vr_softc *);
196 static void vr_clrwol(struct vr_softc *);
197 static int vr_sysctl_stats(SYSCTL_HANDLER_ARGS);
199 static struct vr_tx_threshold_table {
203 } vr_tx_threshold_tables[] = {
204 { VR_TXTHRESH_64BYTES, VR_BCR1_TXTHRESH64BYTES, 64 },
205 { VR_TXTHRESH_128BYTES, VR_BCR1_TXTHRESH128BYTES, 128 },
206 { VR_TXTHRESH_256BYTES, VR_BCR1_TXTHRESH256BYTES, 256 },
207 { VR_TXTHRESH_512BYTES, VR_BCR1_TXTHRESH512BYTES, 512 },
208 { VR_TXTHRESH_1024BYTES, VR_BCR1_TXTHRESH1024BYTES, 1024 },
209 { VR_TXTHRESH_STORENFWD, VR_BCR1_TXTHRESHSTORENFWD, 2048 }
212 static device_method_t vr_methods[] = {
213 /* Device interface */
214 DEVMETHOD(device_probe, vr_probe),
215 DEVMETHOD(device_attach, vr_attach),
216 DEVMETHOD(device_detach, vr_detach),
217 DEVMETHOD(device_shutdown, vr_shutdown),
218 DEVMETHOD(device_suspend, vr_suspend),
219 DEVMETHOD(device_resume, vr_resume),
222 DEVMETHOD(bus_print_child, bus_generic_print_child),
223 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
226 DEVMETHOD(miibus_readreg, vr_miibus_readreg),
227 DEVMETHOD(miibus_writereg, vr_miibus_writereg),
228 DEVMETHOD(miibus_statchg, vr_miibus_statchg),
229 DEVMETHOD(miibus_linkchg, vr_miibus_statchg),
234 static driver_t vr_driver = {
237 sizeof(struct vr_softc)
240 static devclass_t vr_devclass;
242 DRIVER_MODULE(vr, pci, vr_driver, vr_devclass, 0, 0);
243 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0);
246 vr_miibus_readreg(device_t dev, int phy, int reg)
251 sc = device_get_softc(dev);
252 if (sc->vr_phyaddr != phy)
255 /* Set the register address. */
256 CSR_WRITE_1(sc, VR_MIIADDR, reg);
257 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB);
259 for (i = 0; i < VR_MII_TIMEOUT; i++) {
261 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0)
264 if (i == VR_MII_TIMEOUT)
265 device_printf(sc->vr_dev, "phy read timeout %d:%d\n", phy, reg);
267 return (CSR_READ_2(sc, VR_MIIDATA));
271 vr_miibus_writereg(device_t dev, int phy, int reg, int data)
276 sc = device_get_softc(dev);
277 if (sc->vr_phyaddr != phy)
280 /* Set the register address and data to write. */
281 CSR_WRITE_1(sc, VR_MIIADDR, reg);
282 CSR_WRITE_2(sc, VR_MIIDATA, data);
283 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB);
285 for (i = 0; i < VR_MII_TIMEOUT; i++) {
287 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0)
290 if (i == VR_MII_TIMEOUT)
291 device_printf(sc->vr_dev, "phy write timeout %d:%d\n", phy,
298 vr_miibus_statchg(device_t dev)
302 sc = device_get_softc(dev);
303 taskqueue_enqueue(taskqueue_swi, &sc->vr_link_task);
307 * In order to fiddle with the
308 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
309 * first have to put the transmit and/or receive logic in the idle state.
312 vr_link_task(void *arg, int pending)
315 struct mii_data *mii;
318 uint8_t cr0, cr1, fc;
320 sc = (struct vr_softc *)arg;
323 mii = device_get_softc(sc->vr_miibus);
325 if (mii == NULL || ifp == NULL ||
326 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
331 if (mii->mii_media_status & IFM_ACTIVE) {
332 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
337 if (sc->vr_link != 0) {
338 cr0 = CSR_READ_1(sc, VR_CR0);
339 cr1 = CSR_READ_1(sc, VR_CR1);
340 mfdx = (cr1 & VR_CR1_FULLDUPLEX) != 0;
341 lfdx = (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0;
343 if ((cr0 & (VR_CR0_TX_ON | VR_CR0_RX_ON)) != 0) {
344 if (vr_tx_stop(sc) != 0 ||
345 vr_rx_stop(sc) != 0) {
346 device_printf(sc->vr_dev,
347 "%s: Tx/Rx shutdown error -- "
348 "resetting\n", __func__);
349 sc->vr_flags |= VR_F_RESTART;
355 cr1 |= VR_CR1_FULLDUPLEX;
357 cr1 &= ~VR_CR1_FULLDUPLEX;
358 CSR_WRITE_1(sc, VR_CR1, cr1);
362 /* Configure flow-control. */
363 if (sc->vr_revid >= REV_ID_VT6105_A0) {
364 fc = CSR_READ_1(sc, VR_FLOWCR1);
365 fc &= ~(VR_FLOWCR1_TXPAUSE | VR_FLOWCR1_RXPAUSE);
366 if ((IFM_OPTIONS(mii->mii_media_active) &
367 IFM_ETH_RXPAUSE) != 0)
368 fc |= VR_FLOWCR1_RXPAUSE;
369 if ((IFM_OPTIONS(mii->mii_media_active) &
370 IFM_ETH_TXPAUSE) != 0)
371 fc |= VR_FLOWCR1_TXPAUSE;
372 CSR_WRITE_1(sc, VR_FLOWCR1, fc);
373 } else if (sc->vr_revid >= REV_ID_VT6102_A) {
374 /* No Tx puase capability available for Rhine II. */
375 fc = CSR_READ_1(sc, VR_MISC_CR0);
376 fc &= ~VR_MISCCR0_RXPAUSE;
377 if ((IFM_OPTIONS(mii->mii_media_active) &
378 IFM_ETH_RXPAUSE) != 0)
379 fc |= VR_MISCCR0_RXPAUSE;
380 CSR_WRITE_1(sc, VR_MISC_CR0, fc);
386 if (vr_tx_stop(sc) != 0 || vr_rx_stop(sc) != 0) {
387 device_printf(sc->vr_dev,
388 "%s: Tx/Rx shutdown error -- resetting\n",
390 sc->vr_flags |= VR_F_RESTART;
400 vr_cam_mask(struct vr_softc *sc, uint32_t mask, int type)
403 if (type == VR_MCAST_CAM)
404 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST);
406 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN);
407 CSR_WRITE_4(sc, VR_CAMMASK, mask);
408 CSR_WRITE_1(sc, VR_CAMCTL, 0);
412 vr_cam_data(struct vr_softc *sc, int type, int idx, uint8_t *mac)
416 if (type == VR_MCAST_CAM) {
417 if (idx < 0 || idx >= VR_CAM_MCAST_CNT || mac == NULL)
419 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST);
421 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN);
423 /* Set CAM entry address. */
424 CSR_WRITE_1(sc, VR_CAMADDR, idx);
425 /* Set CAM entry data. */
426 if (type == VR_MCAST_CAM) {
427 for (i = 0; i < ETHER_ADDR_LEN; i++)
428 CSR_WRITE_1(sc, VR_MCAM0 + i, mac[i]);
430 CSR_WRITE_1(sc, VR_VCAM0, mac[0]);
431 CSR_WRITE_1(sc, VR_VCAM1, mac[1]);
434 /* Write CAM and wait for self-clear of VR_CAMCTL_WRITE bit. */
435 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_WRITE);
436 for (i = 0; i < VR_TIMEOUT; i++) {
438 if ((CSR_READ_1(sc, VR_CAMCTL) & VR_CAMCTL_WRITE) == 0)
443 device_printf(sc->vr_dev, "%s: setting CAM filter timeout!\n",
445 CSR_WRITE_1(sc, VR_CAMCTL, 0);
447 return (i == VR_TIMEOUT ? ETIMEDOUT : 0);
451 * Program the 64-bit multicast hash filter.
454 vr_set_filter(struct vr_softc *sc)
458 uint32_t hashes[2] = { 0, 0 };
459 struct ifmultiaddr *ifma;
467 rxfilt = CSR_READ_1(sc, VR_RXCFG);
468 rxfilt &= ~(VR_RXCFG_RX_PROMISC | VR_RXCFG_RX_BROAD |
470 if (ifp->if_flags & IFF_BROADCAST)
471 rxfilt |= VR_RXCFG_RX_BROAD;
472 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
473 rxfilt |= VR_RXCFG_RX_MULTI;
474 if (ifp->if_flags & IFF_PROMISC)
475 rxfilt |= VR_RXCFG_RX_PROMISC;
476 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
477 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF);
478 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF);
482 /* Now program new ones. */
486 if ((sc->vr_quirks & VR_Q_CAM) != 0) {
488 * For hardwares that have CAM capability, use
489 * 32 entries multicast perfect filter.
492 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
493 if (ifma->ifma_addr->sa_family != AF_LINK)
495 error = vr_cam_data(sc, VR_MCAST_CAM, mcnt,
496 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
501 cam_mask |= 1 << mcnt;
504 vr_cam_mask(sc, VR_MCAST_CAM, cam_mask);
507 if ((sc->vr_quirks & VR_Q_CAM) == 0 || error != 0) {
509 * If there are too many multicast addresses or
510 * setting multicast CAM filter failed, use hash
511 * table based filtering.
514 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
515 if (ifma->ifma_addr->sa_family != AF_LINK)
517 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
518 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
520 hashes[0] |= (1 << h);
522 hashes[1] |= (1 << (h - 32));
526 if_maddr_runlock(ifp);
529 rxfilt |= VR_RXCFG_RX_MULTI;
531 CSR_WRITE_4(sc, VR_MAR0, hashes[0]);
532 CSR_WRITE_4(sc, VR_MAR1, hashes[1]);
533 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
537 vr_reset(const struct vr_softc *sc)
541 /*VR_LOCK_ASSERT(sc);*/ /* XXX: Called during attach w/o lock. */
543 CSR_WRITE_1(sc, VR_CR1, VR_CR1_RESET);
544 if (sc->vr_revid < REV_ID_VT6102_A) {
545 /* VT86C100A needs more delay after reset. */
548 for (i = 0; i < VR_TIMEOUT; i++) {
550 if (!(CSR_READ_1(sc, VR_CR1) & VR_CR1_RESET))
553 if (i == VR_TIMEOUT) {
554 if (sc->vr_revid < REV_ID_VT6102_A)
555 device_printf(sc->vr_dev, "reset never completed!\n");
557 /* Use newer force reset command. */
558 device_printf(sc->vr_dev,
559 "Using force reset command.\n");
560 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST);
562 * Wait a little while for the chip to get its brains
572 * Probe for a VIA Rhine chip. Check the PCI vendor and device
573 * IDs against our list and return a match or NULL
575 static struct vr_type *
576 vr_match(device_t dev)
578 struct vr_type *t = vr_devs;
580 for (t = vr_devs; t->vr_name != NULL; t++)
581 if ((pci_get_vendor(dev) == t->vr_vid) &&
582 (pci_get_device(dev) == t->vr_did))
588 * Probe for a VIA Rhine chip. Check the PCI vendor and device
589 * IDs against our list and return a device name if we find a match.
592 vr_probe(device_t dev)
598 device_set_desc(dev, t->vr_name);
599 return (BUS_PROBE_DEFAULT);
605 * Attach the interface. Allocate softc structures, do ifmedia
606 * setup and ethernet/BPF attach.
609 vr_attach(device_t dev)
614 uint8_t eaddr[ETHER_ADDR_LEN];
618 sc = device_get_softc(dev);
621 KASSERT(t != NULL, ("Lost if_vr device match"));
622 sc->vr_quirks = t->vr_quirks;
623 device_printf(dev, "Quirks: 0x%x\n", sc->vr_quirks);
625 mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
627 callout_init_mtx(&sc->vr_stat_callout, &sc->vr_mtx, 0);
628 TASK_INIT(&sc->vr_link_task, 0, vr_link_task, sc);
629 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
630 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
631 OID_AUTO, "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
632 vr_sysctl_stats, "I", "Statistics");
637 * Map control/status registers.
639 pci_enable_busmaster(dev);
640 sc->vr_revid = pci_get_revid(dev);
641 device_printf(dev, "Revision: 0x%x\n", sc->vr_revid);
643 sc->vr_res_id = PCIR_BAR(0);
644 sc->vr_res_type = SYS_RES_IOPORT;
645 sc->vr_res = bus_alloc_resource_any(dev, sc->vr_res_type,
646 &sc->vr_res_id, RF_ACTIVE);
647 if (sc->vr_res == NULL) {
648 device_printf(dev, "couldn't map ports\n");
653 /* Allocate interrupt. */
655 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
656 RF_SHAREABLE | RF_ACTIVE);
658 if (sc->vr_irq == NULL) {
659 device_printf(dev, "couldn't map interrupt\n");
664 /* Allocate ifnet structure. */
665 ifp = sc->vr_ifp = if_alloc(IFT_ETHER);
667 device_printf(dev, "couldn't allocate ifnet structure\n");
672 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
673 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
674 ifp->if_ioctl = vr_ioctl;
675 ifp->if_start = vr_start;
676 ifp->if_init = vr_init;
677 IFQ_SET_MAXLEN(&ifp->if_snd, VR_TX_RING_CNT - 1);
678 ifp->if_snd.ifq_maxlen = VR_TX_RING_CNT - 1;
679 IFQ_SET_READY(&ifp->if_snd);
681 /* Configure Tx FIFO threshold. */
682 sc->vr_txthresh = VR_TXTHRESH_MIN;
683 if (sc->vr_revid < REV_ID_VT6105_A0) {
685 * Use store and forward mode for Rhine I/II.
686 * Otherwise they produce a lot of Tx underruns and
687 * it would take a while to get working FIFO threshold
690 sc->vr_txthresh = VR_TXTHRESH_MAX;
692 if ((sc->vr_quirks & VR_Q_CSUM) != 0) {
693 ifp->if_hwassist = VR_CSUM_FEATURES;
694 ifp->if_capabilities |= IFCAP_HWCSUM;
696 * To update checksum field the hardware may need to
697 * store entire frames into FIFO before transmitting.
699 sc->vr_txthresh = VR_TXTHRESH_MAX;
702 if (sc->vr_revid >= REV_ID_VT6102_A &&
703 pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
704 ifp->if_capabilities |= IFCAP_WOL_UCAST | IFCAP_WOL_MAGIC;
706 /* Rhine supports oversized VLAN frame. */
707 ifp->if_capabilities |= IFCAP_VLAN_MTU;
708 ifp->if_capenable = ifp->if_capabilities;
709 #ifdef DEVICE_POLLING
710 ifp->if_capabilities |= IFCAP_POLLING;
714 * Windows may put the chip in suspend mode when it
715 * shuts down. Be sure to kick it in the head to wake it
718 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
719 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1));
722 * Get station address. The way the Rhine chips work,
723 * you're not allowed to directly access the EEPROM once
724 * they've been programmed a special way. Consequently,
725 * we need to read the node address from the PAR0 and PAR1
727 * Reloading EEPROM also overwrites VR_CFGA, VR_CFGB,
728 * VR_CFGC and VR_CFGD such that memory mapped IO configured
729 * by driver is reset to default state.
731 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD);
732 for (i = VR_TIMEOUT; i > 0; i--) {
734 if ((CSR_READ_1(sc, VR_EECSR) & VR_EECSR_LOAD) == 0)
738 device_printf(dev, "Reloading EEPROM timeout!\n");
739 for (i = 0; i < ETHER_ADDR_LEN; i++)
740 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i);
742 /* Reset the adapter. */
744 /* Ack intr & disable further interrupts. */
745 CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
746 CSR_WRITE_2(sc, VR_IMR, 0);
747 if (sc->vr_revid >= REV_ID_VT6102_A)
748 CSR_WRITE_2(sc, VR_MII_IMR, 0);
750 if (sc->vr_revid < REV_ID_VT6102_A) {
751 pci_write_config(dev, VR_PCI_MODE2,
752 pci_read_config(dev, VR_PCI_MODE2, 1) |
753 VR_MODE2_MODE10T, 1);
755 /* Report error instead of retrying forever. */
756 pci_write_config(dev, VR_PCI_MODE2,
757 pci_read_config(dev, VR_PCI_MODE2, 1) |
758 VR_MODE2_PCEROPT, 1);
759 /* Detect MII coding error. */
760 pci_write_config(dev, VR_PCI_MODE3,
761 pci_read_config(dev, VR_PCI_MODE3, 1) |
763 if (sc->vr_revid >= REV_ID_VT6105_LOM &&
764 sc->vr_revid < REV_ID_VT6105M_A0)
765 pci_write_config(dev, VR_PCI_MODE2,
766 pci_read_config(dev, VR_PCI_MODE2, 1) |
767 VR_MODE2_MODE10T, 1);
768 /* Enable Memory-Read-Multiple. */
769 if (sc->vr_revid >= REV_ID_VT6107_A1 &&
770 sc->vr_revid < REV_ID_VT6105M_A0)
771 pci_write_config(dev, VR_PCI_MODE2,
772 pci_read_config(dev, VR_PCI_MODE2, 1) |
775 /* Disable MII AUTOPOLL. */
776 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL);
778 if (vr_dma_alloc(sc) != 0) {
783 /* Save PHY address. */
784 if (sc->vr_revid >= REV_ID_VT6105_A0)
787 sc->vr_phyaddr = CSR_READ_1(sc, VR_PHYADDR) & VR_PHYADDR_MASK;
790 if (mii_phy_probe(dev, &sc->vr_miibus,
791 vr_ifmedia_upd, vr_ifmedia_sts)) {
792 device_printf(dev, "MII without any phy!\n");
797 /* Call MI attach routine. */
798 ether_ifattach(ifp, eaddr);
800 * Tell the upper layer(s) we support long frames.
801 * Must appear after the call to ether_ifattach() because
802 * ether_ifattach() sets ifi_hdrlen to the default value.
804 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
806 /* Hook interrupt last to avoid having to lock softc. */
807 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET | INTR_MPSAFE,
808 NULL, vr_intr, sc, &sc->vr_intrhand);
811 device_printf(dev, "couldn't set up irq\n");
824 * Shutdown hardware and free up resources. This can be called any
825 * time after the mutex has been initialized. It is called in both
826 * the error case in attach and the normal detach case so it needs
827 * to be careful about only freeing resources that have actually been
831 vr_detach(device_t dev)
833 struct vr_softc *sc = device_get_softc(dev);
834 struct ifnet *ifp = sc->vr_ifp;
836 KASSERT(mtx_initialized(&sc->vr_mtx), ("vr mutex not initialized"));
838 #ifdef DEVICE_POLLING
839 if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING)
840 ether_poll_deregister(ifp);
843 /* These should only be active if attach succeeded. */
844 if (device_is_attached(dev)) {
849 callout_drain(&sc->vr_stat_callout);
850 taskqueue_drain(taskqueue_swi, &sc->vr_link_task);
854 device_delete_child(dev, sc->vr_miibus);
855 bus_generic_detach(dev);
858 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand);
860 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
862 bus_release_resource(dev, sc->vr_res_type, sc->vr_res_id,
870 mtx_destroy(&sc->vr_mtx);
875 struct vr_dmamap_arg {
876 bus_addr_t vr_busaddr;
880 vr_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
882 struct vr_dmamap_arg *ctx;
887 ctx->vr_busaddr = segs[0].ds_addr;
891 vr_dma_alloc(struct vr_softc *sc)
893 struct vr_dmamap_arg ctx;
894 struct vr_txdesc *txd;
895 struct vr_rxdesc *rxd;
896 bus_size_t tx_alignment;
899 /* Create parent DMA tag. */
900 error = bus_dma_tag_create(
901 bus_get_dma_tag(sc->vr_dev), /* parent */
902 1, 0, /* alignment, boundary */
903 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
904 BUS_SPACE_MAXADDR, /* highaddr */
905 NULL, NULL, /* filter, filterarg */
906 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
908 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
910 NULL, NULL, /* lockfunc, lockarg */
911 &sc->vr_cdata.vr_parent_tag);
913 device_printf(sc->vr_dev, "failed to create parent DMA tag\n");
916 /* Create tag for Tx ring. */
917 error = bus_dma_tag_create(
918 sc->vr_cdata.vr_parent_tag, /* parent */
919 VR_RING_ALIGN, 0, /* alignment, boundary */
920 BUS_SPACE_MAXADDR, /* lowaddr */
921 BUS_SPACE_MAXADDR, /* highaddr */
922 NULL, NULL, /* filter, filterarg */
923 VR_TX_RING_SIZE, /* maxsize */
925 VR_TX_RING_SIZE, /* maxsegsize */
927 NULL, NULL, /* lockfunc, lockarg */
928 &sc->vr_cdata.vr_tx_ring_tag);
930 device_printf(sc->vr_dev, "failed to create Tx ring DMA tag\n");
934 /* Create tag for Rx ring. */
935 error = bus_dma_tag_create(
936 sc->vr_cdata.vr_parent_tag, /* parent */
937 VR_RING_ALIGN, 0, /* alignment, boundary */
938 BUS_SPACE_MAXADDR, /* lowaddr */
939 BUS_SPACE_MAXADDR, /* highaddr */
940 NULL, NULL, /* filter, filterarg */
941 VR_RX_RING_SIZE, /* maxsize */
943 VR_RX_RING_SIZE, /* maxsegsize */
945 NULL, NULL, /* lockfunc, lockarg */
946 &sc->vr_cdata.vr_rx_ring_tag);
948 device_printf(sc->vr_dev, "failed to create Rx ring DMA tag\n");
952 if ((sc->vr_quirks & VR_Q_NEEDALIGN) != 0)
953 tx_alignment = sizeof(uint32_t);
956 /* Create tag for Tx buffers. */
957 error = bus_dma_tag_create(
958 sc->vr_cdata.vr_parent_tag, /* parent */
959 tx_alignment, 0, /* alignment, boundary */
960 BUS_SPACE_MAXADDR, /* lowaddr */
961 BUS_SPACE_MAXADDR, /* highaddr */
962 NULL, NULL, /* filter, filterarg */
963 MCLBYTES * VR_MAXFRAGS, /* maxsize */
964 VR_MAXFRAGS, /* nsegments */
965 MCLBYTES, /* maxsegsize */
967 NULL, NULL, /* lockfunc, lockarg */
968 &sc->vr_cdata.vr_tx_tag);
970 device_printf(sc->vr_dev, "failed to create Tx DMA tag\n");
974 /* Create tag for Rx buffers. */
975 error = bus_dma_tag_create(
976 sc->vr_cdata.vr_parent_tag, /* parent */
977 VR_RX_ALIGN, 0, /* alignment, boundary */
978 BUS_SPACE_MAXADDR, /* lowaddr */
979 BUS_SPACE_MAXADDR, /* highaddr */
980 NULL, NULL, /* filter, filterarg */
981 MCLBYTES, /* maxsize */
983 MCLBYTES, /* maxsegsize */
985 NULL, NULL, /* lockfunc, lockarg */
986 &sc->vr_cdata.vr_rx_tag);
988 device_printf(sc->vr_dev, "failed to create Rx DMA tag\n");
992 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
993 error = bus_dmamem_alloc(sc->vr_cdata.vr_tx_ring_tag,
994 (void **)&sc->vr_rdata.vr_tx_ring, BUS_DMA_WAITOK |
995 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->vr_cdata.vr_tx_ring_map);
997 device_printf(sc->vr_dev,
998 "failed to allocate DMA'able memory for Tx ring\n");
1003 error = bus_dmamap_load(sc->vr_cdata.vr_tx_ring_tag,
1004 sc->vr_cdata.vr_tx_ring_map, sc->vr_rdata.vr_tx_ring,
1005 VR_TX_RING_SIZE, vr_dmamap_cb, &ctx, 0);
1006 if (error != 0 || ctx.vr_busaddr == 0) {
1007 device_printf(sc->vr_dev,
1008 "failed to load DMA'able memory for Tx ring\n");
1011 sc->vr_rdata.vr_tx_ring_paddr = ctx.vr_busaddr;
1013 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
1014 error = bus_dmamem_alloc(sc->vr_cdata.vr_rx_ring_tag,
1015 (void **)&sc->vr_rdata.vr_rx_ring, BUS_DMA_WAITOK |
1016 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->vr_cdata.vr_rx_ring_map);
1018 device_printf(sc->vr_dev,
1019 "failed to allocate DMA'able memory for Rx ring\n");
1024 error = bus_dmamap_load(sc->vr_cdata.vr_rx_ring_tag,
1025 sc->vr_cdata.vr_rx_ring_map, sc->vr_rdata.vr_rx_ring,
1026 VR_RX_RING_SIZE, vr_dmamap_cb, &ctx, 0);
1027 if (error != 0 || ctx.vr_busaddr == 0) {
1028 device_printf(sc->vr_dev,
1029 "failed to load DMA'able memory for Rx ring\n");
1032 sc->vr_rdata.vr_rx_ring_paddr = ctx.vr_busaddr;
1034 /* Create DMA maps for Tx buffers. */
1035 for (i = 0; i < VR_TX_RING_CNT; i++) {
1036 txd = &sc->vr_cdata.vr_txdesc[i];
1038 txd->tx_dmamap = NULL;
1039 error = bus_dmamap_create(sc->vr_cdata.vr_tx_tag, 0,
1042 device_printf(sc->vr_dev,
1043 "failed to create Tx dmamap\n");
1047 /* Create DMA maps for Rx buffers. */
1048 if ((error = bus_dmamap_create(sc->vr_cdata.vr_rx_tag, 0,
1049 &sc->vr_cdata.vr_rx_sparemap)) != 0) {
1050 device_printf(sc->vr_dev,
1051 "failed to create spare Rx dmamap\n");
1054 for (i = 0; i < VR_RX_RING_CNT; i++) {
1055 rxd = &sc->vr_cdata.vr_rxdesc[i];
1057 rxd->rx_dmamap = NULL;
1058 error = bus_dmamap_create(sc->vr_cdata.vr_rx_tag, 0,
1061 device_printf(sc->vr_dev,
1062 "failed to create Rx dmamap\n");
1072 vr_dma_free(struct vr_softc *sc)
1074 struct vr_txdesc *txd;
1075 struct vr_rxdesc *rxd;
1079 if (sc->vr_cdata.vr_tx_ring_tag) {
1080 if (sc->vr_cdata.vr_tx_ring_map)
1081 bus_dmamap_unload(sc->vr_cdata.vr_tx_ring_tag,
1082 sc->vr_cdata.vr_tx_ring_map);
1083 if (sc->vr_cdata.vr_tx_ring_map &&
1084 sc->vr_rdata.vr_tx_ring)
1085 bus_dmamem_free(sc->vr_cdata.vr_tx_ring_tag,
1086 sc->vr_rdata.vr_tx_ring,
1087 sc->vr_cdata.vr_tx_ring_map);
1088 sc->vr_rdata.vr_tx_ring = NULL;
1089 sc->vr_cdata.vr_tx_ring_map = NULL;
1090 bus_dma_tag_destroy(sc->vr_cdata.vr_tx_ring_tag);
1091 sc->vr_cdata.vr_tx_ring_tag = NULL;
1094 if (sc->vr_cdata.vr_rx_ring_tag) {
1095 if (sc->vr_cdata.vr_rx_ring_map)
1096 bus_dmamap_unload(sc->vr_cdata.vr_rx_ring_tag,
1097 sc->vr_cdata.vr_rx_ring_map);
1098 if (sc->vr_cdata.vr_rx_ring_map &&
1099 sc->vr_rdata.vr_rx_ring)
1100 bus_dmamem_free(sc->vr_cdata.vr_rx_ring_tag,
1101 sc->vr_rdata.vr_rx_ring,
1102 sc->vr_cdata.vr_rx_ring_map);
1103 sc->vr_rdata.vr_rx_ring = NULL;
1104 sc->vr_cdata.vr_rx_ring_map = NULL;
1105 bus_dma_tag_destroy(sc->vr_cdata.vr_rx_ring_tag);
1106 sc->vr_cdata.vr_rx_ring_tag = NULL;
1109 if (sc->vr_cdata.vr_tx_tag) {
1110 for (i = 0; i < VR_TX_RING_CNT; i++) {
1111 txd = &sc->vr_cdata.vr_txdesc[i];
1112 if (txd->tx_dmamap) {
1113 bus_dmamap_destroy(sc->vr_cdata.vr_tx_tag,
1115 txd->tx_dmamap = NULL;
1118 bus_dma_tag_destroy(sc->vr_cdata.vr_tx_tag);
1119 sc->vr_cdata.vr_tx_tag = NULL;
1122 if (sc->vr_cdata.vr_rx_tag) {
1123 for (i = 0; i < VR_RX_RING_CNT; i++) {
1124 rxd = &sc->vr_cdata.vr_rxdesc[i];
1125 if (rxd->rx_dmamap) {
1126 bus_dmamap_destroy(sc->vr_cdata.vr_rx_tag,
1128 rxd->rx_dmamap = NULL;
1131 if (sc->vr_cdata.vr_rx_sparemap) {
1132 bus_dmamap_destroy(sc->vr_cdata.vr_rx_tag,
1133 sc->vr_cdata.vr_rx_sparemap);
1134 sc->vr_cdata.vr_rx_sparemap = 0;
1136 bus_dma_tag_destroy(sc->vr_cdata.vr_rx_tag);
1137 sc->vr_cdata.vr_rx_tag = NULL;
1140 if (sc->vr_cdata.vr_parent_tag) {
1141 bus_dma_tag_destroy(sc->vr_cdata.vr_parent_tag);
1142 sc->vr_cdata.vr_parent_tag = NULL;
1147 * Initialize the transmit descriptors.
1150 vr_tx_ring_init(struct vr_softc *sc)
1152 struct vr_ring_data *rd;
1153 struct vr_txdesc *txd;
1157 sc->vr_cdata.vr_tx_prod = 0;
1158 sc->vr_cdata.vr_tx_cons = 0;
1159 sc->vr_cdata.vr_tx_cnt = 0;
1160 sc->vr_cdata.vr_tx_pkts = 0;
1163 bzero(rd->vr_tx_ring, VR_TX_RING_SIZE);
1164 for (i = 0; i < VR_TX_RING_CNT; i++) {
1165 if (i == VR_TX_RING_CNT - 1)
1166 addr = VR_TX_RING_ADDR(sc, 0);
1168 addr = VR_TX_RING_ADDR(sc, i + 1);
1169 rd->vr_tx_ring[i].vr_nextphys = htole32(VR_ADDR_LO(addr));
1170 txd = &sc->vr_cdata.vr_txdesc[i];
1174 bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag,
1175 sc->vr_cdata.vr_tx_ring_map,
1176 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1182 * Initialize the RX descriptors and allocate mbufs for them. Note that
1183 * we arrange the descriptors in a closed ring, so that the last descriptor
1184 * points back to the first.
1187 vr_rx_ring_init(struct vr_softc *sc)
1189 struct vr_ring_data *rd;
1190 struct vr_rxdesc *rxd;
1194 sc->vr_cdata.vr_rx_cons = 0;
1197 bzero(rd->vr_rx_ring, VR_RX_RING_SIZE);
1198 for (i = 0; i < VR_RX_RING_CNT; i++) {
1199 rxd = &sc->vr_cdata.vr_rxdesc[i];
1201 rxd->desc = &rd->vr_rx_ring[i];
1202 if (i == VR_RX_RING_CNT - 1)
1203 addr = VR_RX_RING_ADDR(sc, 0);
1205 addr = VR_RX_RING_ADDR(sc, i + 1);
1206 rd->vr_rx_ring[i].vr_nextphys = htole32(VR_ADDR_LO(addr));
1207 if (vr_newbuf(sc, i) != 0)
1211 bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag,
1212 sc->vr_cdata.vr_rx_ring_map,
1213 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1218 static __inline void
1219 vr_discard_rxbuf(struct vr_rxdesc *rxd)
1221 struct vr_desc *desc;
1224 desc->vr_ctl = htole32(VR_RXCTL | (MCLBYTES - sizeof(uint64_t)));
1225 desc->vr_status = htole32(VR_RXSTAT_OWN);
1229 * Initialize an RX descriptor and attach an MBUF cluster.
1230 * Note: the length fields are only 11 bits wide, which means the
1231 * largest size we can specify is 2047. This is important because
1232 * MCLBYTES is 2048, so we have to subtract one otherwise we'll
1233 * overflow the field and make a mess.
1236 vr_newbuf(struct vr_softc *sc, int idx)
1238 struct vr_desc *desc;
1239 struct vr_rxdesc *rxd;
1241 bus_dma_segment_t segs[1];
1245 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1248 m->m_len = m->m_pkthdr.len = MCLBYTES;
1249 m_adj(m, sizeof(uint64_t));
1251 if (bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_rx_tag,
1252 sc->vr_cdata.vr_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1256 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1258 rxd = &sc->vr_cdata.vr_rxdesc[idx];
1259 if (rxd->rx_m != NULL) {
1260 bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap,
1261 BUS_DMASYNC_POSTREAD);
1262 bus_dmamap_unload(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap);
1264 map = rxd->rx_dmamap;
1265 rxd->rx_dmamap = sc->vr_cdata.vr_rx_sparemap;
1266 sc->vr_cdata.vr_rx_sparemap = map;
1267 bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap,
1268 BUS_DMASYNC_PREREAD);
1271 desc->vr_data = htole32(VR_ADDR_LO(segs[0].ds_addr));
1272 desc->vr_ctl = htole32(VR_RXCTL | segs[0].ds_len);
1273 desc->vr_status = htole32(VR_RXSTAT_OWN);
1278 #ifndef __NO_STRICT_ALIGNMENT
1279 static __inline void
1280 vr_fixup_rx(struct mbuf *m)
1282 uint16_t *src, *dst;
1285 src = mtod(m, uint16_t *);
1288 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1291 m->m_data -= ETHER_ALIGN;
1296 * A frame has been uploaded: pass the resulting mbuf chain up to
1297 * the higher level protocols.
1300 vr_rxeof(struct vr_softc *sc)
1302 struct vr_rxdesc *rxd;
1305 struct vr_desc *cur_rx;
1306 int cons, prog, total_len, rx_npkts;
1307 uint32_t rxstat, rxctl;
1311 cons = sc->vr_cdata.vr_rx_cons;
1314 bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag,
1315 sc->vr_cdata.vr_rx_ring_map,
1316 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1318 for (prog = 0; prog < VR_RX_RING_CNT; VR_INC(cons, VR_RX_RING_CNT)) {
1319 #ifdef DEVICE_POLLING
1320 if (ifp->if_capenable & IFCAP_POLLING) {
1321 if (sc->rxcycles <= 0)
1326 cur_rx = &sc->vr_rdata.vr_rx_ring[cons];
1327 rxstat = le32toh(cur_rx->vr_status);
1328 rxctl = le32toh(cur_rx->vr_ctl);
1329 if ((rxstat & VR_RXSTAT_OWN) == VR_RXSTAT_OWN)
1333 rxd = &sc->vr_cdata.vr_rxdesc[cons];
1337 * If an error occurs, update stats, clear the
1338 * status word and leave the mbuf cluster in place:
1339 * it should simply get re-used next time this descriptor
1340 * comes up in the ring.
1341 * We don't support SG in Rx path yet, so discard
1344 if ((rxstat & VR_RXSTAT_RX_OK) == 0 ||
1345 (rxstat & (VR_RXSTAT_FIRSTFRAG | VR_RXSTAT_LASTFRAG)) !=
1346 (VR_RXSTAT_FIRSTFRAG | VR_RXSTAT_LASTFRAG)) {
1348 sc->vr_stat.rx_errors++;
1349 if (rxstat & VR_RXSTAT_CRCERR)
1350 sc->vr_stat.rx_crc_errors++;
1351 if (rxstat & VR_RXSTAT_FRAMEALIGNERR)
1352 sc->vr_stat.rx_alignment++;
1353 if (rxstat & VR_RXSTAT_FIFOOFLOW)
1354 sc->vr_stat.rx_fifo_overflows++;
1355 if (rxstat & VR_RXSTAT_GIANT)
1356 sc->vr_stat.rx_giants++;
1357 if (rxstat & VR_RXSTAT_RUNT)
1358 sc->vr_stat.rx_runts++;
1359 if (rxstat & VR_RXSTAT_BUFFERR)
1360 sc->vr_stat.rx_no_buffers++;
1361 #ifdef VR_SHOW_ERRORS
1362 device_printf(sc->vr_dev, "%s: receive error = 0x%b\n",
1363 __func__, rxstat & 0xff, VR_RXSTAT_ERR_BITS);
1365 vr_discard_rxbuf(rxd);
1369 if (vr_newbuf(sc, cons) != 0) {
1371 sc->vr_stat.rx_errors++;
1372 sc->vr_stat.rx_no_mbufs++;
1373 vr_discard_rxbuf(rxd);
1378 * XXX The VIA Rhine chip includes the CRC with every
1379 * received frame, and there's no way to turn this
1380 * behavior off (at least, I can't find anything in
1381 * the manual that explains how to do it) so we have
1382 * to trim off the CRC manually.
1384 total_len = VR_RXBYTES(rxstat);
1385 total_len -= ETHER_CRC_LEN;
1386 m->m_pkthdr.len = m->m_len = total_len;
1387 #ifndef __NO_STRICT_ALIGNMENT
1389 * RX buffers must be 32-bit aligned.
1390 * Ignore the alignment problems on the non-strict alignment
1391 * platform. The performance hit incurred due to unaligned
1392 * accesses is much smaller than the hit produced by forcing
1393 * buffer copies all the time.
1397 m->m_pkthdr.rcvif = ifp;
1399 sc->vr_stat.rx_ok++;
1400 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 &&
1401 (rxstat & VR_RXSTAT_FRAG) == 0 &&
1402 (rxctl & VR_RXCTL_IP) != 0) {
1403 /* Checksum is valid for non-fragmented IP packets. */
1404 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1405 if ((rxctl & VR_RXCTL_IPOK) == VR_RXCTL_IPOK) {
1406 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1407 if (rxctl & (VR_RXCTL_TCP | VR_RXCTL_UDP)) {
1408 m->m_pkthdr.csum_flags |=
1409 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1410 if ((rxctl & VR_RXCTL_TCPUDPOK) != 0)
1411 m->m_pkthdr.csum_data = 0xffff;
1416 (*ifp->if_input)(ifp, m);
1422 sc->vr_cdata.vr_rx_cons = cons;
1423 bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag,
1424 sc->vr_cdata.vr_rx_ring_map,
1425 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1431 * A frame was downloaded to the chip. It's safe for us to clean up
1435 vr_txeof(struct vr_softc *sc)
1437 struct vr_txdesc *txd;
1438 struct vr_desc *cur_tx;
1440 uint32_t txctl, txstat;
1445 cons = sc->vr_cdata.vr_tx_cons;
1446 prod = sc->vr_cdata.vr_tx_prod;
1450 bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag,
1451 sc->vr_cdata.vr_tx_ring_map,
1452 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1456 * Go through our tx list and free mbufs for those
1457 * frames that have been transmitted.
1459 for (; cons != prod; VR_INC(cons, VR_TX_RING_CNT)) {
1460 cur_tx = &sc->vr_rdata.vr_tx_ring[cons];
1461 txctl = le32toh(cur_tx->vr_ctl);
1462 txstat = le32toh(cur_tx->vr_status);
1463 if ((txstat & VR_TXSTAT_OWN) == VR_TXSTAT_OWN)
1466 sc->vr_cdata.vr_tx_cnt--;
1467 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1468 /* Only the first descriptor in the chain is valid. */
1469 if ((txctl & VR_TXCTL_FIRSTFRAG) == 0)
1472 txd = &sc->vr_cdata.vr_txdesc[cons];
1473 KASSERT(txd->tx_m != NULL, ("%s: accessing NULL mbuf!\n",
1476 if ((txstat & VR_TXSTAT_ERRSUM) != 0) {
1478 sc->vr_stat.tx_errors++;
1479 if ((txstat & VR_TXSTAT_ABRT) != 0) {
1480 /* Give up and restart Tx. */
1481 sc->vr_stat.tx_abort++;
1482 bus_dmamap_sync(sc->vr_cdata.vr_tx_tag,
1483 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
1484 bus_dmamap_unload(sc->vr_cdata.vr_tx_tag,
1488 VR_INC(cons, VR_TX_RING_CNT);
1489 sc->vr_cdata.vr_tx_cons = cons;
1490 if (vr_tx_stop(sc) != 0) {
1491 device_printf(sc->vr_dev,
1492 "%s: Tx shutdown error -- "
1493 "resetting\n", __func__);
1494 sc->vr_flags |= VR_F_RESTART;
1500 if ((sc->vr_revid < REV_ID_VT3071_A &&
1501 (txstat & VR_TXSTAT_UNDERRUN)) ||
1502 (txstat & (VR_TXSTAT_UDF | VR_TXSTAT_TBUFF))) {
1503 sc->vr_stat.tx_underrun++;
1504 /* Retry and restart Tx. */
1505 sc->vr_cdata.vr_tx_cnt++;
1506 sc->vr_cdata.vr_tx_cons = cons;
1507 cur_tx->vr_status = htole32(VR_TXSTAT_OWN);
1508 bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag,
1509 sc->vr_cdata.vr_tx_ring_map,
1510 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1514 if ((txstat & VR_TXSTAT_DEFER) != 0) {
1515 ifp->if_collisions++;
1516 sc->vr_stat.tx_collisions++;
1518 if ((txstat & VR_TXSTAT_LATECOLL) != 0) {
1519 ifp->if_collisions++;
1520 sc->vr_stat.tx_late_collisions++;
1523 sc->vr_stat.tx_ok++;
1527 bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap,
1528 BUS_DMASYNC_POSTWRITE);
1529 bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap);
1530 if (sc->vr_revid < REV_ID_VT3071_A) {
1531 ifp->if_collisions +=
1532 (txstat & VR_TXSTAT_COLLCNT) >> 3;
1533 sc->vr_stat.tx_collisions +=
1534 (txstat & VR_TXSTAT_COLLCNT) >> 3;
1536 ifp->if_collisions += (txstat & 0x0f);
1537 sc->vr_stat.tx_collisions += (txstat & 0x0f);
1543 sc->vr_cdata.vr_tx_cons = cons;
1544 if (sc->vr_cdata.vr_tx_cnt == 0)
1545 sc->vr_watchdog_timer = 0;
1551 struct vr_softc *sc;
1552 struct mii_data *mii;
1554 sc = (struct vr_softc *)xsc;
1558 if ((sc->vr_flags & VR_F_RESTART) != 0) {
1559 device_printf(sc->vr_dev, "restarting\n");
1560 sc->vr_stat.num_restart++;
1564 sc->vr_flags &= ~VR_F_RESTART;
1567 mii = device_get_softc(sc->vr_miibus);
1570 callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc);
1573 #ifdef DEVICE_POLLING
1574 static poll_handler_t vr_poll;
1575 static poll_handler_t vr_poll_locked;
1578 vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1580 struct vr_softc *sc;
1587 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1588 rx_npkts = vr_poll_locked(ifp, cmd, count);
1594 vr_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1596 struct vr_softc *sc;
1603 sc->rxcycles = count;
1604 rx_npkts = vr_rxeof(sc);
1606 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1607 vr_start_locked(ifp);
1609 if (cmd == POLL_AND_CHECK_STATUS) {
1612 /* Also check status register. */
1613 status = CSR_READ_2(sc, VR_ISR);
1615 CSR_WRITE_2(sc, VR_ISR, status);
1617 if ((status & VR_INTRS) == 0)
1620 if ((status & (VR_ISR_BUSERR | VR_ISR_LINKSTAT2 |
1621 VR_ISR_STATSOFLOW)) != 0) {
1622 if (vr_error(sc, status) != 0)
1625 if ((status & (VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) != 0) {
1626 #ifdef VR_SHOW_ERRORS
1627 device_printf(sc->vr_dev, "%s: receive error : 0x%b\n",
1628 __func__, status, VR_ISR_ERR_BITS);
1635 #endif /* DEVICE_POLLING */
1637 /* Back off the transmit threshold. */
1639 vr_tx_underrun(struct vr_softc *sc)
1643 device_printf(sc->vr_dev, "Tx underrun -- ");
1644 if (sc->vr_txthresh < VR_TXTHRESH_MAX) {
1645 thresh = sc->vr_txthresh;
1647 if (sc->vr_txthresh >= VR_TXTHRESH_MAX) {
1648 sc->vr_txthresh = VR_TXTHRESH_MAX;
1649 printf("using store and forward mode\n");
1651 printf("increasing Tx threshold(%d -> %d)\n",
1652 vr_tx_threshold_tables[thresh].value,
1653 vr_tx_threshold_tables[thresh + 1].value);
1656 sc->vr_stat.tx_underrun++;
1657 if (vr_tx_stop(sc) != 0) {
1658 device_printf(sc->vr_dev, "%s: Tx shutdown error -- "
1659 "resetting\n", __func__);
1660 sc->vr_flags |= VR_F_RESTART;
1669 struct vr_softc *sc;
1673 sc = (struct vr_softc *)arg;
1677 if (sc->vr_suspended != 0)
1680 status = CSR_READ_2(sc, VR_ISR);
1681 if (status == 0 || status == 0xffff || (status & VR_INTRS) == 0)
1685 #ifdef DEVICE_POLLING
1686 if ((ifp->if_capenable & IFCAP_POLLING) != 0)
1690 /* Suppress unwanted interrupts. */
1691 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ||
1692 (sc->vr_flags & VR_F_RESTART) != 0) {
1693 CSR_WRITE_2(sc, VR_IMR, 0);
1694 CSR_WRITE_2(sc, VR_ISR, status);
1698 /* Disable interrupts. */
1699 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1701 for (; (status & VR_INTRS) != 0;) {
1702 CSR_WRITE_2(sc, VR_ISR, status);
1703 if ((status & (VR_ISR_BUSERR | VR_ISR_LINKSTAT2 |
1704 VR_ISR_STATSOFLOW)) != 0) {
1705 if (vr_error(sc, status) != 0) {
1711 if ((status & (VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) != 0) {
1712 #ifdef VR_SHOW_ERRORS
1713 device_printf(sc->vr_dev, "%s: receive error = 0x%b\n",
1714 __func__, status, VR_ISR_ERR_BITS);
1716 /* Restart Rx if RxDMA SM was stopped. */
1720 status = CSR_READ_2(sc, VR_ISR);
1723 /* Re-enable interrupts. */
1724 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1726 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1727 vr_start_locked(ifp);
1734 vr_error(struct vr_softc *sc, uint16_t status)
1738 status &= VR_ISR_BUSERR | VR_ISR_LINKSTAT2 | VR_ISR_STATSOFLOW;
1739 if ((status & VR_ISR_BUSERR) != 0) {
1740 status &= ~VR_ISR_BUSERR;
1741 sc->vr_stat.bus_errors++;
1742 /* Disable further interrupts. */
1743 CSR_WRITE_2(sc, VR_IMR, 0);
1744 pcis = pci_read_config(sc->vr_dev, PCIR_STATUS, 2);
1745 device_printf(sc->vr_dev, "PCI bus error(0x%04x) -- "
1746 "resetting\n", pcis);
1747 pci_write_config(sc->vr_dev, PCIR_STATUS, pcis, 2);
1748 sc->vr_flags |= VR_F_RESTART;
1751 if ((status & VR_ISR_LINKSTAT2) != 0) {
1752 /* Link state change, duplex changes etc. */
1753 status &= ~VR_ISR_LINKSTAT2;
1755 if ((status & VR_ISR_STATSOFLOW) != 0) {
1756 status &= ~VR_ISR_STATSOFLOW;
1757 if (sc->vr_revid >= REV_ID_VT6105M_A0) {
1758 /* Update MIB counters. */
1763 device_printf(sc->vr_dev,
1764 "unhandled interrupt, status = 0x%04x\n", status);
1769 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1770 * pointers to the fragment pointers.
1773 vr_encap(struct vr_softc *sc, struct mbuf **m_head)
1775 struct vr_txdesc *txd;
1776 struct vr_desc *desc;
1778 bus_dma_segment_t txsegs[VR_MAXFRAGS];
1779 uint32_t csum_flags, txctl;
1780 int error, i, nsegs, prod, si;
1785 M_ASSERTPKTHDR((*m_head));
1788 * Some VIA Rhine wants packet buffers to be longword
1789 * aligned, but very often our mbufs aren't. Rather than
1790 * waste time trying to decide when to copy and when not
1791 * to copy, just do it all the time.
1793 if ((sc->vr_quirks & VR_Q_NEEDALIGN) != 0) {
1794 m = m_defrag(*m_head, M_DONTWAIT);
1804 * The Rhine chip doesn't auto-pad, so we have to make
1805 * sure to pad short frames out to the minimum frame length
1808 if ((*m_head)->m_pkthdr.len < VR_MIN_FRAMELEN) {
1810 padlen = VR_MIN_FRAMELEN - m->m_pkthdr.len;
1811 if (M_WRITABLE(m) == 0) {
1812 /* Get a writable copy. */
1813 m = m_dup(*m_head, M_DONTWAIT);
1821 if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) {
1822 m = m_defrag(m, M_DONTWAIT);
1830 * Manually pad short frames, and zero the pad space
1831 * to avoid leaking data.
1833 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
1834 m->m_pkthdr.len += padlen;
1835 m->m_len = m->m_pkthdr.len;
1839 prod = sc->vr_cdata.vr_tx_prod;
1840 txd = &sc->vr_cdata.vr_txdesc[prod];
1841 error = bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap,
1842 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
1843 if (error == EFBIG) {
1844 m = m_collapse(*m_head, M_DONTWAIT, VR_MAXFRAGS);
1851 error = bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_tx_tag,
1852 txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
1858 } else if (error != 0)
1866 /* Check number of available descriptors. */
1867 if (sc->vr_cdata.vr_tx_cnt + nsegs >= (VR_TX_RING_CNT - 1)) {
1868 bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap);
1872 txd->tx_m = *m_head;
1873 bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap,
1874 BUS_DMASYNC_PREWRITE);
1876 /* Set checksum offload. */
1878 if (((*m_head)->m_pkthdr.csum_flags & VR_CSUM_FEATURES) != 0) {
1879 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP)
1880 csum_flags |= VR_TXCTL_IPCSUM;
1881 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP)
1882 csum_flags |= VR_TXCTL_TCPCSUM;
1883 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP)
1884 csum_flags |= VR_TXCTL_UDPCSUM;
1888 * Quite contrary to datasheet for VIA Rhine, VR_TXCTL_TLINK bit
1889 * is required for all descriptors regardless of single or
1890 * multiple buffers. Also VR_TXSTAT_OWN bit is valid only for
1891 * the first descriptor for a multi-fragmented frames. Without
1892 * that VIA Rhine chip generates Tx underrun interrupts and can't
1896 for (i = 0; i < nsegs; i++) {
1897 desc = &sc->vr_rdata.vr_tx_ring[prod];
1898 desc->vr_status = 0;
1899 txctl = txsegs[i].ds_len | VR_TXCTL_TLINK | csum_flags;
1901 txctl |= VR_TXCTL_FIRSTFRAG;
1902 desc->vr_ctl = htole32(txctl);
1903 desc->vr_data = htole32(VR_ADDR_LO(txsegs[i].ds_addr));
1904 sc->vr_cdata.vr_tx_cnt++;
1905 VR_INC(prod, VR_TX_RING_CNT);
1907 /* Update producer index. */
1908 sc->vr_cdata.vr_tx_prod = prod;
1910 prod = (prod + VR_TX_RING_CNT - 1) % VR_TX_RING_CNT;
1911 desc = &sc->vr_rdata.vr_tx_ring[prod];
1914 * Set EOP on the last desciptor and reuqest Tx completion
1915 * interrupt for every VR_TX_INTR_THRESH-th frames.
1917 VR_INC(sc->vr_cdata.vr_tx_pkts, VR_TX_INTR_THRESH);
1918 if (sc->vr_cdata.vr_tx_pkts == 0)
1919 desc->vr_ctl |= htole32(VR_TXCTL_LASTFRAG | VR_TXCTL_FINT);
1921 desc->vr_ctl |= htole32(VR_TXCTL_LASTFRAG);
1923 /* Lastly turn the first descriptor ownership to hardware. */
1924 desc = &sc->vr_rdata.vr_tx_ring[si];
1925 desc->vr_status |= htole32(VR_TXSTAT_OWN);
1927 /* Sync descriptors. */
1928 bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag,
1929 sc->vr_cdata.vr_tx_ring_map,
1930 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1936 vr_start(struct ifnet *ifp)
1938 struct vr_softc *sc;
1942 vr_start_locked(ifp);
1947 vr_start_locked(struct ifnet *ifp)
1949 struct vr_softc *sc;
1950 struct mbuf *m_head;
1957 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1958 IFF_DRV_RUNNING || sc->vr_link == 0)
1961 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
1962 sc->vr_cdata.vr_tx_cnt < VR_TX_RING_CNT - 2; ) {
1963 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1967 * Pack the data into the transmit ring. If we
1968 * don't have room, set the OACTIVE flag and wait
1969 * for the NIC to drain the ring.
1971 if (vr_encap(sc, &m_head)) {
1974 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1975 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1981 * If there's a BPF listener, bounce a copy of this frame
1984 ETHER_BPF_MTAP(ifp, m_head);
1988 /* Tell the chip to start transmitting. */
1989 VR_SETBIT(sc, VR_CR0, VR_CR0_TX_GO);
1990 /* Set a timeout in case the chip goes out to lunch. */
1991 sc->vr_watchdog_timer = 5;
1998 struct vr_softc *sc;
2000 sc = (struct vr_softc *)xsc;
2007 vr_init_locked(struct vr_softc *sc)
2010 struct mii_data *mii;
2017 mii = device_get_softc(sc->vr_miibus);
2019 /* Cancel pending I/O and free all RX/TX buffers. */
2023 /* Set our station address. */
2024 for (i = 0; i < ETHER_ADDR_LEN; i++)
2025 CSR_WRITE_1(sc, VR_PAR0 + i, IF_LLADDR(sc->vr_ifp)[i]);
2028 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH);
2029 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD);
2032 * BCR0 and BCR1 can override the RXCFG and TXCFG registers,
2033 * so we must set both.
2035 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH);
2036 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES);
2038 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH);
2039 VR_SETBIT(sc, VR_BCR1, vr_tx_threshold_tables[sc->vr_txthresh].bcr_cfg);
2041 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH);
2042 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES);
2044 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH);
2045 VR_SETBIT(sc, VR_TXCFG, vr_tx_threshold_tables[sc->vr_txthresh].tx_cfg);
2047 /* Init circular RX list. */
2048 if (vr_rx_ring_init(sc) != 0) {
2049 device_printf(sc->vr_dev,
2050 "initialization failed: no memory for rx buffers\n");
2055 /* Init tx descriptors. */
2056 vr_tx_ring_init(sc);
2058 if ((sc->vr_quirks & VR_Q_CAM) != 0) {
2059 uint8_t vcam[2] = { 0, 0 };
2061 /* Disable VLAN hardware tag insertion/stripping. */
2062 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TXTAGEN | VR_TXCFG_RXTAGCTL);
2063 /* Disable VLAN hardware filtering. */
2064 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_VLANFILT_ENB);
2065 /* Disable all CAM entries. */
2066 vr_cam_mask(sc, VR_MCAST_CAM, 0);
2067 vr_cam_mask(sc, VR_VLAN_CAM, 0);
2068 /* Enable the first VLAN CAM. */
2069 vr_cam_data(sc, VR_VLAN_CAM, 0, vcam);
2070 vr_cam_mask(sc, VR_VLAN_CAM, 1);
2074 * Set up receive filter.
2079 * Load the address of the RX ring.
2081 addr = VR_RX_RING_ADDR(sc, 0);
2082 CSR_WRITE_4(sc, VR_RXADDR, VR_ADDR_LO(addr));
2084 * Load the address of the TX ring.
2086 addr = VR_TX_RING_ADDR(sc, 0);
2087 CSR_WRITE_4(sc, VR_TXADDR, VR_ADDR_LO(addr));
2088 /* Default : full-duplex, no Tx poll. */
2089 CSR_WRITE_1(sc, VR_CR1, VR_CR1_FULLDUPLEX | VR_CR1_TX_NOPOLL);
2091 /* Set flow-control parameters for Rhine III. */
2092 if (sc->vr_revid >= REV_ID_VT6105_A0) {
2093 /* Rx buffer count available for incoming packet. */
2094 CSR_WRITE_1(sc, VR_FLOWCR0, VR_RX_RING_CNT);
2096 * Tx pause low threshold : 16 free receive buffers
2097 * Tx pause XON high threshold : 48 free receive buffers
2099 CSR_WRITE_1(sc, VR_FLOWCR1,
2100 VR_FLOWCR1_TXLO16 | VR_FLOWCR1_TXHI48 | VR_FLOWCR1_XONXOFF);
2101 /* Set Tx pause timer. */
2102 CSR_WRITE_2(sc, VR_PAUSETIMER, 0xffff);
2105 /* Enable receiver and transmitter. */
2106 CSR_WRITE_1(sc, VR_CR0,
2107 VR_CR0_START | VR_CR0_TX_ON | VR_CR0_RX_ON | VR_CR0_RX_GO);
2109 CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
2110 #ifdef DEVICE_POLLING
2112 * Disable interrupts if we are polling.
2114 if (ifp->if_capenable & IFCAP_POLLING)
2115 CSR_WRITE_2(sc, VR_IMR, 0);
2119 * Enable interrupts and disable MII intrs.
2121 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
2122 if (sc->vr_revid > REV_ID_VT6102_A)
2123 CSR_WRITE_2(sc, VR_MII_IMR, 0);
2128 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2129 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2131 callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc);
2135 * Set media options.
2138 vr_ifmedia_upd(struct ifnet *ifp)
2140 struct vr_softc *sc;
2141 struct mii_data *mii;
2142 struct mii_softc *miisc;
2147 mii = device_get_softc(sc->vr_miibus);
2148 if (mii->mii_instance) {
2149 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2150 mii_phy_reset(miisc);
2152 error = mii_mediachg(mii);
2159 * Report current media status.
2162 vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2164 struct vr_softc *sc;
2165 struct mii_data *mii;
2168 mii = device_get_softc(sc->vr_miibus);
2172 ifmr->ifm_active = mii->mii_media_active;
2173 ifmr->ifm_status = mii->mii_media_status;
2177 vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2179 struct vr_softc *sc;
2181 struct mii_data *mii;
2185 ifr = (struct ifreq *)data;
2191 if (ifp->if_flags & IFF_UP) {
2192 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2193 if ((ifp->if_flags ^ sc->vr_if_flags) &
2194 (IFF_PROMISC | IFF_ALLMULTI))
2197 if (sc->vr_detach == 0)
2201 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2204 sc->vr_if_flags = ifp->if_flags;
2215 mii = device_get_softc(sc->vr_miibus);
2216 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2219 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2220 #ifdef DEVICE_POLLING
2221 if (mask & IFCAP_POLLING) {
2222 if (ifr->ifr_reqcap & IFCAP_POLLING) {
2223 error = ether_poll_register(vr_poll, ifp);
2227 /* Disable interrupts. */
2228 CSR_WRITE_2(sc, VR_IMR, 0x0000);
2229 ifp->if_capenable |= IFCAP_POLLING;
2232 error = ether_poll_deregister(ifp);
2233 /* Enable interrupts. */
2235 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
2236 ifp->if_capenable &= ~IFCAP_POLLING;
2240 #endif /* DEVICE_POLLING */
2241 if ((mask & IFCAP_TXCSUM) != 0 &&
2242 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) {
2243 ifp->if_capenable ^= IFCAP_TXCSUM;
2244 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0)
2245 ifp->if_hwassist |= VR_CSUM_FEATURES;
2247 ifp->if_hwassist &= ~VR_CSUM_FEATURES;
2249 if ((mask & IFCAP_RXCSUM) != 0 &&
2250 (IFCAP_RXCSUM & ifp->if_capabilities) != 0)
2251 ifp->if_capenable ^= IFCAP_RXCSUM;
2252 if ((mask & IFCAP_WOL_UCAST) != 0 &&
2253 (ifp->if_capabilities & IFCAP_WOL_UCAST) != 0)
2254 ifp->if_capenable ^= IFCAP_WOL_UCAST;
2255 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2256 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
2257 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2260 error = ether_ioctl(ifp, command, data);
2268 vr_watchdog(struct vr_softc *sc)
2274 if (sc->vr_watchdog_timer == 0 || --sc->vr_watchdog_timer)
2279 * Reclaim first as we don't request interrupt for every packets.
2282 if (sc->vr_cdata.vr_tx_cnt == 0)
2285 if (sc->vr_link == 0) {
2287 if_printf(sc->vr_ifp, "watchdog timeout "
2295 if_printf(ifp, "watchdog timeout\n");
2301 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2302 vr_start_locked(ifp);
2306 vr_tx_start(struct vr_softc *sc)
2311 cmd = CSR_READ_1(sc, VR_CR0);
2312 if ((cmd & VR_CR0_TX_ON) == 0) {
2313 addr = VR_TX_RING_ADDR(sc, sc->vr_cdata.vr_tx_cons);
2314 CSR_WRITE_4(sc, VR_TXADDR, VR_ADDR_LO(addr));
2315 cmd |= VR_CR0_TX_ON;
2316 CSR_WRITE_1(sc, VR_CR0, cmd);
2318 if (sc->vr_cdata.vr_tx_cnt != 0) {
2319 sc->vr_watchdog_timer = 5;
2320 VR_SETBIT(sc, VR_CR0, VR_CR0_TX_GO);
2325 vr_rx_start(struct vr_softc *sc)
2330 cmd = CSR_READ_1(sc, VR_CR0);
2331 if ((cmd & VR_CR0_RX_ON) == 0) {
2332 addr = VR_RX_RING_ADDR(sc, sc->vr_cdata.vr_rx_cons);
2333 CSR_WRITE_4(sc, VR_RXADDR, VR_ADDR_LO(addr));
2334 cmd |= VR_CR0_RX_ON;
2335 CSR_WRITE_1(sc, VR_CR0, cmd);
2337 CSR_WRITE_1(sc, VR_CR0, cmd | VR_CR0_RX_GO);
2341 vr_tx_stop(struct vr_softc *sc)
2346 cmd = CSR_READ_1(sc, VR_CR0);
2347 if ((cmd & VR_CR0_TX_ON) != 0) {
2348 cmd &= ~VR_CR0_TX_ON;
2349 CSR_WRITE_1(sc, VR_CR0, cmd);
2350 for (i = VR_TIMEOUT; i > 0; i--) {
2352 cmd = CSR_READ_1(sc, VR_CR0);
2353 if ((cmd & VR_CR0_TX_ON) == 0)
2363 vr_rx_stop(struct vr_softc *sc)
2368 cmd = CSR_READ_1(sc, VR_CR0);
2369 if ((cmd & VR_CR0_RX_ON) != 0) {
2370 cmd &= ~VR_CR0_RX_ON;
2371 CSR_WRITE_1(sc, VR_CR0, cmd);
2372 for (i = VR_TIMEOUT; i > 0; i--) {
2374 cmd = CSR_READ_1(sc, VR_CR0);
2375 if ((cmd & VR_CR0_RX_ON) == 0)
2385 * Stop the adapter and free any mbufs allocated to the
2389 vr_stop(struct vr_softc *sc)
2391 struct vr_txdesc *txd;
2392 struct vr_rxdesc *rxd;
2399 sc->vr_watchdog_timer = 0;
2401 callout_stop(&sc->vr_stat_callout);
2402 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2404 CSR_WRITE_1(sc, VR_CR0, VR_CR0_STOP);
2405 if (vr_rx_stop(sc) != 0)
2406 device_printf(sc->vr_dev, "%s: Rx shutdown error\n", __func__);
2407 if (vr_tx_stop(sc) != 0)
2408 device_printf(sc->vr_dev, "%s: Tx shutdown error\n", __func__);
2409 /* Clear pending interrupts. */
2410 CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
2411 CSR_WRITE_2(sc, VR_IMR, 0x0000);
2412 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000);
2413 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000);
2416 * Free RX and TX mbufs still in the queues.
2418 for (i = 0; i < VR_RX_RING_CNT; i++) {
2419 rxd = &sc->vr_cdata.vr_rxdesc[i];
2420 if (rxd->rx_m != NULL) {
2421 bus_dmamap_sync(sc->vr_cdata.vr_rx_tag,
2422 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2423 bus_dmamap_unload(sc->vr_cdata.vr_rx_tag,
2429 for (i = 0; i < VR_TX_RING_CNT; i++) {
2430 txd = &sc->vr_cdata.vr_txdesc[i];
2431 if (txd->tx_m != NULL) {
2432 bus_dmamap_sync(sc->vr_cdata.vr_tx_tag,
2433 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2434 bus_dmamap_unload(sc->vr_cdata.vr_tx_tag,
2443 * Stop all chip I/O so that the kernel's probe routines don't
2444 * get confused by errant DMAs when rebooting.
2447 vr_shutdown(device_t dev)
2450 return (vr_suspend(dev));
2454 vr_suspend(device_t dev)
2456 struct vr_softc *sc;
2458 sc = device_get_softc(dev);
2463 sc->vr_suspended = 1;
2470 vr_resume(device_t dev)
2472 struct vr_softc *sc;
2475 sc = device_get_softc(dev);
2481 if (ifp->if_flags & IFF_UP)
2484 sc->vr_suspended = 0;
2491 vr_setwol(struct vr_softc *sc)
2500 if (sc->vr_revid < REV_ID_VT6102_A ||
2501 pci_find_extcap(sc->vr_dev, PCIY_PMG, &pmc) != 0)
2506 /* Clear WOL configuration. */
2507 CSR_WRITE_1(sc, VR_WOLCR_CLR, 0xFF);
2508 CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_SAB | VR_WOLCFG_SAM);
2509 CSR_WRITE_1(sc, VR_PWRCSR_CLR, 0xFF);
2510 CSR_WRITE_1(sc, VR_PWRCFG_CLR, VR_PWRCFG_WOLEN);
2511 if (sc->vr_revid > REV_ID_VT6105_B0) {
2512 /* Newer Rhine III supports two additional patterns. */
2513 CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_PATTERN_PAGE);
2514 CSR_WRITE_1(sc, VR_TESTREG_CLR, 3);
2515 CSR_WRITE_1(sc, VR_PWRCSR1_CLR, 3);
2517 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
2518 CSR_WRITE_1(sc, VR_WOLCR_SET, VR_WOLCR_UCAST);
2519 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2520 CSR_WRITE_1(sc, VR_WOLCR_SET, VR_WOLCR_MAGIC);
2522 * It seems that multicast wakeup frames require programming pattern
2523 * registers and valid CRC as well as pattern mask for each pattern.
2524 * While it's possible to setup such a pattern it would complicate
2525 * WOL configuration so ignore multicast wakeup frames.
2527 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
2528 CSR_WRITE_1(sc, VR_WOLCFG_SET, VR_WOLCFG_SAB | VR_WOLCFG_SAM);
2529 v = CSR_READ_1(sc, VR_STICKHW);
2530 CSR_WRITE_1(sc, VR_STICKHW, v | VR_STICKHW_WOL_ENB);
2531 CSR_WRITE_1(sc, VR_PWRCFG_SET, VR_PWRCFG_WOLEN);
2534 /* Put hardware into sleep. */
2535 v = CSR_READ_1(sc, VR_STICKHW);
2536 v |= VR_STICKHW_DS0 | VR_STICKHW_DS1;
2537 CSR_WRITE_1(sc, VR_STICKHW, v);
2539 /* Request PME if WOL is requested. */
2540 pmstat = pci_read_config(sc->vr_dev, pmc + PCIR_POWER_STATUS, 2);
2541 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2542 if ((ifp->if_capenable & IFCAP_WOL) != 0)
2543 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2544 pci_write_config(sc->vr_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
2548 vr_clrwol(struct vr_softc *sc)
2554 if (sc->vr_revid < REV_ID_VT6102_A)
2557 /* Take hardware out of sleep. */
2558 v = CSR_READ_1(sc, VR_STICKHW);
2559 v &= ~(VR_STICKHW_DS0 | VR_STICKHW_DS1 | VR_STICKHW_WOL_ENB);
2560 CSR_WRITE_1(sc, VR_STICKHW, v);
2562 /* Clear WOL configuration as WOL may interfere normal operation. */
2563 CSR_WRITE_1(sc, VR_WOLCR_CLR, 0xFF);
2564 CSR_WRITE_1(sc, VR_WOLCFG_CLR,
2565 VR_WOLCFG_SAB | VR_WOLCFG_SAM | VR_WOLCFG_PMEOVR);
2566 CSR_WRITE_1(sc, VR_PWRCSR_CLR, 0xFF);
2567 CSR_WRITE_1(sc, VR_PWRCFG_CLR, VR_PWRCFG_WOLEN);
2568 if (sc->vr_revid > REV_ID_VT6105_B0) {
2569 /* Newer Rhine III supports two additional patterns. */
2570 CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_PATTERN_PAGE);
2571 CSR_WRITE_1(sc, VR_TESTREG_CLR, 3);
2572 CSR_WRITE_1(sc, VR_PWRCSR1_CLR, 3);
2577 vr_sysctl_stats(SYSCTL_HANDLER_ARGS)
2579 struct vr_softc *sc;
2580 struct vr_statistics *stat;
2585 error = sysctl_handle_int(oidp, &result, 0, req);
2587 if (error != 0 || req->newptr == NULL)
2591 sc = (struct vr_softc *)arg1;
2592 stat = &sc->vr_stat;
2594 printf("%s statistics:\n", device_get_nameunit(sc->vr_dev));
2595 printf("Outbound good frames : %ju\n",
2596 (uintmax_t)stat->tx_ok);
2597 printf("Inbound good frames : %ju\n",
2598 (uintmax_t)stat->rx_ok);
2599 printf("Outbound errors : %u\n", stat->tx_errors);
2600 printf("Inbound errors : %u\n", stat->rx_errors);
2601 printf("Inbound no buffers : %u\n", stat->rx_no_buffers);
2602 printf("Inbound no mbuf clusters: %d\n", stat->rx_no_mbufs);
2603 printf("Inbound FIFO overflows : %d\n",
2604 stat->rx_fifo_overflows);
2605 printf("Inbound CRC errors : %u\n", stat->rx_crc_errors);
2606 printf("Inbound frame alignment errors : %u\n",
2607 stat->rx_alignment);
2608 printf("Inbound giant frames : %u\n", stat->rx_giants);
2609 printf("Inbound runt frames : %u\n", stat->rx_runts);
2610 printf("Outbound aborted with excessive collisions : %u\n",
2612 printf("Outbound collisions : %u\n", stat->tx_collisions);
2613 printf("Outbound late collisions : %u\n",
2614 stat->tx_late_collisions);
2615 printf("Outbound underrun : %u\n", stat->tx_underrun);
2616 printf("PCI bus errors : %u\n", stat->bus_errors);
2617 printf("driver restarted due to Rx/Tx shutdown failure : %u\n",