2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * 3Com 3c90x Etherlink XL PCI NIC driver
39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
40 * bus-master chips (3c90x cards and embedded controllers) including
43 * 3Com 3c900-TPO 10Mbps/RJ-45
44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC
45 * 3Com 3c905-TX 10/100Mbps/RJ-45
46 * 3Com 3c905-T4 10/100Mbps/RJ-45
47 * 3Com 3c900B-TPO 10Mbps/RJ-45
48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC
49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC
50 * 3Com 3c900B-FL 10Mbps/Fiber-optic
51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC
52 * 3Com 3c905B-TX 10/100Mbps/RJ-45
53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic
54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC)
55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC)
56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC)
57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC)
58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC)
59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane)
60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
69 * Dell on-board 3c920 10/100Mbps/RJ-45
70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
71 * Dell Latitude laptop docking station embedded 3c905-TX
73 * Written by Bill Paul <wpaul@ctr.columbia.edu>
74 * Electrical Engineering Department
75 * Columbia University, New York City
78 * The 3c90x series chips use a bus-master DMA interface for transfering
79 * packets to and from the controller chip. Some of the "vortex" cards
80 * (3c59x) also supported a bus master mode, however for those chips
81 * you could only DMA packets to/from a contiguous memory buffer. For
82 * transmission this would mean copying the contents of the queued mbuf
83 * chain into an mbuf cluster and then DMAing the cluster. This extra
84 * copy would sort of defeat the purpose of the bus master support for
85 * any packet that doesn't fit into a single mbuf.
87 * By contrast, the 3c90x cards support a fragment-based bus master
88 * mode where mbuf chains can be encapsulated using TX descriptors.
89 * This is similar to other PCI chips such as the Texas Instruments
90 * ThunderLAN and the Intel 82557/82558.
92 * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
93 * bus master chips because they maintain the old PIO interface for
94 * backwards compatibility, but starting with the 3c905B and the
95 * "cyclone" chips, the compatibility interface has been dropped.
96 * Since using bus master DMA is a big win, we use this driver to
97 * support the PCI "boomerang" chips even though they work with the
98 * "vortex" driver in order to obtain better performance.
101 #ifdef HAVE_KERNEL_OPTION_HEADERS
102 #include "opt_device_polling.h"
105 #include <sys/param.h>
106 #include <sys/systm.h>
107 #include <sys/sockio.h>
108 #include <sys/endian.h>
109 #include <sys/mbuf.h>
110 #include <sys/kernel.h>
111 #include <sys/module.h>
112 #include <sys/socket.h>
113 #include <sys/taskqueue.h>
116 #include <net/if_arp.h>
117 #include <net/ethernet.h>
118 #include <net/if_dl.h>
119 #include <net/if_media.h>
120 #include <net/if_types.h>
124 #include <machine/bus.h>
125 #include <machine/resource.h>
127 #include <sys/rman.h>
129 #include <dev/mii/mii.h>
130 #include <dev/mii/miivar.h>
132 #include <dev/pci/pcireg.h>
133 #include <dev/pci/pcivar.h>
135 MODULE_DEPEND(xl, pci, 1, 1, 1);
136 MODULE_DEPEND(xl, ether, 1, 1, 1);
137 MODULE_DEPEND(xl, miibus, 1, 1, 1);
139 /* "device miibus" required. See GENERIC if you get errors here. */
140 #include "miibus_if.h"
142 #include <dev/xl/if_xlreg.h>
145 * TX Checksumming is disabled by default for two reasons:
146 * - TX Checksumming will occasionally produce corrupt packets
147 * - TX Checksumming seems to reduce performance
149 * Only 905B/C cards were reported to have this problem, it is possible
150 * that later chips _may_ be immune.
152 #define XL905B_TXCSUM_BROKEN 1
154 #ifdef XL905B_TXCSUM_BROKEN
155 #define XL905B_CSUM_FEATURES 0
157 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
161 * Various supported device vendors/types and their names.
163 static const struct xl_type xl_devs[] = {
164 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
165 "3Com 3c900-TPO Etherlink XL" },
166 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
167 "3Com 3c900-COMBO Etherlink XL" },
168 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
169 "3Com 3c905-TX Fast Etherlink XL" },
170 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
171 "3Com 3c905-T4 Fast Etherlink XL" },
172 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
173 "3Com 3c900B-TPO Etherlink XL" },
174 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
175 "3Com 3c900B-COMBO Etherlink XL" },
176 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
177 "3Com 3c900B-TPC Etherlink XL" },
178 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
179 "3Com 3c900B-FL Etherlink XL" },
180 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
181 "3Com 3c905B-TX Fast Etherlink XL" },
182 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
183 "3Com 3c905B-T4 Fast Etherlink XL" },
184 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
185 "3Com 3c905B-FX/SC Fast Etherlink XL" },
186 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
187 "3Com 3c905B-COMBO Fast Etherlink XL" },
188 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
189 "3Com 3c905C-TX Fast Etherlink XL" },
190 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B,
191 "3Com 3c920B-EMB Integrated Fast Etherlink XL" },
192 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM,
193 "3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" },
194 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
195 "3Com 3c980 Fast Etherlink XL" },
196 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
197 "3Com 3c980C Fast Etherlink XL" },
198 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
199 "3Com 3cSOHO100-TX OfficeConnect" },
200 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
201 "3Com 3c450-TX HomeConnect" },
202 { TC_VENDORID, TC_DEVICEID_HURRICANE_555,
203 "3Com 3c555 Fast Etherlink XL" },
204 { TC_VENDORID, TC_DEVICEID_HURRICANE_556,
205 "3Com 3c556 Fast Etherlink XL" },
206 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
207 "3Com 3c556B Fast Etherlink XL" },
208 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
209 "3Com 3c575TX Fast Etherlink XL" },
210 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
211 "3Com 3c575B Fast Etherlink XL" },
212 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
213 "3Com 3c575C Fast Etherlink XL" },
214 { TC_VENDORID, TC_DEVICEID_HURRICANE_656,
215 "3Com 3c656 Fast Etherlink XL" },
216 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B,
217 "3Com 3c656B Fast Etherlink XL" },
218 { TC_VENDORID, TC_DEVICEID_TORNADO_656C,
219 "3Com 3c656C Fast Etherlink XL" },
223 static int xl_probe(device_t);
224 static int xl_attach(device_t);
225 static int xl_detach(device_t);
227 static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *);
228 static void xl_stats_update(void *);
229 static void xl_stats_update_locked(struct xl_softc *);
230 static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf **);
231 static int xl_rxeof(struct xl_softc *);
232 static void xl_rxeof_task(void *, int);
233 static int xl_rx_resync(struct xl_softc *);
234 static void xl_txeof(struct xl_softc *);
235 static void xl_txeof_90xB(struct xl_softc *);
236 static void xl_txeoc(struct xl_softc *);
237 static void xl_intr(void *);
238 static void xl_start(struct ifnet *);
239 static void xl_start_locked(struct ifnet *);
240 static void xl_start_90xB_locked(struct ifnet *);
241 static int xl_ioctl(struct ifnet *, u_long, caddr_t);
242 static void xl_init(void *);
243 static void xl_init_locked(struct xl_softc *);
244 static void xl_stop(struct xl_softc *);
245 static int xl_watchdog(struct xl_softc *);
246 static int xl_shutdown(device_t);
247 static int xl_suspend(device_t);
248 static int xl_resume(device_t);
250 #ifdef DEVICE_POLLING
251 static int xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
252 static int xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
255 static int xl_ifmedia_upd(struct ifnet *);
256 static void xl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
258 static int xl_eeprom_wait(struct xl_softc *);
259 static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int);
260 static void xl_mii_sync(struct xl_softc *);
261 static void xl_mii_send(struct xl_softc *, u_int32_t, int);
262 static int xl_mii_readreg(struct xl_softc *, struct xl_mii_frame *);
263 static int xl_mii_writereg(struct xl_softc *, struct xl_mii_frame *);
265 static void xl_setcfg(struct xl_softc *);
266 static void xl_setmode(struct xl_softc *, int);
267 static void xl_setmulti(struct xl_softc *);
268 static void xl_setmulti_hash(struct xl_softc *);
269 static void xl_reset(struct xl_softc *);
270 static int xl_list_rx_init(struct xl_softc *);
271 static int xl_list_tx_init(struct xl_softc *);
272 static int xl_list_tx_init_90xB(struct xl_softc *);
273 static void xl_wait(struct xl_softc *);
274 static void xl_mediacheck(struct xl_softc *);
275 static void xl_choose_media(struct xl_softc *sc, int *media);
276 static void xl_choose_xcvr(struct xl_softc *, int);
277 static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int);
279 static void xl_testpacket(struct xl_softc *);
282 static int xl_miibus_readreg(device_t, int, int);
283 static int xl_miibus_writereg(device_t, int, int, int);
284 static void xl_miibus_statchg(device_t);
285 static void xl_miibus_mediainit(device_t);
287 static device_method_t xl_methods[] = {
288 /* Device interface */
289 DEVMETHOD(device_probe, xl_probe),
290 DEVMETHOD(device_attach, xl_attach),
291 DEVMETHOD(device_detach, xl_detach),
292 DEVMETHOD(device_shutdown, xl_shutdown),
293 DEVMETHOD(device_suspend, xl_suspend),
294 DEVMETHOD(device_resume, xl_resume),
297 DEVMETHOD(bus_print_child, bus_generic_print_child),
298 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
301 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
302 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
303 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
304 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
309 static driver_t xl_driver = {
312 sizeof(struct xl_softc)
315 static devclass_t xl_devclass;
317 DRIVER_MODULE(xl, pci, xl_driver, xl_devclass, 0, 0);
318 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0);
321 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
326 *paddr = segs->ds_addr;
330 * Murphy's law says that it's possible the chip can wedge and
331 * the 'command in progress' bit may never clear. Hence, we wait
332 * only a finite amount of time to avoid getting caught in an
333 * infinite loop. Normally this delay routine would be a macro,
334 * but it isn't called during normal operation so we can afford
335 * to make it a function.
338 xl_wait(struct xl_softc *sc)
342 for (i = 0; i < XL_TIMEOUT; i++) {
343 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0)
348 device_printf(sc->xl_dev, "command never completed!\n");
352 * MII access routines are provided for adapters with external
353 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
354 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
355 * Note: if you don't perform the MDIO operations just right,
356 * it's possible to end up with code that works correctly with
357 * some chips/CPUs/processor speeds/bus speeds/etc but not
361 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
362 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x))
365 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
366 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x))
369 * Sync the PHYs by setting data bit and strobing the clock 32 times.
372 xl_mii_sync(struct xl_softc *sc)
377 MII_SET(XL_MII_DIR|XL_MII_DATA);
379 for (i = 0; i < 32; i++) {
381 MII_SET(XL_MII_DATA);
382 MII_SET(XL_MII_DATA);
384 MII_SET(XL_MII_DATA);
385 MII_SET(XL_MII_DATA);
390 * Clock a series of bits through the MII.
393 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt)
400 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
402 MII_SET(XL_MII_DATA);
404 MII_CLR(XL_MII_DATA);
412 * Read an PHY register through the MII.
415 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame)
419 /* Set up frame for RX. */
420 frame->mii_stdelim = XL_MII_STARTDELIM;
421 frame->mii_opcode = XL_MII_READOP;
422 frame->mii_turnaround = 0;
425 /* Select register window 4. */
428 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0);
429 /* Turn on data xmit. */
434 /* Send command/address info. */
435 xl_mii_send(sc, frame->mii_stdelim, 2);
436 xl_mii_send(sc, frame->mii_opcode, 2);
437 xl_mii_send(sc, frame->mii_phyaddr, 5);
438 xl_mii_send(sc, frame->mii_regaddr, 5);
441 MII_CLR((XL_MII_CLK|XL_MII_DATA));
449 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
453 * Now try reading data bits. If the ack failed, we still
454 * need to clock through 16 cycles to keep the PHY(s) in sync.
457 for (i = 0; i < 16; i++) {
464 for (i = 0x8000; i; i >>= 1) {
467 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA)
468 frame->mii_data |= i;
477 return (ack ? 1 : 0);
481 * Write to a PHY register through the MII.
484 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame)
487 /* Set up frame for TX. */
488 frame->mii_stdelim = XL_MII_STARTDELIM;
489 frame->mii_opcode = XL_MII_WRITEOP;
490 frame->mii_turnaround = XL_MII_TURNAROUND;
492 /* Select the window 4. */
495 /* Turn on data output. */
500 xl_mii_send(sc, frame->mii_stdelim, 2);
501 xl_mii_send(sc, frame->mii_opcode, 2);
502 xl_mii_send(sc, frame->mii_phyaddr, 5);
503 xl_mii_send(sc, frame->mii_regaddr, 5);
504 xl_mii_send(sc, frame->mii_turnaround, 2);
505 xl_mii_send(sc, frame->mii_data, 16);
518 xl_miibus_readreg(device_t dev, int phy, int reg)
521 struct xl_mii_frame frame;
523 sc = device_get_softc(dev);
526 * Pretend that PHYs are only available at MII address 24.
527 * This is to guard against problems with certain 3Com ASIC
528 * revisions that incorrectly map the internal transceiver
529 * control registers at all MII addresses. This can cause
530 * the miibus code to attach the same PHY several times over.
532 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0 && phy != 24)
535 bzero((char *)&frame, sizeof(frame));
536 frame.mii_phyaddr = phy;
537 frame.mii_regaddr = reg;
539 xl_mii_readreg(sc, &frame);
541 return (frame.mii_data);
545 xl_miibus_writereg(device_t dev, int phy, int reg, int data)
548 struct xl_mii_frame frame;
550 sc = device_get_softc(dev);
552 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0 && phy != 24)
555 bzero((char *)&frame, sizeof(frame));
556 frame.mii_phyaddr = phy;
557 frame.mii_regaddr = reg;
558 frame.mii_data = data;
560 xl_mii_writereg(sc, &frame);
566 xl_miibus_statchg(device_t dev)
569 struct mii_data *mii;
571 sc = device_get_softc(dev);
572 mii = device_get_softc(sc->xl_miibus);
576 /* Set ASIC's duplex mode to match the PHY. */
578 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
579 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
581 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
582 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
586 * Special support for the 3c905B-COMBO. This card has 10/100 support
587 * plus BNC and AUI ports. This means we will have both an miibus attached
588 * plus some non-MII media settings. In order to allow this, we have to
589 * add the extra media to the miibus's ifmedia struct, but we can't do
590 * that during xl_attach() because the miibus hasn't been attached yet.
591 * So instead, we wait until the miibus probe/attach is done, at which
592 * point we will get a callback telling is that it's safe to add our
596 xl_miibus_mediainit(device_t dev)
599 struct mii_data *mii;
602 sc = device_get_softc(dev);
603 mii = device_get_softc(sc->xl_miibus);
604 ifm = &mii->mii_media;
606 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) {
608 * Check for a 10baseFL board in disguise.
610 if (sc->xl_type == XL_TYPE_905B &&
611 sc->xl_media == XL_MEDIAOPT_10FL) {
613 device_printf(sc->xl_dev, "found 10baseFL\n");
614 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL);
615 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0,
617 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
619 IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL);
622 device_printf(sc->xl_dev, "found AUI\n");
623 ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL);
627 if (sc->xl_media & XL_MEDIAOPT_BNC) {
629 device_printf(sc->xl_dev, "found BNC\n");
630 ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL);
635 * The EEPROM is slow: give it time to come ready after issuing
639 xl_eeprom_wait(struct xl_softc *sc)
643 for (i = 0; i < 100; i++) {
644 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
651 device_printf(sc->xl_dev, "eeprom failed to come ready\n");
659 * Read a sequence of words from the EEPROM. Note that ethernet address
660 * data is stored in the EEPROM in network byte order.
663 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap)
666 u_int16_t word = 0, *ptr;
668 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
669 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
671 * XXX: WARNING! DANGER!
672 * It's easy to accidentally overwrite the rom content!
673 * Note: the 3c575 uses 8bit EEPROM offsets.
677 if (xl_eeprom_wait(sc))
680 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
683 for (i = 0; i < cnt; i++) {
684 if (sc->xl_flags & XL_FLAG_8BITROM)
685 CSR_WRITE_2(sc, XL_W0_EE_CMD,
686 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
688 CSR_WRITE_2(sc, XL_W0_EE_CMD,
689 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
690 err = xl_eeprom_wait(sc);
693 word = CSR_READ_2(sc, XL_W0_EE_DATA);
694 ptr = (u_int16_t *)(dest + (i * 2));
701 return (err ? 1 : 0);
705 * NICs older than the 3c905B have only one multicast option, which
706 * is to enable reception of all multicast frames.
709 xl_setmulti(struct xl_softc *sc)
711 struct ifnet *ifp = sc->xl_ifp;
712 struct ifmultiaddr *ifma;
719 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
721 if (ifp->if_flags & IFF_ALLMULTI) {
722 rxfilt |= XL_RXFILTER_ALLMULTI;
723 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
728 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link)
730 if_maddr_runlock(ifp);
733 rxfilt |= XL_RXFILTER_ALLMULTI;
735 rxfilt &= ~XL_RXFILTER_ALLMULTI;
737 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
741 * 3c905B adapters have a hash filter that we can program.
744 xl_setmulti_hash(struct xl_softc *sc)
746 struct ifnet *ifp = sc->xl_ifp;
748 struct ifmultiaddr *ifma;
755 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
757 if (ifp->if_flags & IFF_ALLMULTI) {
758 rxfilt |= XL_RXFILTER_ALLMULTI;
759 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
762 rxfilt &= ~XL_RXFILTER_ALLMULTI;
764 /* first, zot all the existing hash bits */
765 for (i = 0; i < XL_HASHFILT_SIZE; i++)
766 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i);
768 /* now program new ones */
770 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
771 if (ifma->ifma_addr->sa_family != AF_LINK)
774 * Note: the 3c905B currently only supports a 64-bit hash
775 * table, which means we really only need 6 bits, but the
776 * manual indicates that future chip revisions will have a
777 * 256-bit hash table, hence the routine is set up to
778 * calculate 8 bits of position info in case we need it some
780 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have
781 * a 256 bit hash table. This means we have to use all 8 bits
782 * regardless. On older cards, the upper 2 bits will be
785 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
786 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF;
787 CSR_WRITE_2(sc, XL_COMMAND,
788 h | XL_CMD_RX_SET_HASH | XL_HASH_SET);
791 if_maddr_runlock(ifp);
794 rxfilt |= XL_RXFILTER_MULTIHASH;
796 rxfilt &= ~XL_RXFILTER_MULTIHASH;
798 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
802 xl_setcfg(struct xl_softc *sc)
806 /*XL_LOCK_ASSERT(sc);*/
809 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
810 icfg &= ~XL_ICFG_CONNECTOR_MASK;
811 if (sc->xl_media & XL_MEDIAOPT_MII ||
812 sc->xl_media & XL_MEDIAOPT_BT4)
813 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
814 if (sc->xl_media & XL_MEDIAOPT_BTX)
815 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
817 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
818 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
822 xl_setmode(struct xl_softc *sc, int media)
826 char *pmsg = "", *dmsg = "";
831 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
833 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
835 if (sc->xl_media & XL_MEDIAOPT_BT) {
836 if (IFM_SUBTYPE(media) == IFM_10_T) {
837 pmsg = "10baseT transceiver";
838 sc->xl_xcvr = XL_XCVR_10BT;
839 icfg &= ~XL_ICFG_CONNECTOR_MASK;
840 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
841 mediastat |= XL_MEDIASTAT_LINKBEAT |
842 XL_MEDIASTAT_JABGUARD;
843 mediastat &= ~XL_MEDIASTAT_SQEENB;
847 if (sc->xl_media & XL_MEDIAOPT_BFX) {
848 if (IFM_SUBTYPE(media) == IFM_100_FX) {
849 pmsg = "100baseFX port";
850 sc->xl_xcvr = XL_XCVR_100BFX;
851 icfg &= ~XL_ICFG_CONNECTOR_MASK;
852 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
853 mediastat |= XL_MEDIASTAT_LINKBEAT;
854 mediastat &= ~XL_MEDIASTAT_SQEENB;
858 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
859 if (IFM_SUBTYPE(media) == IFM_10_5) {
861 sc->xl_xcvr = XL_XCVR_AUI;
862 icfg &= ~XL_ICFG_CONNECTOR_MASK;
863 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
864 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
865 XL_MEDIASTAT_JABGUARD);
866 mediastat |= ~XL_MEDIASTAT_SQEENB;
868 if (IFM_SUBTYPE(media) == IFM_10_FL) {
869 pmsg = "10baseFL transceiver";
870 sc->xl_xcvr = XL_XCVR_AUI;
871 icfg &= ~XL_ICFG_CONNECTOR_MASK;
872 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
873 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
874 XL_MEDIASTAT_JABGUARD);
875 mediastat |= ~XL_MEDIASTAT_SQEENB;
879 if (sc->xl_media & XL_MEDIAOPT_BNC) {
880 if (IFM_SUBTYPE(media) == IFM_10_2) {
882 sc->xl_xcvr = XL_XCVR_COAX;
883 icfg &= ~XL_ICFG_CONNECTOR_MASK;
884 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
885 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
886 XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB);
890 if ((media & IFM_GMASK) == IFM_FDX ||
891 IFM_SUBTYPE(media) == IFM_100_FX) {
894 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
898 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
899 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
902 if (IFM_SUBTYPE(media) == IFM_10_2)
903 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
905 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
907 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
909 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
914 device_printf(sc->xl_dev, "selecting %s, %s duplex\n", pmsg, dmsg);
918 xl_reset(struct xl_softc *sc)
925 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
926 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
927 XL_RESETOPT_DISADVFD:0));
930 * If we're using memory mapped register mode, pause briefly
931 * after issuing the reset command before trying to access any
932 * other registers. With my 3c575C cardbus card, failing to do
933 * this results in the system locking up while trying to poll
934 * the command busy bit in the status register.
936 if (sc->xl_flags & XL_FLAG_USE_MMIO)
939 for (i = 0; i < XL_TIMEOUT; i++) {
941 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
946 device_printf(sc->xl_dev, "reset didn't complete\n");
948 /* Reset TX and RX. */
949 /* Note: the RX reset takes an absurd amount of time
950 * on newer versions of the Tornado chips such as those
951 * on the 3c905CX and newer 3c908C cards. We wait an
952 * extra amount of time so that xl_wait() doesn't complain
953 * and annoy the users.
955 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
958 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
961 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
962 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
964 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS,
965 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) |
966 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ?
967 XL_RESETOPT_INVERT_LED : 0) |
968 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ?
969 XL_RESETOPT_INVERT_MII : 0));
972 /* Wait a little while for the chip to get its brains in order. */
977 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
978 * IDs against our list and return a device name if we find a match.
981 xl_probe(device_t dev)
983 const struct xl_type *t;
987 while (t->xl_name != NULL) {
988 if ((pci_get_vendor(dev) == t->xl_vid) &&
989 (pci_get_device(dev) == t->xl_did)) {
990 device_set_desc(dev, t->xl_name);
991 return (BUS_PROBE_DEFAULT);
1000 * This routine is a kludge to work around possible hardware faults
1001 * or manufacturing defects that can cause the media options register
1002 * (or reset options register, as it's called for the first generation
1003 * 3c90x adapters) to return an incorrect result. I have encountered
1004 * one Dell Latitude laptop docking station with an integrated 3c905-TX
1005 * which doesn't have any of the 'mediaopt' bits set. This screws up
1006 * the attach routine pretty badly because it doesn't know what media
1007 * to look for. If we find ourselves in this predicament, this routine
1008 * will try to guess the media options values and warn the user of a
1009 * possible manufacturing defect with his adapter/system/whatever.
1012 xl_mediacheck(struct xl_softc *sc)
1016 * If some of the media options bits are set, assume they are
1017 * correct. If not, try to figure it out down below.
1018 * XXX I should check for 10baseFL, but I don't have an adapter
1021 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
1023 * Check the XCVR value. If it's not in the normal range
1024 * of values, we need to fake it up here.
1026 if (sc->xl_xcvr <= XL_XCVR_AUTO)
1029 device_printf(sc->xl_dev,
1030 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr);
1031 device_printf(sc->xl_dev,
1032 "choosing new default based on card type\n");
1035 if (sc->xl_type == XL_TYPE_905B &&
1036 sc->xl_media & XL_MEDIAOPT_10FL)
1038 device_printf(sc->xl_dev,
1039 "WARNING: no media options bits set in the media options register!!\n");
1040 device_printf(sc->xl_dev,
1041 "this could be a manufacturing defect in your adapter or system\n");
1042 device_printf(sc->xl_dev,
1043 "attempting to guess media type; you should probably consult your vendor\n");
1046 xl_choose_xcvr(sc, 1);
1050 xl_choose_xcvr(struct xl_softc *sc, int verbose)
1055 * Read the device ID from the EEPROM.
1056 * This is what's loaded into the PCI device ID register, so it has
1057 * to be correct otherwise we wouldn't have gotten this far.
1059 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
1062 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
1063 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
1064 sc->xl_media = XL_MEDIAOPT_BT;
1065 sc->xl_xcvr = XL_XCVR_10BT;
1067 device_printf(sc->xl_dev,
1068 "guessing 10BaseT transceiver\n");
1070 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
1071 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
1072 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1073 sc->xl_xcvr = XL_XCVR_10BT;
1075 device_printf(sc->xl_dev,
1076 "guessing COMBO (AUI/BNC/TP)\n");
1078 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
1079 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1080 sc->xl_xcvr = XL_XCVR_10BT;
1082 device_printf(sc->xl_dev, "guessing TPC (BNC/TP)\n");
1084 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1085 sc->xl_media = XL_MEDIAOPT_10FL;
1086 sc->xl_xcvr = XL_XCVR_AUI;
1088 device_printf(sc->xl_dev, "guessing 10baseFL\n");
1090 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1091 case TC_DEVICEID_HURRICANE_555: /* 3c555 */
1092 case TC_DEVICEID_HURRICANE_556: /* 3c556 */
1093 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */
1094 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */
1095 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */
1096 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */
1097 case TC_DEVICEID_HURRICANE_656: /* 3c656 */
1098 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */
1099 case TC_DEVICEID_TORNADO_656C: /* 3c656C */
1100 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */
1101 case TC_DEVICEID_TORNADO_10_100BT_920B_WNM: /* 3c920B-EMB-WNM */
1102 sc->xl_media = XL_MEDIAOPT_MII;
1103 sc->xl_xcvr = XL_XCVR_MII;
1105 device_printf(sc->xl_dev, "guessing MII\n");
1107 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1108 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1109 sc->xl_media = XL_MEDIAOPT_BT4;
1110 sc->xl_xcvr = XL_XCVR_MII;
1112 device_printf(sc->xl_dev, "guessing 100baseT4/MII\n");
1114 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1115 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1116 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1117 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1118 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1119 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1120 sc->xl_media = XL_MEDIAOPT_BTX;
1121 sc->xl_xcvr = XL_XCVR_AUTO;
1123 device_printf(sc->xl_dev, "guessing 10/100 internal\n");
1125 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1126 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1127 sc->xl_xcvr = XL_XCVR_AUTO;
1129 device_printf(sc->xl_dev,
1130 "guessing 10/100 plus BNC/AUI\n");
1133 device_printf(sc->xl_dev,
1134 "unknown device ID: %x -- defaulting to 10baseT\n", devid);
1135 sc->xl_media = XL_MEDIAOPT_BT;
1141 * Attach the interface. Allocate softc structures, do ifmedia
1142 * setup and ethernet/BPF attach.
1145 xl_attach(device_t dev)
1147 u_char eaddr[ETHER_ADDR_LEN];
1149 struct xl_softc *sc;
1152 int unit, error = 0, rid, res;
1155 sc = device_get_softc(dev);
1158 unit = device_get_unit(dev);
1160 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1162 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1164 did = pci_get_device(dev);
1167 if (did == TC_DEVICEID_HURRICANE_555)
1168 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1169 if (did == TC_DEVICEID_HURRICANE_556 ||
1170 did == TC_DEVICEID_HURRICANE_556B)
1171 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1172 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1173 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1174 if (did == TC_DEVICEID_HURRICANE_555 ||
1175 did == TC_DEVICEID_HURRICANE_556)
1176 sc->xl_flags |= XL_FLAG_8BITROM;
1177 if (did == TC_DEVICEID_HURRICANE_556B)
1178 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1180 if (did == TC_DEVICEID_HURRICANE_575B ||
1181 did == TC_DEVICEID_HURRICANE_575C ||
1182 did == TC_DEVICEID_HURRICANE_656B ||
1183 did == TC_DEVICEID_TORNADO_656C)
1184 sc->xl_flags |= XL_FLAG_FUNCREG;
1185 if (did == TC_DEVICEID_HURRICANE_575A ||
1186 did == TC_DEVICEID_HURRICANE_575B ||
1187 did == TC_DEVICEID_HURRICANE_575C ||
1188 did == TC_DEVICEID_HURRICANE_656B ||
1189 did == TC_DEVICEID_TORNADO_656C)
1190 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 |
1192 if (did == TC_DEVICEID_HURRICANE_656)
1193 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1194 if (did == TC_DEVICEID_HURRICANE_575B)
1195 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1196 if (did == TC_DEVICEID_HURRICANE_575C)
1197 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1198 if (did == TC_DEVICEID_TORNADO_656C)
1199 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1200 if (did == TC_DEVICEID_HURRICANE_656 ||
1201 did == TC_DEVICEID_HURRICANE_656B)
1202 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1203 XL_FLAG_INVERT_LED_PWR;
1204 if (did == TC_DEVICEID_TORNADO_10_100BT_920B ||
1205 did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM)
1206 sc->xl_flags |= XL_FLAG_PHYOK;
1209 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1210 case TC_DEVICEID_HURRICANE_575A:
1211 case TC_DEVICEID_HURRICANE_575B:
1212 case TC_DEVICEID_HURRICANE_575C:
1213 sc->xl_flags |= XL_FLAG_NO_MMIO;
1220 * Map control/status registers.
1222 pci_enable_busmaster(dev);
1224 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) {
1226 res = SYS_RES_MEMORY;
1228 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1231 if (sc->xl_res != NULL) {
1232 sc->xl_flags |= XL_FLAG_USE_MMIO;
1234 device_printf(dev, "using memory mapped I/O\n");
1237 res = SYS_RES_IOPORT;
1238 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1239 if (sc->xl_res == NULL) {
1240 device_printf(dev, "couldn't map ports/memory\n");
1245 device_printf(dev, "using port I/O\n");
1248 sc->xl_btag = rman_get_bustag(sc->xl_res);
1249 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1251 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1252 rid = XL_PCI_FUNCMEM;
1253 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1256 if (sc->xl_fres == NULL) {
1257 device_printf(dev, "couldn't map funcreg memory\n");
1262 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1263 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1266 /* Allocate interrupt */
1268 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1269 RF_SHAREABLE | RF_ACTIVE);
1270 if (sc->xl_irq == NULL) {
1271 device_printf(dev, "couldn't map interrupt\n");
1276 /* Initialize interface name. */
1277 ifp = sc->xl_ifp = if_alloc(IFT_ETHER);
1279 device_printf(dev, "can not if_alloc()\n");
1284 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1286 /* Reset the adapter. */
1292 * Get station address from the EEPROM.
1294 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1295 device_printf(dev, "failed to read station address\n");
1300 callout_init_mtx(&sc->xl_stat_callout, &sc->xl_mtx, 0);
1301 TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc);
1304 * Now allocate a tag for the DMA descriptor lists and a chunk
1305 * of DMA-able memory based on the tag. Also obtain the DMA
1306 * addresses of the RX and TX ring, which we'll need later.
1307 * All of our lists are allocated as a contiguous block
1310 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
1311 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1312 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL,
1313 &sc->xl_ldata.xl_rx_tag);
1315 device_printf(dev, "failed to allocate rx dma tag\n");
1319 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag,
1320 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1321 &sc->xl_ldata.xl_rx_dmamap);
1323 device_printf(dev, "no memory for rx list buffers!\n");
1324 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1325 sc->xl_ldata.xl_rx_tag = NULL;
1329 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag,
1330 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list,
1331 XL_RX_LIST_SZ, xl_dma_map_addr,
1332 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT);
1334 device_printf(dev, "cannot get dma address of the rx ring!\n");
1335 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1336 sc->xl_ldata.xl_rx_dmamap);
1337 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1338 sc->xl_ldata.xl_rx_tag = NULL;
1342 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
1343 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1344 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL,
1345 &sc->xl_ldata.xl_tx_tag);
1347 device_printf(dev, "failed to allocate tx dma tag\n");
1351 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag,
1352 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1353 &sc->xl_ldata.xl_tx_dmamap);
1355 device_printf(dev, "no memory for list buffers!\n");
1356 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1357 sc->xl_ldata.xl_tx_tag = NULL;
1361 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag,
1362 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list,
1363 XL_TX_LIST_SZ, xl_dma_map_addr,
1364 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT);
1366 device_printf(dev, "cannot get dma address of the tx ring!\n");
1367 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1368 sc->xl_ldata.xl_tx_dmamap);
1369 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1370 sc->xl_ldata.xl_tx_tag = NULL;
1375 * Allocate a DMA tag for the mapping of mbufs.
1377 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
1378 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1379 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL,
1380 NULL, &sc->xl_mtag);
1382 device_printf(dev, "failed to allocate mbuf dma tag\n");
1386 /* We need a spare DMA map for the RX ring. */
1387 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap);
1392 * Figure out the card type. 3c905B adapters have the
1393 * 'supportsNoTxLength' bit set in the capabilities
1394 * word in the EEPROM.
1395 * Note: my 3c575C cardbus card lies. It returns a value
1396 * of 0x1578 for its capabilities word, which is somewhat
1397 * nonsensical. Another way to distinguish a 3c90x chip
1398 * from a 3c90xB/C chip is to check for the 'supportsLargePackets'
1399 * bit. This will only be set for 3c90x boomerage chips.
1401 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1402 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
1403 !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
1404 sc->xl_type = XL_TYPE_905B;
1406 sc->xl_type = XL_TYPE_90X;
1408 /* Set the TX start threshold for best performance. */
1409 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
1411 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1412 ifp->if_ioctl = xl_ioctl;
1413 ifp->if_capabilities = IFCAP_VLAN_MTU;
1414 if (sc->xl_type == XL_TYPE_905B) {
1415 ifp->if_hwassist = XL905B_CSUM_FEATURES;
1416 #ifdef XL905B_TXCSUM_BROKEN
1417 ifp->if_capabilities |= IFCAP_RXCSUM;
1419 ifp->if_capabilities |= IFCAP_HWCSUM;
1422 ifp->if_capenable = ifp->if_capabilities;
1423 #ifdef DEVICE_POLLING
1424 ifp->if_capabilities |= IFCAP_POLLING;
1426 ifp->if_start = xl_start;
1427 ifp->if_init = xl_init;
1428 IFQ_SET_MAXLEN(&ifp->if_snd, XL_TX_LIST_CNT - 1);
1429 ifp->if_snd.ifq_drv_maxlen = XL_TX_LIST_CNT - 1;
1430 IFQ_SET_READY(&ifp->if_snd);
1433 * Now we have to see what sort of media we have.
1434 * This includes probing for an MII interace and a
1438 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1440 device_printf(dev, "media options word: %x\n", sc->xl_media);
1442 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1443 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1444 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1445 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1449 if (sc->xl_media & XL_MEDIAOPT_MII ||
1450 sc->xl_media & XL_MEDIAOPT_BTX ||
1451 sc->xl_media & XL_MEDIAOPT_BT4) {
1453 device_printf(dev, "found MII/AUTO\n");
1455 if (mii_phy_probe(dev, &sc->xl_miibus,
1456 xl_ifmedia_upd, xl_ifmedia_sts)) {
1457 device_printf(dev, "no PHY found!\n");
1465 * Sanity check. If the user has selected "auto" and this isn't
1466 * a 10/100 card of some kind, we need to force the transceiver
1467 * type to something sane.
1469 if (sc->xl_xcvr == XL_XCVR_AUTO)
1470 xl_choose_xcvr(sc, bootverbose);
1475 if (sc->xl_media & XL_MEDIAOPT_BT) {
1477 device_printf(dev, "found 10baseT\n");
1478 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1479 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1480 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1481 ifmedia_add(&sc->ifmedia,
1482 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1485 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1487 * Check for a 10baseFL board in disguise.
1489 if (sc->xl_type == XL_TYPE_905B &&
1490 sc->xl_media == XL_MEDIAOPT_10FL) {
1492 device_printf(dev, "found 10baseFL\n");
1493 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1494 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1496 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1497 ifmedia_add(&sc->ifmedia,
1498 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1501 device_printf(dev, "found AUI\n");
1502 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1506 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1508 device_printf(dev, "found BNC\n");
1509 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1512 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1514 device_printf(dev, "found 100baseFX\n");
1515 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1518 media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1519 xl_choose_media(sc, &media);
1521 if (sc->xl_miibus == NULL)
1522 ifmedia_set(&sc->ifmedia, media);
1525 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1527 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1531 * Call MI attach routine.
1533 ether_ifattach(ifp, eaddr);
1535 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE,
1536 NULL, xl_intr, sc, &sc->xl_intrhand);
1538 device_printf(dev, "couldn't set up irq\n");
1539 ether_ifdetach(ifp);
1551 * Choose a default media.
1552 * XXX This is a leaf function only called by xl_attach() and
1553 * acquires/releases the non-recursible driver mutex to
1554 * satisfy lock assertions.
1557 xl_choose_media(struct xl_softc *sc, int *media)
1562 switch (sc->xl_xcvr) {
1564 *media = IFM_ETHER|IFM_10_T;
1565 xl_setmode(sc, *media);
1568 if (sc->xl_type == XL_TYPE_905B &&
1569 sc->xl_media == XL_MEDIAOPT_10FL) {
1570 *media = IFM_ETHER|IFM_10_FL;
1571 xl_setmode(sc, *media);
1573 *media = IFM_ETHER|IFM_10_5;
1574 xl_setmode(sc, *media);
1578 *media = IFM_ETHER|IFM_10_2;
1579 xl_setmode(sc, *media);
1582 case XL_XCVR_100BTX:
1584 /* Chosen by miibus */
1586 case XL_XCVR_100BFX:
1587 *media = IFM_ETHER|IFM_100_FX;
1590 device_printf(sc->xl_dev, "unknown XCVR type: %d\n",
1593 * This will probably be wrong, but it prevents
1594 * the ifmedia code from panicking.
1596 *media = IFM_ETHER|IFM_10_T;
1604 * Shutdown hardware and free up resources. This can be called any
1605 * time after the mutex has been initialized. It is called in both
1606 * the error case in attach and the normal detach case so it needs
1607 * to be careful about only freeing resources that have actually been
1611 xl_detach(device_t dev)
1613 struct xl_softc *sc;
1617 sc = device_get_softc(dev);
1620 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized"));
1622 #ifdef DEVICE_POLLING
1623 if (ifp && ifp->if_capenable & IFCAP_POLLING)
1624 ether_poll_deregister(ifp);
1627 if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1629 res = SYS_RES_MEMORY;
1632 res = SYS_RES_IOPORT;
1635 /* These should only be active if attach succeeded */
1636 if (device_is_attached(dev)) {
1641 taskqueue_drain(taskqueue_swi, &sc->xl_task);
1642 callout_drain(&sc->xl_stat_callout);
1643 ether_ifdetach(ifp);
1646 device_delete_child(dev, sc->xl_miibus);
1647 bus_generic_detach(dev);
1648 ifmedia_removeall(&sc->ifmedia);
1650 if (sc->xl_intrhand)
1651 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1653 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1654 if (sc->xl_fres != NULL)
1655 bus_release_resource(dev, SYS_RES_MEMORY,
1656 XL_PCI_FUNCMEM, sc->xl_fres);
1658 bus_release_resource(dev, res, rid, sc->xl_res);
1664 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap);
1665 bus_dma_tag_destroy(sc->xl_mtag);
1667 if (sc->xl_ldata.xl_rx_tag) {
1668 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag,
1669 sc->xl_ldata.xl_rx_dmamap);
1670 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1671 sc->xl_ldata.xl_rx_dmamap);
1672 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1674 if (sc->xl_ldata.xl_tx_tag) {
1675 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag,
1676 sc->xl_ldata.xl_tx_dmamap);
1677 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1678 sc->xl_ldata.xl_tx_dmamap);
1679 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1682 mtx_destroy(&sc->xl_mtx);
1688 * Initialize the transmit descriptors.
1691 xl_list_tx_init(struct xl_softc *sc)
1693 struct xl_chain_data *cd;
1694 struct xl_list_data *ld;
1701 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1702 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1703 error = bus_dmamap_create(sc->xl_mtag, 0,
1704 &cd->xl_tx_chain[i].xl_map);
1707 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1708 i * sizeof(struct xl_list);
1709 if (i == (XL_TX_LIST_CNT - 1))
1710 cd->xl_tx_chain[i].xl_next = NULL;
1712 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1715 cd->xl_tx_free = &cd->xl_tx_chain[0];
1716 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1718 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1723 * Initialize the transmit descriptors.
1726 xl_list_tx_init_90xB(struct xl_softc *sc)
1728 struct xl_chain_data *cd;
1729 struct xl_list_data *ld;
1736 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1737 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1738 error = bus_dmamap_create(sc->xl_mtag, 0,
1739 &cd->xl_tx_chain[i].xl_map);
1742 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1743 i * sizeof(struct xl_list);
1744 if (i == (XL_TX_LIST_CNT - 1))
1745 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1747 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1749 cd->xl_tx_chain[i].xl_prev =
1750 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1752 cd->xl_tx_chain[i].xl_prev =
1753 &cd->xl_tx_chain[i - 1];
1756 bzero(ld->xl_tx_list, XL_TX_LIST_SZ);
1757 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY);
1763 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1768 * Initialize the RX descriptors and allocate mbufs for them. Note that
1769 * we arrange the descriptors in a closed ring, so that the last descriptor
1770 * points back to the first.
1773 xl_list_rx_init(struct xl_softc *sc)
1775 struct xl_chain_data *cd;
1776 struct xl_list_data *ld;
1785 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1786 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i];
1787 error = bus_dmamap_create(sc->xl_mtag, 0,
1788 &cd->xl_rx_chain[i].xl_map);
1791 error = xl_newbuf(sc, &cd->xl_rx_chain[i]);
1794 if (i == (XL_RX_LIST_CNT - 1))
1798 nextptr = ld->xl_rx_dmaaddr +
1799 next * sizeof(struct xl_list_onefrag);
1800 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next];
1801 ld->xl_rx_list[i].xl_next = htole32(nextptr);
1804 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1805 cd->xl_rx_head = &cd->xl_rx_chain[0];
1811 * Initialize an RX descriptor and attach an MBUF cluster.
1812 * If we fail to do so, we need to leave the old mbuf and
1813 * the old DMA map untouched so that it can be reused.
1816 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c)
1818 struct mbuf *m_new = NULL;
1820 bus_dma_segment_t segs[1];
1825 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1829 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1831 /* Force longword alignment for packet payload. */
1832 m_adj(m_new, ETHER_ALIGN);
1834 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, sc->xl_tmpmap, m_new,
1835 segs, &nseg, BUS_DMA_NOWAIT);
1838 device_printf(sc->xl_dev, "can't map mbuf (error %d)\n",
1843 ("%s: too many DMA segments (%d)", __func__, nseg));
1845 bus_dmamap_unload(sc->xl_mtag, c->xl_map);
1847 c->xl_map = sc->xl_tmpmap;
1848 sc->xl_tmpmap = map;
1850 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG);
1851 c->xl_ptr->xl_status = 0;
1852 c->xl_ptr->xl_frag.xl_addr = htole32(segs->ds_addr);
1853 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD);
1858 xl_rx_resync(struct xl_softc *sc)
1860 struct xl_chain_onefrag *pos;
1865 pos = sc->xl_cdata.xl_rx_head;
1867 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1868 if (pos->xl_ptr->xl_status)
1873 if (i == XL_RX_LIST_CNT)
1876 sc->xl_cdata.xl_rx_head = pos;
1882 * A frame has been uploaded: pass the resulting mbuf chain up to
1883 * the higher level protocols.
1886 xl_rxeof(struct xl_softc *sc)
1889 struct ifnet *ifp = sc->xl_ifp;
1890 struct xl_chain_onefrag *cur_rx;
1897 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap,
1898 BUS_DMASYNC_POSTREAD);
1899 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
1900 #ifdef DEVICE_POLLING
1901 if (ifp->if_capenable & IFCAP_POLLING) {
1902 if (sc->rxcycles <= 0)
1907 cur_rx = sc->xl_cdata.xl_rx_head;
1908 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
1909 total_len = rxstat & XL_RXSTAT_LENMASK;
1912 * Since we have told the chip to allow large frames,
1913 * we need to trap giant frame errors in software. We allow
1914 * a little more than the normal frame size to account for
1915 * frames with VLAN tags.
1917 if (total_len > XL_MAX_FRAMELEN)
1918 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE);
1921 * If an error occurs, update stats, clear the
1922 * status word and leave the mbuf cluster in place:
1923 * it should simply get re-used next time this descriptor
1924 * comes up in the ring.
1926 if (rxstat & XL_RXSTAT_UP_ERROR) {
1928 cur_rx->xl_ptr->xl_status = 0;
1929 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1930 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1935 * If the error bit was not set, the upload complete
1936 * bit should be set which means we have a valid packet.
1937 * If not, something truly strange has happened.
1939 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
1940 device_printf(sc->xl_dev,
1941 "bad receive status -- packet dropped\n");
1943 cur_rx->xl_ptr->xl_status = 0;
1944 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1945 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1949 /* No errors; receive the packet. */
1950 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map,
1951 BUS_DMASYNC_POSTREAD);
1952 m = cur_rx->xl_mbuf;
1955 * Try to conjure up a new mbuf cluster. If that
1956 * fails, it means we have an out of memory condition and
1957 * should leave the buffer in place and continue. This will
1958 * result in a lost packet, but there's little else we
1959 * can do in this situation.
1961 if (xl_newbuf(sc, cur_rx)) {
1963 cur_rx->xl_ptr->xl_status = 0;
1964 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1965 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1968 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1969 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1972 m->m_pkthdr.rcvif = ifp;
1973 m->m_pkthdr.len = m->m_len = total_len;
1975 if (ifp->if_capenable & IFCAP_RXCSUM) {
1976 /* Do IP checksum checking. */
1977 if (rxstat & XL_RXSTAT_IPCKOK)
1978 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1979 if (!(rxstat & XL_RXSTAT_IPCKERR))
1980 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1981 if ((rxstat & XL_RXSTAT_TCPCOK &&
1982 !(rxstat & XL_RXSTAT_TCPCKERR)) ||
1983 (rxstat & XL_RXSTAT_UDPCKOK &&
1984 !(rxstat & XL_RXSTAT_UDPCKERR))) {
1985 m->m_pkthdr.csum_flags |=
1986 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1987 m->m_pkthdr.csum_data = 0xffff;
1992 (*ifp->if_input)(ifp, m);
1997 * If we are running from the taskqueue, the interface
1998 * might have been stopped while we were passing the last
1999 * packet up the network stack.
2001 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
2006 * Handle the 'end of channel' condition. When the upload
2007 * engine hits the end of the RX ring, it will stall. This
2008 * is our cue to flush the RX ring, reload the uplist pointer
2009 * register and unstall the engine.
2010 * XXX This is actually a little goofy. With the ThunderLAN
2011 * chip, you get an interrupt when the receiver hits the end
2012 * of the receive ring, which tells you exactly when you
2013 * you need to reload the ring pointer. Here we have to
2014 * fake it. I'm mad at myself for not being clever enough
2015 * to avoid the use of a goto here.
2017 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
2018 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
2019 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2021 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2022 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
2023 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2030 * Taskqueue wrapper for xl_rxeof().
2033 xl_rxeof_task(void *arg, int pending)
2035 struct xl_softc *sc = (struct xl_softc *)arg;
2038 if (sc->xl_ifp->if_drv_flags & IFF_DRV_RUNNING)
2044 * A frame was downloaded to the chip. It's safe for us to clean up
2048 xl_txeof(struct xl_softc *sc)
2050 struct xl_chain *cur_tx;
2051 struct ifnet *ifp = sc->xl_ifp;
2056 * Go through our tx list and free mbufs for those
2057 * frames that have been uploaded. Note: the 3c905B
2058 * sets a special bit in the status word to let us
2059 * know that a frame has been downloaded, but the
2060 * original 3c900/3c905 adapters don't do that.
2061 * Consequently, we have to use a different test if
2062 * xl_type != XL_TYPE_905B.
2064 while (sc->xl_cdata.xl_tx_head != NULL) {
2065 cur_tx = sc->xl_cdata.xl_tx_head;
2067 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
2070 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
2071 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2072 BUS_DMASYNC_POSTWRITE);
2073 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2074 m_freem(cur_tx->xl_mbuf);
2075 cur_tx->xl_mbuf = NULL;
2077 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2079 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2080 sc->xl_cdata.xl_tx_free = cur_tx;
2083 if (sc->xl_cdata.xl_tx_head == NULL) {
2084 sc->xl_wdog_timer = 0;
2085 sc->xl_cdata.xl_tx_tail = NULL;
2087 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2088 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2089 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2090 sc->xl_cdata.xl_tx_head->xl_phys);
2091 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2097 xl_txeof_90xB(struct xl_softc *sc)
2099 struct xl_chain *cur_tx = NULL;
2100 struct ifnet *ifp = sc->xl_ifp;
2105 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2106 BUS_DMASYNC_POSTREAD);
2107 idx = sc->xl_cdata.xl_tx_cons;
2108 while (idx != sc->xl_cdata.xl_tx_prod) {
2109 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2111 if (!(le32toh(cur_tx->xl_ptr->xl_status) &
2112 XL_TXSTAT_DL_COMPLETE))
2115 if (cur_tx->xl_mbuf != NULL) {
2116 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2117 BUS_DMASYNC_POSTWRITE);
2118 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2119 m_freem(cur_tx->xl_mbuf);
2120 cur_tx->xl_mbuf = NULL;
2125 sc->xl_cdata.xl_tx_cnt--;
2126 XL_INC(idx, XL_TX_LIST_CNT);
2129 if (sc->xl_cdata.xl_tx_cnt == 0)
2130 sc->xl_wdog_timer = 0;
2131 sc->xl_cdata.xl_tx_cons = idx;
2134 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2138 * TX 'end of channel' interrupt handler. Actually, we should
2139 * only get a 'TX complete' interrupt if there's a transmit error,
2140 * so this is really TX error handler.
2143 xl_txeoc(struct xl_softc *sc)
2149 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2150 if (txstat & XL_TXSTATUS_UNDERRUN ||
2151 txstat & XL_TXSTATUS_JABBER ||
2152 txstat & XL_TXSTATUS_RECLAIM) {
2153 device_printf(sc->xl_dev,
2154 "transmission error: %x\n", txstat);
2155 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2157 if (sc->xl_type == XL_TYPE_905B) {
2158 if (sc->xl_cdata.xl_tx_cnt) {
2162 i = sc->xl_cdata.xl_tx_cons;
2163 c = &sc->xl_cdata.xl_tx_chain[i];
2164 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2166 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2169 if (sc->xl_cdata.xl_tx_head != NULL)
2170 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2171 sc->xl_cdata.xl_tx_head->xl_phys);
2174 * Remember to set this for the
2175 * first generation 3c90X chips.
2177 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2178 if (txstat & XL_TXSTATUS_UNDERRUN &&
2179 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2180 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2181 device_printf(sc->xl_dev,
2182 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh);
2184 CSR_WRITE_2(sc, XL_COMMAND,
2185 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2186 if (sc->xl_type == XL_TYPE_905B) {
2187 CSR_WRITE_2(sc, XL_COMMAND,
2188 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2190 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2191 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2193 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2194 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2197 * Write an arbitrary byte to the TX_STATUS register
2198 * to clear this interrupt/error and advance to the next.
2200 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2207 struct xl_softc *sc = arg;
2208 struct ifnet *ifp = sc->xl_ifp;
2213 #ifdef DEVICE_POLLING
2214 if (ifp->if_capenable & IFCAP_POLLING) {
2220 while ((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS &&
2222 CSR_WRITE_2(sc, XL_COMMAND,
2223 XL_CMD_INTR_ACK|(status & XL_INTRS));
2225 if (status & XL_STAT_UP_COMPLETE) {
2228 curpkts = ifp->if_ipackets;
2230 if (curpkts == ifp->if_ipackets) {
2231 while (xl_rx_resync(sc))
2236 if (status & XL_STAT_DOWN_COMPLETE) {
2237 if (sc->xl_type == XL_TYPE_905B)
2243 if (status & XL_STAT_TX_COMPLETE) {
2248 if (status & XL_STAT_ADFAIL) {
2253 if (status & XL_STAT_STATSOFLOW) {
2254 sc->xl_stats_no_timeout = 1;
2255 xl_stats_update_locked(sc);
2256 sc->xl_stats_no_timeout = 0;
2260 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
2261 if (sc->xl_type == XL_TYPE_905B)
2262 xl_start_90xB_locked(ifp);
2264 xl_start_locked(ifp);
2270 #ifdef DEVICE_POLLING
2272 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2274 struct xl_softc *sc = ifp->if_softc;
2278 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2279 rx_npkts = xl_poll_locked(ifp, cmd, count);
2285 xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
2287 struct xl_softc *sc = ifp->if_softc;
2292 sc->rxcycles = count;
2293 rx_npkts = xl_rxeof(sc);
2294 if (sc->xl_type == XL_TYPE_905B)
2299 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
2300 if (sc->xl_type == XL_TYPE_905B)
2301 xl_start_90xB_locked(ifp);
2303 xl_start_locked(ifp);
2306 if (cmd == POLL_AND_CHECK_STATUS) {
2309 status = CSR_READ_2(sc, XL_STATUS);
2310 if (status & XL_INTRS && status != 0xFFFF) {
2311 CSR_WRITE_2(sc, XL_COMMAND,
2312 XL_CMD_INTR_ACK|(status & XL_INTRS));
2314 if (status & XL_STAT_TX_COMPLETE) {
2319 if (status & XL_STAT_ADFAIL) {
2324 if (status & XL_STAT_STATSOFLOW) {
2325 sc->xl_stats_no_timeout = 1;
2326 xl_stats_update_locked(sc);
2327 sc->xl_stats_no_timeout = 0;
2333 #endif /* DEVICE_POLLING */
2336 * XXX: This is an entry point for callout which needs to take the lock.
2339 xl_stats_update(void *xsc)
2341 struct xl_softc *sc = xsc;
2345 if (xl_watchdog(sc) == EJUSTRETURN)
2348 xl_stats_update_locked(sc);
2352 xl_stats_update_locked(struct xl_softc *sc)
2354 struct ifnet *ifp = sc->xl_ifp;
2355 struct xl_stats xl_stats;
2358 struct mii_data *mii = NULL;
2362 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2364 if (sc->xl_miibus != NULL)
2365 mii = device_get_softc(sc->xl_miibus);
2367 p = (u_int8_t *)&xl_stats;
2369 /* Read all the stats registers. */
2372 for (i = 0; i < 16; i++)
2373 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2375 ifp->if_ierrors += xl_stats.xl_rx_overrun;
2377 ifp->if_collisions += xl_stats.xl_tx_multi_collision +
2378 xl_stats.xl_tx_single_collision + xl_stats.xl_tx_late_collision;
2381 * Boomerang and cyclone chips have an extra stats counter
2382 * in window 4 (BadSSD). We have to read this too in order
2383 * to clear out all the stats registers and avoid a statsoflow
2387 CSR_READ_1(sc, XL_W4_BADSSD);
2389 if ((mii != NULL) && (!sc->xl_stats_no_timeout))
2394 if (!sc->xl_stats_no_timeout)
2395 callout_reset(&sc->xl_stat_callout, hz, xl_stats_update, sc);
2399 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2400 * pointers to the fragment pointers.
2403 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf **m_head)
2406 struct ifnet *ifp = sc->xl_ifp;
2407 int error, i, nseg, total_len;
2412 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, *m_head,
2413 sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT);
2415 if (error && error != EFBIG) {
2416 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2421 * Handle special case: we used up all 63 fragments,
2422 * but we have more mbufs left in the chain. Copy the
2423 * data into an mbuf cluster. Note that we don't
2424 * bother clearing the values in the other fragment
2425 * pointers/counters; it wouldn't gain us anything,
2426 * and would waste cycles.
2429 m_new = m_collapse(*m_head, M_DONTWAIT, XL_MAXFRAGS);
2430 if (m_new == NULL) {
2437 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map,
2438 *m_head, sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT);
2442 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2447 KASSERT(nseg <= XL_MAXFRAGS,
2448 ("%s: too many DMA segments (%d)", __func__, nseg));
2456 for (i = 0; i < nseg; i++) {
2457 KASSERT(sc->xl_cdata.xl_tx_segs[i].ds_len <= MCLBYTES,
2458 ("segment size too large"));
2459 c->xl_ptr->xl_frag[i].xl_addr =
2460 htole32(sc->xl_cdata.xl_tx_segs[i].ds_addr);
2461 c->xl_ptr->xl_frag[i].xl_len =
2462 htole32(sc->xl_cdata.xl_tx_segs[i].ds_len);
2463 total_len += sc->xl_cdata.xl_tx_segs[i].ds_len;
2465 c->xl_ptr->xl_frag[nseg - 1].xl_len =
2466 htole32(sc->xl_cdata.xl_tx_segs[nseg - 1].ds_len | XL_LAST_FRAG);
2467 c->xl_ptr->xl_status = htole32(total_len);
2468 c->xl_ptr->xl_next = 0;
2470 if (sc->xl_type == XL_TYPE_905B) {
2471 status = XL_TXSTAT_RND_DEFEAT;
2473 #ifndef XL905B_TXCSUM_BROKEN
2474 if ((*m_head)->m_pkthdr.csum_flags) {
2475 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP)
2476 status |= XL_TXSTAT_IPCKSUM;
2477 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP)
2478 status |= XL_TXSTAT_TCPCKSUM;
2479 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP)
2480 status |= XL_TXSTAT_UDPCKSUM;
2483 c->xl_ptr->xl_status = htole32(status);
2486 c->xl_mbuf = *m_head;
2487 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2492 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2493 * to the mbuf data regions directly in the transmit lists. We also save a
2494 * copy of the pointers since the transmit list fragment pointers are
2495 * physical addresses.
2499 xl_start(struct ifnet *ifp)
2501 struct xl_softc *sc = ifp->if_softc;
2505 if (sc->xl_type == XL_TYPE_905B)
2506 xl_start_90xB_locked(ifp);
2508 xl_start_locked(ifp);
2514 xl_start_locked(struct ifnet *ifp)
2516 struct xl_softc *sc = ifp->if_softc;
2517 struct mbuf *m_head = NULL;
2518 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2524 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2528 * Check for an available queue slot. If there are none,
2531 if (sc->xl_cdata.xl_tx_free == NULL) {
2534 if (sc->xl_cdata.xl_tx_free == NULL) {
2535 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2540 start_tx = sc->xl_cdata.xl_tx_free;
2542 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2543 sc->xl_cdata.xl_tx_free != NULL;) {
2544 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2548 /* Pick a descriptor off the free list. */
2549 cur_tx = sc->xl_cdata.xl_tx_free;
2551 /* Pack the data into the descriptor. */
2552 error = xl_encap(sc, cur_tx, &m_head);
2556 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2557 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2561 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2562 cur_tx->xl_next = NULL;
2564 /* Chain it together. */
2566 prev->xl_next = cur_tx;
2567 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2572 * If there's a BPF listener, bounce a copy of this frame
2575 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2579 * If there are no packets queued, bail.
2585 * Place the request for the upload interrupt
2586 * in the last descriptor in the chain. This way, if
2587 * we're chaining several packets at once, we'll only
2588 * get an interrupt once for the whole chain rather than
2589 * once for each packet.
2591 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2593 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2594 BUS_DMASYNC_PREWRITE);
2597 * Queue the packets. If the TX channel is clear, update
2598 * the downlist pointer register.
2600 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2603 if (sc->xl_cdata.xl_tx_head != NULL) {
2604 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2605 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2606 htole32(start_tx->xl_phys);
2607 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status;
2608 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status =
2609 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR);
2610 sc->xl_cdata.xl_tx_tail = cur_tx;
2612 sc->xl_cdata.xl_tx_head = start_tx;
2613 sc->xl_cdata.xl_tx_tail = cur_tx;
2615 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2616 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2618 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2623 * Set a timeout in case the chip goes out to lunch.
2625 sc->xl_wdog_timer = 5;
2628 * XXX Under certain conditions, usually on slower machines
2629 * where interrupts may be dropped, it's possible for the
2630 * adapter to chew up all the buffers in the receive ring
2631 * and stall, without us being able to do anything about it.
2632 * To guard against this, we need to make a pass over the
2633 * RX queue to make sure there aren't any packets pending.
2634 * Doing it here means we can flush the receive ring at the
2635 * same time the chip is DMAing the transmit descriptors we
2638 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm)
2639 * nature of their chips in all their marketing literature;
2640 * we may as well take advantage of it. :)
2642 taskqueue_enqueue(taskqueue_swi, &sc->xl_task);
2646 xl_start_90xB_locked(struct ifnet *ifp)
2648 struct xl_softc *sc = ifp->if_softc;
2649 struct mbuf *m_head = NULL;
2650 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2655 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2659 idx = sc->xl_cdata.xl_tx_prod;
2660 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2662 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2663 sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL;) {
2664 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2665 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2669 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2673 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2675 /* Pack the data into the descriptor. */
2676 error = xl_encap(sc, cur_tx, &m_head);
2680 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2681 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2685 /* Chain it together. */
2687 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2691 * If there's a BPF listener, bounce a copy of this frame
2694 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2696 XL_INC(idx, XL_TX_LIST_CNT);
2697 sc->xl_cdata.xl_tx_cnt++;
2701 * If there are no packets queued, bail.
2707 * Place the request for the upload interrupt
2708 * in the last descriptor in the chain. This way, if
2709 * we're chaining several packets at once, we'll only
2710 * get an interrupt once for the whole chain rather than
2711 * once for each packet.
2713 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2715 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2716 BUS_DMASYNC_PREWRITE);
2718 /* Start transmission */
2719 sc->xl_cdata.xl_tx_prod = idx;
2720 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys);
2723 * Set a timeout in case the chip goes out to lunch.
2725 sc->xl_wdog_timer = 5;
2731 struct xl_softc *sc = xsc;
2739 xl_init_locked(struct xl_softc *sc)
2741 struct ifnet *ifp = sc->xl_ifp;
2743 u_int16_t rxfilt = 0;
2744 struct mii_data *mii = NULL;
2749 * Cancel pending I/O and free all RX/TX buffers.
2753 if (sc->xl_miibus == NULL) {
2754 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2757 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2761 if (sc->xl_miibus != NULL)
2762 mii = device_get_softc(sc->xl_miibus);
2764 /* Init our MAC address */
2766 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2767 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2768 IF_LLADDR(sc->xl_ifp)[i]);
2771 /* Clear the station mask. */
2772 for (i = 0; i < 3; i++)
2773 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2775 /* Reset TX and RX. */
2776 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2778 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2781 /* Init circular RX list. */
2782 error = xl_list_rx_init(sc);
2784 device_printf(sc->xl_dev, "initialization of the rx ring failed (%d)\n",
2790 /* Init TX descriptors. */
2791 if (sc->xl_type == XL_TYPE_905B)
2792 error = xl_list_tx_init_90xB(sc);
2794 error = xl_list_tx_init(sc);
2796 device_printf(sc->xl_dev, "initialization of the tx ring failed (%d)\n",
2803 * Set the TX freethresh value.
2804 * Note that this has no effect on 3c905B "cyclone"
2805 * cards but is required for 3c900/3c905 "boomerang"
2806 * cards in order to enable the download engine.
2808 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2810 /* Set the TX start threshold for best performance. */
2811 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2814 * If this is a 3c905B, also set the tx reclaim threshold.
2815 * This helps cut down on the number of tx reclaim errors
2816 * that could happen on a busy network. The chip multiplies
2817 * the register value by 16 to obtain the actual threshold
2818 * in bytes, so we divide by 16 when setting the value here.
2819 * The existing threshold value can be examined by reading
2820 * the register at offset 9 in window 5.
2822 if (sc->xl_type == XL_TYPE_905B) {
2823 CSR_WRITE_2(sc, XL_COMMAND,
2824 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2827 /* Set RX filter bits. */
2829 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
2831 /* Set the individual bit to receive frames for this host only. */
2832 rxfilt |= XL_RXFILTER_INDIVIDUAL;
2834 /* If we want promiscuous mode, set the allframes bit. */
2835 if (ifp->if_flags & IFF_PROMISC) {
2836 rxfilt |= XL_RXFILTER_ALLFRAMES;
2837 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2839 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
2840 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2844 * Set capture broadcast bit to capture broadcast frames.
2846 if (ifp->if_flags & IFF_BROADCAST) {
2847 rxfilt |= XL_RXFILTER_BROADCAST;
2848 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2850 rxfilt &= ~XL_RXFILTER_BROADCAST;
2851 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2855 * Program the multicast filter, if necessary.
2857 if (sc->xl_type == XL_TYPE_905B)
2858 xl_setmulti_hash(sc);
2863 * Load the address of the RX list. We have to
2864 * stall the upload engine before we can manipulate
2865 * the uplist pointer register, then unstall it when
2866 * we're finished. We also have to wait for the
2867 * stall command to complete before proceeding.
2868 * Note that we have to do this after any RX resets
2869 * have completed since the uplist register is cleared
2872 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2874 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2875 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2878 if (sc->xl_type == XL_TYPE_905B) {
2879 /* Set polling interval */
2880 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2881 /* Load the address of the TX list */
2882 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2884 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2885 sc->xl_cdata.xl_tx_chain[0].xl_phys);
2886 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2891 * If the coax transceiver is on, make sure to enable
2892 * the DC-DC converter.
2895 if (sc->xl_xcvr == XL_XCVR_COAX)
2896 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2898 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2901 * increase packet size to allow reception of 802.1q or ISL packets.
2902 * For the 3c90x chip, set the 'allow large packets' bit in the MAC
2903 * control register. For 3c90xB/C chips, use the RX packet size
2907 if (sc->xl_type == XL_TYPE_905B)
2908 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2911 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2912 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK;
2913 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
2916 /* Clear out the stats counters. */
2917 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2918 sc->xl_stats_no_timeout = 1;
2919 xl_stats_update_locked(sc);
2920 sc->xl_stats_no_timeout = 0;
2922 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2923 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2926 * Enable interrupts.
2928 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2929 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
2930 #ifdef DEVICE_POLLING
2931 /* Disable interrupts if we are polling. */
2932 if (ifp->if_capenable & IFCAP_POLLING)
2933 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
2936 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2937 if (sc->xl_flags & XL_FLAG_FUNCREG)
2938 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
2940 /* Set the RX early threshold */
2941 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2942 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2944 /* Enable receiver and transmitter. */
2945 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2947 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2950 /* XXX Downcall to miibus. */
2954 /* Select window 7 for normal operations. */
2957 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2958 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2960 sc->xl_wdog_timer = 0;
2961 callout_reset(&sc->xl_stat_callout, hz, xl_stats_update, sc);
2965 * Set media options.
2968 xl_ifmedia_upd(struct ifnet *ifp)
2970 struct xl_softc *sc = ifp->if_softc;
2971 struct ifmedia *ifm = NULL;
2972 struct mii_data *mii = NULL;
2976 if (sc->xl_miibus != NULL)
2977 mii = device_get_softc(sc->xl_miibus);
2981 ifm = &mii->mii_media;
2983 switch (IFM_SUBTYPE(ifm->ifm_media)) {
2988 xl_setmode(sc, ifm->ifm_media);
2993 if (sc->xl_media & XL_MEDIAOPT_MII ||
2994 sc->xl_media & XL_MEDIAOPT_BTX ||
2995 sc->xl_media & XL_MEDIAOPT_BT4) {
2998 xl_setmode(sc, ifm->ifm_media);
3007 * Report current media status.
3010 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3012 struct xl_softc *sc = ifp->if_softc;
3014 u_int16_t status = 0;
3015 struct mii_data *mii = NULL;
3019 if (sc->xl_miibus != NULL)
3020 mii = device_get_softc(sc->xl_miibus);
3023 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3026 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
3027 icfg >>= XL_ICFG_CONNECTOR_BITS;
3029 ifmr->ifm_active = IFM_ETHER;
3030 ifmr->ifm_status = IFM_AVALID;
3032 if ((status & XL_MEDIASTAT_CARRIER) == 0)
3033 ifmr->ifm_status |= IFM_ACTIVE;
3037 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
3038 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3039 ifmr->ifm_active |= IFM_FDX;
3041 ifmr->ifm_active |= IFM_HDX;
3044 if (sc->xl_type == XL_TYPE_905B &&
3045 sc->xl_media == XL_MEDIAOPT_10FL) {
3046 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
3047 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3048 ifmr->ifm_active |= IFM_FDX;
3050 ifmr->ifm_active |= IFM_HDX;
3052 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
3055 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
3058 * XXX MII and BTX/AUTO should be separate cases.
3061 case XL_XCVR_100BTX:
3066 ifmr->ifm_active = mii->mii_media_active;
3067 ifmr->ifm_status = mii->mii_media_status;
3070 case XL_XCVR_100BFX:
3071 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
3074 if_printf(ifp, "unknown XCVR type: %d\n", icfg);
3082 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3084 struct xl_softc *sc = ifp->if_softc;
3085 struct ifreq *ifr = (struct ifreq *) data;
3087 struct mii_data *mii = NULL;
3095 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
3096 if (ifp->if_flags & IFF_UP) {
3097 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3098 ifp->if_flags & IFF_PROMISC &&
3099 !(sc->xl_if_flags & IFF_PROMISC)) {
3100 rxfilt |= XL_RXFILTER_ALLFRAMES;
3101 CSR_WRITE_2(sc, XL_COMMAND,
3102 XL_CMD_RX_SET_FILT|rxfilt);
3104 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3105 !(ifp->if_flags & IFF_PROMISC) &&
3106 sc->xl_if_flags & IFF_PROMISC) {
3107 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
3108 CSR_WRITE_2(sc, XL_COMMAND,
3109 XL_CMD_RX_SET_FILT|rxfilt);
3112 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
3116 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3119 sc->xl_if_flags = ifp->if_flags;
3125 /* XXX Downcall from if_addmulti() possibly with locks held. */
3127 if (sc->xl_type == XL_TYPE_905B)
3128 xl_setmulti_hash(sc);
3136 if (sc->xl_miibus != NULL)
3137 mii = device_get_softc(sc->xl_miibus);
3139 error = ifmedia_ioctl(ifp, ifr,
3140 &sc->ifmedia, command);
3142 error = ifmedia_ioctl(ifp, ifr,
3143 &mii->mii_media, command);
3146 #ifdef DEVICE_POLLING
3147 if (ifr->ifr_reqcap & IFCAP_POLLING &&
3148 !(ifp->if_capenable & IFCAP_POLLING)) {
3149 error = ether_poll_register(xl_poll, ifp);
3153 /* Disable interrupts */
3154 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3155 ifp->if_capenable |= IFCAP_POLLING;
3159 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
3160 ifp->if_capenable & IFCAP_POLLING) {
3161 error = ether_poll_deregister(ifp);
3162 /* Enable interrupts. */
3164 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
3165 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
3166 if (sc->xl_flags & XL_FLAG_FUNCREG)
3167 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle,
3169 ifp->if_capenable &= ~IFCAP_POLLING;
3173 #endif /* DEVICE_POLLING */
3175 ifp->if_capenable = ifr->ifr_reqcap;
3176 if (ifp->if_capenable & IFCAP_TXCSUM)
3177 ifp->if_hwassist = XL905B_CSUM_FEATURES;
3179 ifp->if_hwassist = 0;
3183 error = ether_ioctl(ifp, command, data);
3191 xl_watchdog(struct xl_softc *sc)
3193 struct ifnet *ifp = sc->xl_ifp;
3194 u_int16_t status = 0;
3199 if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0)
3205 if (sc->xl_type == XL_TYPE_905B) {
3207 if (sc->xl_cdata.xl_tx_cnt == 0)
3211 if (sc->xl_cdata.xl_tx_head == NULL)
3215 device_printf(sc->xl_dev,
3216 "watchdog timeout (missed Tx interrupts) -- recovering\n");
3222 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3223 device_printf(sc->xl_dev, "watchdog timeout\n");
3225 if (status & XL_MEDIASTAT_CARRIER)
3226 device_printf(sc->xl_dev,
3227 "no carrier - transceiver cable problem?\n");
3232 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
3233 if (sc->xl_type == XL_TYPE_905B)
3234 xl_start_90xB_locked(ifp);
3236 xl_start_locked(ifp);
3239 return (EJUSTRETURN);
3243 * Stop the adapter and free any mbufs allocated to the
3247 xl_stop(struct xl_softc *sc)
3250 struct ifnet *ifp = sc->xl_ifp;
3254 sc->xl_wdog_timer = 0;
3256 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3257 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3258 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3259 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3261 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3262 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3266 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3268 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3272 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3273 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3274 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3275 if (sc->xl_flags & XL_FLAG_FUNCREG)
3276 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3278 /* Stop the stats updater. */
3279 callout_stop(&sc->xl_stat_callout);
3282 * Free data in the RX lists.
3284 for (i = 0; i < XL_RX_LIST_CNT; i++) {
3285 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3286 bus_dmamap_unload(sc->xl_mtag,
3287 sc->xl_cdata.xl_rx_chain[i].xl_map);
3288 bus_dmamap_destroy(sc->xl_mtag,
3289 sc->xl_cdata.xl_rx_chain[i].xl_map);
3290 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3291 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3294 if (sc->xl_ldata.xl_rx_list != NULL)
3295 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3297 * Free the TX list buffers.
3299 for (i = 0; i < XL_TX_LIST_CNT; i++) {
3300 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3301 bus_dmamap_unload(sc->xl_mtag,
3302 sc->xl_cdata.xl_tx_chain[i].xl_map);
3303 bus_dmamap_destroy(sc->xl_mtag,
3304 sc->xl_cdata.xl_tx_chain[i].xl_map);
3305 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3306 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3309 if (sc->xl_ldata.xl_tx_list != NULL)
3310 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3312 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3316 * Stop all chip I/O so that the kernel's probe routines don't
3317 * get confused by errant DMAs when rebooting.
3320 xl_shutdown(device_t dev)
3322 struct xl_softc *sc;
3324 sc = device_get_softc(dev);
3335 xl_suspend(device_t dev)
3337 struct xl_softc *sc;
3339 sc = device_get_softc(dev);
3349 xl_resume(device_t dev)
3351 struct xl_softc *sc;
3354 sc = device_get_softc(dev);
3360 if (ifp->if_flags & IFF_UP)