sys/i386/cpufreq/hwpstate.c

   1 /*-
   2  * Copyright (c) 2005 Nate Lawson
   3  * Copyright (c) 2004 Colin Percival
   4  * Copyright (c) 2004-2005 Bruno Durcot
   5  * Copyright (c) 2004 FUKUDA Nobuhiko
   6  * Copyright (c) 2009 Michael Reifenberger
   7  * Copyright (c) 2009 Norikatsu Shigemura
   8  * Copyright (c) 2008-2009 Gen Otsuji
   9  *
  10  * This code is depending on kern_cpu.c, est.c, powernow.c, p4tcc.c, smist.c
  11  * in various parts. The authors of these files are Nate Lawson,
  12  * Colin Percival, Bruno Durcot, and FUKUDA Nobuhiko.
  13  * This code contains patches by Michael Reifenberger and Norikatsu Shigemura.
  14  * Thank you.
  15  *
  16  * Redistribution and use in source and binary forms, with or without
  17  * modification, are permitted providing that the following conditions
  18  * are met:
  19  * 1. Redistributions of source code must retain the above copyright
  20  *    notice, this list of conditions and the following disclaimer.
  21  * 2. Redistributions in binary form must reproduce the above copyright
  22  *    notice, this list of conditions and the following disclaimer in the
  23  *    documentation and/or other materials provided with the distribution.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR
  26  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  27  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  28  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  29  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  30  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  31  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  32  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  33  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  34  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35  * POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 /*
  39  * For more info:
  40  * BIOS and Kernel Developer's Guide(BKDG) for AMD Family 10h Processors
  41  * 31116 Rev 3.20  February 04, 2009
  42  * BIOS and Kernel Developer's Guide(BKDG) for AMD Family 11h Processors
  43  * 41256 Rev 3.00 - July 07, 2008
  44  */
  45
  46 #include <sys/cdefs.h>
  47 __FBSDID("$FreeBSD$");
  48
  49 #include <sys/param.h>
  50 #include <sys/bus.h>
  51 #include <sys/cpu.h>
  52 #include <sys/kernel.h>
  53 #include <sys/module.h>
  54 #include <sys/malloc.h>
  55 #include <sys/proc.h>
  56 #include <sys/pcpu.h>
  57 #include <sys/smp.h>
  58 #include <sys/sched.h>
  59
  60 #include <machine/md_var.h>
  61 #include <machine/cputypes.h>
  62 #include <machine/specialreg.h>
  63
  64 #include <contrib/dev/acpica/include/acpi.h>
  65
  66 #include <dev/acpica/acpivar.h>
  67
  68 #include "acpi_if.h"
  69 #include "cpufreq_if.h"
  70
  71 #define MSR_AMD_10H_11H_LIMIT   0xc0010061
  72 #define MSR_AMD_10H_11H_CONTROL 0xc0010062
  73 #define MSR_AMD_10H_11H_STATUS  0xc0010063
  74 #define MSR_AMD_10H_11H_CONFIG  0xc0010064
  75
  76 #define AMD_10H_11H_MAX_STATES  16
  77
  78 /* for MSR_AMD_10H_11H_LIMIT C001_0061 */
  79 #define AMD_10H_11H_GET_PSTATE_MAX_VAL(msr)     (((msr) >> 4) & 0x7)
  80 #define AMD_10H_11H_GET_PSTATE_LIMIT(msr)       (((msr)) & 0x7)
  81 /* for MSR_AMD_10H_11H_CONFIG 10h:C001_0064:68 / 11h:C001_0064:6B */
  82 #define AMD_10H_11H_CUR_VID(msr)                (((msr) >> 9) & 0x7F)
  83 #define AMD_10H_11H_CUR_DID(msr)                (((msr) >> 6) & 0x07)
  84 #define AMD_10H_11H_CUR_FID(msr)                ((msr) & 0x3F)
  85
  86 #if defined(__amd64__)
  87 #define CPU_FAMILY(id)  AMD64_CPU_FAMILY(id)
  88 #elif defined(__i386__)
  89 #define CPU_FAMILY(id)  I386_CPU_FAMILY(id)
  90 #endif
  91
  92 #define HWPSTATE_DEBUG(dev, msg...)                     \
  93         do{                                             \
  94                 if(hwpstate_verbose)                    \
  95                         device_printf(dev, msg);        \
  96         }while(0)
  97
  98 struct hwpstate_setting {
  99         int     freq;           /* CPU clock in Mhz or 100ths of a percent. */
 100         int     volts;          /* Voltage in mV. */
 101         int     power;          /* Power consumed in mW. */
 102         int     lat;            /* Transition latency in us. */
 103         int     pstate_id;      /* P-State id */
 104 };
 105
 106 struct hwpstate_softc {
 107         device_t                dev;
 108         struct hwpstate_setting hwpstate_settings[AMD_10H_11H_MAX_STATES];
 109         int                     cfnum;
 110 };
 111
 112 static void     hwpstate_identify(driver_t *driver, device_t parent);
 113 static int      hwpstate_probe(device_t dev);
 114 static int      hwpstate_attach(device_t dev);
 115 static int      hwpstate_detach(device_t dev);
 116 static int      hwpstate_set(device_t dev, const struct cf_setting *cf);
 117 static int      hwpstate_get(device_t dev, struct cf_setting *cf);
 118 static int      hwpstate_settings(device_t dev, struct cf_setting *sets, int *count);
 119 static int      hwpstate_type(device_t dev, int *type);
 120 static int      hwpstate_shutdown(device_t dev);
 121 static int      hwpstate_features(driver_t *driver, u_int *features);
 122 static int      hwpstate_get_info_from_acpi_perf(device_t dev, device_t perf_dev);
 123 static int      hwpstate_get_info_from_msr(device_t dev);
 124 static int      hwpstate_goto_pstate(device_t dev, int pstate_id);
 125
 126 static int      hwpstate_verbose = 0;
 127 SYSCTL_INT(_debug, OID_AUTO, hwpstate_verbose, CTLFLAG_RDTUN,
 128        &hwpstate_verbose, 0, "Debug hwpstate");
 129
 130 static device_method_t hwpstate_methods[] = {
 131         /* Device interface */
 132         DEVMETHOD(device_identify,      hwpstate_identify),
 133         DEVMETHOD(device_probe,         hwpstate_probe),
 134         DEVMETHOD(device_attach,        hwpstate_attach),
 135         DEVMETHOD(device_detach,        hwpstate_detach),
 136         DEVMETHOD(device_shutdown,      hwpstate_shutdown),
 137
 138         /* cpufreq interface */
 139         DEVMETHOD(cpufreq_drv_set,      hwpstate_set),
 140         DEVMETHOD(cpufreq_drv_get,      hwpstate_get),
 141         DEVMETHOD(cpufreq_drv_settings, hwpstate_settings),
 142         DEVMETHOD(cpufreq_drv_type,     hwpstate_type),
 143
 144         /* ACPI interface */
 145         DEVMETHOD(acpi_get_features,    hwpstate_features),
 146
 147         {0, 0}
 148 };
 149
 150 static devclass_t hwpstate_devclass;
 151 static driver_t hwpstate_driver = {
 152         "hwpstate",
 153         hwpstate_methods,
 154         sizeof(struct hwpstate_softc),
 155 };
 156
 157 DRIVER_MODULE(hwpstate, cpu, hwpstate_driver, hwpstate_devclass, 0, 0);
 158
 159 /*
 160  * Go to Px-state on all cpus considering the limit.
 161  */
 162 static int
 163 hwpstate_goto_pstate(device_t dev, int pstate)
 164 {
 165         struct pcpu *pc;
 166         int i;
 167         uint64_t msr;
 168         int j;
 169         int limit;
 170         int id = pstate;
 171         int error;
 172
 173         /* get the current pstate limit */
 174         msr = rdmsr(MSR_AMD_10H_11H_LIMIT);
 175         limit = AMD_10H_11H_GET_PSTATE_LIMIT(msr);
 176         if(limit > id)
 177                 id = limit;
 178
 179         error = 0;
 180         /*
 181          * We are going to the same Px-state on all cpus.
 182          */
 183         for (i = 0; i < mp_ncpus; i++) {
 184                 /* Find each cpu. */
 185                 pc = pcpu_find(i);
 186                 if (pc == NULL)
 187                         return (ENXIO);
 188                 thread_lock(curthread);
 189                 /* Bind to each cpu. */
 190                 sched_bind(curthread, pc->pc_cpuid);
 191                 thread_unlock(curthread);
 192                 HWPSTATE_DEBUG(dev, "setting P%d-state on cpu%d\n",
 193                         id, PCPU_GET(cpuid));
 194                 /* Go To Px-state */
 195                 wrmsr(MSR_AMD_10H_11H_CONTROL, id);
 196                 /* wait loop (100*100 usec is enough ?) */
 197                 for(j = 0; j < 100; j++){
 198                         msr = rdmsr(MSR_AMD_10H_11H_STATUS);
 199                         if(msr == id){
 200                                 break;
 201                         }
 202                         DELAY(100);
 203                 }
 204                 /* get the result. not assure msr=id */
 205                 msr = rdmsr(MSR_AMD_10H_11H_STATUS);
 206                 HWPSTATE_DEBUG(dev, "result  P%d-state on cpu%d\n",
 207                     (int)msr, PCPU_GET(cpuid));
 208                 if (msr != id) {
 209                         HWPSTATE_DEBUG(dev, "error: loop is not enough.\n");
 210                         error = ENXIO;
 211                 }
 212                 thread_lock(curthread);
 213                 sched_unbind(curthread);
 214                 thread_unlock(curthread);
 215         }
 216         return (error);
 217 }
 218
 219 static int
 220 hwpstate_set(device_t dev, const struct cf_setting *cf)
 221 {
 222         struct hwpstate_softc *sc;
 223         struct hwpstate_setting *set;
 224         int i;
 225
 226         if (cf == NULL)
 227                 return (EINVAL);
 228         sc = device_get_softc(dev);
 229         set = sc->hwpstate_settings;
 230         for (i = 0; i < sc->cfnum; i++)
 231                 if (CPUFREQ_CMP(cf->freq, set[i].freq))
 232                         break;
 233         if (i == sc->cfnum)
 234                 return (EINVAL);
 235
 236         return (hwpstate_goto_pstate(dev, set[i].pstate_id));
 237 }
 238
 239 static int
 240 hwpstate_get(device_t dev, struct cf_setting *cf)
 241 {
 242         struct hwpstate_softc *sc;
 243         struct hwpstate_setting set;
 244         uint64_t msr;
 245
 246         sc = device_get_softc(dev);
 247         if (cf == NULL)
 248                 return (EINVAL);
 249         msr = rdmsr(MSR_AMD_10H_11H_STATUS);
 250         if(msr >= sc->cfnum)
 251                 return (EINVAL);
 252         set = sc->hwpstate_settings[msr];
 253
 254         cf->freq = set.freq;
 255         cf->volts = set.volts;
 256         cf->power = set.power;
 257         cf->lat = set.lat;
 258         cf->dev = dev;
 259         return (0);
 260 }
 261
 262 static int
 263 hwpstate_settings(device_t dev, struct cf_setting *sets, int *count)
 264 {
 265         struct hwpstate_softc *sc;
 266         struct hwpstate_setting set;
 267         int i;
 268
 269         if (sets == NULL || count == NULL)
 270                 return (EINVAL);
 271         sc = device_get_softc(dev);
 272         if (*count < sc->cfnum)
 273                 return (E2BIG);
 274         for (i = 0; i < sc->cfnum; i++, sets++) {
 275                 set = sc->hwpstate_settings[i];
 276                 sets->freq = set.freq;
 277                 sets->volts = set.volts;
 278                 sets->power = set.power;
 279                 sets->lat = set.lat;
 280                 sets->dev = dev;
 281         }
 282         *count = sc->cfnum;
 283
 284         return (0);
 285 }
 286
 287 static int
 288 hwpstate_type(device_t dev, int *type)
 289 {
 290
 291         if (type == NULL)
 292                 return (EINVAL);
 293
 294         *type = CPUFREQ_TYPE_ABSOLUTE;
 295         return (0);
 296 }
 297
 298 static void
 299 hwpstate_identify(driver_t *driver, device_t parent)
 300 {
 301
 302         if (device_find_child(parent, "hwpstate", -1) != NULL)
 303                 return;
 304
 305         if (cpu_vendor_id != CPU_VENDOR_AMD || CPU_FAMILY(cpu_id) < 0x10)
 306                 return;
 307
 308         /*
 309          * Check if hardware pstate enable bit is set.
 310          */
 311         if ((amd_pminfo & AMDPM_HW_PSTATE) == 0) {
 312                 HWPSTATE_DEBUG(parent, "hwpstate enable bit is not set.\n");
 313                 return;
 314         }
 315
 316         if (resource_disabled("hwpstate", 0))
 317                 return;
 318
 319         if (BUS_ADD_CHILD(parent, 10, "hwpstate", -1) == NULL)
 320                 device_printf(parent, "hwpstate: add child failed\n");
 321 }
 322
 323 static int
 324 hwpstate_probe(device_t dev)
 325 {
 326         struct hwpstate_softc *sc;
 327         device_t perf_dev;
 328         uint64_t msr;
 329         int error, type;
 330
 331         /*
 332          * Only hwpstate0.
 333          * It goes well with acpi_throttle.
 334          */
 335         if (device_get_unit(dev) != 0)
 336                 return (ENXIO);
 337
 338         sc = device_get_softc(dev);
 339         sc->dev = dev;
 340
 341         /*
 342          * Check if acpi_perf has INFO only flag.
 343          */
 344         perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
 345         error = TRUE;
 346         if (perf_dev && device_is_attached(perf_dev)) {
 347                 error = CPUFREQ_DRV_TYPE(perf_dev, &type);
 348                 if (error == 0) {
 349                         if ((type & CPUFREQ_FLAG_INFO_ONLY) == 0) {
 350                                 /*
 351                                  * If acpi_perf doesn't have INFO_ONLY flag,
 352                                  * it will take care of pstate transitions.
 353                                  */
 354                                 HWPSTATE_DEBUG(dev, "acpi_perf will take care of pstate transitions.\n");
 355                                 return (ENXIO);
 356                         } else {
 357                                 /*
 358                                  * If acpi_perf has INFO_ONLY flag, (_PCT has FFixedHW)
 359                                  * we can get _PSS info from acpi_perf
 360                                  * without going into ACPI.
 361                                  */
 362                                 HWPSTATE_DEBUG(dev, "going to fetch info from acpi_perf\n");
 363                                 error = hwpstate_get_info_from_acpi_perf(dev, perf_dev);
 364                         }
 365                 }
 366         }
 367
 368         if (error == 0) {
 369                 /*
 370                  * Now we get _PSS info from acpi_perf without error.
 371                  * Let's check it.
 372                  */
 373                 msr = rdmsr(MSR_AMD_10H_11H_LIMIT);
 374                 if (sc->cfnum != 1 + AMD_10H_11H_GET_PSTATE_MAX_VAL(msr)) {
 375                         HWPSTATE_DEBUG(dev, "msr and acpi _PSS count mismatch.\n");
 376                         error = TRUE;
 377                 }
 378         }
 379
 380         /*
 381          * If we cannot get info from acpi_perf,
 382          * Let's get info from MSRs.
 383          */
 384         if (error)
 385                 error = hwpstate_get_info_from_msr(dev);
 386         if (error)
 387                 return (error);
 388
 389         device_set_desc(dev, "Cool`n'Quiet 2.0");
 390         return (0);
 391 }
 392
 393 static int
 394 hwpstate_attach(device_t dev)
 395 {
 396
 397         return (cpufreq_register(dev));
 398 }
 399
 400 static int
 401 hwpstate_get_info_from_msr(device_t dev)
 402 {
 403         struct hwpstate_softc *sc;
 404         struct hwpstate_setting *hwpstate_set;
 405         uint64_t msr;
 406         int family, i, fid, did;
 407
 408         family = CPU_FAMILY(cpu_id);
 409         sc = device_get_softc(dev);
 410         /* Get pstate count */
 411         msr = rdmsr(MSR_AMD_10H_11H_LIMIT);
 412         sc->cfnum = 1 + AMD_10H_11H_GET_PSTATE_MAX_VAL(msr);
 413         hwpstate_set = sc->hwpstate_settings;
 414         for (i = 0; i < sc->cfnum; i++) {
 415                 msr = rdmsr(MSR_AMD_10H_11H_CONFIG + i);
 416                 if ((msr & ((uint64_t)1 << 63)) != ((uint64_t)1 << 63)) {
 417                         HWPSTATE_DEBUG(dev, "msr is not valid.\n");
 418                         return (ENXIO);
 419                 }
 420                 did = AMD_10H_11H_CUR_DID(msr);
 421                 fid = AMD_10H_11H_CUR_FID(msr);
 422                 switch(family) {
 423                 case 0x11:
 424                         /* fid/did to frequency */
 425                         hwpstate_set[i].freq = 100 * (fid + 0x08) / (1 << did);
 426                         break;
 427                 case 0x10:
 428                         /* fid/did to frequency */
 429                         hwpstate_set[i].freq = 100 * (fid + 0x10) / (1 << did);
 430                         break;
 431                 default:
 432                         HWPSTATE_DEBUG(dev, "get_info_from_msr: AMD family %d CPU's are not implemented yet. sorry.\n", family);
 433                         return (ENXIO);
 434                         break;
 435                 }
 436                 hwpstate_set[i].pstate_id = i;
 437                 /* There was volts calculation, but deleted it. */
 438                 hwpstate_set[i].volts = CPUFREQ_VAL_UNKNOWN;
 439                 hwpstate_set[i].power = CPUFREQ_VAL_UNKNOWN;
 440                 hwpstate_set[i].lat = CPUFREQ_VAL_UNKNOWN;
 441         }
 442         return (0);
 443 }
 444
 445 static int
 446 hwpstate_get_info_from_acpi_perf(device_t dev, device_t perf_dev)
 447 {
 448         struct hwpstate_softc *sc;
 449         struct cf_setting *perf_set;
 450         struct hwpstate_setting *hwpstate_set;
 451         int count, error, i;
 452
 453         perf_set = malloc(MAX_SETTINGS * sizeof(*perf_set), M_TEMP, M_NOWAIT);
 454         if (perf_set == NULL) {
 455                 HWPSTATE_DEBUG(dev, "nomem\n");
 456                 return (ENOMEM);
 457         }
 458         /*
 459          * Fetch settings from acpi_perf.
 460          * Now it is attached, and has info only flag.
 461          */
 462         count = MAX_SETTINGS;
 463         error = CPUFREQ_DRV_SETTINGS(perf_dev, perf_set, &count);
 464         if (error) {
 465                 HWPSTATE_DEBUG(dev, "error: CPUFREQ_DRV_SETTINGS.\n");
 466                 goto out;
 467         }
 468         sc = device_get_softc(dev);
 469         sc->cfnum = count;
 470         hwpstate_set = sc->hwpstate_settings;
 471         for (i = 0; i < count; i++) {
 472                 if (i == perf_set[i].spec[0]) {
 473                         hwpstate_set[i].pstate_id = i;
 474                         hwpstate_set[i].freq = perf_set[i].freq;
 475                         hwpstate_set[i].volts = perf_set[i].volts;
 476                         hwpstate_set[i].power = perf_set[i].power;
 477                         hwpstate_set[i].lat = perf_set[i].lat;
 478                 } else {
 479                         HWPSTATE_DEBUG(dev, "ACPI _PSS object mismatch.\n");
 480                         error = ENXIO;
 481                         goto out;
 482                 }
 483         }
 484 out:
 485         if (perf_set)
 486                 free(perf_set, M_TEMP);
 487         return (error);
 488 }
 489
 490 static int
 491 hwpstate_detach(device_t dev)
 492 {
 493
 494         hwpstate_goto_pstate(dev, 0);
 495         return (cpufreq_unregister(dev));
 496 }
 497
 498 static int
 499 hwpstate_shutdown(device_t dev)
 500 {
 501
 502         /* hwpstate_goto_pstate(dev, 0); */
 503         return (0);
 504 }
 505
 506 static int
 507 hwpstate_features(driver_t *driver, u_int *features)
 508 {
 509
 510         /* Notify the ACPI CPU that we support direct access to MSRs */
 511         *features = ACPI_CAP_PERF_MSRS;
 512         return (0);
 513 }