1 /* $NetBSD: cpu.h,v 1.70 2003/01/17 23:36:08 thorpej Exp $ */
4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved.
7 * This code is derived from software contributed to Berkeley by
8 * Ralph Campbell and Rick Macklem.
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20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
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39 * @(#)cpu.h 8.4 (Berkeley) 1/4/94
46 * Exported definitions unique to NetBSD/mips cpu support.
57 u_int16_t tlb_nentries;
58 u_int8_t icache_virtual;
71 /* TODO: Merge above structure with NetBSD's below. */
75 struct schedstate_percpu ci_schedstate; /* scheduler state */
77 u_long ci_cpu_freq; /* CPU frequency */
78 u_long ci_cycles_per_hz; /* CPU freq / hz */
79 u_long ci_divisor_delay; /* for delay/DELAY */
80 u_long ci_divisor_recip; /* scaled reciprocal of previous;
82 #if defined(DIAGNOSTIC) || defined(LOCKDEBUG)
83 u_long ci_spin_locks; /* # of spin locks held */
84 u_long ci_simple_locks; /* # of simple locks held */
89 * To implement a more accurate microtime using the CP0 COUNT register
90 * we need to divide that register by the number of cycles per MHz.
93 * DIV and DIVU are expensive on MIPS (eg 75 clocks on the R4000). MULT
94 * and MULTU are only 12 clocks on the same CPU.
96 * The strategy we use is to calculate the reciprical of cycles per MHz,
97 * scaled by 1<<32. Then we can simply issue a MULTU and pluck of the
98 * HI register and have the results of the division.
100 #define MIPS_SET_CI_RECIPRICAL(cpu) \
102 KASSERT((cpu)->ci_divisor_delay != 0, ("divisor delay")); \
103 (cpu)->ci_divisor_recip = 0x100000000ULL / (cpu)->ci_divisor_delay; \
106 #define MIPS_COUNT_TO_MHZ(cpu, count, res) \
107 __asm __volatile ("multu %1,%2 ; mfhi %0" \
108 : "=r"((res)) : "r"((count)), "r"((cpu)->ci_divisor_recip))
111 extern struct cpu_info cpu_info_store;
114 #define curcpu() (&cpu_info_store)
115 #define cpu_number() (0)
120 #endif /* _CPUINFO_H_ */