1 /* $NetBSD: cpuregs.h,v 1.70 2006/05/15 02:26:54 simonb Exp $ */
4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved.
7 * This code is derived from software contributed to Berkeley by
8 * Ralph Campbell and Rick Macklem.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * @(#)machConst.h 8.1 (Berkeley) 6/10/93
38 * Machine dependent constants.
40 * Copyright (C) 1989 Digital Equipment Corporation.
41 * Permission to use, copy, modify, and distribute this software and
42 * its documentation for any purpose and without fee is hereby granted,
43 * provided that the above copyright notice appears in all copies.
44 * Digital Equipment Corporation makes no representations about the
45 * suitability of this software for any purpose. It is provided "as is"
46 * without express or implied warranty.
48 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h,
49 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL)
50 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h,
51 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL)
52 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h,
53 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL)
58 #ifndef _MIPS_CPUREGS_H_
59 #define _MIPS_CPUREGS_H_
61 #include <sys/cdefs.h> /* For __CONCAT() */
63 #if defined(_KERNEL_OPT)
64 #include "opt_cputype.h"
69 * 32-bit mips CPUS partition their 32-bit address space into four segments:
71 * kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped
72 * kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped
73 * kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped
74 * kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped
76 * mips1 physical memory is limited to 512Mbytes, which is
77 * doubly mapped in kseg0 (cached) and kseg1 (uncached.)
78 * Caching of mapped addresses is controlled by bits in the TLB entry.
81 #define MIPS_KUSEG_START 0x0
82 #define MIPS_KSEG0_START 0x80000000
83 #define MIPS_KSEG0_END 0x9fffffff
84 #define MIPS_KSEG1_START 0xa0000000
85 #define MIPS_KSEG1_END 0xbfffffff
86 #define MIPS_KSSEG_START 0xc0000000
87 #define MIPS_KSSEG_END 0xdfffffff
88 #define MIPS_KSEG2_START MIPS_KSSEG_START
89 #define MIPS_KSEG2_END MIPS_KSSEG_END
90 #define MIPS_KSEG3_START 0xe0000000
91 #define MIPS_KSEG3_END 0xffffffff
92 #define MIPS_MAX_MEM_ADDR 0xbe000000
93 #define MIPS_RESERVED_ADDR 0xbfc80000
95 /* Map virtual address to index in mips3 r4k virtually-indexed cache */
96 #define MIPS3_VA_TO_CINDEX(x) \
97 ((unsigned)(x) & 0xffffff | MIPS_KSEG0_START)
99 #define MIPS_PHYS_TO_XKPHYS(cca,x) \
100 ((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x))
101 #define MIPS_XKPHYS_TO_PHYS(x) ((x) & 0x0effffffffffffffULL)
103 /* CPU dependent mtc0 hazard hook */
105 #define COP0_SYNC nop; nop; nop; nop; nop;
107 #define COP0_SYNC /* nothing */
109 #define COP0_HAZARD_FPUENABLE nop; nop; nop; nop;
112 * The bits in the cause register.
114 * Bits common to r3000 and r4000:
116 * MIPS_CR_BR_DELAY Exception happened in branch delay slot.
117 * MIPS_CR_COP_ERR Coprocessor error.
118 * MIPS_CR_IP Interrupt pending bits defined below.
119 * (same meaning as in CAUSE register).
120 * MIPS_CR_EXC_CODE The exception type (see exception codes below).
123 * r3k has 4 bits of execption type, r4k has 5 bits.
125 #define MIPS_CR_BR_DELAY 0x80000000
126 #define MIPS_CR_COP_ERR 0x30000000
127 #define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */
128 #define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */
129 #define MIPS_CR_IP 0x0000FF00
130 #define MIPS_CR_EXC_CODE_SHIFT 2
133 * The bits in the status register. All bits are active when set to 1.
135 * R3000 status register fields:
136 * MIPS_SR_COP_USABILITY Control the usability of the four coprocessors.
137 * MIPS_SR_TS TLB shutdown.
139 * MIPS_SR_INT_IE Master (current) interrupt enable bit.
142 * r3k has cache control is via frobbing SR register bits, whereas the
143 * r4k cache control is via explicit instructions.
144 * r3k has a 3-entry stack of kernel/user bits, whereas the
145 * r4k has kernel/supervisor/user.
147 #define MIPS_SR_COP_USABILITY 0xf0000000
148 #define MIPS_SR_COP_0_BIT 0x10000000
149 #define MIPS_SR_COP_1_BIT 0x20000000
150 #define MIPS_SR_COP_2_BIT 0x40000000
152 /* r4k and r3k differences, see below */
154 #define MIPS_SR_MX 0x01000000 /* MIPS64 */
155 #define MIPS_SR_PX 0x00800000 /* MIPS64 */
156 #define MIPS_SR_BEV 0x00400000 /* Use boot exception vector */
157 #define MIPS_SR_TS 0x00200000
158 #define MIPS_SR_DE 0x00010000
160 #define MIPS_SR_INT_IE 0x00000001
161 /*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */
162 /*#define MIPS_SR_INT_MASK 0x0000ff00*/
165 * The R2000/R3000-specific status register bit definitions.
166 * all bits are active when set to 1.
168 * MIPS_SR_PARITY_ERR Parity error.
169 * MIPS_SR_CACHE_MISS Most recent D-cache load resulted in a miss.
170 * MIPS_SR_PARITY_ZERO Zero replaces outgoing parity bits.
171 * MIPS_SR_SWAP_CACHES Swap I-cache and D-cache.
172 * MIPS_SR_ISOL_CACHES Isolate D-cache from main memory.
173 * Interrupt enable bits defined below.
174 * MIPS_SR_KU_OLD Old kernel/user mode bit. 1 => user mode.
175 * MIPS_SR_INT_ENA_OLD Old interrupt enable bit.
176 * MIPS_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode.
177 * MIPS_SR_INT_ENA_PREV Previous interrupt enable bit.
178 * MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode.
181 #define MIPS1_PARITY_ERR 0x00100000
182 #define MIPS1_CACHE_MISS 0x00080000
183 #define MIPS1_PARITY_ZERO 0x00040000
184 #define MIPS1_SWAP_CACHES 0x00020000
185 #define MIPS1_ISOL_CACHES 0x00010000
187 #define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/
188 #define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/
189 #define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/
190 #define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/
191 #define MIPS1_SR_KU_CUR 0x00000002 /* current KU */
193 /* backwards compatibility */
194 #define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR
195 #define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS
196 #define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO
197 #define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES
198 #define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES
200 #define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD
201 #define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD
202 #define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV
203 #define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR
204 #define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV
207 * R4000 status register bit definitons,
208 * where different from r2000/r3000.
210 #define MIPS3_SR_XX 0x80000000
211 #define MIPS3_SR_RP 0x08000000
212 #define MIPS3_SR_FR 0x04000000
213 #define MIPS3_SR_RE 0x02000000
215 #define MIPS3_SR_DIAG_DL 0x01000000 /* QED 52xx */
216 #define MIPS3_SR_DIAG_IL 0x00800000 /* QED 52xx */
217 #define MIPS3_SR_SR 0x00100000
218 #define MIPS3_SR_NMI 0x00080000 /* MIPS32/64 */
219 #define MIPS3_SR_DIAG_CH 0x00040000
220 #define MIPS3_SR_DIAG_CE 0x00020000
221 #define MIPS3_SR_DIAG_PE 0x00010000
222 #define MIPS3_SR_EIE 0x00010000 /* TX79/R5900 */
223 #define MIPS3_SR_KX 0x00000080
224 #define MIPS3_SR_SX 0x00000040
225 #define MIPS3_SR_UX 0x00000020
226 #define MIPS3_SR_KSU_MASK 0x00000018
227 #define MIPS3_SR_KSU_USER 0x00000010
228 #define MIPS3_SR_KSU_SUPER 0x00000008
229 #define MIPS3_SR_KSU_KERNEL 0x00000000
230 #define MIPS3_SR_ERL 0x00000004
231 #define MIPS3_SR_EXL 0x00000002
234 #undef MIPS_SR_INT_IE
235 #define MIPS_SR_INT_IE 0x00010001 /* XXX */
239 * These definitions are for MIPS32 processors.
241 #define MIPS32_SR_RP 0x08000000 /* reduced power mode */
242 #define MIPS32_SR_FR 0x04000000 /* 64-bit capable fpu */
243 #define MIPS32_SR_RE 0x02000000 /* reverse user endian */
244 #define MIPS32_SR_MX 0x01000000 /* MIPS64 */
245 #define MIPS32_SR_PX 0x00800000 /* MIPS64 */
246 #define MIPS32_SR_BEV 0x00400000 /* Use boot exception vector */
247 #define MIPS32_SR_TS 0x00200000 /* TLB multiple match */
248 #define MIPS32_SR_SOFT_RESET 0x00100000 /* soft reset occurred */
249 #define MIPS32_SR_NMI 0x00080000 /* NMI occurred */
250 #define MIPS32_SR_INT_MASK 0x0000ff00
251 #define MIPS32_SR_KX 0x00000080 /* MIPS64 */
252 #define MIPS32_SR_SX 0x00000040 /* MIPS64 */
253 #define MIPS32_SR_UX 0x00000020 /* MIPS64 */
254 #define MIPS32_SR_KSU_MASK 0x00000018 /* privilege mode */
255 #define MIPS32_SR_KSU_USER 0x00000010
256 #define MIPS32_SR_KSU_SUPER 0x00000008
257 #define MIPS32_SR_KSU_KERNEL 0x00000000
258 #define MIPS32_SR_ERL 0x00000004 /* error level */
259 #define MIPS32_SR_EXL 0x00000002 /* exception level */
261 #define MIPS_SR_SOFT_RESET MIPS3_SR_SR
262 #define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH
263 #define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE
264 #define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE
265 #define MIPS_SR_KX MIPS3_SR_KX
266 #define MIPS_SR_SX MIPS3_SR_SX
267 #define MIPS_SR_UX MIPS3_SR_UX
269 #define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK
270 #define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER
271 #define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER
272 #define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL
273 #define MIPS_SR_ERL MIPS3_SR_ERL
274 #define MIPS_SR_EXL MIPS3_SR_EXL
278 * The interrupt masks.
279 * If a bit in the mask is 1 then the interrupt is enabled (or pending).
281 #define MIPS_INT_MASK 0xff00
282 #define MIPS_INT_MASK_5 0x8000
283 #define MIPS_INT_MASK_4 0x4000
284 #define MIPS_INT_MASK_3 0x2000
285 #define MIPS_INT_MASK_2 0x1000
286 #define MIPS_INT_MASK_1 0x0800
287 #define MIPS_INT_MASK_0 0x0400
288 #define MIPS_HARD_INT_MASK 0xfc00
289 #define MIPS_SOFT_INT_MASK_1 0x0200
290 #define MIPS_SOFT_INT_MASK_0 0x0100
293 * mips3 CPUs have on-chip timer at INT_MASK_5. Each platform can
294 * choose to enable this interrupt.
296 #if defined(MIPS3_ENABLE_CLOCK_INTR)
297 #define MIPS3_INT_MASK MIPS_INT_MASK
298 #define MIPS3_HARD_INT_MASK MIPS_HARD_INT_MASK
300 #define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5)
301 #define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5)
305 * The bits in the context register.
307 #define MIPS1_CNTXT_PTE_BASE 0xFFE00000
308 #define MIPS1_CNTXT_BAD_VPN 0x001FFFFC
310 #define MIPS3_CNTXT_PTE_BASE 0xFF800000
311 #define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0
314 * Location of MIPS32 exception vectors. Most are multiplexed in
315 * the sense that further decoding is necessary (e.g. reading the
316 * CAUSE register or NMI bits in STATUS).
317 * Most interrupts go via the
318 * The INT vector is dedicated for hardware interrupts; it is
319 * only referenced if the IV bit in CAUSE is set to 1.
321 #define MIPS_VEC_RESET 0xBFC00000 /* Hard, soft, or NMI */
322 #define MIPS_VEC_EJTAG 0xBFC00480
323 #define MIPS_VEC_TLB 0x80000000
324 #define MIPS_VEC_XTLB 0x80000080
325 #define MIPS_VEC_CACHE 0x80000100
326 #define MIPS_VEC_GENERIC 0x80000180 /* Most exceptions */
327 #define MIPS_VEC_INTERRUPT 0x80000200
330 * The bits in the MIPS3 config register.
332 * bit 0..5: R/W, Bit 6..31: R/O
335 /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
336 #define MIPS3_CONFIG_K0_MASK 0x00000007
339 * R/W Update on Store Conditional
340 * 0: Store Conditional uses coherency algorithm specified by TLB
341 * 1: Store Conditional uses cacheable coherent update on write
343 #define MIPS3_CONFIG_CU 0x00000008
345 #define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */
346 #define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */
347 #define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \
348 (((config) & (bit)) ? 32 : 16)
350 #define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */
351 #define MIPS3_CONFIG_DC_SHIFT 6
352 #define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */
353 #define MIPS3_CONFIG_IC_SHIFT 9
354 #define MIPS3_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */
356 /* Cache size mode indication: available only on Vr41xx CPUs */
357 #define MIPS3_CONFIG_CS 0x00001000
358 #define MIPS3_CONFIG_C_4100BASE 0x0400 /* base is 2^10 if CS=1 */
359 #define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift) \
360 ((base) << (((config) & (mask)) >> (shift)))
362 /* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */
363 #define MIPS3_CONFIG_SE 0x00001000
365 /* Block ordering: 0: sequential, 1: sub-block */
366 #define MIPS3_CONFIG_EB 0x00002000
368 /* ECC mode - 0: ECC mode, 1: parity mode */
369 #define MIPS3_CONFIG_EM 0x00004000
371 /* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */
372 #define MIPS3_CONFIG_BE 0x00008000
374 /* Dirty Shared coherency state - 0: enabled, 1: disabled */
375 #define MIPS3_CONFIG_SM 0x00010000
377 /* Secondary Cache - 0: present, 1: not present */
378 #define MIPS3_CONFIG_SC 0x00020000
380 /* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */
381 #define MIPS3_CONFIG_EW_MASK 0x000c0000
382 #define MIPS3_CONFIG_EW_SHIFT 18
384 /* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */
385 #define MIPS3_CONFIG_SW 0x00100000
387 /* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */
388 #define MIPS3_CONFIG_SS 0x00200000
390 /* Secondary Cache line size */
391 #define MIPS3_CONFIG_SB_MASK 0x00c00000
392 #define MIPS3_CONFIG_SB_SHIFT 22
393 #define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \
394 (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT))
396 /* Write back data rate */
397 #define MIPS3_CONFIG_EP_MASK 0x0f000000
398 #define MIPS3_CONFIG_EP_SHIFT 24
400 /* System clock ratio - this value is CPU dependent */
401 #define MIPS3_CONFIG_EC_MASK 0x70000000
402 #define MIPS3_CONFIG_EC_SHIFT 28
404 /* Master-Checker Mode - 1: enabled */
405 #define MIPS3_CONFIG_CM 0x80000000
408 * The bits in the MIPS4 config register.
411 /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
412 #define MIPS4_CONFIG_K0_MASK MIPS3_CONFIG_K0_MASK
413 #define MIPS4_CONFIG_DN_MASK 0x00000018 /* Device number */
414 #define MIPS4_CONFIG_CT 0x00000020 /* CohPrcReqTar */
415 #define MIPS4_CONFIG_PE 0x00000040 /* PreElmReq */
416 #define MIPS4_CONFIG_PM_MASK 0x00000180 /* PreReqMax */
417 #define MIPS4_CONFIG_EC_MASK 0x00001e00 /* SysClkDiv */
418 #define MIPS4_CONFIG_SB 0x00002000 /* SCBlkSize */
419 #define MIPS4_CONFIG_SK 0x00004000 /* SCColEn */
420 #define MIPS4_CONFIG_BE 0x00008000 /* MemEnd */
421 #define MIPS4_CONFIG_SS_MASK 0x00070000 /* SCSize */
422 #define MIPS4_CONFIG_SC_MASK 0x00380000 /* SCClkDiv */
423 #define MIPS4_CONFIG_RESERVED 0x03c00000 /* Reserved wired 0 */
424 #define MIPS4_CONFIG_DC_MASK 0x1c000000 /* Primary D-Cache size */
425 #define MIPS4_CONFIG_IC_MASK 0xe0000000 /* Primary I-Cache size */
427 #define MIPS4_CONFIG_DC_SHIFT 26
428 #define MIPS4_CONFIG_IC_SHIFT 29
430 #define MIPS4_CONFIG_CACHE_SIZE(config, mask, base, shift) \
431 ((base) << (((config) & (mask)) >> (shift)))
433 #define MIPS4_CONFIG_CACHE_L2_LSIZE(config) \
434 (((config) & MIPS4_CONFIG_SB) ? 128 : 64)
437 * Location of exception vectors.
439 * Common vectors: reset and UTLB miss.
441 #define MIPS_RESET_EXC_VEC 0xBFC00000
442 #define MIPS_UTLB_MISS_EXC_VEC 0x80000000
445 * MIPS-1 general exception vector (everything else)
447 #define MIPS1_GEN_EXC_VEC 0x80000080
450 * MIPS-III exception vectors
452 #define MIPS3_XTLB_MISS_EXC_VEC 0x80000080
453 #define MIPS3_CACHE_ERR_EXC_VEC 0x80000100
454 #define MIPS3_GEN_EXC_VEC 0x80000180
457 * TX79 (R5900) exception vectors
459 #define MIPS_R5900_COUNTER_EXC_VEC 0x80000080
460 #define MIPS_R5900_DEBUG_EXC_VEC 0x80000100
463 * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector.
465 #define MIPS3_INTR_EXC_VEC 0x80000200
468 * Coprocessor 0 registers:
470 * v--- width for mips I,III,32,64
471 * (3=32bit, 6=64bit, i=impl dep)
472 * 0 MIPS_COP_0_TLB_INDEX 3333 TLB Index.
473 * 1 MIPS_COP_0_TLB_RANDOM 3333 TLB Random.
474 * 2 MIPS_COP_0_TLB_LOW 3... r3k TLB entry low.
475 * 2 MIPS_COP_0_TLB_LO0 .636 r4k TLB entry low.
476 * 3 MIPS_COP_0_TLB_LO1 .636 r4k TLB entry low, extended.
477 * 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context.
478 * 5 MIPS_COP_0_TLB_PG_MASK .333 TLB Page Mask register.
479 * 6 MIPS_COP_0_TLB_WIRED .333 Wired TLB number.
480 * 8 MIPS_COP_0_BAD_VADDR 3636 Bad virtual address.
481 * 9 MIPS_COP_0_COUNT .333 Count register.
482 * 10 MIPS_COP_0_TLB_HI 3636 TLB entry high.
483 * 11 MIPS_COP_0_COMPARE .333 Compare (against Count).
484 * 12 MIPS_COP_0_STATUS 3333 Status register.
485 * 13 MIPS_COP_0_CAUSE 3333 Exception cause register.
486 * 14 MIPS_COP_0_EXC_PC 3636 Exception PC.
487 * 15 MIPS_COP_0_PRID 3333 Processor revision identifier.
488 * 16 MIPS_COP_0_CONFIG 3333 Configuration register.
489 * 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1.
490 * 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2.
491 * 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3.
492 * 17 MIPS_COP_0_LLADDR .336 Load Linked Address.
493 * 18 MIPS_COP_0_WATCH_LO .336 WatchLo register.
494 * 19 MIPS_COP_0_WATCH_HI .333 WatchHi register.
495 * 20 MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register.
496 * 23 MIPS_COP_0_DEBUG .... Debug JTAG register.
497 * 24 MIPS_COP_0_DEPC .... DEPC JTAG register.
498 * 25 MIPS_COP_0_PERFCNT ..36 Performance Counter register.
499 * 26 MIPS_COP_0_ECC .3ii ECC / Error Control register.
500 * 27 MIPS_COP_0_CACHE_ERR .3ii Cache Error register.
501 * 28/0 MIPS_COP_0_TAG_LO .3ii Cache TagLo register (instr).
502 * 28/1 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (instr).
503 * 28/2 MIPS_COP_0_TAG_LO ..ii Cache TagLo register (data).
504 * 28/3 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (data).
505 * 29/0 MIPS_COP_0_TAG_HI .3ii Cache TagHi register (instr).
506 * 29/1 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (instr).
507 * 29/2 MIPS_COP_0_TAG_HI ..ii Cache TagHi register (data).
508 * 29/3 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (data).
509 * 30 MIPS_COP_0_ERROR_PC .636 Error EPC register.
510 * 31 MIPS_COP_0_DESAVE .... DESAVE JTAG register.
513 /* Deal with inclusion from an assembly file. */
514 #if defined(_LOCORE) || defined(LOCORE)
521 #define MIPS_COP_0_TLB_INDEX _(0)
522 #define MIPS_COP_0_TLB_RANDOM _(1)
523 /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */
525 #define MIPS_COP_0_TLB_CONTEXT _(4)
526 /* $5 and $6 new with MIPS-III */
527 #define MIPS_COP_0_BAD_VADDR _(8)
528 #define MIPS_COP_0_TLB_HI _(10)
529 #define MIPS_COP_0_STATUS _(12)
530 #define MIPS_COP_0_CAUSE _(13)
531 #define MIPS_COP_0_EXC_PC _(14)
532 #define MIPS_COP_0_PRID _(15)
536 #define MIPS_COP_0_TLB_LOW _(2)
539 #define MIPS_COP_0_TLB_LO0 _(2)
540 #define MIPS_COP_0_TLB_LO1 _(3)
542 #define MIPS_COP_0_TLB_PG_MASK _(5)
543 #define MIPS_COP_0_TLB_WIRED _(6)
545 #define MIPS_COP_0_COUNT _(9)
546 #define MIPS_COP_0_COMPARE _(11)
548 #define MIPS_COP_0_CONFIG _(16)
549 #define MIPS_COP_0_LLADDR _(17)
550 #define MIPS_COP_0_WATCH_LO _(18)
551 #define MIPS_COP_0_WATCH_HI _(19)
552 #define MIPS_COP_0_TLB_XCONTEXT _(20)
553 #define MIPS_COP_0_ECC _(26)
554 #define MIPS_COP_0_CACHE_ERR _(27)
555 #define MIPS_COP_0_TAG_LO _(28)
556 #define MIPS_COP_0_TAG_HI _(29)
557 #define MIPS_COP_0_ERROR_PC _(30)
560 #define MIPS_COP_0_DEBUG _(23)
561 #define MIPS_COP_0_DEPC _(24)
562 #define MIPS_COP_0_PERFCNT _(25)
563 #define MIPS_COP_0_DATA_LO _(28)
564 #define MIPS_COP_0_DATA_HI _(29)
565 #define MIPS_COP_0_DESAVE _(31)
567 /* MIPS32 Config register definitions */
568 #define MIPS_MMU_NONE 0x00 /* No MMU present */
569 #define MIPS_MMU_TLB 0x01 /* Standard TLB */
570 #define MIPS_MMU_BAT 0x02 /* Standard BAT */
571 #define MIPS_MMU_FIXED 0x03 /* Standard fixed mapping */
573 #define MIPS_CONFIG0_MT_MASK 0x00000380 /* bits 9..7 MMU Type */
574 #define MIPS_CONFIG0_MT_SHIFT 7
575 #define MIPS_CONFIG0_BE 0x00008000 /* data is big-endian */
576 #define MIPS_CONFIG0_VI 0x00000004 /* instruction cache is virtual */
578 #define MIPS_CONFIG1_TLBSZ_MASK 0x7E000000 /* bits 30..25 # tlb entries minus one */
579 #define MIPS_CONFIG1_TLBSZ_SHIFT 25
580 #define MIPS_CONFIG1_IS_MASK 0x01C00000 /* bits 24..22 icache sets per way */
581 #define MIPS_CONFIG1_IS_SHIFT 22
582 #define MIPS_CONFIG1_IL_MASK 0x00380000 /* bits 21..19 icache line size */
583 #define MIPS_CONFIG1_IL_SHIFT 19
584 #define MIPS_CONFIG1_IA_MASK 0x00070000 /* bits 18..16 icache associativity */
585 #define MIPS_CONFIG1_IA_SHIFT 16
586 #define MIPS_CONFIG1_DS_MASK 0x0000E000 /* bits 15..13 dcache sets per way */
587 #define MIPS_CONFIG1_DS_SHIFT 13
588 #define MIPS_CONFIG1_DL_MASK 0x00001C00 /* bits 12..10 dcache line size */
589 #define MIPS_CONFIG1_DL_SHIFT 10
590 #define MIPS_CONFIG1_DA_MASK 0x00000380 /* bits 9.. 7 dcache associativity */
591 #define MIPS_CONFIG1_DA_SHIFT 7
592 #define MIPS_CONFIG1_LOWBITS 0x0000007F
593 #define MIPS_CONFIG1_C2 0x00000040 /* Coprocessor 2 implemented */
594 #define MIPS_CONFIG1_MD 0x00000020 /* MDMX ASE implemented (MIPS64) */
595 #define MIPS_CONFIG1_PC 0x00000010 /* Performance counters implemented */
596 #define MIPS_CONFIG1_WR 0x00000008 /* Watch registers implemented */
597 #define MIPS_CONFIG1_CA 0x00000004 /* MIPS16e ISA implemented */
598 #define MIPS_CONFIG1_EP 0x00000002 /* EJTAG implemented */
599 #define MIPS_CONFIG1_FP 0x00000001 /* FPU implemented */
602 * Values for the code field in a break instruction.
604 #define MIPS_BREAK_INSTR 0x0000000d
605 #define MIPS_BREAK_VAL_MASK 0x03ff0000
606 #define MIPS_BREAK_VAL_SHIFT 16
607 #define MIPS_BREAK_KDB_VAL 512
608 #define MIPS_BREAK_SSTEP_VAL 513
609 #define MIPS_BREAK_BRKPT_VAL 514
610 #define MIPS_BREAK_SOVER_VAL 515
611 #define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \
612 (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT))
613 #define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \
614 (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT))
615 #define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \
616 (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT))
617 #define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \
618 (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT))
621 * Mininum and maximum cache sizes.
623 #define MIPS_MIN_CACHE_SIZE (16 * 1024)
624 #define MIPS_MAX_CACHE_SIZE (256 * 1024)
625 #define MIPS3_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */
628 * The floating point version and status registers.
630 #define MIPS_FPU_ID $0
631 #define MIPS_FPU_CSR $31
634 * The floating point coprocessor status register bits.
636 #define MIPS_FPU_ROUNDING_BITS 0x00000003
637 #define MIPS_FPU_ROUND_RN 0x00000000
638 #define MIPS_FPU_ROUND_RZ 0x00000001
639 #define MIPS_FPU_ROUND_RP 0x00000002
640 #define MIPS_FPU_ROUND_RM 0x00000003
641 #define MIPS_FPU_STICKY_BITS 0x0000007c
642 #define MIPS_FPU_STICKY_INEXACT 0x00000004
643 #define MIPS_FPU_STICKY_UNDERFLOW 0x00000008
644 #define MIPS_FPU_STICKY_OVERFLOW 0x00000010
645 #define MIPS_FPU_STICKY_DIV0 0x00000020
646 #define MIPS_FPU_STICKY_INVALID 0x00000040
647 #define MIPS_FPU_ENABLE_BITS 0x00000f80
648 #define MIPS_FPU_ENABLE_INEXACT 0x00000080
649 #define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100
650 #define MIPS_FPU_ENABLE_OVERFLOW 0x00000200
651 #define MIPS_FPU_ENABLE_DIV0 0x00000400
652 #define MIPS_FPU_ENABLE_INVALID 0x00000800
653 #define MIPS_FPU_EXCEPTION_BITS 0x0003f000
654 #define MIPS_FPU_EXCEPTION_INEXACT 0x00001000
655 #define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000
656 #define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000
657 #define MIPS_FPU_EXCEPTION_DIV0 0x00008000
658 #define MIPS_FPU_EXCEPTION_INVALID 0x00010000
659 #define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000
660 #define MIPS_FPU_COND_BIT 0x00800000
661 #define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */
662 #define MIPS1_FPC_MBZ_BITS 0xff7c0000
663 #define MIPS3_FPC_MBZ_BITS 0xfe7c0000
667 * Constants to determine if have a floating point instruction.
669 #define MIPS_OPCODE_SHIFT 26
670 #define MIPS_OPCODE_C1 0x11
674 * The low part of the TLB entry.
676 #define MIPS1_TLB_PFN 0xfffff000
677 #define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800
678 #define MIPS1_TLB_DIRTY_BIT 0x00000400
679 #define MIPS1_TLB_VALID_BIT 0x00000200
680 #define MIPS1_TLB_GLOBAL_BIT 0x00000100
682 #define MIPS3_TLB_PFN 0x3fffffc0
683 #define MIPS3_TLB_ATTR_MASK 0x00000038
684 #define MIPS3_TLB_ATTR_SHIFT 3
685 #define MIPS3_TLB_DIRTY_BIT 0x00000004
686 #define MIPS3_TLB_VALID_BIT 0x00000002
687 #define MIPS3_TLB_GLOBAL_BIT 0x00000001
689 #define MIPS1_TLB_PHYS_PAGE_SHIFT 12
690 #define MIPS3_TLB_PHYS_PAGE_SHIFT 6
691 #define MIPS1_TLB_PF_NUM MIPS1_TLB_PFN
692 #define MIPS3_TLB_PF_NUM MIPS3_TLB_PFN
693 #define MIPS1_TLB_MOD_BIT MIPS1_TLB_DIRTY_BIT
694 #define MIPS3_TLB_MOD_BIT MIPS3_TLB_DIRTY_BIT
697 * MIPS3_TLB_ATTR values - coherency algorithm:
698 * 0: cacheable, noncoherent, write-through, no write allocate
699 * 1: cacheable, noncoherent, write-through, write allocate
701 * 3: cacheable, noncoherent, write-back (noncoherent)
702 * 4: cacheable, coherent, write-back, exclusive (exclusive)
703 * 5: cacheable, coherent, write-back, exclusive on write (sharable)
704 * 6: cacheable, coherent, write-back, update on write (update)
705 * 7: uncached, accelerated (gather STORE operations)
707 #define MIPS3_TLB_ATTR_WT 0 /* IDT */
708 #define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */
709 #define MIPS3_TLB_ATTR_UNCACHED 2 /* R4000/R4400, IDT */
710 #define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */
711 #define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */
712 #define MIPS3_TLB_ATTR_WB_SHARABLE 5 /* R4000/R4400 */
713 #define MIPS3_TLB_ATTR_WB_UPDATE 6 /* R4000/R4400 */
714 #define MIPS4_TLB_ATTR_UNCACHED_ACCELERATED 7 /* R10000 */
718 * The high part of the TLB entry.
720 #define MIPS1_TLB_VPN 0xfffff000
721 #define MIPS1_TLB_PID 0x00000fc0
722 #define MIPS1_TLB_PID_SHIFT 6
724 #define MIPS3_TLB_VPN2 0xffffe000
725 #define MIPS3_TLB_ASID 0x000000ff
727 #define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN
728 #define MIPS3_TLB_VIRT_PAGE_NUM MIPS3_TLB_VPN2
729 #define MIPS3_TLB_PID MIPS3_TLB_ASID
730 #define MIPS_TLB_VIRT_PAGE_SHIFT 12
733 * r3000: shift count to put the index in the right spot.
735 #define MIPS1_TLB_INDEX_SHIFT 8
738 * The first TLB that write random hits.
740 #define MIPS1_TLB_FIRST_RAND_ENTRY 8
741 #define MIPS3_TLB_WIRED_UPAGES 1
744 * The number of process id entries.
746 #define MIPS1_TLB_NUM_PIDS 64
747 #define MIPS3_TLB_NUM_ASIDS 256
750 * Patch codes to hide CPU design differences between MIPS1 and MIPS3.
753 /* XXX simonb: this is before MIPS3_PLUS is defined (and is ugly!) */
755 #if !(defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \
756 && defined(MIPS1) /* XXX simonb must be neater! */
757 #define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT
758 #define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS
761 #if (defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \
762 && !defined(MIPS1) /* XXX simonb must be neater! */
763 #define MIPS_TLB_PID_SHIFT 0
764 #define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS
768 #if !defined(MIPS_TLB_PID_SHIFT)
769 #define MIPS_TLB_PID_SHIFT \
770 ((MIPS_HAS_R4K_MMU) ? 0 : MIPS1_TLB_PID_SHIFT)
772 #define MIPS_TLB_NUM_PIDS \
773 ((MIPS_HAS_R4K_MMU) ? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS)
777 * CPU processor revision IDs for company ID == 0 (non mips32/64 chips)
779 #define MIPS_R2000 0x01 /* MIPS R2000 ISA I */
780 #define MIPS_R3000 0x02 /* MIPS R3000 ISA I */
781 #define MIPS_R6000 0x03 /* MIPS R6000 ISA II */
782 #define MIPS_R4000 0x04 /* MIPS R4000/R4400 ISA III */
783 #define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivative ISA I */
784 #define MIPS_R6000A 0x06 /* MIPS R6000A ISA II */
785 #define MIPS_R3IDT 0x07 /* IDT R3041 or RC36100 ISA I */
786 #define MIPS_R10000 0x09 /* MIPS R10000 ISA IV */
787 #define MIPS_R4200 0x0a /* NEC VR4200 ISA III */
788 #define MIPS_R4300 0x0b /* NEC VR4300 ISA III */
789 #define MIPS_R4100 0x0c /* NEC VR4100 ISA III */
790 #define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */
791 #define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */
792 #define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
793 #define MIPS_RC32300 0x18 /* IDT RC32334,332,355 ISA 32 */
794 #define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */
795 #define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */
796 #define MIPS_R3SONY 0x21 /* Sony R3000 based ISA I */
797 #define MIPS_R4650 0x22 /* QED R4650 ISA III */
798 #define MIPS_TX3900 0x22 /* Toshiba TX39 family ISA I */
799 #define MIPS_R5000 0x23 /* MIPS R5000 ISA IV */
800 #define MIPS_R3NKK 0x23 /* NKK R3000 based ISA I */
801 #define MIPS_RC32364 0x26 /* IDT RC32364 ISA 32 */
802 #define MIPS_RM7000 0x27 /* QED RM7000 ISA IV */
803 #define MIPS_RM5200 0x28 /* QED RM5200s ISA IV */
804 #define MIPS_TX4900 0x2d /* Toshiba TX49 family ISA III */
805 #define MIPS_R5900 0x2e /* Toshiba R5900 (EECore) ISA --- */
806 #define MIPS_RC64470 0x30 /* IDT RC64474/RC64475 ISA III */
807 #define MIPS_TX7900 0x38 /* Toshiba TX79 ISA III+*/
808 #define MIPS_R5400 0x54 /* NEC VR5400 ISA IV */
809 #define MIPS_R5500 0x55 /* NEC VR5500 ISA IV */
812 * CPU revision IDs for some prehistoric processors.
816 #define MIPS_REV_R3000 0x20
817 #define MIPS_REV_R3000A 0x30
819 /* For MIPS_TX3900 */
820 #define MIPS_REV_TX3912 0x10
821 #define MIPS_REV_TX3922 0x30
822 #define MIPS_REV_TX3927 0x40
825 #define MIPS_REV_R4000_A 0x00
826 #define MIPS_REV_R4000_B 0x22
827 #define MIPS_REV_R4000_C 0x30
828 #define MIPS_REV_R4400_A 0x40
829 #define MIPS_REV_R4400_B 0x50
830 #define MIPS_REV_R4400_C 0x60
832 /* For MIPS_TX4900 */
833 #define MIPS_REV_TX4927 0x22
836 * CPU processor revision IDs for company ID == 1 (MIPS)
838 #define MIPS_4Kc 0x80 /* MIPS 4Kc ISA 32 */
839 #define MIPS_5Kc 0x81 /* MIPS 5Kc ISA 64 */
840 #define MIPS_20Kc 0x82 /* MIPS 20Kc ISA 64 */
841 #define MIPS_4Kmp 0x83 /* MIPS 4Km/4Kp ISA 32 */
842 #define MIPS_4KEc 0x84 /* MIPS 4KEc ISA 32 */
843 #define MIPS_4KEmp 0x85 /* MIPS 4KEm/4KEp ISA 32 */
844 #define MIPS_4KSc 0x86 /* MIPS 4KSc ISA 32 */
845 #define MIPS_M4K 0x87 /* MIPS M4K ISA 32 Rel 2 */
846 #define MIPS_25Kf 0x88 /* MIPS 25Kf ISA 64 */
847 #define MIPS_5KE 0x89 /* MIPS 5KE ISA 64 Rel 2 */
848 #define MIPS_4KEc_R2 0x90 /* MIPS 4KEc_R2 ISA 32 Rel 2 */
849 #define MIPS_4KEmp_R2 0x91 /* MIPS 4KEm/4KEp_R2 ISA 32 Rel 2 */
850 #define MIPS_4KSd 0x92 /* MIPS 4KSd ISA 32 Rel 2 */
853 * AMD (company ID 3) use the processor ID field to donote the CPU core
854 * revision and the company options field do donate the SOC chip type.
857 /* CPU processor revision IDs */
858 #define MIPS_AU_REV1 0x01 /* Alchemy Au1000 (Rev 1) ISA 32 */
859 #define MIPS_AU_REV2 0x02 /* Alchemy Au1000 (Rev 2) ISA 32 */
861 /* CPU company options IDs */
862 #define MIPS_AU1000 0x00
863 #define MIPS_AU1500 0x01
864 #define MIPS_AU1100 0x02
865 #define MIPS_AU1550 0x03
868 * CPU processor revision IDs for company ID == 4 (Broadcom)
870 #define MIPS_SB1 0x01 /* SiByte SB1 ISA 64 */
873 * CPU processor revision IDs for company ID == 5 (SandCraft)
875 #define MIPS_SR7100 0x04 /* SandCraft SR7100 ISA 64 */
878 * FPU processor revision ID
880 #define MIPS_SOFT 0x00 /* Software emulation ISA I */
881 #define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */
882 #define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */
883 #define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */
884 #define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */
885 #define MIPS_R4010 0x05 /* MIPS R4010 FPC ISA II */
886 #define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */
887 #define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */
889 #ifdef ENABLE_MIPS_TX3900
890 #include <mips/r3900regs.h>
893 #include <mips/r5900regs.h>
896 #include <mips/sb1regs.h>
899 #endif /* _MIPS_CPUREGS_H_ */