3 * Copyright (c) 2001 Opsycon AB (www.opsycon.se / www.opsycon.com)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Opsycon AB, Sweden.
16 * 4. The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
20 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * JNPR: psraccess.S,v 1.4.2.1 2007/09/10 10:36:50 girish
37 * Low level code to manage processor specific registers.
40 #include <machine/asm.h>
41 #include <machine/cpu.h>
42 #include <machine/regnum.h>
47 * FREEBSD_DEVELOPERS_FIXME
48 * Some MIPS CPU may need delays using nops between executing CP0 Instructions
50 #define MIPS_CPU_NOP_DELAY nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;
52 .set noreorder # Noreorder is default style!
55 * Set/clear software interrupt.
59 mfc0 v0, COP_0_CAUSE_REG # read cause register
61 or v0, v0, SOFT_INT_MASK_0 # set soft clock interrupt
62 mtc0 v0, COP_0_CAUSE_REG # save it
68 mfc0 v0, COP_0_CAUSE_REG # read cause register
70 and v0, v0, ~SOFT_INT_MASK_0 # clear soft clock interrupt
71 mtc0 v0, COP_0_CAUSE_REG # save it
77 mfc0 v0, COP_0_CAUSE_REG # read cause register
79 or v0, v0, SOFT_INT_MASK_1 # set soft net interrupt
80 mtc0 v0, COP_0_CAUSE_REG # save it
86 mfc0 v0, COP_0_CAUSE_REG # read cause register
88 and v0, v0, ~SOFT_INT_MASK_1 # clear soft net interrupt
89 mtc0 v0, COP_0_CAUSE_REG # save it
95 * Set/change interrupt priority routines.
96 * These routines return the previous state.
99 mfc0 t0,COP_0_STATUS_REG
100 and t1,t0,SR_INT_ENAB
106 mtc0 t0,COP_0_STATUS_REG
117 * Set/change interrupt priority routines.
118 * These routines return the previous state.
125 and v0, SR_INT_ENAB # return old interrupt enable bit
128 mfc0 v0, COP_0_STATUS_REG # read status register
130 or v1, v0, SR_INT_ENAB
131 mtc0 v1, COP_0_STATUS_REG # enable all interrupts
132 and v0, SR_INT_ENAB # return old interrupt enable
143 and v0, SR_INT_ENAB # return old interrupt enable bit
146 mfc0 v0, COP_0_STATUS_REG # read status register
148 and v1, v0, ~SR_INT_ENAB
149 mtc0 v1, COP_0_STATUS_REG # disable all interrupts
151 and v0, SR_INT_ENAB # return old interrupt enable
158 li t0, SR_INT_MASK # 1 means masked so invert.
159 not a0, a0 # 1 means masked so invert.
160 and a0, t0 # 1 means masked so invert.
161 mfc0 v0, COP_0_STATUS_REG
165 mtc0 v1, COP_0_STATUS_REG
175 mfc0 v0, COP_0_STATUS_REG
185 * u_int32_t mips_cp0_config1_read(void)
187 * Return the current value of the CP0 Config (Select 1) register.
189 LEAF(mips_cp0_config1_read)
192 mfc0 v0, COP_0_CONFIG, 1
196 END(mips_cp0_config1_read)