2 /* $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ */
5 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
6 * Copyright (C) 1995, 1996 TooLs GmbH.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by TooLs GmbH.
20 * 4. The name of TooLs GmbH may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * NOTICE: This is not a standalone file. to use it, #include it in
37 * your port's locore.S, like so:
39 * #include <powerpc/aim/trap_subr.S>
43 * Save/restore segment registers
45 #define RESTORE_SRS(pmap,sr) mtsr 0,sr; \
46 lwz sr,1*4(pmap); mtsr 1,sr; \
47 lwz sr,2*4(pmap); mtsr 2,sr; \
48 lwz sr,3*4(pmap); mtsr 3,sr; \
49 lwz sr,4*4(pmap); mtsr 4,sr; \
50 lwz sr,5*4(pmap); mtsr 5,sr; \
51 lwz sr,6*4(pmap); mtsr 6,sr; \
52 lwz sr,7*4(pmap); mtsr 7,sr; \
53 lwz sr,8*4(pmap); mtsr 8,sr; \
54 lwz sr,9*4(pmap); mtsr 9,sr; \
55 lwz sr,10*4(pmap); mtsr 10,sr; \
56 lwz sr,11*4(pmap); mtsr 11,sr; \
57 lwz sr,12*4(pmap); mtsr 12,sr; \
58 lwz sr,13*4(pmap); mtsr 13,sr; \
59 lwz sr,14*4(pmap); mtsr 14,sr; \
60 lwz sr,15*4(pmap); mtsr 15,sr; isync;
63 * User SRs are loaded through a pointer to the current pmap.
65 #define RESTORE_USER_SRS(pmap,sr) \
67 lwz pmap,PC_CURPMAP(pmap); \
68 lwzu sr,PM_SR(pmap); \
72 * Kernel SRs are loaded directly from kernel_pmap_
74 #define RESTORE_KERN_SRS(pmap,sr) \
75 lis pmap,CNAME(kernel_pmap_store)@ha; \
76 lwzu sr,CNAME(kernel_pmap_store)+PM_SR@l(pmap); \
80 * FRAME_SETUP assumes:
83 * savearea r28-r31,DAR,DSISR (DAR & DSISR only for DSI traps)
89 * SRR0/1 as at start of trap
91 #define FRAME_SETUP(savearea) \
92 /* Have to enable translation to allow access of kernel stack: */ \
95 stw %r30,(savearea+CPUSAVE_SRR0)(%r31); /* save SRR0 */ \
97 stw %r30,(savearea+CPUSAVE_SRR1)(%r31); /* save SRR1 */ \
99 ori %r30,%r30,(PSL_DR|PSL_IR|PSL_RI)@l; /* relocation on */ \
100 mtmsr %r30; /* stack can now be accessed */ \
102 mfsprg1 %r31; /* get saved SP */ \
103 stwu %r31,-FRAMELEN(%r1); /* save it in the callframe */ \
104 stw %r0, FRAME_0+8(%r1); /* save r0 in the trapframe */ \
105 stw %r31,FRAME_1+8(%r1); /* save SP " " */ \
106 stw %r2, FRAME_2+8(%r1); /* save r2 " " */ \
107 stw %r28,FRAME_LR+8(%r1); /* save LR " " */ \
108 stw %r29,FRAME_CR+8(%r1); /* save CR " " */ \
110 lwz %r28,(savearea+CPUSAVE_R28)(%r2); /* get saved r28 */ \
111 lwz %r29,(savearea+CPUSAVE_R29)(%r2); /* get saved r29 */ \
112 lwz %r30,(savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \
113 lwz %r31,(savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \
114 stw %r3, FRAME_3+8(%r1); /* save r3-r31 */ \
115 stw %r4, FRAME_4+8(%r1); \
116 stw %r5, FRAME_5+8(%r1); \
117 stw %r6, FRAME_6+8(%r1); \
118 stw %r7, FRAME_7+8(%r1); \
119 stw %r8, FRAME_8+8(%r1); \
120 stw %r9, FRAME_9+8(%r1); \
121 stw %r10, FRAME_10+8(%r1); \
122 stw %r11, FRAME_11+8(%r1); \
123 stw %r12, FRAME_12+8(%r1); \
124 stw %r13, FRAME_13+8(%r1); \
125 stw %r14, FRAME_14+8(%r1); \
126 stw %r15, FRAME_15+8(%r1); \
127 stw %r16, FRAME_16+8(%r1); \
128 stw %r17, FRAME_17+8(%r1); \
129 stw %r18, FRAME_18+8(%r1); \
130 stw %r19, FRAME_19+8(%r1); \
131 stw %r20, FRAME_20+8(%r1); \
132 stw %r21, FRAME_21+8(%r1); \
133 stw %r22, FRAME_22+8(%r1); \
134 stw %r23, FRAME_23+8(%r1); \
135 stw %r24, FRAME_24+8(%r1); \
136 stw %r25, FRAME_25+8(%r1); \
137 stw %r26, FRAME_26+8(%r1); \
138 stw %r27, FRAME_27+8(%r1); \
139 stw %r28, FRAME_28+8(%r1); \
140 stw %r29, FRAME_29+8(%r1); \
141 stw %r30, FRAME_30+8(%r1); \
142 stw %r31, FRAME_31+8(%r1); \
143 lwz %r28,(savearea+CPUSAVE_AIM_DAR)(%r2); /* saved DAR */ \
144 lwz %r29,(savearea+CPUSAVE_AIM_DSISR)(%r2);/* saved DSISR */\
145 lwz %r30,(savearea+CPUSAVE_SRR0)(%r2); /* saved SRR0 */ \
146 lwz %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */ \
150 stw %r3, FRAME_XER+8(1); /* save xer/ctr/exc */ \
151 stw %r4, FRAME_CTR+8(1); \
152 stw %r5, FRAME_EXC+8(1); \
153 stw %r28,FRAME_AIM_DAR+8(1); \
154 stw %r29,FRAME_AIM_DSISR+8(1); /* save dsisr/srr0/srr1 */ \
155 stw %r30,FRAME_SRR0+8(1); \
156 stw %r31,FRAME_SRR1+8(1)
158 #define FRAME_LEAVE(savearea) \
159 /* Now restore regs: */ \
160 lwz %r2,FRAME_SRR0+8(%r1); \
161 lwz %r3,FRAME_SRR1+8(%r1); \
162 lwz %r4,FRAME_CTR+8(%r1); \
163 lwz %r5,FRAME_XER+8(%r1); \
164 lwz %r6,FRAME_LR+8(%r1); \
166 stw %r2,(savearea+CPUSAVE_SRR0)(%r7); /* save SRR0 */ \
167 stw %r3,(savearea+CPUSAVE_SRR1)(%r7); /* save SRR1 */ \
168 lwz %r7,FRAME_CR+8(%r1); \
172 mtsprg1 %r7; /* save cr */ \
173 lwz %r31,FRAME_31+8(%r1); /* restore r0-31 */ \
174 lwz %r30,FRAME_30+8(%r1); \
175 lwz %r29,FRAME_29+8(%r1); \
176 lwz %r28,FRAME_28+8(%r1); \
177 lwz %r27,FRAME_27+8(%r1); \
178 lwz %r26,FRAME_26+8(%r1); \
179 lwz %r25,FRAME_25+8(%r1); \
180 lwz %r24,FRAME_24+8(%r1); \
181 lwz %r23,FRAME_23+8(%r1); \
182 lwz %r22,FRAME_22+8(%r1); \
183 lwz %r21,FRAME_21+8(%r1); \
184 lwz %r20,FRAME_20+8(%r1); \
185 lwz %r19,FRAME_19+8(%r1); \
186 lwz %r18,FRAME_18+8(%r1); \
187 lwz %r17,FRAME_17+8(%r1); \
188 lwz %r16,FRAME_16+8(%r1); \
189 lwz %r15,FRAME_15+8(%r1); \
190 lwz %r14,FRAME_14+8(%r1); \
191 lwz %r13,FRAME_13+8(%r1); \
192 lwz %r12,FRAME_12+8(%r1); \
193 lwz %r11,FRAME_11+8(%r1); \
194 lwz %r10,FRAME_10+8(%r1); \
195 lwz %r9, FRAME_9+8(%r1); \
196 lwz %r8, FRAME_8+8(%r1); \
197 lwz %r7, FRAME_7+8(%r1); \
198 lwz %r6, FRAME_6+8(%r1); \
199 lwz %r5, FRAME_5+8(%r1); \
200 lwz %r4, FRAME_4+8(%r1); \
201 lwz %r3, FRAME_3+8(%r1); \
202 lwz %r2, FRAME_2+8(%r1); \
203 lwz %r0, FRAME_0+8(%r1); \
204 lwz %r1, FRAME_1+8(%r1); \
205 /* Can't touch %r1 from here on */ \
206 mtsprg2 %r2; /* save r2 & r3 */ \
208 /* Disable translation, machine check and recoverability: */ \
210 andi. %r2,%r2,~(PSL_DR|PSL_IR|PSL_EE|PSL_ME|PSL_RI)@l; \
213 /* Decide whether we return to user mode: */ \
215 lwz %r3,(savearea+CPUSAVE_SRR1)(%r2); \
217 bf 17,1f; /* branch if PSL_PR is false */ \
218 /* Restore user SRs */ \
219 RESTORE_USER_SRS(%r2,%r3); \
220 1: mfsprg1 %r2; /* restore cr */ \
223 lwz %r3,(savearea+CPUSAVE_SRR0)(%r2); /* restore srr0 */ \
225 lwz %r3,(savearea+CPUSAVE_SRR1)(%r2); /* restore srr1 */ \
227 /* Make sure HV bit of MSR propagated to SRR1 */ \
232 mfsprg2 %r2; /* restore r2 & r3 */ \
236 * The next two routines are 64-bit glue code. The first is used to test if
237 * we are on a 64-bit system. By copying it to the illegal instruction
238 * handler, we can test for 64-bit mode by trying to execute a 64-bit
239 * instruction and seeing what happens. The second gets copied in front
240 * of all the other handlers to restore 32-bit bridge mode when traps
244 /* 64-bit test code. Sets SPRG2 to 0 if an illegal instruction is executed */
246 .globl CNAME(testppc64),CNAME(testppc64size)
258 CNAME(testppc64size) = .-CNAME(testppc64)
261 /* 64-bit bridge mode restore snippet. Gets copied in front of everything else
262 * on 64-bit systems. */
264 .globl CNAME(restorebridge),CNAME(restorebridgesize)
265 CNAME(restorebridge):
272 CNAME(restorebridgesize) = .-CNAME(restorebridge)
276 * Processor reset exception handler. These are typically
277 * the first instructions the processor executes after a
280 .globl CNAME(rstcode), CNAME(rstsize)
288 addi %r1,%r1,(124-16)@l
291 bla CNAME(pmap_cpu_bootstrap)
292 bla CNAME(cpudep_ap_bootstrap)
294 bla CNAME(machdep_ap_bootstrap)
296 /* Should not be reached */
299 CNAME(rstsize) = . - CNAME(rstcode)
303 * This code gets copied to all the trap vectors
304 * (except ISI/DSI, ALI, and the interrupts)
307 .globl CNAME(trapcode),CNAME(trapsize)
309 mtsprg1 %r1 /* save SP */
310 mflr %r1 /* Save the old LR in r1 */
311 mtsprg2 %r1 /* And then in SPRG2 */
312 li %r1, 0x20 /* How to get the vector from LR */
313 bla generictrap /* LR & SPRG3 is exception # */
314 CNAME(trapsize) = .-CNAME(trapcode)
317 * 64-bit version of trapcode. Identical, except it calls generictrap64.
319 .globl CNAME(trapcode64)
321 mtsprg1 %r1 /* save SP */
322 mflr %r1 /* Save the old LR in r1 */
323 mtsprg2 %r1 /* And then in SPRG2 */
324 li %r1, 0x20 /* How to get the vector from LR */
325 bla generictrap64 /* LR & SPRG3 is exception # */
328 * For ALI: has to save DSISR and DAR
330 .globl CNAME(alitrap),CNAME(alisize)
332 mtsprg1 %r1 /* save SP */
334 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */
335 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
336 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
337 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
340 stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
341 stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1)
342 mfsprg1 %r1 /* restore SP, in case of branch */
343 mflr %r28 /* save LR */
344 mfcr %r29 /* save CR */
346 /* Put our exception vector in SPRG3 */
350 /* Test whether we already had PR set */
354 CNAME(alisize) = .-CNAME(alitrap)
357 * Similar to the above for DSI
358 * Has to handle BAT spills
359 * and standard pagetable spills
361 .globl CNAME(dsitrap),CNAME(dsisize)
363 mtsprg1 %r1 /* save SP */
365 stw %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */
366 stw %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1)
367 stw %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
368 stw %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
369 mfsprg1 %r1 /* restore SP */
370 mfcr %r29 /* save CR */
371 mfxer %r30 /* save XER */
372 mtsprg2 %r30 /* in SPRG2 */
373 mfsrr1 %r31 /* test kernel mode */
375 bt 17,1f /* branch if PSL_PR is set */
376 mfdar %r31 /* get fault address */
377 rlwinm %r31,%r31,7,25,28 /* get segment * 8 */
380 addis %r31,%r31,CNAME(battable)@ha
381 lwz %r30,CNAME(battable)@l(31)
383 bf 30,1f /* branch if supervisor valid is
386 lwz %r31,CNAME(battable)+4@l(31)
387 /* We randomly use the highest two bat registers here */
398 mfsprg2 %r30 /* restore XER */
400 mtcr %r29 /* restore CR */
403 lwz %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* restore r28-r31 */
404 lwz %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1)
405 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
406 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
408 rfi /* return to trapped code */
410 mflr %r28 /* save LR (SP already saved) */
412 CNAME(dsisize) = .-CNAME(dsitrap)
415 * Preamble code for DSI/ISI traps
418 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */
424 lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1)
425 stw %r30,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
426 lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1)
427 stw %r31,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
428 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
429 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
430 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
431 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
434 stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
435 stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1)
438 /* Try and detect a kernel stack overflow */
441 bt 17,realtrap /* branch is user mode */
442 mfsprg1 %r31 /* get old SP */
443 sub. %r30,%r31,%r30 /* SP - DAR */
445 neg %r30,%r30 /* modulo value */
446 1: cmplwi %cr0,%r30,4096 /* is DAR within a page of SP? */
447 bge %cr0,realtrap /* no, too far away. */
449 /* Now convert this DSI into a DDB trap. */
451 lwz %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) /* get DAR */
452 stw %r30,(PC_DBSAVE +CPUSAVE_AIM_DAR)(%r1) /* save DAR */
453 lwz %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) /* get DSISR */
454 lwz %r30,(PC_DBSAVE +CPUSAVE_AIM_DSISR)(%r1) /* save DSISR */
455 lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* get r28 */
456 stw %r30,(PC_DBSAVE +CPUSAVE_R28)(%r1) /* save r28 */
457 lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) /* get r29 */
458 stw %r31,(PC_DBSAVE +CPUSAVE_R29)(%r1) /* save r29 */
459 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) /* get r30 */
460 stw %r30,(PC_DBSAVE +CPUSAVE_R30)(%r1) /* save r30 */
461 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) /* get r31 */
462 stw %r31,(PC_DBSAVE +CPUSAVE_R31)(%r1) /* save r31 */
466 /* XXX need stack probe here */
468 /* Test whether we already had PR set */
471 mfsprg1 %r1 /* restore SP (might have been
473 bf 17,k_trap /* branch if PSL_PR is false */
475 lwz %r1,PC_CURPCB(%r1)
476 RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */
480 * generictrap does some standard setup for trap handling to minimize
481 * the code that need be installed in the actual vectors. It expects
482 * the following conditions.
484 * R1 - Trap vector = LR & (0xff00 | R1)
485 * SPRG1 - Original R1 contents
486 * SPRG2 - Original LR
498 /* Save R1 for computing the exception vector */
501 /* Save interesting registers */
503 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */
504 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
505 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
506 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
507 mfsprg1 %r1 /* restore SP, in case of branch */
508 mfsprg2 %r28 /* save LR */
509 mfcr %r29 /* save CR */
511 /* Compute the exception vector from the link register */
518 /* Test whether we already had PR set */
523 bf 17,k_trap /* branch if PSL_PR is false */
526 lwz %r1,PC_CURPCB(%r1)
527 RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */
530 * Now the common trap catching code.
533 FRAME_SETUP(PC_TEMPSAVE)
534 /* Call C interrupt dispatcher: */
537 bl CNAME(powerpc_interrupt)
538 .globl CNAME(trapexit) /* backtrace code sentinel */
541 /* Disable interrupts: */
543 andi. %r3,%r3,~PSL_EE@l
545 /* Test AST pending: */
546 lwz %r5,FRAME_SRR1+8(%r1)
548 bf 17,1f /* branch if PSL_PR is false */
550 GET_CPUINFO(%r3) /* get per-CPU pointer */
551 lwz %r4, PC_CURTHREAD(%r3) /* deref to get curthread */
552 lwz %r4, TD_FLAGS(%r4) /* get thread flags value */
553 lis %r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@h
554 ori %r5,%r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@l
557 mfmsr %r3 /* re-enable interrupts */
563 .globl CNAME(asttrapexit) /* backtrace code sentinel #2 */
565 b trapexit /* test ast ret value ? */
567 FRAME_LEAVE(PC_TEMPSAVE)
569 .globl CNAME(rfi_patch1) /* replace rfi with rfid on ppc64 */
573 .globl CNAME(rfid_patch)
579 * Deliberate entry to dbtrap
581 .globl CNAME(breakpoint)
586 andi. %r3,%r3,~(PSL_EE|PSL_ME)@l
587 mtmsr %r3 /* disable interrupts */
590 stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r3)
591 stw %r29,(PC_DBSAVE+CPUSAVE_R29)(%r3)
592 stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r3)
593 stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r3)
601 * Now the kdb trap catching code.
604 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */
609 lis %r1,(tmpstk+TMPSTKSZ-16)@ha /* get new SP */
610 addi %r1,%r1,(tmpstk+TMPSTKSZ-16)@l
612 FRAME_SETUP(PC_DBSAVE)
613 /* Call C trap code: */
615 bl CNAME(db_trap_glue)
618 /* This wasn't for KDB, so switch to real trap: */
619 lwz %r3,FRAME_EXC+8(%r1) /* save exception */
621 stw %r3,(PC_DBSAVE+CPUSAVE_R31)(%r4)
622 FRAME_LEAVE(PC_DBSAVE)
623 mtsprg1 %r1 /* prepare for entrance to realtrap */
625 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
626 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
627 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
628 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
631 lwz %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1)
632 mtsprg3 %r31 /* SPRG3 was clobbered by FRAME_LEAVE */
636 FRAME_LEAVE(PC_DBSAVE)
637 .globl CNAME(rfi_patch2) /* replace rfi with rfid on ppc64 */
642 * In case of KDB we want a separate trap catcher for it
644 .globl CNAME(dblow),CNAME(dbsize)
646 mtsprg1 %r1 /* save SP */
647 mtsprg2 %r29 /* save r29 */
648 mfcr %r29 /* save CR in r29 */
651 bf 17,1f /* branch if privileged */
653 /* Unprivileged case */
654 mtcr %r29 /* put the condition register back */
655 mfsprg2 %r29 /* ... and r29 */
656 mflr %r1 /* save LR */
657 mtsprg2 %r1 /* And then in SPRG2 */
658 li %r1, 0 /* How to get the vector from LR */
660 bla generictrap /* and we look like a generic trap */
662 /* Privileged, so drop to KDB */
664 stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r1) /* free r28 */
665 mfsprg2 %r28 /* r29 holds cr... */
666 stw %r28,(PC_DBSAVE+CPUSAVE_R29)(%r1) /* free r29 */
667 stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1) /* free r30 */
668 stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) /* free r31 */
669 mflr %r28 /* save LR */
671 CNAME(dbsize) = .-CNAME(dblow)