2 * Copyright (C) 2008 Semihalf, Rafal Jaworowski
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
34 #include <vm/vm_param.h>
36 #include <machine/cpu.h>
37 #include <machine/cpufunc.h>
38 #include <machine/spr.h>
40 #include <powerpc/mpc85xx/ocpbus.h>
41 #include <powerpc/mpc85xx/mpc85xx.h>
44 * MPC85xx system specific routines
48 ccsr_read4(uintptr_t addr)
50 volatile uint32_t *ptr = (void *)addr;
56 ccsr_write4(uintptr_t addr, uint32_t val)
58 volatile uint32_t *ptr = (void *)addr;
61 __asm __volatile("eieio; sync");
69 ver = SVR_VER(mfspr(SPR_SVR));
70 if (ver == SVR_MPC8572E || ver == SVR_MPC8572)
72 else if (ver == SVR_MPC8548E || ver == SVR_MPC8548)
78 #define _LAW_SR(trgt,size) (0x80000000 | (trgt << 20) | (ffsl(size) - 2))
79 #define _LAW_BAR(addr) (addr >> 12)
82 law_enable(int trgt, u_long addr, u_long size)
87 law_max = law_getmax();
89 sr = _LAW_SR(trgt, size);
91 /* Bail if already programmed. */
92 for (i = 0; i < law_max; i++)
93 if (sr == ccsr_read4(OCP85XX_LAWSR(i)) &&
94 bar == ccsr_read4(OCP85XX_LAWBAR(i)))
97 /* Find an unused access window. */
98 for (i = 0; i < law_max; i++)
99 if ((ccsr_read4(OCP85XX_LAWSR(i)) & 0x80000000) == 0)
105 ccsr_write4(OCP85XX_LAWBAR(i), bar);
106 ccsr_write4(OCP85XX_LAWSR(i), sr);
111 law_disable(int trgt, u_long addr, u_long size)
116 law_max = law_getmax();
117 bar = _LAW_BAR(addr);
118 sr = _LAW_SR(trgt, size);
120 /* Find and disable requested LAW. */
121 for (i = 0; i < law_max; i++)
122 if (sr == ccsr_read4(OCP85XX_LAWSR(i)) &&
123 bar == ccsr_read4(OCP85XX_LAWBAR(i))) {
124 ccsr_write4(OCP85XX_LAWBAR(i), 0);
125 ccsr_write4(OCP85XX_LAWSR(i), 0);
135 uint32_t ver = SVR_VER(mfspr(SPR_SVR));
137 if (ver == SVR_MPC8572E || ver == SVR_MPC8572 ||
138 ver == SVR_MPC8548E || ver == SVR_MPC8548)
139 /* Systems with dedicated reset register */
140 ccsr_write4(OCP85XX_RSTCR, 2);
142 /* Clear DBCR0, disables debug interrupts and events. */
144 __asm __volatile("isync");
146 /* Enable Debug Interrupts in MSR. */
147 mtmsr(mfmsr() | PSL_DE);
149 /* Enable debug interrupts and issue reset. */
150 mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM |
154 printf("Reset failed...\n");