2 * Copyright 2006 by Juniper Networks. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #ifndef _MACHINE_OCP85XX_H_
31 #define _MACHINE_OCP85XX_H_
34 * Configuration control and status registers
36 #define OCP85XX_CCSRBAR (CCSRBAR_VA + 0x0)
37 #define OCP85XX_BPTR (CCSRBAR_VA + 0x20)
40 * E500 Coherency Module registers
42 #define OCP85XX_EEBPCR (CCSRBAR_VA + 0x1010)
45 * Local access registers
47 #define OCP85XX_LAWBAR(n) (CCSRBAR_VA + 0xc08 + 0x20 * (n))
48 #define OCP85XX_LAWSR(n) (CCSRBAR_VA + 0xc10 + 0x20 * (n))
50 #define OCP85XX_TGTIF_PCI0 0
51 #define OCP85XX_TGTIF_PCI1 1
52 #define OCP85XX_TGTIF_PCI2 2
53 #define OCP85XX_TGTIF_LBC 4
54 #define OCP85XX_TGTIF_RAM_INTL 11
55 #define OCP85XX_TGTIF_RIO 12
56 #define OCP85XX_TGTIF_RAM1 15
57 #define OCP85XX_TGTIF_RAM2 22
62 #define OCP85XX_L2CTL (CCSRBAR_VA + 0x20000)
65 * Power-On Reset configuration
67 #define OCP85XX_PORDEVSR (CCSRBAR_VA + 0xe000c)
68 #define OCP85XX_PORDEVSR2 (CCSRBAR_VA + 0xe0014)
73 #define OCP85XX_RSTCR (CCSRBAR_VA + 0xe00b0)
78 #define OCP85XX_I2C0_OFF 0x03000
79 #define OCP85XX_I2C1_OFF 0x03100
80 #define OCP85XX_I2C_SIZE 0x16
81 #define OCP85XX_UART0_OFF 0x04500
82 #define OCP85XX_UART1_OFF 0x04600
83 #define OCP85XX_UART_SIZE 0x10
84 #define OCP85XX_LBC_OFF 0x05000
85 #define OCP85XX_LBC_SIZE 0x1000
86 #define OCP85XX_PCI0_OFF 0x08000
87 #define OCP85XX_PCI1_OFF 0x09000
88 #define OCP85XX_PCI2_OFF 0x0A000
89 #define OCP85XX_PCI_SIZE 0x1000
90 #define OCP85XX_TSEC0_OFF 0x24000
91 #define OCP85XX_TSEC1_OFF 0x25000
92 #define OCP85XX_TSEC2_OFF 0x26000
93 #define OCP85XX_TSEC3_OFF 0x27000
94 #define OCP85XX_TSEC_SIZE 0x1000
95 #define OCP85XX_OPENPIC_OFF 0x40000
96 #define OCP85XX_OPENPIC_SIZE 0x200B4
97 #define OCP85XX_QUICC_OFF 0x80000
98 #define OCP85XX_QUICC_SIZE 0x20000
99 #define OCP85XX_SEC_OFF 0x30000
100 #define OCP85XX_SEC_SIZE 0x10000
105 #define ISA_IRQ_START 0
106 #define PIC_IRQ_START (ISA_IRQ_START + 16)
108 #define ISA_IRQ(n) (ISA_IRQ_START + (n))
109 #define PIC_IRQ_EXT(n) (PIC_IRQ_START + (n))
110 #define PIC_IRQ_INT(n) (PIC_IRQ_START + 16 + (n))
112 #endif /* _MACHINE_OCP85XX_H */