2 * Copyright (c) 2001 Matt Thomas.
3 * Copyright (c) 2001 Tsubai Masanari.
4 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by
18 * Internet Research Institute, Inc.
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (C) 2003 Benno Rice.
35 * All rights reserved.
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
40 * 1. Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * 2. Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in the
44 * documentation and/or other materials provided with the distribution.
46 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
48 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
49 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
50 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
51 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
52 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
53 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
54 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
55 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57 * from $NetBSD: cpu_subr.c,v 1.1 2003/02/03 17:10:09 matt Exp $
61 #include <sys/param.h>
62 #include <sys/systm.h>
66 #include <sys/kernel.h>
67 #include <sys/sysctl.h>
69 #include <machine/bus.h>
70 #include <machine/hid.h>
71 #include <machine/md_var.h>
72 #include <machine/spr.h>
74 int powerpc_pow_enabled;
81 #define REVFMT_MAJMIN 1 /* %u.%u */
82 #define REVFMT_HEX 2 /* 0x%04x */
83 #define REVFMT_DEC 3 /* %u */
84 static const struct cputab models[] = {
85 { "Motorola PowerPC 601", MPC601, REVFMT_DEC },
86 { "Motorola PowerPC 602", MPC602, REVFMT_DEC },
87 { "Motorola PowerPC 603", MPC603, REVFMT_MAJMIN },
88 { "Motorola PowerPC 603e", MPC603e, REVFMT_MAJMIN },
89 { "Motorola PowerPC 603ev", MPC603ev, REVFMT_MAJMIN },
90 { "Motorola PowerPC 604", MPC604, REVFMT_MAJMIN },
91 { "Motorola PowerPC 604ev", MPC604ev, REVFMT_MAJMIN },
92 { "Motorola PowerPC 620", MPC620, REVFMT_HEX },
93 { "Motorola PowerPC 750", MPC750, REVFMT_MAJMIN },
94 { "IBM PowerPC 750FX", IBM750FX, REVFMT_MAJMIN },
95 { "IBM PowerPC 970", IBM970, REVFMT_MAJMIN },
96 { "IBM PowerPC 970FX", IBM970FX, REVFMT_MAJMIN },
97 { "IBM PowerPC 970GX", IBM970GX, REVFMT_MAJMIN },
98 { "IBM PowerPC 970MP", IBM970MP, REVFMT_MAJMIN },
99 { "Motorola PowerPC 7400", MPC7400, REVFMT_MAJMIN },
100 { "Motorola PowerPC 7410", MPC7410, REVFMT_MAJMIN },
101 { "Motorola PowerPC 7450", MPC7450, REVFMT_MAJMIN },
102 { "Motorola PowerPC 7455", MPC7455, REVFMT_MAJMIN },
103 { "Motorola PowerPC 7457", MPC7457, REVFMT_MAJMIN },
104 { "Motorola PowerPC 7447A", MPC7447A, REVFMT_MAJMIN },
105 { "Motorola PowerPC 7448", MPC7448, REVFMT_MAJMIN },
106 { "Motorola PowerPC 8240", MPC8240, REVFMT_MAJMIN },
107 { "Freescale e500v1 core", FSL_E500v1, REVFMT_MAJMIN },
108 { "Freescale e500v2 core", FSL_E500v2, REVFMT_MAJMIN },
109 { "Unknown PowerPC CPU", 0, REVFMT_HEX }
112 static char model[64];
113 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, model, 0, "");
115 register_t l2cr_config = 0;
116 register_t l3cr_config = 0;
118 static void cpu_print_speed(void);
119 static void cpu_print_cacheinfo(u_int, uint16_t);
122 cpu_setup(u_int cpuid)
124 u_int pvr, maj, min, hid0;
125 uint16_t vers, rev, revfmt;
126 const struct cputab *cp;
135 min = (pvr >> 0) & 0xff;
136 maj = min <= 4 ? 1 : 2;
140 maj = (pvr >> 4) & 0xf;
141 min = (pvr >> 0) & 0xf;
144 maj = (pvr >> 8) & 0xf;
145 min = (pvr >> 0) & 0xf;
148 for (cp = models; cp->version != 0; cp++) {
149 if (cp->version == vers)
155 if (rev == MPC750 && pvr == 15) {
156 name = "Motorola MPC755";
159 strncpy(model, name, sizeof(model) - 1);
161 printf("cpu%d: %s revision ", cpuid, name);
165 printf("%u.%u", maj, min);
168 printf("0x%04x", rev);
175 hid0 = mfspr(SPR_HID0);
178 * Configure power-saving mode.
191 /* Select DOZE mode. */
192 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
193 hid0 |= HID0_DOZE | HID0_DPM;
194 powerpc_pow_enabled = 1;
202 /* Enable the 7450 branch caches */
203 hid0 |= HID0_SGE | HID0_BTIC;
204 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT;
205 /* Disable BTIC on 7450 Rev 2.0 or earlier and on 7457 */
206 if (((pvr >> 16) == MPC7450 && (pvr & 0xFFFF) <= 0x0200)
207 || (pvr >> 16) == MPC7457)
209 /* Select NAP mode. */
210 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
211 hid0 |= HID0_NAP | HID0_DPM;
212 powerpc_pow_enabled = 1;
216 /* No power-saving mode is available. */ ;
222 hid0 &= ~HID0_DBP; /* XXX correct? */
223 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
229 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
238 mtspr(SPR_HID0, hid0);
246 bitmask = HID0_7450_BITMASK;
250 bitmask = HID0_E500_BITMASK;
253 bitmask = HID0_BITMASK;
261 /* Only MPC745x CPUs have an L3 cache. */
263 l3cr_config = mfspr(SPR_L3CR);
275 l2cr_config = mfspr(SPR_L2CR);
278 cpu_print_cacheinfo(cpuid, vers);
291 printf("cpu%d: HID0 %b\n", cpuid, hid0, bitmask);
295 cpu_print_speed(void)
299 if (cpu_est_clockrate(0, &cps) == 0)
300 printf(", %lld.%02lld MHz", cps / 1000000, (cps / 10000) % 100);
303 /* Get current clock frequency for the given cpu id. */
305 cpu_est_clockrate(int cpu_id, uint64_t *cps)
310 vers = mfpvr() >> 16;
312 mtmsr(msr & ~PSL_EE);
324 mtspr(SPR_MMCR0, SPR_MMCR0_FC);
326 mtspr(SPR_MMCR0, SPR_MMCR0_PMC1SEL(PMCN_CYCLES));
328 *cps = (mfspr(SPR_PMC1) * 1000) + 4999;
329 mtspr(SPR_MMCR0, SPR_MMCR0_FC);
337 mtspr(SPR_970MMCR0, SPR_MMCR0_FC);
339 mtspr(SPR_970MMCR1, 0);
340 mtspr(SPR_970MMCRA, 0);
341 mtspr(SPR_970PMC1, 0);
343 SPR_970MMCR0_PMC1SEL(PMC970N_CYCLES));
347 mtspr(SPR_970MMCR0, SPR_MMCR0_FC);
348 *cps = (mfspr(SPR_970PMC1) * 1000) + 4999;
358 cpu_print_cacheinfo(u_int cpuid, uint16_t vers)
363 hid = mfspr(SPR_HID0);
364 printf("cpu%u: ", cpuid);
365 printf("L1 I-cache %sabled, ", (hid & HID0_ICE) ? "en" : "dis");
366 printf("L1 D-cache %sabled\n", (hid & HID0_DCE) ? "en" : "dis");
368 printf("cpu%u: ", cpuid);
369 if (l2cr_config & L2CR_L2E) {
374 printf("256KB L2 cache, ");
375 if (l3cr_config & L3CR_L3E)
376 printf("%cMB L3 backside cache",
377 l3cr_config & L3CR_L3SIZ ? '2' : '1');
379 printf("L3 cache disabled");
383 printf("512KB L2 cache\n");
386 switch (l2cr_config & L2CR_L2SIZ) {
397 printf("write-%s", (l2cr_config & L2CR_L2WT)
398 ? "through" : "back");
399 if (l2cr_config & L2CR_L2PE)
400 printf(", with parity");
401 printf(" backside cache\n");
405 printf("L2 cache disabled\n");