2 * Copyright (c) 2001 Jake Burkholder.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <machine/asm.h>
28 __FBSDID("$FreeBSD$");
30 #include <machine/asi.h>
31 #include <machine/asmacros.h>
32 #include <machine/pstate.h>
39 .set kernbase, KERNBASE
42 * void _start(caddr_t metadata, u_long o1, u_long o2, u_long o3,
48 * Initialize misc. state to known values: interrupts disabled, normal
49 * globals, windows flushed (cr = 0, cs = nwindows - 1), no clean
50 * windows, pil 0, and floating point disabled.
52 wrpr %g0, PSTATE_NORMAL, %pstate
54 wrpr %g0, 0, %cleanwin
59 * Get onto our per-CPU panic stack, which precedes the struct pcpu in
62 SET(pcpu0 + (PCPU_PAGES * PAGE_SIZE) - PC_SIZEOF, %l1, %l0)
63 sub %l0, SPOFF + CCFSZ, %sp
68 wrpr %g0, PSTATE_KERNEL, %pstate
71 * Do initial bootstrap to setup pmap and thread0.
77 * Get onto thread0's kstack.
79 sub PCB_REG, SPOFF + CCFSZ, %sp
82 * And away we go. This doesn't return.
91 * void cpu_setregs(struct pcpu *pc)
94 ldx [%o0 + PC_CURPCB], %o1
97 * Disable interrupts, normal globals.
99 wrpr %g0, PSTATE_NORMAL, %pstate
102 * Normal %g6 points to the current thread's PCB, and %g7 points to
103 * the per-CPU data structure.
109 * Switch to alternate globals.
111 wrpr %g0, PSTATE_ALT, %pstate
114 * Alternate %g5 points to a per-CPU panic stack, %g6 points to the
115 * current thread's PCB, and %g7 points to the per-CPU data structure.
122 * Switch to interrupt globals.
124 wrpr %g0, PSTATE_INTR, %pstate
127 * Interrupt %g7 points to the per-CPU data structure.
132 * Switch to normal globals again.
134 wrpr %g0, PSTATE_NORMAL, %pstate
137 * Force trap level 1 and take over the trap table.
139 SET(tl0_base, %o2, %o1)
144 * Re-enable interrupts.
146 wrpr %g0, PSTATE_KERNEL, %pstate