2 * Copyright (c) 2006 Marius Strobl <marius@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/module.h>
35 #include <sys/resource.h>
38 #include <dev/ofw/ofw_bus.h>
39 #include <dev/ofw/ofw_bus_subr.h>
40 #include <dev/ofw/openfirm.h>
42 #include <machine/bus.h>
43 #include <machine/bus_common.h>
44 #include <machine/intr_machdep.h>
45 #include <machine/resource.h>
54 #define UPA_CFG_UPA0 0x00 /* UPA0 config register */
55 #define UPA_CFG_UPA1 0x08 /* UPA1 config register */
56 #define UPA_CFG_IF 0x10 /* interface config register */
57 #define UPA_CFG_IF_RST 0x00
58 #define UPA_CFG_IF_POK_RST 0x02
59 #define UPA_CFG_IF_POK 0x03
60 #define UPA_CFG_ESTAR 0x18 /* Estar config register */
61 #define UPA_CFG_ESTAR_SPEED_FULL 0x01
62 #define UPA_CFG_ESTAR_SPEED_1_2 0x02
63 #define UPA_CFG_ESTAR_SPEED_1_64 0x40
65 #define UPA_INO_BASE 0x2a
66 #define UPA_INO_MAX 0x2b
80 struct ofw_bus_devinfo udi_obdinfo;
81 struct resource_list udi_rl;
85 struct resource *sc_res[UPA_NREG];
86 bus_space_tag_t sc_bt[UPA_NREG];
87 bus_space_handle_t sc_bh[UPA_NREG];
92 struct upa_ranges *sc_ranges;
95 #define UPA_READ(sc, reg, off) \
96 bus_space_read_8((sc)->sc_bt[(reg)], (sc)->sc_bh[(reg)], (off))
97 #define UPA_WRITE(sc, reg, off, val) \
98 bus_space_write_8((sc)->sc_bt[(reg)], (sc)->sc_bh[(reg)], (off), (val))
100 static device_probe_t upa_probe;
101 static device_attach_t upa_attach;
102 static bus_alloc_resource_t upa_alloc_resource;
103 static bus_setup_intr_t upa_setup_intr;
104 static bus_print_child_t upa_print_child;
105 static bus_probe_nomatch_t upa_probe_nomatch;
106 static bus_get_resource_list_t upa_get_resource_list;
107 static ofw_bus_get_devinfo_t upa_get_devinfo;
109 static void upa_intr_enable(void *);
110 static void upa_intr_disable(void *);
111 static void upa_intr_assign(void *);
112 static struct upa_devinfo *upa_setup_dinfo(device_t, struct upa_softc *,
113 phandle_t, uint32_t);
114 static void upa_destroy_dinfo(struct upa_devinfo *);
115 static int upa_print_res(struct upa_devinfo *);
117 static device_method_t upa_methods[] = {
118 /* Device interface */
119 DEVMETHOD(device_probe, upa_probe),
120 DEVMETHOD(device_attach, upa_attach),
121 DEVMETHOD(device_shutdown, bus_generic_shutdown),
122 DEVMETHOD(device_suspend, bus_generic_suspend),
123 DEVMETHOD(device_resume, bus_generic_resume),
126 DEVMETHOD(bus_print_child, upa_print_child),
127 DEVMETHOD(bus_probe_nomatch, upa_probe_nomatch),
128 DEVMETHOD(bus_read_ivar, bus_generic_read_ivar),
129 DEVMETHOD(bus_write_ivar, bus_generic_write_ivar),
130 DEVMETHOD(bus_alloc_resource, upa_alloc_resource),
131 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
132 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
133 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
134 DEVMETHOD(bus_setup_intr, upa_setup_intr),
135 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
136 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
137 DEVMETHOD(bus_get_resource_list, upa_get_resource_list),
138 DEVMETHOD(bus_child_pnpinfo_str, ofw_bus_gen_child_pnpinfo_str),
140 /* ofw_bus interface */
141 DEVMETHOD(ofw_bus_get_devinfo, upa_get_devinfo),
142 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
143 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
144 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
145 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
146 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
151 static devclass_t upa_devclass;
153 DEFINE_CLASS_0(upa, upa_driver, upa_methods, sizeof(struct upa_softc));
154 DRIVER_MODULE(upa, nexus, upa_driver, upa_devclass, 0, 0);
156 static const struct intr_controller upa_ic = {
160 /* The interrupts are pulse type and thus automatically cleared. */
165 struct upa_softc *uica_sc;
170 upa_probe(device_t dev)
174 compat = ofw_bus_get_compat(dev);
175 if (compat != NULL && strcmp(ofw_bus_get_name(dev), "upa") == 0 &&
176 strcmp(compat, "upa64s") == 0) {
177 device_set_desc(dev, "UPA bridge");
178 return (BUS_PROBE_DEFAULT);
184 upa_attach(device_t dev)
186 struct upa_devinfo *udi;
187 struct upa_icarg *uica;
188 struct upa_softc *sc;
189 phandle_t child, node;
194 device_t *children, schizo;
195 u_long scount, sstart, ucount, ustart;
199 sc = device_get_softc(dev);
200 node = ofw_bus_get_node(dev);
201 for (i = UPA_CFG; i <= UPA_IMR2; i++) {
204 * The UPA_IMR{1,2} resources are shared with that of the
205 * Schizo PCI bus B CSR bank.
208 sc->sc_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
209 &rid, ((i == UPA_IMR1 || i == UPA_IMR2) ? RF_SHAREABLE :
211 if (sc->sc_res[i] == NULL) {
213 "could not allocate resource %d\n", i);
216 sc->sc_bt[i] = rman_get_bustag(sc->sc_res[i]);
217 sc->sc_bh[i] = rman_get_bushandle(sc->sc_res[i]);
220 * Workaround for the fact that rman(9) only allows to
221 * share resources of the same size.
223 if (i == UPA_IMR1 || i == UPA_IMR2) {
224 if (bus_get_resource(dev, SYS_RES_MEMORY, i, &ustart,
227 "could not determine UPA resource\n");
230 if (device_get_children(device_get_parent(dev),
231 &children, &nchildren) != 0) {
232 device_printf(dev, "could not get children\n");
236 for (j = 0; j < nchildren; j++) {
237 if (ofw_bus_get_type(children[j]) != NULL &&
238 strcmp(ofw_bus_get_type(children[j]),
240 ofw_bus_get_compat(children[j]) != NULL &&
241 strcmp(ofw_bus_get_compat(children[j]),
242 "pci108e,8001") == 0 &&
243 ((bus_get_resource_start(children[j],
244 SYS_RES_MEMORY, 0) >> 20) & 1) == 1) {
245 schizo = children[j];
249 free(children, M_TEMP);
250 if (schizo == NULL) {
251 device_printf(dev, "could not find Schizo\n");
254 if (bus_get_resource(schizo, SYS_RES_MEMORY, 0,
255 &sstart, &scount) != 0) {
257 "could not determine Schizo resource\n");
260 sc->sc_res[i] = bus_alloc_resource(dev, SYS_RES_MEMORY,
261 &rid, sstart, sstart + scount - 1, scount,
262 RF_SHAREABLE | RF_ACTIVE);
264 sc->sc_res[i] = bus_alloc_resource_any(dev,
265 SYS_RES_MEMORY, &rid, RF_ACTIVE);
266 if (sc->sc_res[i] == NULL) {
268 "could not allocate resource %d\n", i);
271 sc->sc_bt[i] = rman_get_bustag(sc->sc_res[i]);
272 sc->sc_bh[i] = rman_get_bushandle(sc->sc_res[i]);
273 if (i == UPA_IMR1 || i == UPA_IMR2)
274 bus_space_subregion(sc->sc_bt[i], sc->sc_bh[i],
275 ustart - sstart, ucount, &sc->sc_bh[i]);
279 if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1) {
280 device_printf(dev, "could not determine IGN\n");
284 sc->sc_nrange = OF_getprop_alloc(node, "ranges", sizeof(*sc->sc_ranges),
285 (void **)&sc->sc_ranges);
286 if (sc->sc_nrange == -1) {
287 device_printf(dev, "could not determine ranges\n");
292 * Hunt through all the interrupt mapping regs and register our
293 * interrupt controller for the corresponding interrupt vectors.
294 * We do this early in order to be able to catch stray interrupts.
296 for (i = UPA_INO_BASE; i <= UPA_INO_MAX; i++) {
298 for (j = UPA_IMR1; j <= UPA_IMR2; j++) {
299 if (INTVEC(UPA_READ(sc, j, 0x0)) ==
300 INTMAP_VEC(sc->sc_ign, i)) {
307 uica = malloc(sizeof(*uica), M_DEVBUF, M_NOWAIT);
309 panic("%s: could not allocate interrupt controller "
310 "argument", __func__);
312 uica->uica_imr = imr;
314 device_printf(dev, "intr map (INO %d) IMR%d: %#lx\n",
315 i, imr, (u_long)UPA_READ(sc, imr, 0x0));
317 j = intr_controller_register(INTMAP_VEC(sc->sc_ign, i),
320 device_printf(dev, "could not register interrupt "
321 "controller for INO %d (%d)\n", i, j);
324 /* Make sure the power level is appropriate for normal operation. */
325 if (UPA_READ(sc, UPA_CFG, UPA_CFG_IF) != UPA_CFG_IF_POK) {
327 device_printf(dev, "applying power\n");
328 UPA_WRITE(sc, UPA_CFG, UPA_CFG_ESTAR, UPA_CFG_ESTAR_SPEED_1_2);
329 UPA_WRITE(sc, UPA_CFG, UPA_CFG_ESTAR, UPA_CFG_ESTAR_SPEED_FULL);
330 (void)UPA_READ(sc, UPA_CFG, UPA_CFG_ESTAR);
331 UPA_WRITE(sc, UPA_CFG, UPA_CFG_IF, UPA_CFG_IF_POK_RST);
332 (void)UPA_READ(sc, UPA_CFG, UPA_CFG_IF);
334 UPA_WRITE(sc, UPA_CFG, UPA_CFG_IF, UPA_CFG_IF_POK);
335 (void)UPA_READ(sc, UPA_CFG, UPA_CFG_IF);
338 for (child = OF_child(node); child != 0; child = OF_peer(child)) {
340 * The `upa-portid' properties of the children are used as
341 * index for the interrupt mapping registers.
342 * The `upa-portid' properties are also used to make up the
343 * INOs of the children as the values contained in their
344 * `interrupts' properties are bogus.
346 if (OF_getprop(child, "upa-portid", &portid,
347 sizeof(portid)) == -1) {
349 "could not determine upa-portid of child 0x%lx\n",
350 (unsigned long)child);
355 "upa-portid %d of child 0x%lx invalid\n", portid,
356 (unsigned long)child);
359 if ((udi = upa_setup_dinfo(dev, sc, child, portid)) == NULL)
361 if ((cdev = device_add_child(dev, NULL, -1)) == NULL) {
362 device_printf(dev, "<%s>: device_add_child failed\n",
363 udi->udi_obdinfo.obd_name);
364 upa_destroy_dinfo(udi);
367 device_set_ivars(cdev, udi);
370 return (bus_generic_attach(dev));
373 for (i = UPA_CFG; i <= UPA_IMR2 && sc->sc_res[i] != NULL; i++)
374 bus_release_resource(dev, SYS_RES_MEMORY,
375 rman_get_rid(sc->sc_res[i]), sc->sc_res[i]);
380 upa_print_child(device_t dev, device_t child)
384 rv = bus_print_child_header(dev, child);
385 rv += upa_print_res(device_get_ivars(child));
386 rv += bus_print_child_footer(dev, child);
391 upa_probe_nomatch(device_t dev, device_t child)
395 device_printf(dev, "<%s>", ofw_bus_get_name(child));
396 upa_print_res(device_get_ivars(child));
397 type = ofw_bus_get_type(child);
398 printf(" type %s (no driver attached)\n",
399 type != NULL ? type : "unknown");
402 static struct resource *
403 upa_alloc_resource(device_t dev, device_t child, int type, int *rid,
404 u_long start, u_long end, u_long count, u_int flags)
406 struct resource_list *rl;
407 struct resource_list_entry *rle;
408 struct upa_softc *sc;
410 bus_addr_t cend, cstart;
411 int i, isdefault, passthrough;
413 isdefault = (start == 0UL && end == ~0UL);
414 passthrough = (device_get_parent(child) != dev);
415 sc = device_get_softc(dev);
416 rl = BUS_GET_RESOURCE_LIST(dev, child);
420 return (resource_list_alloc(rl, dev, child, type, rid, start,
424 rle = resource_list_find(rl, type, *rid);
427 if (rle->res != NULL)
428 panic("%s: resource entry is busy", __func__);
431 count = ulmax(count, rle->count);
432 end = ulmax(rle->end, start + count - 1);
435 for (i = 0; i < sc->sc_nrange; i++) {
436 cstart = sc->sc_ranges[i].child;
437 cend = cstart + sc->sc_ranges[i].size - 1;
438 if (start < cstart || start > cend)
440 if (end < cstart || end > cend)
442 start += sc->sc_ranges[i].parent - cstart;
443 end += sc->sc_ranges[i].parent - cstart;
444 rv = bus_generic_alloc_resource(dev, child, type, rid,
445 start, end, count, flags);
457 upa_intr_enable(void *arg)
459 struct intr_vector *iv = arg;
460 struct upa_icarg *uica = iv->iv_icarg;
462 UPA_WRITE(uica->uica_sc, uica->uica_imr, 0x0,
463 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid));
464 (void)UPA_READ(uica->uica_sc, uica->uica_imr, 0x0);
468 upa_intr_disable(void *arg)
470 struct intr_vector *iv = arg;
471 struct upa_icarg *uica = iv->iv_icarg;
473 UPA_WRITE(uica->uica_sc, uica->uica_imr, 0x0, iv->iv_vec);
474 (void)UPA_READ(uica->uica_sc, uica->uica_imr, 0x0);
478 upa_intr_assign(void *arg)
480 struct intr_vector *iv = arg;
481 struct upa_icarg *uica = iv->iv_icarg;
483 UPA_WRITE(uica->uica_sc, uica->uica_imr, 0x0, INTMAP_TID(
484 UPA_READ(uica->uica_sc, uica->uica_imr, 0x0), iv->iv_mid));
485 (void)UPA_READ(uica->uica_sc, uica->uica_imr, 0x0);
489 upa_setup_intr(device_t dev, device_t child, struct resource *ires, int flags,
490 driver_filter_t *filt, driver_intr_t *func, void *arg, void **cookiep)
492 struct upa_softc *sc;
495 sc = device_get_softc(dev);
497 * Make sure the vector is fully specified and we registered
498 * our interrupt controller for it.
500 vec = rman_get_start(ires);
501 if (INTIGN(vec) != sc->sc_ign || intr_vectors[vec].iv_ic != &upa_ic) {
502 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec);
505 return (bus_generic_setup_intr(dev, child, ires, flags, filt, func,
509 static struct resource_list *
510 upa_get_resource_list(device_t dev, device_t child)
512 struct upa_devinfo *udi;
514 udi = device_get_ivars(child);
515 return (&udi->udi_rl);
518 static const struct ofw_bus_devinfo *
519 upa_get_devinfo(device_t dev, device_t child)
521 struct upa_devinfo *udi;
523 udi = device_get_ivars(child);
524 return (&udi->udi_obdinfo);
527 static struct upa_devinfo *
528 upa_setup_dinfo(device_t dev, struct upa_softc *sc, phandle_t node,
531 struct upa_devinfo *udi;
532 struct upa_regs *reg;
536 udi = malloc(sizeof(*udi), M_DEVBUF, M_WAITOK | M_ZERO);
537 if (ofw_bus_gen_setup_devinfo(&udi->udi_obdinfo, node) != 0) {
541 resource_list_init(&udi->udi_rl);
543 nreg = OF_getprop_alloc(node, "reg", sizeof(*reg), (void **)®);
545 device_printf(dev, "<%s>: incomplete\n",
546 udi->udi_obdinfo.obd_name);
549 for (i = 0; i < nreg; i++)
550 resource_list_add(&udi->udi_rl, SYS_RES_MEMORY, i, reg[i].phys,
551 reg[i].phys + reg[i].size - 1, reg[i].size);
552 free(reg, M_OFWPROP);
554 intr = INTMAP_VEC(sc->sc_ign, (UPA_INO_BASE + portid));
555 resource_list_add(&udi->udi_rl, SYS_RES_IRQ, 0, intr, intr, 1);
560 upa_destroy_dinfo(udi);
565 upa_destroy_dinfo(struct upa_devinfo *dinfo)
568 resource_list_free(&dinfo->udi_rl);
569 ofw_bus_gen_destroy_devinfo(&dinfo->udi_obdinfo);
570 free(dinfo, M_DEVBUF);
574 upa_print_res(struct upa_devinfo *udi)
579 rv += resource_list_print_type(&udi->udi_rl, "mem", SYS_RES_MEMORY,
581 rv += resource_list_print_type(&udi->udi_rl, "irq", SYS_RES_IRQ,