2 * Copyright (c) 2009 Hudson River Trading LLC
3 * Written by: John H. Baldwin <jhb@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Support for x86 machine check architecture.
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
41 #include <sys/param.h>
43 #include <sys/interrupt.h>
44 #include <sys/kernel.h>
46 #include <sys/malloc.h>
47 #include <sys/mutex.h>
49 #include <sys/sched.h>
51 #include <sys/sysctl.h>
52 #include <sys/systm.h>
53 #include <sys/taskqueue.h>
54 #include <machine/intr_machdep.h>
55 #include <machine/apicvar.h>
56 #include <machine/cpu.h>
57 #include <machine/cputypes.h>
58 #include <machine/mca.h>
59 #include <machine/md_var.h>
60 #include <machine/specialreg.h>
62 /* Modes for mca_scan() */
71 * State maintained for each monitored MCx bank to control the
72 * corrected machine check interrupt threshold.
81 struct mca_record rec;
83 STAILQ_ENTRY(mca_internal) link;
86 static MALLOC_DEFINE(M_MCA, "MCA", "Machine Check Architecture");
88 static volatile int mca_count; /* Number of records stored. */
89 static int mca_banks; /* Number of per-CPU register banks. */
91 SYSCTL_NODE(_hw, OID_AUTO, mca, CTLFLAG_RD, NULL, "Machine Check Architecture");
93 static int mca_enabled = 1;
94 TUNABLE_INT("hw.mca.enabled", &mca_enabled);
95 SYSCTL_INT(_hw_mca, OID_AUTO, enabled, CTLFLAG_RDTUN, &mca_enabled, 0,
96 "Administrative toggle for machine check support");
98 static int amd10h_L1TP = 1;
99 TUNABLE_INT("hw.mca.amd10h_L1TP", &amd10h_L1TP);
100 SYSCTL_INT(_hw_mca, OID_AUTO, amd10h_L1TP, CTLFLAG_RDTUN, &amd10h_L1TP, 0,
101 "Administrative toggle for logging of level one TLB parity (L1TP) errors");
103 static int intel6h_HSD131;
104 TUNABLE_INT("hw.mca.intel6h_hsd131", &intel6h_HSD131);
105 SYSCTL_INT(_hw_mca, OID_AUTO, intel6h_HSD131, CTLFLAG_RDTUN, &intel6h_HSD131, 0,
106 "Administrative toggle for logging of spurious corrected errors");
108 int workaround_erratum383;
109 SYSCTL_INT(_hw_mca, OID_AUTO, erratum383, CTLFLAG_RD, &workaround_erratum383, 0,
110 "Is the workaround for Erratum 383 on AMD Family 10h processors enabled?");
112 static STAILQ_HEAD(, mca_internal) mca_freelist;
113 static int mca_freecount;
114 static STAILQ_HEAD(, mca_internal) mca_records;
115 static struct callout mca_timer;
116 static int mca_ticks = 3600; /* Check hourly by default. */
117 static struct taskqueue *mca_tq;
118 static struct task mca_refill_task, mca_scan_task;
119 static struct mtx mca_lock;
122 static struct cmc_state **cmc_state; /* Indexed by cpuid, bank */
123 static int cmc_throttle = 60; /* Time in seconds to throttle CMCI. */
127 sysctl_positive_int(SYSCTL_HANDLER_ARGS)
131 value = *(int *)arg1;
132 error = sysctl_handle_int(oidp, &value, 0, req);
133 if (error || req->newptr == NULL)
137 *(int *)arg1 = value;
142 sysctl_mca_records(SYSCTL_HANDLER_ARGS)
144 int *name = (int *)arg1;
145 u_int namelen = arg2;
146 struct mca_record record;
147 struct mca_internal *rec;
153 if (name[0] < 0 || name[0] >= mca_count)
156 mtx_lock_spin(&mca_lock);
157 if (name[0] >= mca_count) {
158 mtx_unlock_spin(&mca_lock);
162 STAILQ_FOREACH(rec, &mca_records, link) {
169 mtx_unlock_spin(&mca_lock);
170 return (SYSCTL_OUT(req, &record, sizeof(record)));
174 mca_error_ttype(uint16_t mca_error)
177 switch ((mca_error & 0x000c) >> 2) {
189 mca_error_level(uint16_t mca_error)
192 switch (mca_error & 0x0003) {
206 mca_error_request(uint16_t mca_error)
209 switch ((mca_error & 0x00f0) >> 4) {
233 mca_error_mmtype(uint16_t mca_error)
236 switch ((mca_error & 0x70) >> 4) {
251 static int __nonnull(1)
252 mca_mute(const struct mca_record *rec)
256 * Skip spurious corrected parity errors generated by desktop Haswell
257 * (see HSD131 erratum) unless reporting is enabled.
258 * Note that these errors also have been observed with D0-stepping,
259 * while the revision 014 desktop Haswell specification update only
260 * talks about C0-stepping.
262 if (rec->mr_cpu_vendor_id == CPU_VENDOR_INTEL &&
263 rec->mr_cpu_id == 0x306c3 && rec->mr_bank == 0 &&
264 rec->mr_status == 0x90000040000f0005 && !intel6h_HSD131)
270 /* Dump details about a single machine check. */
271 static void __nonnull(1)
272 mca_log(const struct mca_record *rec)
279 printf("MCA: Bank %d, Status 0x%016llx\n", rec->mr_bank,
280 (long long)rec->mr_status);
281 printf("MCA: Global Cap 0x%016llx, Status 0x%016llx\n",
282 (long long)rec->mr_mcg_cap, (long long)rec->mr_mcg_status);
283 printf("MCA: Vendor \"%s\", ID 0x%x, APIC ID %d\n", cpu_vendor,
284 rec->mr_cpu_id, rec->mr_apic_id);
285 printf("MCA: CPU %d ", rec->mr_cpu);
286 if (rec->mr_status & MC_STATUS_UC)
290 if (rec->mr_mcg_cap & MCG_CAP_CMCI_P)
291 printf("(%lld) ", ((long long)rec->mr_status &
292 MC_STATUS_COR_COUNT) >> 38);
294 if (rec->mr_status & MC_STATUS_PCC)
296 if (rec->mr_status & MC_STATUS_OVER)
298 mca_error = rec->mr_status & MC_STATUS_MCA_ERROR;
300 /* Simple error codes. */
305 printf("unclassified error");
308 printf("ucode ROM parity error");
311 printf("external error");
317 printf("internal parity error");
320 printf("internal timer error");
323 if ((mca_error & 0xfc00) == 0x0400) {
324 printf("internal error %x", mca_error & 0x03ff);
328 /* Compound error codes. */
330 /* Memory hierarchy error. */
331 if ((mca_error & 0xeffc) == 0x000c) {
332 printf("%s memory error", mca_error_level(mca_error));
337 if ((mca_error & 0xeff0) == 0x0010) {
338 printf("%sTLB %s error", mca_error_ttype(mca_error),
339 mca_error_level(mca_error));
343 /* Memory controller error. */
344 if ((mca_error & 0xef80) == 0x0080) {
345 printf("%s channel ", mca_error_mmtype(mca_error));
346 if ((mca_error & 0x000f) != 0x000f)
347 printf("%d", mca_error & 0x000f);
350 printf(" memory error");
355 if ((mca_error & 0xef00) == 0x0100) {
356 printf("%sCACHE %s %s error",
357 mca_error_ttype(mca_error),
358 mca_error_level(mca_error),
359 mca_error_request(mca_error));
363 /* Bus and/or Interconnect error. */
364 if ((mca_error & 0xe800) == 0x0800) {
365 printf("BUS%s ", mca_error_level(mca_error));
366 switch ((mca_error & 0x0600) >> 9) {
380 printf(" %s ", mca_error_request(mca_error));
381 switch ((mca_error & 0x000c) >> 2) {
395 if (mca_error & 0x0100)
396 printf(" timed out");
400 printf("unknown error %x", mca_error);
404 if (rec->mr_status & MC_STATUS_ADDRV)
405 printf("MCA: Address 0x%llx\n", (long long)rec->mr_addr);
406 if (rec->mr_status & MC_STATUS_MISCV)
407 printf("MCA: Misc 0x%llx\n", (long long)rec->mr_misc);
410 static int __nonnull(2)
411 mca_check_status(int bank, struct mca_record *rec)
416 status = rdmsr(MSR_MC_STATUS(bank));
417 if (!(status & MC_STATUS_VAL))
420 /* Save exception information. */
421 rec->mr_status = status;
424 if (status & MC_STATUS_ADDRV)
425 rec->mr_addr = rdmsr(MSR_MC_ADDR(bank));
427 if (status & MC_STATUS_MISCV)
428 rec->mr_misc = rdmsr(MSR_MC_MISC(bank));
429 rec->mr_tsc = rdtsc();
430 rec->mr_apic_id = PCPU_GET(apic_id);
431 rec->mr_mcg_cap = rdmsr(MSR_MCG_CAP);
432 rec->mr_mcg_status = rdmsr(MSR_MCG_STATUS);
433 rec->mr_cpu_id = cpu_id;
434 rec->mr_cpu_vendor_id = cpu_vendor_id;
435 rec->mr_cpu = PCPU_GET(cpuid);
438 * Clear machine check. Don't do this for uncorrectable
439 * errors so that the BIOS can see them.
441 if (!(rec->mr_status & (MC_STATUS_PCC | MC_STATUS_UC))) {
442 wrmsr(MSR_MC_STATUS(bank), 0);
449 mca_fill_freelist(void)
451 struct mca_internal *rec;
455 * Ensure we have at least one record for each bank and one
458 desired = imax(mp_ncpus, mca_banks);
459 mtx_lock_spin(&mca_lock);
460 while (mca_freecount < desired) {
461 mtx_unlock_spin(&mca_lock);
462 rec = malloc(sizeof(*rec), M_MCA, M_WAITOK);
463 mtx_lock_spin(&mca_lock);
464 STAILQ_INSERT_TAIL(&mca_freelist, rec, link);
467 mtx_unlock_spin(&mca_lock);
471 mca_refill(void *context, int pending)
477 static void __nonnull(2)
478 mca_record_entry(enum scan_mode mode, const struct mca_record *record)
480 struct mca_internal *rec;
482 if (mode == POLLED) {
483 rec = malloc(sizeof(*rec), M_MCA, M_WAITOK);
484 mtx_lock_spin(&mca_lock);
486 mtx_lock_spin(&mca_lock);
487 rec = STAILQ_FIRST(&mca_freelist);
489 printf("MCA: Unable to allocate space for an event.\n");
491 mtx_unlock_spin(&mca_lock);
494 STAILQ_REMOVE_HEAD(&mca_freelist, link);
500 STAILQ_INSERT_TAIL(&mca_records, rec, link);
502 mtx_unlock_spin(&mca_lock);
504 taskqueue_enqueue_fast(mca_tq, &mca_refill_task);
509 * Update the interrupt threshold for a CMCI. The strategy is to use
510 * a low trigger that interrupts as soon as the first event occurs.
511 * However, if a steady stream of events arrive, the threshold is
512 * increased until the interrupts are throttled to once every
513 * cmc_throttle seconds or the periodic scan. If a periodic scan
514 * finds that the threshold is too high, it is lowered.
517 cmci_update(enum scan_mode mode, int bank, int valid, struct mca_record *rec)
519 struct cmc_state *cc;
524 /* Fetch the current limit for this bank. */
525 cc = &cmc_state[PCPU_GET(cpuid)][bank];
526 ctl = rdmsr(MSR_MC_CTL2(bank));
527 count = (rec->mr_status & MC_STATUS_COR_COUNT) >> 38;
528 delta = (u_int)(ticks - cc->last_intr);
531 * If an interrupt was received less than cmc_throttle seconds
532 * since the previous interrupt and the count from the current
533 * event is greater than or equal to the current threshold,
534 * double the threshold up to the max.
536 if (mode == CMCI && valid) {
537 limit = ctl & MC_CTL2_THRESHOLD;
538 if (delta < cmc_throttle && count >= limit &&
539 limit < cc->max_threshold) {
540 limit = min(limit << 1, cc->max_threshold);
541 ctl &= ~MC_CTL2_THRESHOLD;
543 wrmsr(MSR_MC_CTL2(bank), limit);
545 cc->last_intr = ticks;
550 * When the banks are polled, check to see if the threshold
556 /* If a CMCI occured recently, do nothing for now. */
557 if (delta < cmc_throttle)
561 * Compute a new limit based on the average rate of events per
562 * cmc_throttle seconds since the last interrupt.
565 count = (rec->mr_status & MC_STATUS_COR_COUNT) >> 38;
566 limit = count * cmc_throttle / delta;
569 else if (limit > cc->max_threshold)
570 limit = cc->max_threshold;
573 if ((ctl & MC_CTL2_THRESHOLD) != limit) {
574 ctl &= ~MC_CTL2_THRESHOLD;
576 wrmsr(MSR_MC_CTL2(bank), limit);
582 * This scans all the machine check banks of the current CPU to see if
583 * there are any machine checks. Any non-recoverable errors are
584 * reported immediately via mca_log(). The current thread must be
585 * pinned when this is called. The 'mode' parameter indicates if we
586 * are being called from the MC exception handler, the CMCI handler,
587 * or the periodic poller. In the MC exception case this function
588 * returns true if the system is restartable. Otherwise, it returns a
589 * count of the number of valid MC records found.
592 mca_scan(enum scan_mode mode)
594 struct mca_record rec;
595 uint64_t mcg_cap, ucmask;
596 int count, i, recoverable, valid;
600 ucmask = MC_STATUS_UC | MC_STATUS_PCC;
602 /* When handling a MCE#, treat the OVER flag as non-restartable. */
604 ucmask |= MC_STATUS_OVER;
605 mcg_cap = rdmsr(MSR_MCG_CAP);
606 for (i = 0; i < (mcg_cap & MCG_CAP_COUNT); i++) {
609 * For a CMCI, only check banks this CPU is
612 if (mode == CMCI && !(PCPU_GET(cmci_mask) & 1 << i))
616 valid = mca_check_status(i, &rec);
619 if (rec.mr_status & ucmask) {
621 mtx_lock_spin(&mca_lock);
623 mtx_unlock_spin(&mca_lock);
625 mca_record_entry(mode, &rec);
630 * If this is a bank this CPU monitors via CMCI,
631 * update the threshold.
633 if (PCPU_GET(cmci_mask) & 1 << i)
634 cmci_update(mode, i, valid, &rec);
639 return (mode == MCE ? recoverable : count);
643 * Scan the machine check banks on all CPUs by binding to each CPU in
644 * turn. If any of the CPUs contained new machine check records, log
645 * them to the console.
648 mca_scan_cpus(void *context, int pending)
650 struct mca_internal *mca;
661 count += mca_scan(POLLED);
667 mtx_lock_spin(&mca_lock);
668 STAILQ_FOREACH(mca, &mca_records, link) {
674 mtx_unlock_spin(&mca_lock);
679 mca_periodic_scan(void *arg)
682 taskqueue_enqueue_fast(mca_tq, &mca_scan_task);
683 callout_reset(&mca_timer, mca_ticks * hz, mca_periodic_scan, NULL);
687 sysctl_mca_scan(SYSCTL_HANDLER_ARGS)
692 error = sysctl_handle_int(oidp, &i, 0, req);
696 taskqueue_enqueue_fast(mca_tq, &mca_scan_task);
701 mca_createtq(void *dummy)
706 mca_tq = taskqueue_create_fast("mca", M_WAITOK,
707 taskqueue_thread_enqueue, &mca_tq);
708 taskqueue_start_threads(&mca_tq, 1, PI_SWI(SWI_TQ), "mca taskq");
710 SYSINIT(mca_createtq, SI_SUB_CONFIGURE, SI_ORDER_ANY, mca_createtq, NULL);
713 mca_startup(void *dummy)
719 callout_reset(&mca_timer, mca_ticks * hz, mca_periodic_scan, NULL);
721 SYSINIT(mca_startup, SI_SUB_SMP, SI_ORDER_ANY, mca_startup, NULL);
729 cmc_state = malloc((mp_maxid + 1) * sizeof(struct cmc_state *), M_MCA,
731 for (i = 0; i <= mp_maxid; i++)
732 cmc_state[i] = malloc(sizeof(struct cmc_state) * mca_banks,
733 M_MCA, M_WAITOK | M_ZERO);
734 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
735 "cmc_throttle", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
736 &cmc_throttle, 0, sysctl_positive_int, "I",
737 "Interval in seconds to throttle corrected MC interrupts");
742 mca_setup(uint64_t mcg_cap)
746 * On AMD Family 10h processors, unless logging of level one TLB
747 * parity (L1TP) errors is disabled, enable the recommended workaround
750 if (cpu_vendor_id == CPU_VENDOR_AMD &&
751 CPUID_TO_FAMILY(cpu_id) == 0x10 && amd10h_L1TP)
752 workaround_erratum383 = 1;
754 mca_banks = mcg_cap & MCG_CAP_COUNT;
755 mtx_init(&mca_lock, "mca", NULL, MTX_SPIN);
756 STAILQ_INIT(&mca_records);
757 TASK_INIT(&mca_scan_task, 0, mca_scan_cpus, NULL);
758 callout_init(&mca_timer, CALLOUT_MPSAFE);
759 STAILQ_INIT(&mca_freelist);
760 TASK_INIT(&mca_refill_task, 0, mca_refill, NULL);
762 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
763 "count", CTLFLAG_RD, (int *)(uintptr_t)&mca_count, 0,
765 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
766 "interval", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, &mca_ticks,
767 0, sysctl_positive_int, "I",
768 "Periodic interval in seconds to scan for machine checks");
769 SYSCTL_ADD_NODE(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
770 "records", CTLFLAG_RD, sysctl_mca_records, "Machine check records");
771 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
772 "force_scan", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, NULL, 0,
773 sysctl_mca_scan, "I", "Force an immediate scan for machine checks");
775 if (mcg_cap & MCG_CAP_CMCI_P)
782 * See if we should monitor CMCI for this bank. If CMCI_EN is already
783 * set in MC_CTL2, then another CPU is responsible for this bank, so
784 * ignore it. If CMCI_EN returns zero after being set, then this bank
785 * does not support CMCI_EN. If this CPU sets CMCI_EN, then it should
786 * now monitor this bank.
791 struct cmc_state *cc;
794 KASSERT(i < mca_banks, ("CPU %d has more MC banks", PCPU_GET(cpuid)));
796 ctl = rdmsr(MSR_MC_CTL2(i));
797 if (ctl & MC_CTL2_CMCI_EN)
798 /* Already monitored by another CPU. */
801 /* Set the threshold to one event for now. */
802 ctl &= ~MC_CTL2_THRESHOLD;
803 ctl |= MC_CTL2_CMCI_EN | 1;
804 wrmsr(MSR_MC_CTL2(i), ctl);
805 ctl = rdmsr(MSR_MC_CTL2(i));
806 if (!(ctl & MC_CTL2_CMCI_EN))
807 /* This bank does not support CMCI. */
810 cc = &cmc_state[PCPU_GET(cpuid)][i];
812 /* Determine maximum threshold. */
813 ctl &= ~MC_CTL2_THRESHOLD;
815 wrmsr(MSR_MC_CTL2(i), ctl);
816 ctl = rdmsr(MSR_MC_CTL2(i));
817 cc->max_threshold = ctl & MC_CTL2_THRESHOLD;
819 /* Start off with a threshold of 1. */
820 ctl &= ~MC_CTL2_THRESHOLD;
822 wrmsr(MSR_MC_CTL2(i), ctl);
824 /* Mark this bank as monitored. */
825 PCPU_SET(cmci_mask, PCPU_GET(cmci_mask) | 1 << i);
829 * For resume, reset the threshold for any banks we monitor back to
830 * one and throw away the timestamp of the last interrupt.
835 struct cmc_state *cc;
838 KASSERT(i < mca_banks, ("CPU %d has more MC banks", PCPU_GET(cpuid)));
840 /* Ignore banks not monitored by this CPU. */
841 if (!(PCPU_GET(cmci_mask) & 1 << i))
844 cc = &cmc_state[PCPU_GET(cpuid)][i];
845 cc->last_intr = -ticks;
846 ctl = rdmsr(MSR_MC_CTL2(i));
847 ctl &= ~MC_CTL2_THRESHOLD;
848 ctl |= MC_CTL2_CMCI_EN | 1;
849 wrmsr(MSR_MC_CTL2(i), ctl);
854 * Initializes per-CPU machine check registers and enables corrected
855 * machine check interrupts.
864 /* MCE is required. */
865 if (!mca_enabled || !(cpu_feature & CPUID_MCE))
868 if (cpu_feature & CPUID_MCA) {
870 PCPU_SET(cmci_mask, 0);
872 mcg_cap = rdmsr(MSR_MCG_CAP);
873 if (mcg_cap & MCG_CAP_CTL_P)
874 /* Enable MCA features. */
875 wrmsr(MSR_MCG_CTL, MCG_CTL_ENABLE);
876 if (PCPU_GET(cpuid) == 0 && boot)
880 * Disable logging of level one TLB parity (L1TP) errors by
881 * the data cache as an alternative workaround for AMD Family
882 * 10h Erratum 383. Unlike the recommended workaround, there
883 * is no performance penalty to this workaround. However,
884 * L1TP errors will go unreported.
886 if (cpu_vendor_id == CPU_VENDOR_AMD &&
887 CPUID_TO_FAMILY(cpu_id) == 0x10 && !amd10h_L1TP) {
888 mask = rdmsr(MSR_MC0_CTL_MASK);
889 if ((mask & (1UL << 5)) == 0)
890 wrmsr(MSR_MC0_CTL_MASK, mask | (1UL << 5));
892 for (i = 0; i < (mcg_cap & MCG_CAP_COUNT); i++) {
893 /* By default enable logging of all errors. */
894 ctl = 0xffffffffffffffffUL;
897 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
899 * For P6 models before Nehalem MC0_CTL is
900 * always enabled and reserved.
902 if (i == 0 && CPUID_TO_FAMILY(cpu_id) == 0x6
903 && CPUID_TO_MODEL(cpu_id) < 0x1a)
905 } else if (cpu_vendor_id == CPU_VENDOR_AMD) {
906 /* BKDG for Family 10h: unset GartTblWkEn. */
907 if (i == 4 && CPUID_TO_FAMILY(cpu_id) >= 0xf)
912 wrmsr(MSR_MC_CTL(i), ctl);
915 if (mcg_cap & MCG_CAP_CMCI_P) {
923 /* Clear all errors. */
924 wrmsr(MSR_MC_STATUS(i), 0);
928 if (PCPU_GET(cmci_mask) != 0 && boot)
933 load_cr4(rcr4() | CR4_MCE);
936 /* Must be executed on each CPU during boot. */
944 /* Must be executed on each CPU during resume. */
953 * The machine check registers for the BSP cannot be initialized until
954 * the local APIC is initialized. This happens at SI_SUB_CPU,
958 mca_init_bsp(void *arg __unused)
963 SYSINIT(mca_init_bsp, SI_SUB_CPU, SI_ORDER_ANY, mca_init_bsp, NULL);
965 /* Called when a machine check exception fires. */
970 int old_count, recoverable;
972 if (!(cpu_feature & CPUID_MCA)) {
974 * Just print the values of the old Pentium registers
977 printf("MC Type: 0x%jx Address: 0x%jx\n",
978 (uintmax_t)rdmsr(MSR_P5_MC_TYPE),
979 (uintmax_t)rdmsr(MSR_P5_MC_ADDR));
980 panic("Machine check");
983 /* Scan the banks and check for any non-recoverable errors. */
984 old_count = mca_count;
985 recoverable = mca_scan(MCE);
986 mcg_status = rdmsr(MSR_MCG_STATUS);
987 if (!(mcg_status & MCG_STATUS_RIPV))
992 * Wait for at least one error to be logged before
993 * panic'ing. Some errors will assert a machine check
994 * on all CPUs, but only certain CPUs will find a valid
997 while (mca_count == old_count)
1000 panic("Unrecoverable machine check exception");
1004 wrmsr(MSR_MCG_STATUS, mcg_status & ~MCG_STATUS_MCIP);
1008 /* Called for a CMCI (correctable machine check interrupt). */
1012 struct mca_internal *mca;
1016 * Serialize MCA bank scanning to prevent collisions from
1019 count = mca_scan(CMCI);
1021 /* If we found anything, log them to the console. */
1023 mtx_lock_spin(&mca_lock);
1024 STAILQ_FOREACH(mca, &mca_records, link) {
1030 mtx_unlock_spin(&mca_lock);