1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand has floating-point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisVec - The specified operand has a vector type.
40 class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>;
42 // SDTCisSameAs - The two specified operands have identical types.
43 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
44 int OtherOperandNum = OtherOp;
47 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
48 // smaller than the 'Other' operand.
49 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
50 int OtherOperandNum = OtherOp;
53 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
54 int BigOperandNum = BigOp;
57 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
58 /// type as the element type of OtherOp, which is a vector type.
59 class SDTCisEltOfVec<int ThisOp, int OtherOp>
60 : SDTypeConstraint<ThisOp> {
61 int OtherOpNum = OtherOp;
64 /// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type
65 /// with length less that of OtherOp, which is a vector type.
66 class SDTCisSubVecOfVec<int ThisOp, int OtherOp>
67 : SDTypeConstraint<ThisOp> {
68 int OtherOpNum = OtherOp;
71 //===----------------------------------------------------------------------===//
72 // Selection DAG Type Profile definitions.
74 // These use the constraints defined above to describe the type requirements of
75 // the various nodes. These are not hard coded into tblgen, allowing targets to
76 // add their own if needed.
79 // SDTypeProfile - This profile describes the type requirements of a Selection
81 class SDTypeProfile<int numresults, int numoperands,
82 list<SDTypeConstraint> constraints> {
83 int NumResults = numresults;
84 int NumOperands = numoperands;
85 list<SDTypeConstraint> Constraints = constraints;
89 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
90 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
91 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
92 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
93 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
94 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert.
96 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
97 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
99 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
100 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
102 def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem
103 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0>
106 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
107 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
109 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
110 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
112 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
113 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
115 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
116 SDTCisSameAs<0, 1>, SDTCisInt<0>
118 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
119 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
121 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
122 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
124 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
125 SDTCisSameAs<0, 1>, SDTCisFP<0>
127 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
128 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
130 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
131 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
133 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
134 SDTCisFP<0>, SDTCisInt<1>
136 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
137 SDTCisInt<0>, SDTCisFP<1>
139 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
140 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
141 SDTCisVTSmallerThanOp<2, 1>
144 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
145 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
148 def SDTSelect : SDTypeProfile<1, 3, [ // select
149 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
152 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
153 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
157 def SDTBr : SDTypeProfile<0, 1, [ // br
161 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
162 SDTCisInt<0>, SDTCisVT<1, OtherVT>
165 def SDTBrind : SDTypeProfile<0, 1, [ // brind
169 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
171 def SDTLoad : SDTypeProfile<1, 1, [ // load
175 def SDTStore : SDTypeProfile<0, 2, [ // store
179 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
180 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
183 def SDTVecShuffle : SDTypeProfile<1, 2, [
184 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
186 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
187 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
189 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
190 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
193 def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract
194 SDTCisSubVecOfVec<0,1>, SDTCisInt<2>
196 def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert
197 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3>
200 def SDTPrefetch : SDTypeProfile<0, 4, [ // prefetch
201 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisInt<1>
204 def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barier
205 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
208 def SDTAtomic3 : SDTypeProfile<1, 3, [
209 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1>
211 def SDTAtomic2 : SDTypeProfile<1, 2, [
212 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1>
215 def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su
216 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5>
219 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
220 SDTypeProfile<0, 1, constraints>;
221 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
222 SDTypeProfile<0, 2, constraints>;
224 //===----------------------------------------------------------------------===//
225 // Selection DAG Node Properties.
227 // Note: These are hard coded into tblgen.
229 class SDNodeProperty;
230 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
231 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
232 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
233 def SDNPOutGlue : SDNodeProperty; // Write a flag result
234 def SDNPInGlue : SDNodeProperty; // Read a flag operand
235 def SDNPOptInGlue : SDNodeProperty; // Optionally read a flag operand
236 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
237 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
238 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
239 def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand
240 def SDNPVariadic : SDNodeProperty; // Node has variable arguments.
241 def SDNPWantRoot : SDNodeProperty; // ComplexPattern gets the root of match
242 def SDNPWantParent : SDNodeProperty; // ComplexPattern gets the parent
244 //===----------------------------------------------------------------------===//
245 // Selection DAG Pattern Operations
246 class SDPatternOperator;
248 //===----------------------------------------------------------------------===//
249 // Selection DAG Node definitions.
251 class SDNode<string opcode, SDTypeProfile typeprof,
252 list<SDNodeProperty> props = [], string sdclass = "SDNode">
253 : SDPatternOperator {
254 string Opcode = opcode;
255 string SDClass = sdclass;
256 list<SDNodeProperty> Properties = props;
257 SDTypeProfile TypeProfile = typeprof;
260 // Special TableGen-recognized dag nodes
266 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
267 def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">;
268 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
269 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
270 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
271 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
272 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
273 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
274 "GlobalAddressSDNode">;
275 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
276 "GlobalAddressSDNode">;
277 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
278 "GlobalAddressSDNode">;
279 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
280 "GlobalAddressSDNode">;
281 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
282 "ConstantPoolSDNode">;
283 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
284 "ConstantPoolSDNode">;
285 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
287 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
289 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
291 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
293 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
294 "ExternalSymbolSDNode">;
295 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
296 "ExternalSymbolSDNode">;
297 def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [],
298 "BlockAddressSDNode">;
299 def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [],
300 "BlockAddressSDNode">;
302 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
303 [SDNPCommutative, SDNPAssociative]>;
304 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
305 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
306 [SDNPCommutative, SDNPAssociative]>;
307 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
308 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
309 def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>;
310 def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>;
311 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
312 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
313 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
314 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
315 def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>;
316 def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>;
317 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
318 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
319 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
320 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
321 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
322 def and : SDNode<"ISD::AND" , SDTIntBinOp,
323 [SDNPCommutative, SDNPAssociative]>;
324 def or : SDNode<"ISD::OR" , SDTIntBinOp,
325 [SDNPCommutative, SDNPAssociative]>;
326 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
327 [SDNPCommutative, SDNPAssociative]>;
328 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
329 [SDNPCommutative, SDNPOutGlue]>;
330 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
331 [SDNPCommutative, SDNPOutGlue, SDNPInGlue]>;
332 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
334 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
335 [SDNPOutGlue, SDNPInGlue]>;
337 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
338 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
339 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
340 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
341 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
342 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
343 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
344 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
345 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
346 def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>;
347 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
348 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
351 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
352 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
353 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
354 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
355 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
356 def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp>;
357 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
358 def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>;
359 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
360 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
361 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
362 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
363 def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>;
364 def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>;
365 def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;
366 def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>;
367 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
368 def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>;
369 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
371 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
372 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
373 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
375 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
376 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
377 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
378 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
379 def f16_to_f32 : SDNode<"ISD::FP16_TO_FP32", SDTIntToFPOp>;
380 def f32_to_f16 : SDNode<"ISD::FP32_TO_FP16", SDTFPToIntOp>;
382 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
383 def select : SDNode<"ISD::SELECT" , SDTSelect>;
384 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
385 def vsetcc : SDNode<"ISD::VSETCC" , SDTSetCC>;
387 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
388 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
389 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
390 def trap : SDNode<"ISD::TRAP" , SDTNone,
391 [SDNPHasChain, SDNPSideEffect]>;
393 def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch,
394 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
397 def membarrier : SDNode<"ISD::MEMBARRIER" , SDTMemBarrier,
398 [SDNPHasChain, SDNPSideEffect]>;
400 def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3,
401 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
402 def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2,
403 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
404 def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", SDTAtomic2,
405 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
406 def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , SDTAtomic2,
407 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
408 def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , SDTAtomic2,
409 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
410 def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , SDTAtomic2,
411 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
412 def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , SDTAtomic2,
413 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
414 def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2,
415 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
416 def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2,
417 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
418 def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2,
419 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
420 def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2,
421 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
422 def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2,
423 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
425 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
426 // and truncst (see below).
427 def ld : SDNode<"ISD::LOAD" , SDTLoad,
428 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
429 def st : SDNode<"ISD::STORE" , SDTStore,
430 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
431 def ist : SDNode<"ISD::STORE" , SDTIStore,
432 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
434 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
435 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>;
436 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
438 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
439 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
440 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
441 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
443 // This operator does not do subvector type checking. The ARM
444 // backend, at least, needs it.
445 def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR",
446 SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>,
449 // This operator does subvector type checking.
450 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>;
451 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>;
453 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
454 // these internally. Don't reference these directly.
455 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
456 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
458 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
459 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
461 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
462 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
464 // Do not use cvt directly. Use cvt forms below
465 def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>;
467 //===----------------------------------------------------------------------===//
468 // Selection DAG Condition Codes
470 class CondCode; // ISD::CondCode enums
471 def SETOEQ : CondCode; def SETOGT : CondCode;
472 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
473 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
474 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
475 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
477 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
478 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
481 //===----------------------------------------------------------------------===//
482 // Selection DAG Node Transformation Functions.
484 // This mechanism allows targets to manipulate nodes in the output DAG once a
485 // match has been formed. This is typically used to manipulate immediate
488 class SDNodeXForm<SDNode opc, code xformFunction> {
490 code XFormFunction = xformFunction;
493 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
495 //===----------------------------------------------------------------------===//
496 // PatPred Subclasses.
498 // These allow specifying different sorts of predicates that control whether a
503 class CodePatPred<code predicate> : PatPred {
504 code PredicateCode = predicate;
508 //===----------------------------------------------------------------------===//
509 // Selection DAG Pattern Fragments.
511 // Pattern fragments are reusable chunks of dags that match specific things.
512 // They can take arguments and have C++ predicates that control whether they
513 // match. They are intended to make the patterns for common instructions more
514 // compact and readable.
517 /// PatFrag - Represents a pattern fragment. This can match something on the
518 /// DAG, from a single node to multiple nested other fragments.
520 class PatFrag<dag ops, dag frag, code pred = [{}],
521 SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator {
524 code PredicateCode = pred;
525 code ImmediateCode = [{}];
526 SDNodeXForm OperandTransform = xform;
529 // PatLeaf's are pattern fragments that have no operands. This is just a helper
530 // to define immediates and other common things concisely.
531 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
532 : PatFrag<(ops), frag, pred, xform>;
535 // ImmLeaf is a pattern fragment with a constraint on the immediate. The
536 // constraint is a function that is run on the immediate (always with the value
537 // sign extended out to an int64_t) as Imm. For example:
539 // def immSExt8 : ImmLeaf<i16, [{ return (char)Imm == Imm; }]>;
541 // this is a more convenient form to match 'imm' nodes in than PatLeaf and also
542 // is preferred over using PatLeaf because it allows the code generator to
543 // reason more about the constraint.
545 // If FastIsel should ignore all instructions that have an operand of this type,
546 // the FastIselShouldIgnore flag can be set. This is an optimization to reduce
547 // the code size of the generated fast instruction selector.
548 class ImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm>
549 : PatFrag<(ops), (vt imm), [{}], xform> {
550 let ImmediateCode = pred;
551 bit FastIselShouldIgnore = 0;
557 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
558 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
560 def immAllOnesV: PatLeaf<(build_vector), [{
561 return ISD::isBuildVectorAllOnes(N);
563 def immAllZerosV: PatLeaf<(build_vector), [{
564 return ISD::isBuildVectorAllZeros(N);
569 // Other helper fragments.
570 def not : PatFrag<(ops node:$in), (xor node:$in, -1)>;
571 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
572 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
575 def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
576 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
578 def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
579 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
582 // extending load fragments.
583 def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
584 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
586 def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
587 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
589 def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
590 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
593 def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
594 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
596 def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
597 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
599 def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
600 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
602 def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
603 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
605 def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
606 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32;
608 def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
609 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64;
612 def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
613 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
615 def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
616 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
618 def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
619 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
621 def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
622 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
625 def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
626 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
628 def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
629 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
631 def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
632 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
634 def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
635 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
639 def unindexedstore : PatFrag<(ops node:$val, node:$ptr),
640 (st node:$val, node:$ptr), [{
641 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
643 def store : PatFrag<(ops node:$val, node:$ptr),
644 (unindexedstore node:$val, node:$ptr), [{
645 return !cast<StoreSDNode>(N)->isTruncatingStore();
648 // truncstore fragments.
649 def truncstore : PatFrag<(ops node:$val, node:$ptr),
650 (unindexedstore node:$val, node:$ptr), [{
651 return cast<StoreSDNode>(N)->isTruncatingStore();
653 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
654 (truncstore node:$val, node:$ptr), [{
655 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
657 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
658 (truncstore node:$val, node:$ptr), [{
659 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
661 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
662 (truncstore node:$val, node:$ptr), [{
663 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
665 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
666 (truncstore node:$val, node:$ptr), [{
667 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
669 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
670 (truncstore node:$val, node:$ptr), [{
671 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64;
674 // indexed store fragments.
675 def istore : PatFrag<(ops node:$val, node:$base, node:$offset),
676 (ist node:$val, node:$base, node:$offset), [{
677 return !cast<StoreSDNode>(N)->isTruncatingStore();
680 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
681 (istore node:$val, node:$base, node:$offset), [{
682 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
683 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
686 def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset),
687 (ist node:$val, node:$base, node:$offset), [{
688 return cast<StoreSDNode>(N)->isTruncatingStore();
690 def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
691 (itruncstore node:$val, node:$base, node:$offset), [{
692 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
693 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
695 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
696 (pre_truncst node:$val, node:$base, node:$offset), [{
697 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
699 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
700 (pre_truncst node:$val, node:$base, node:$offset), [{
701 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
703 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
704 (pre_truncst node:$val, node:$base, node:$offset), [{
705 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
707 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
708 (pre_truncst node:$val, node:$base, node:$offset), [{
709 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
711 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
712 (pre_truncst node:$val, node:$base, node:$offset), [{
713 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
716 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
717 (istore node:$val, node:$ptr, node:$offset), [{
718 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
719 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
722 def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
723 (itruncstore node:$val, node:$base, node:$offset), [{
724 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
725 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
727 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
728 (post_truncst node:$val, node:$base, node:$offset), [{
729 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
731 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
732 (post_truncst node:$val, node:$base, node:$offset), [{
733 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
735 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
736 (post_truncst node:$val, node:$base, node:$offset), [{
737 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
739 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
740 (post_truncst node:$val, node:$base, node:$offset), [{
741 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
743 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
744 (post_truncst node:$val, node:$base, node:$offset), [{
745 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
748 // setcc convenience fragments.
749 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
750 (setcc node:$lhs, node:$rhs, SETOEQ)>;
751 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
752 (setcc node:$lhs, node:$rhs, SETOGT)>;
753 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
754 (setcc node:$lhs, node:$rhs, SETOGE)>;
755 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
756 (setcc node:$lhs, node:$rhs, SETOLT)>;
757 def setole : PatFrag<(ops node:$lhs, node:$rhs),
758 (setcc node:$lhs, node:$rhs, SETOLE)>;
759 def setone : PatFrag<(ops node:$lhs, node:$rhs),
760 (setcc node:$lhs, node:$rhs, SETONE)>;
761 def seto : PatFrag<(ops node:$lhs, node:$rhs),
762 (setcc node:$lhs, node:$rhs, SETO)>;
763 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
764 (setcc node:$lhs, node:$rhs, SETUO)>;
765 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
766 (setcc node:$lhs, node:$rhs, SETUEQ)>;
767 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
768 (setcc node:$lhs, node:$rhs, SETUGT)>;
769 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
770 (setcc node:$lhs, node:$rhs, SETUGE)>;
771 def setult : PatFrag<(ops node:$lhs, node:$rhs),
772 (setcc node:$lhs, node:$rhs, SETULT)>;
773 def setule : PatFrag<(ops node:$lhs, node:$rhs),
774 (setcc node:$lhs, node:$rhs, SETULE)>;
775 def setune : PatFrag<(ops node:$lhs, node:$rhs),
776 (setcc node:$lhs, node:$rhs, SETUNE)>;
777 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
778 (setcc node:$lhs, node:$rhs, SETEQ)>;
779 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
780 (setcc node:$lhs, node:$rhs, SETGT)>;
781 def setge : PatFrag<(ops node:$lhs, node:$rhs),
782 (setcc node:$lhs, node:$rhs, SETGE)>;
783 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
784 (setcc node:$lhs, node:$rhs, SETLT)>;
785 def setle : PatFrag<(ops node:$lhs, node:$rhs),
786 (setcc node:$lhs, node:$rhs, SETLE)>;
787 def setne : PatFrag<(ops node:$lhs, node:$rhs),
788 (setcc node:$lhs, node:$rhs, SETNE)>;
790 def atomic_cmp_swap_8 :
791 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
792 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
793 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
795 def atomic_cmp_swap_16 :
796 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
797 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
798 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
800 def atomic_cmp_swap_32 :
801 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
802 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
803 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
805 def atomic_cmp_swap_64 :
806 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
807 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
808 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
811 multiclass binary_atomic_op<SDNode atomic_op> {
812 def _8 : PatFrag<(ops node:$ptr, node:$val),
813 (atomic_op node:$ptr, node:$val), [{
814 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
816 def _16 : PatFrag<(ops node:$ptr, node:$val),
817 (atomic_op node:$ptr, node:$val), [{
818 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
820 def _32 : PatFrag<(ops node:$ptr, node:$val),
821 (atomic_op node:$ptr, node:$val), [{
822 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
824 def _64 : PatFrag<(ops node:$ptr, node:$val),
825 (atomic_op node:$ptr, node:$val), [{
826 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
830 defm atomic_load_add : binary_atomic_op<atomic_load_add>;
831 defm atomic_swap : binary_atomic_op<atomic_swap>;
832 defm atomic_load_sub : binary_atomic_op<atomic_load_sub>;
833 defm atomic_load_and : binary_atomic_op<atomic_load_and>;
834 defm atomic_load_or : binary_atomic_op<atomic_load_or>;
835 defm atomic_load_xor : binary_atomic_op<atomic_load_xor>;
836 defm atomic_load_nand : binary_atomic_op<atomic_load_nand>;
837 defm atomic_load_min : binary_atomic_op<atomic_load_min>;
838 defm atomic_load_max : binary_atomic_op<atomic_load_max>;
839 defm atomic_load_umin : binary_atomic_op<atomic_load_umin>;
840 defm atomic_load_umax : binary_atomic_op<atomic_load_umax>;
842 //===----------------------------------------------------------------------===//
843 // Selection DAG CONVERT_RNDSAT patterns
845 def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
846 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
847 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF;
850 def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
851 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
852 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS;
855 def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
856 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
857 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU;
860 def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
861 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
862 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US;
865 def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
866 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
867 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU;
870 def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
871 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
872 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF;
875 def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
876 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
877 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF;
880 def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
881 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
882 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS;
885 def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
886 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
887 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU;
890 //===----------------------------------------------------------------------===//
891 // Selection DAG Pattern Support.
893 // Patterns are what are actually matched against by the target-flavored
894 // instruction selection DAG. Instructions defined by the target implicitly
895 // define patterns in most cases, but patterns can also be explicitly added when
896 // an operation is defined by a sequence of instructions (e.g. loading a large
897 // immediate value on RISC targets that do not support immediates as large as
901 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
902 dag PatternToMatch = patternToMatch;
903 list<dag> ResultInstrs = resultInstrs;
904 list<Predicate> Predicates = []; // See class Instruction in Target.td.
905 int AddedComplexity = 0; // See class Instruction in Target.td.
908 // Pat - A simple (but common) form of a pattern, which produces a simple result
909 // not needing a full list.
910 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
912 //===----------------------------------------------------------------------===//
913 // Complex pattern definitions.
916 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
917 // in C++. NumOperands is the number of operands returned by the select function;
918 // SelectFunc is the name of the function used to pattern match the max. pattern;
919 // RootNodes are the list of possible root nodes of the sub-dags to match.
920 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
922 class ComplexPattern<ValueType ty, int numops, string fn,
923 list<SDNode> roots = [], list<SDNodeProperty> props = []> {
925 int NumOperands = numops;
926 string SelectFunc = fn;
927 list<SDNode> RootNodes = roots;
928 list<SDNodeProperty> Properties = props;