1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
16 #include "PPCRegisterInfo.h"
17 #include "PPCFixupKinds.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/Support/ErrorHandling.h"
25 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
28 class PPCMCCodeEmitter : public MCCodeEmitter {
29 PPCMCCodeEmitter(const PPCMCCodeEmitter &); // DO NOT IMPLEMENT
30 void operator=(const PPCMCCodeEmitter &); // DO NOT IMPLEMENT
33 PPCMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
37 ~PPCMCCodeEmitter() {}
39 unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
40 SmallVectorImpl<MCFixup> &Fixups) const;
41 unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
42 SmallVectorImpl<MCFixup> &Fixups) const;
43 unsigned getHA16Encoding(const MCInst &MI, unsigned OpNo,
44 SmallVectorImpl<MCFixup> &Fixups) const;
45 unsigned getLO16Encoding(const MCInst &MI, unsigned OpNo,
46 SmallVectorImpl<MCFixup> &Fixups) const;
47 unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
48 SmallVectorImpl<MCFixup> &Fixups) const;
49 unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
50 SmallVectorImpl<MCFixup> &Fixups) const;
51 unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
52 SmallVectorImpl<MCFixup> &Fixups) const;
54 /// getMachineOpValue - Return binary encoding of operand. If the machine
55 /// operand requires relocation, record the relocation and return zero.
56 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
57 SmallVectorImpl<MCFixup> &Fixups) const;
59 // getBinaryCodeForInstr - TableGen'erated function for getting the
60 // binary encoding for an instruction.
61 unsigned getBinaryCodeForInstr(const MCInst &MI,
62 SmallVectorImpl<MCFixup> &Fixups) const;
63 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
64 SmallVectorImpl<MCFixup> &Fixups) const {
65 unsigned Bits = getBinaryCodeForInstr(MI, Fixups);
67 // Output the constant in big endian byte order.
68 for (unsigned i = 0; i != 4; ++i) {
69 OS << (char)(Bits >> 24);
73 ++MCNumEmitted; // Keep track of the # of mi's emitted.
78 } // end anonymous namespace
80 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
81 const MCSubtargetInfo &STI,
83 return new PPCMCCodeEmitter(MCII, STI, Ctx);
86 unsigned PPCMCCodeEmitter::
87 getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
88 SmallVectorImpl<MCFixup> &Fixups) const {
89 const MCOperand &MO = MI.getOperand(OpNo);
90 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
92 // Add a fixup for the branch target.
93 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
94 (MCFixupKind)PPC::fixup_ppc_br24));
98 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
99 SmallVectorImpl<MCFixup> &Fixups) const {
100 const MCOperand &MO = MI.getOperand(OpNo);
101 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
103 // Add a fixup for the branch target.
104 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
105 (MCFixupKind)PPC::fixup_ppc_brcond14));
109 unsigned PPCMCCodeEmitter::getHA16Encoding(const MCInst &MI, unsigned OpNo,
110 SmallVectorImpl<MCFixup> &Fixups) const {
111 const MCOperand &MO = MI.getOperand(OpNo);
112 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
114 // Add a fixup for the branch target.
115 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
116 (MCFixupKind)PPC::fixup_ppc_ha16));
120 unsigned PPCMCCodeEmitter::getLO16Encoding(const MCInst &MI, unsigned OpNo,
121 SmallVectorImpl<MCFixup> &Fixups) const {
122 const MCOperand &MO = MI.getOperand(OpNo);
123 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
125 // Add a fixup for the branch target.
126 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
127 (MCFixupKind)PPC::fixup_ppc_lo16));
131 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
132 SmallVectorImpl<MCFixup> &Fixups) const {
133 // Encode (imm, reg) as a memri, which has the low 16-bits as the
134 // displacement and the next 5 bits as the register #.
135 assert(MI.getOperand(OpNo+1).isReg());
136 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 16;
138 const MCOperand &MO = MI.getOperand(OpNo);
140 return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits;
142 // Add a fixup for the displacement field.
143 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
144 (MCFixupKind)PPC::fixup_ppc_lo16));
149 unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
150 SmallVectorImpl<MCFixup> &Fixups) const {
151 // Encode (imm, reg) as a memrix, which has the low 14-bits as the
152 // displacement and the next 5 bits as the register #.
153 assert(MI.getOperand(OpNo+1).isReg());
154 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 14;
156 const MCOperand &MO = MI.getOperand(OpNo);
158 return (getMachineOpValue(MI, MO, Fixups) & 0x3FFF) | RegBits;
160 // Add a fixup for the branch target.
161 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
162 (MCFixupKind)PPC::fixup_ppc_lo14));
167 unsigned PPCMCCodeEmitter::
168 get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
169 SmallVectorImpl<MCFixup> &Fixups) const {
170 const MCOperand &MO = MI.getOperand(OpNo);
171 assert((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFOCRF) &&
172 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
173 return 0x80 >> PPCRegisterInfo::getRegisterNumbering(MO.getReg());
177 unsigned PPCMCCodeEmitter::
178 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
179 SmallVectorImpl<MCFixup> &Fixups) const {
181 // MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
182 // The GPR operand should come through here though.
183 assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) ||
184 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
185 return PPCRegisterInfo::getRegisterNumbering(MO.getReg());
189 "Relocation required in an instruction that we cannot encode!");
194 #include "PPCGenMCCodeEmitter.inc"