contrib/llvm/lib/Target/X86/X86ScheduleAtom.td

   1 //===- X86ScheduleAtom.td - X86 Atom Scheduling Definitions -*- tablegen -*-==//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the itinerary class data for the Intel Atom (Bonnell)
  11 // processors.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 //
  16 // Scheduling information derived from the "Intel 64 and IA32 Architectures
  17 // Optimization Reference Manual", Chapter 13, Section 4.
  18 // Functional Units
  19 //    Port 0
  20 def Port0 : FuncUnit; // ALU: ALU0, shift/rotate, load/store
  21                       // SIMD/FP: SIMD ALU, Shuffle,SIMD/FP multiply, divide
  22 def Port1 : FuncUnit; // ALU: ALU1, bit processing, jump, and LEA
  23                       // SIMD/FP: SIMD ALU, FP Adder
  24
  25 def AtomItineraries : ProcessorItineraries<
  26   [ Port0, Port1 ],
  27   [], [
  28   // P0 only
  29   // InstrItinData<class, [InstrStage<N, [P0]>] >,
  30   // P0 or P1
  31   // InstrItinData<class, [InstrStage<N, [P0, P1]>] >,
  32   // P0 and P1
  33   // InstrItinData<class, [InstrStage<N, [P0], 0>,  InstrStage<N, [P1]>] >,
  34   //
  35   // Default is 1 cycle, port0 or port1
  36   InstrItinData<IIC_DEFAULT, [InstrStage<1, [Port0, Port1]>] >,
  37   InstrItinData<IIC_ALU_MEM, [InstrStage<1, [Port0]>] >,
  38   InstrItinData<IIC_ALU_NONMEM, [InstrStage<1, [Port0, Port1]>] >,
  39   InstrItinData<IIC_LEA, [InstrStage<1, [Port1]>] >,
  40   InstrItinData<IIC_LEA_16, [InstrStage<2, [Port0, Port1]>] >,
  41   // mul
  42   InstrItinData<IIC_MUL8, [InstrStage<7, [Port0, Port1]>] >,
  43   InstrItinData<IIC_MUL16_MEM, [InstrStage<8, [Port0, Port1]>] >,
  44   InstrItinData<IIC_MUL16_REG, [InstrStage<7, [Port0, Port1]>] >,
  45   InstrItinData<IIC_MUL32_MEM, [InstrStage<7, [Port0, Port1]>] >,
  46   InstrItinData<IIC_MUL32_REG, [InstrStage<6, [Port0, Port1]>] >,
  47   InstrItinData<IIC_MUL64, [InstrStage<12, [Port0, Port1]>] >,
  48   // imul by al, ax, eax, rax
  49   InstrItinData<IIC_IMUL8, [InstrStage<7, [Port0, Port1]>] >,
  50   InstrItinData<IIC_IMUL16_MEM, [InstrStage<8, [Port0, Port1]>] >,
  51   InstrItinData<IIC_IMUL16_REG, [InstrStage<7, [Port0, Port1]>] >,
  52   InstrItinData<IIC_IMUL32_MEM, [InstrStage<7, [Port0, Port1]>] >,
  53   InstrItinData<IIC_IMUL32_REG, [InstrStage<6, [Port0, Port1]>] >,
  54   InstrItinData<IIC_IMUL64, [InstrStage<12, [Port0, Port1]>] >,
  55   // imul reg by reg|mem
  56   InstrItinData<IIC_IMUL16_RM, [InstrStage<7, [Port0, Port1]>] >,
  57   InstrItinData<IIC_IMUL16_RR, [InstrStage<6, [Port0, Port1]>] >,
  58   InstrItinData<IIC_IMUL32_RM, [InstrStage<5, [Port0]>] >,
  59   InstrItinData<IIC_IMUL32_RR, [InstrStage<5, [Port0]>] >,
  60   InstrItinData<IIC_IMUL64_RM, [InstrStage<12, [Port0, Port1]>] >,
  61   InstrItinData<IIC_IMUL64_RR, [InstrStage<12, [Port0, Port1]>] >,
  62   // imul reg = reg/mem * imm
  63   InstrItinData<IIC_IMUL16_RRI, [InstrStage<6, [Port0, Port1]>] >,
  64   InstrItinData<IIC_IMUL32_RRI, [InstrStage<5, [Port0]>] >,
  65   InstrItinData<IIC_IMUL64_RRI, [InstrStage<14, [Port0, Port1]>] >,
  66   InstrItinData<IIC_IMUL16_RMI, [InstrStage<7, [Port0, Port1]>] >,
  67   InstrItinData<IIC_IMUL32_RMI, [InstrStage<5, [Port0]>] >,
  68   InstrItinData<IIC_IMUL64_RMI, [InstrStage<14, [Port0, Port1]>] >,
  69   // idiv
  70   InstrItinData<IIC_IDIV8, [InstrStage<62, [Port0, Port1]>] >,
  71   InstrItinData<IIC_IDIV16, [InstrStage<62, [Port0, Port1]>] >,
  72   InstrItinData<IIC_IDIV32, [InstrStage<62, [Port0, Port1]>] >,
  73   InstrItinData<IIC_IDIV64, [InstrStage<130, [Port0, Port1]>] >,
  74   // div
  75   InstrItinData<IIC_DIV8_REG, [InstrStage<50, [Port0, Port1]>] >,
  76   InstrItinData<IIC_DIV8_MEM, [InstrStage<68, [Port0, Port1]>] >,
  77   InstrItinData<IIC_DIV16, [InstrStage<50, [Port0, Port1]>] >,
  78   InstrItinData<IIC_DIV32, [InstrStage<50, [Port0, Port1]>] >,
  79   InstrItinData<IIC_DIV64, [InstrStage<130, [Port0, Port1]>] >,
  80   // neg/not/inc/dec
  81   InstrItinData<IIC_UNARY_REG, [InstrStage<1, [Port0, Port1]>] >,
  82   InstrItinData<IIC_UNARY_MEM, [InstrStage<1, [Port0]>] >,
  83   // add/sub/and/or/xor/adc/sbc/cmp/test
  84   InstrItinData<IIC_BIN_NONMEM, [InstrStage<1, [Port0, Port1]>] >,
  85   InstrItinData<IIC_BIN_MEM, [InstrStage<1, [Port0]>] >,
  86   // shift/rotate
  87   InstrItinData<IIC_SR, [InstrStage<1, [Port0]>] >,
  88   // shift double
  89   InstrItinData<IIC_SHD16_REG_IM, [InstrStage<6, [Port0, Port1]>] >,
  90   InstrItinData<IIC_SHD16_REG_CL, [InstrStage<6, [Port0, Port1]>] >,
  91   InstrItinData<IIC_SHD16_MEM_IM, [InstrStage<6, [Port0, Port1]>] >,
  92   InstrItinData<IIC_SHD16_MEM_CL, [InstrStage<6, [Port0, Port1]>] >,
  93   InstrItinData<IIC_SHD32_REG_IM, [InstrStage<2, [Port0, Port1]>] >,
  94   InstrItinData<IIC_SHD32_REG_CL, [InstrStage<2, [Port0, Port1]>] >,
  95   InstrItinData<IIC_SHD32_MEM_IM, [InstrStage<4, [Port0, Port1]>] >,
  96   InstrItinData<IIC_SHD32_MEM_CL, [InstrStage<4, [Port0, Port1]>] >,
  97   InstrItinData<IIC_SHD64_REG_IM, [InstrStage<9, [Port0, Port1]>] >,
  98   InstrItinData<IIC_SHD64_REG_CL, [InstrStage<8, [Port0, Port1]>] >,
  99   InstrItinData<IIC_SHD64_MEM_IM, [InstrStage<9, [Port0, Port1]>] >,
 100   InstrItinData<IIC_SHD64_MEM_CL, [InstrStage<9, [Port0, Port1]>] >,
 101   // cmov
 102   InstrItinData<IIC_CMOV16_RM, [InstrStage<1, [Port0]>] >,
 103   InstrItinData<IIC_CMOV16_RR, [InstrStage<1, [Port0, Port1]>] >,
 104   InstrItinData<IIC_CMOV32_RM, [InstrStage<1, [Port0]>] >,
 105   InstrItinData<IIC_CMOV32_RR, [InstrStage<1, [Port0, Port1]>] >,
 106   InstrItinData<IIC_CMOV64_RM, [InstrStage<1, [Port0]>] >,
 107   InstrItinData<IIC_CMOV64_RR, [InstrStage<1, [Port0, Port1]>] >,
 108   // set
 109   InstrItinData<IIC_SET_M, [InstrStage<2, [Port0, Port1]>] >,
 110   InstrItinData<IIC_SET_R, [InstrStage<1, [Port0, Port1]>] >,
 111   // jcc
 112   InstrItinData<IIC_Jcc, [InstrStage<1, [Port1]>] >,
 113   // jcxz/jecxz/jrcxz
 114   InstrItinData<IIC_JCXZ, [InstrStage<4, [Port0, Port1]>] >,
 115   // jmp rel
 116   InstrItinData<IIC_JMP_REL, [InstrStage<1, [Port1]>] >,
 117   // jmp indirect
 118   InstrItinData<IIC_JMP_REG, [InstrStage<1, [Port1]>] >,
 119   InstrItinData<IIC_JMP_MEM, [InstrStage<2, [Port0, Port1]>] >,
 120   // jmp far
 121   InstrItinData<IIC_JMP_FAR_MEM, [InstrStage<32, [Port0, Port1]>] >,
 122   InstrItinData<IIC_JMP_FAR_PTR, [InstrStage<31, [Port0, Port1]>] >,
 123   // loop/loope/loopne
 124   InstrItinData<IIC_LOOP, [InstrStage<18, [Port0, Port1]>] >,
 125   InstrItinData<IIC_LOOPE, [InstrStage<8, [Port0, Port1]>] >,
 126   InstrItinData<IIC_LOOPNE, [InstrStage<17, [Port0, Port1]>] >,
 127   // call - all but reg/imm
 128   InstrItinData<IIC_CALL_RI, [InstrStage<1, [Port0], 0>,
 129                               InstrStage<1, [Port1]>] >,
 130   InstrItinData<IIC_CALL_MEM, [InstrStage<15, [Port0, Port1]>] >,
 131   InstrItinData<IIC_CALL_FAR_MEM, [InstrStage<40, [Port0, Port1]>] >,
 132   InstrItinData<IIC_CALL_FAR_PTR, [InstrStage<39, [Port0, Port1]>] >,
 133   //ret
 134   InstrItinData<IIC_RET, [InstrStage<79, [Port0, Port1]>] >,
 135   InstrItinData<IIC_RET_IMM, [InstrStage<1, [Port0], 0>,  InstrStage<1, [Port1]>] >,
 136   //sign extension movs
 137   InstrItinData<IIC_MOVSX,[InstrStage<1, [Port0] >] >,
 138   InstrItinData<IIC_MOVSX_R16_R8, [InstrStage<2, [Port0, Port1]>] >,
 139   InstrItinData<IIC_MOVSX_R16_M8, [InstrStage<3, [Port0, Port1]>] >,
 140   InstrItinData<IIC_MOVSX_R16_R16, [InstrStage<1, [Port0, Port1]>] >,
 141   InstrItinData<IIC_MOVSX_R32_R32, [InstrStage<1, [Port0, Port1]>] >,
 142   //zero extension movs
 143   InstrItinData<IIC_MOVZX,[InstrStage<1, [Port0]>] >,
 144   InstrItinData<IIC_MOVZX_R16_R8, [InstrStage<2, [Port0, Port1]>] >,
 145   InstrItinData<IIC_MOVZX_R16_M8, [InstrStage<3, [Port0, Port1]>] >,
 146
 147   InstrItinData<IIC_REP_MOVS, [InstrStage<75, [Port0, Port1]>] >,
 148   InstrItinData<IIC_REP_STOS, [InstrStage<74, [Port0, Port1]>] >,
 149
 150   // SSE binary operations
 151   // arithmetic fp scalar
 152   InstrItinData<IIC_SSE_ALU_F32S_RR, [InstrStage<5, [Port1]>] >,
 153   InstrItinData<IIC_SSE_ALU_F32S_RM, [InstrStage<5, [Port0], 0>,
 154                                    InstrStage<5, [Port1]>] >,
 155   InstrItinData<IIC_SSE_ALU_F64S_RR, [InstrStage<5, [Port1]>] >,
 156   InstrItinData<IIC_SSE_ALU_F64S_RM, [InstrStage<5, [Port0], 0>,
 157                                    InstrStage<5, [Port1]>] >,
 158   InstrItinData<IIC_SSE_MUL_F32S_RR, [InstrStage<4, [Port0]>] >,
 159   InstrItinData<IIC_SSE_MUL_F32S_RM, [InstrStage<4, [Port0]>] >,
 160   InstrItinData<IIC_SSE_MUL_F64S_RR, [InstrStage<5, [Port0]>] >,
 161   InstrItinData<IIC_SSE_MUL_F64S_RM, [InstrStage<5, [Port0]>] >,
 162   InstrItinData<IIC_SSE_DIV_F32S_RR, [InstrStage<34, [Port0, Port1]>] >,
 163   InstrItinData<IIC_SSE_DIV_F32S_RM, [InstrStage<34, [Port0, Port1]>] >,
 164   InstrItinData<IIC_SSE_DIV_F64S_RR, [InstrStage<62, [Port0, Port1]>] >,
 165   InstrItinData<IIC_SSE_DIV_F64S_RM, [InstrStage<62, [Port0, Port1]>] >,
 166
 167   InstrItinData<IIC_SSE_COMIS_RR, [InstrStage<9, [Port0, Port1]>] >,
 168   InstrItinData<IIC_SSE_COMIS_RM, [InstrStage<10, [Port0, Port1]>] >,
 169
 170   InstrItinData<IIC_SSE_HADDSUB_RR, [InstrStage<8, [Port0, Port1]>] >,
 171   InstrItinData<IIC_SSE_HADDSUB_RM, [InstrStage<9, [Port0, Port1]>] >,
 172
 173   // arithmetic fp parallel
 174   InstrItinData<IIC_SSE_ALU_F32P_RR, [InstrStage<5, [Port1]>] >,
 175   InstrItinData<IIC_SSE_ALU_F32P_RM, [InstrStage<5, [Port0], 0>,
 176                                    InstrStage<5, [Port1]>] >,
 177   InstrItinData<IIC_SSE_ALU_F64P_RR, [InstrStage<6, [Port0, Port1]>] >,
 178   InstrItinData<IIC_SSE_ALU_F64P_RM, [InstrStage<7, [Port0, Port1]>] >,
 179   InstrItinData<IIC_SSE_MUL_F32P_RR, [InstrStage<5, [Port0]>] >,
 180   InstrItinData<IIC_SSE_MUL_F32P_RM, [InstrStage<5, [Port0]>] >,
 181   InstrItinData<IIC_SSE_MUL_F64P_RR, [InstrStage<9, [Port0, Port1]>] >,
 182   InstrItinData<IIC_SSE_MUL_F64P_RM, [InstrStage<10, [Port0, Port1]>] >,
 183   InstrItinData<IIC_SSE_DIV_F32P_RR, [InstrStage<70, [Port0, Port1]>] >,
 184   InstrItinData<IIC_SSE_DIV_F32P_RM, [InstrStage<70, [Port0, Port1]>] >,
 185   InstrItinData<IIC_SSE_DIV_F64P_RR, [InstrStage<125, [Port0, Port1]>] >,
 186   InstrItinData<IIC_SSE_DIV_F64P_RM, [InstrStage<125, [Port0, Port1]>] >,
 187
 188   // bitwise parallel
 189   InstrItinData<IIC_SSE_BIT_P_RR, [InstrStage<1, [Port0, Port1]>] >,
 190   InstrItinData<IIC_SSE_BIT_P_RM, [InstrStage<1, [Port0]>] >,
 191
 192   // arithmetic int parallel
 193   InstrItinData<IIC_SSE_INTALU_P_RR, [InstrStage<1, [Port0, Port1]>] >,
 194   InstrItinData<IIC_SSE_INTALU_P_RM, [InstrStage<1, [Port0]>] >,
 195   InstrItinData<IIC_SSE_INTALUQ_P_RR, [InstrStage<2, [Port0, Port1]>] >,
 196   InstrItinData<IIC_SSE_INTALUQ_P_RM, [InstrStage<3, [Port0, Port1]>] >,
 197
 198   // multiply int parallel
 199   InstrItinData<IIC_SSE_INTMUL_P_RR, [InstrStage<5, [Port0]>] >,
 200   InstrItinData<IIC_SSE_INTMUL_P_RM, [InstrStage<5, [Port0]>] >,
 201
 202   // shift parallel
 203   InstrItinData<IIC_SSE_INTSH_P_RR, [InstrStage<2, [Port0, Port1]>] >,
 204   InstrItinData<IIC_SSE_INTSH_P_RM, [InstrStage<3, [Port0, Port1]>] >,
 205   InstrItinData<IIC_SSE_INTSH_P_RI, [InstrStage<1, [Port0, Port1]>] >,
 206
 207   InstrItinData<IIC_SSE_CMPP_RR, [InstrStage<6, [Port0, Port1]>] >,
 208   InstrItinData<IIC_SSE_CMPP_RM, [InstrStage<7, [Port0, Port1]>] >,
 209
 210   InstrItinData<IIC_SSE_SHUFP, [InstrStage<1, [Port0]>] >,
 211   InstrItinData<IIC_SSE_PSHUF, [InstrStage<1, [Port0]>] >,
 212
 213   InstrItinData<IIC_SSE_UNPCK, [InstrStage<1, [Port0]>] >,
 214
 215   InstrItinData<IIC_SSE_SQRTP_RR, [InstrStage<13, [Port0, Port1]>] >,
 216   InstrItinData<IIC_SSE_SQRTP_RM, [InstrStage<14, [Port0, Port1]>] >,
 217   InstrItinData<IIC_SSE_SQRTS_RR, [InstrStage<11, [Port0, Port1]>] >,
 218   InstrItinData<IIC_SSE_SQRTS_RM, [InstrStage<12, [Port0, Port1]>] >,
 219
 220   InstrItinData<IIC_SSE_RCPP_RR, [InstrStage<9, [Port0, Port1]>] >,
 221   InstrItinData<IIC_SSE_RCPP_RM, [InstrStage<10, [Port0, Port1]>] >,
 222   InstrItinData<IIC_SSE_RCPS_RR, [InstrStage<4, [Port0]>] >,
 223   InstrItinData<IIC_SSE_RCPS_RM, [InstrStage<4, [Port0]>] >,
 224
 225   InstrItinData<IIC_SSE_MOVMSK, [InstrStage<3, [Port0]>] >,
 226   InstrItinData<IIC_SSE_MASKMOV, [InstrStage<2, [Port0, Port1]>] >,
 227
 228   InstrItinData<IIC_SSE_PEXTRW, [InstrStage<4, [Port0, Port1]>] >,
 229   InstrItinData<IIC_SSE_PINSRW, [InstrStage<1, [Port0]>] >,
 230
 231   InstrItinData<IIC_SSE_PABS_RR, [InstrStage<1, [Port0, Port1]>] >,
 232   InstrItinData<IIC_SSE_PABS_RM, [InstrStage<1, [Port0]>] >,
 233
 234   InstrItinData<IIC_SSE_MOV_S_RR, [InstrStage<1, [Port0, Port1]>] >,
 235   InstrItinData<IIC_SSE_MOV_S_RM, [InstrStage<1, [Port0]>] >,
 236   InstrItinData<IIC_SSE_MOV_S_MR, [InstrStage<1, [Port0]>] >,
 237
 238   InstrItinData<IIC_SSE_MOVA_P_RR, [InstrStage<1, [Port0, Port1]>] >,
 239   InstrItinData<IIC_SSE_MOVA_P_RM, [InstrStage<1, [Port0]>] >,
 240   InstrItinData<IIC_SSE_MOVA_P_MR, [InstrStage<1, [Port0]>] >,
 241
 242   InstrItinData<IIC_SSE_MOVU_P_RR, [InstrStage<1, [Port0, Port1]>] >,
 243   InstrItinData<IIC_SSE_MOVU_P_RM, [InstrStage<3, [Port0, Port1]>] >,
 244   InstrItinData<IIC_SSE_MOVU_P_MR, [InstrStage<2, [Port0, Port1]>] >,
 245
 246   InstrItinData<IIC_SSE_MOV_LH, [InstrStage<1, [Port0]>] >,
 247
 248   InstrItinData<IIC_SSE_LDDQU, [InstrStage<3, [Port0, Port1]>] >,
 249
 250   InstrItinData<IIC_SSE_MOVDQ, [InstrStage<1, [Port0]>] >,
 251   InstrItinData<IIC_SSE_MOVD_ToGP, [InstrStage<3, [Port0]>] >,
 252   InstrItinData<IIC_SSE_MOVQ_RR, [InstrStage<1, [Port0, Port1]>] >,
 253
 254   InstrItinData<IIC_SSE_MOVNT, [InstrStage<1, [Port0]>] >,
 255
 256   InstrItinData<IIC_SSE_PREFETCH, [InstrStage<1, [Port0]>] >,
 257   InstrItinData<IIC_SSE_PAUSE, [InstrStage<17, [Port0, Port1]>] >,
 258   InstrItinData<IIC_SSE_LFENCE, [InstrStage<1, [Port0, Port1]>] >,
 259   InstrItinData<IIC_SSE_MFENCE, [InstrStage<1, [Port0]>] >,
 260   InstrItinData<IIC_SSE_SFENCE, [InstrStage<1, [Port0]>] >,
 261   InstrItinData<IIC_SSE_LDMXCSR, [InstrStage<5, [Port0, Port1]>] >,
 262   InstrItinData<IIC_SSE_STMXCSR, [InstrStage<15, [Port0, Port1]>] >,
 263
 264   InstrItinData<IIC_SSE_PHADDSUBD_RR, [InstrStage<3, [Port0, Port1]>] >,
 265   InstrItinData<IIC_SSE_PHADDSUBD_RM, [InstrStage<4, [Port0, Port1]>] >,
 266   InstrItinData<IIC_SSE_PHADDSUBSW_RR, [InstrStage<7, [Port0, Port1]>] >,
 267   InstrItinData<IIC_SSE_PHADDSUBSW_RM, [InstrStage<8, [Port0, Port1]>] >,
 268   InstrItinData<IIC_SSE_PHADDSUBW_RR, [InstrStage<7, [Port0, Port1]>] >,
 269   InstrItinData<IIC_SSE_PHADDSUBW_RM, [InstrStage<8, [Port0, Port1]>] >,
 270   InstrItinData<IIC_SSE_PSHUFB_RR, [InstrStage<4, [Port0, Port1]>] >,
 271   InstrItinData<IIC_SSE_PSHUFB_RM, [InstrStage<5, [Port0, Port1]>] >,
 272   InstrItinData<IIC_SSE_PSIGN_RR, [InstrStage<1, [Port0, Port1]>] >,
 273   InstrItinData<IIC_SSE_PSIGN_RM, [InstrStage<1, [Port0]>] >,
 274
 275   InstrItinData<IIC_SSE_PMADD, [InstrStage<5, [Port0]>] >,
 276   InstrItinData<IIC_SSE_PMULHRSW, [InstrStage<5, [Port0]>] >,
 277   InstrItinData<IIC_SSE_PALIGNR, [InstrStage<1, [Port0]>] >,
 278   InstrItinData<IIC_SSE_MWAIT, [InstrStage<46, [Port0, Port1]>] >,
 279   InstrItinData<IIC_SSE_MONITOR, [InstrStage<45, [Port0, Port1]>] >,
 280
 281   // conversions
 282   // to/from PD ...
 283   InstrItinData<IIC_SSE_CVT_PD_RR, [InstrStage<7, [Port0, Port1]>] >,
 284   InstrItinData<IIC_SSE_CVT_PD_RM, [InstrStage<8, [Port0, Port1]>] >,
 285   // to/from PS except to/from PD and PS2PI
 286   InstrItinData<IIC_SSE_CVT_PS_RR, [InstrStage<6, [Port0, Port1]>] >,
 287   InstrItinData<IIC_SSE_CVT_PS_RM, [InstrStage<7, [Port0, Port1]>] >,
 288   InstrItinData<IIC_SSE_CVT_Scalar_RR, [InstrStage<6, [Port0, Port1]>] >,
 289   InstrItinData<IIC_SSE_CVT_Scalar_RM, [InstrStage<7, [Port0, Port1]>] >,
 290   InstrItinData<IIC_SSE_CVT_SS2SI32_RR, [InstrStage<8, [Port0, Port1]>] >,
 291   InstrItinData<IIC_SSE_CVT_SS2SI32_RM, [InstrStage<9, [Port0, Port1]>] >,
 292   InstrItinData<IIC_SSE_CVT_SS2SI64_RR, [InstrStage<9, [Port0, Port1]>] >,
 293   InstrItinData<IIC_SSE_CVT_SS2SI64_RM, [InstrStage<10, [Port0, Port1]>] >,
 294   InstrItinData<IIC_SSE_CVT_SD2SI_RR, [InstrStage<8, [Port0, Port1]>] >,
 295   InstrItinData<IIC_SSE_CVT_SD2SI_RM, [InstrStage<9, [Port0, Port1]>] >,
 296
 297   InstrItinData<IIC_CMPX_LOCK, [InstrStage<14, [Port0, Port1]>] >,
 298   InstrItinData<IIC_CMPX_LOCK_8, [InstrStage<6, [Port0, Port1]>] >,
 299   InstrItinData<IIC_CMPX_LOCK_8B, [InstrStage<18, [Port0, Port1]>] >,
 300   InstrItinData<IIC_CMPX_LOCK_16B, [InstrStage<22, [Port0, Port1]>] >,
 301
 302   InstrItinData<IIC_XADD_LOCK_MEM, [InstrStage<2, [Port0, Port1]>] >,
 303   InstrItinData<IIC_XADD_LOCK_MEM, [InstrStage<3, [Port0, Port1]>] >
 304   ]>;
 305