2 * Copyright (c) 1996, by Steve Passe
3 * Copyright (c) 2003, by Peter Wemm
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 #include "opt_kstack_pages.h"
32 #include "opt_sched.h"
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/cpuset.h>
42 #include <sys/kernel.h>
45 #include <sys/malloc.h>
46 #include <sys/memrange.h>
47 #include <sys/mutex.h>
50 #include <sys/sched.h>
52 #include <sys/sysctl.h>
55 #include <vm/vm_param.h>
57 #include <vm/vm_kern.h>
58 #include <vm/vm_extern.h>
60 #include <x86/apicreg.h>
61 #include <machine/clock.h>
62 #include <machine/cputypes.h>
63 #include <machine/cpufunc.h>
65 #include <machine/md_var.h>
66 #include <machine/pcb.h>
67 #include <machine/psl.h>
68 #include <machine/smp.h>
69 #include <machine/specialreg.h>
70 #include <machine/tss.h>
72 #define WARMBOOT_TARGET 0
73 #define WARMBOOT_OFF (KERNBASE + 0x0467)
74 #define WARMBOOT_SEG (KERNBASE + 0x0469)
76 #define CMOS_REG (0x70)
77 #define CMOS_DATA (0x71)
78 #define BIOS_RESET (0x0f)
79 #define BIOS_WARM (0x0a)
81 /* lock region used by kernel profiling */
84 int mp_naps; /* # of Applications processors */
85 int boot_cpu_id = -1; /* designated BSP */
87 extern struct pcpu __pcpu[];
89 /* AP uses this during bootstrap. Do not staticize. */
93 /* Free these after use */
94 void *bootstacks[MAXCPU];
96 /* Temporary variables for init_secondary() */
97 char *doublefault_stack;
101 struct pcb stoppcbs[MAXCPU];
102 struct pcb **susppcbs = NULL;
104 /* Variables needed for SMP tlb shootdown. */
105 vm_offset_t smp_tlb_addr1;
106 vm_offset_t smp_tlb_addr2;
107 volatile int smp_tlb_wait;
110 /* Interrupt counts. */
111 static u_long *ipi_preempt_counts[MAXCPU];
112 static u_long *ipi_ast_counts[MAXCPU];
113 u_long *ipi_invltlb_counts[MAXCPU];
114 u_long *ipi_invlrng_counts[MAXCPU];
115 u_long *ipi_invlpg_counts[MAXCPU];
116 u_long *ipi_invlcache_counts[MAXCPU];
117 u_long *ipi_rendezvous_counts[MAXCPU];
118 static u_long *ipi_hardclock_counts[MAXCPU];
121 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
124 * Local data and functions.
127 static volatile cpuset_t ipi_nmi_pending;
129 /* used to hold the AP's until we are ready to release them */
130 static struct mtx ap_boot_mtx;
132 /* Set to 1 once we're ready to let the APs out of the pen. */
133 static volatile int aps_ready = 0;
136 * Store data from cpu_add() until later in the boot when we actually setup
143 int cpu_hyperthread:1;
144 } static cpu_info[MAX_APIC_ID + 1];
145 int cpu_apic_ids[MAXCPU];
146 int apic_cpuids[MAX_APIC_ID + 1];
148 /* Holds pending bitmap based IPIs per CPU */
149 static volatile u_int cpu_ipi_pending[MAXCPU];
151 static u_int boot_address;
152 static int cpu_logical; /* logical cpus per core */
153 static int cpu_cores; /* cores per package */
155 static void assign_cpu_ids(void);
156 static void set_interrupt_apic_ids(void);
157 static int start_all_aps(void);
158 static int start_ap(int apic_id);
159 static void release_aps(void *dummy);
161 static u_int hyperthreading_cpus; /* logical cpus sharing L1 cache */
162 static int hyperthreading_allowed = 1;
163 static u_int bootMP_size;
166 mem_range_AP_init(void)
168 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP)
169 mem_range_softc.mr_op->initAP(&mem_range_softc);
178 /* AMD processors do not support HTT. */
181 if ((amd_feature2 & AMDID2_CMP) == 0) {
186 core_id_bits = (cpu_procinfo2 & AMDID_COREID_SIZE) >>
187 AMDID_COREID_SIZE_SHIFT;
188 if (core_id_bits == 0) {
189 cpu_cores = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
193 /* Fam 10h and newer should get here. */
194 for (id = 0; id <= MAX_APIC_ID; id++) {
195 /* Check logical CPU availability. */
196 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled)
198 /* Check if logical CPU has the same package ID. */
199 if ((id >> core_id_bits) != (boot_cpu_id >> core_id_bits))
206 * Round up to the next power of two, if necessary, and then
208 * Returns -1 if argument is zero.
214 return (fls(x << (1 - powerof2(x))) - 1);
227 /* Both zero and one here mean one logical processor per package. */
228 max_logical = (cpu_feature & CPUID_HTT) != 0 ?
229 (cpu_procinfo & CPUID_HTT_CORES) >> 16 : 1;
230 if (max_logical <= 1)
234 * Because of uniformity assumption we examine only
235 * those logical processors that belong to the same
236 * package as BSP. Further, we count number of
237 * logical processors that belong to the same core
238 * as BSP thus deducing number of threads per core.
240 if (cpu_high >= 0x4) {
241 cpuid_count(0x04, 0, p);
242 max_cores = ((p[0] >> 26) & 0x3f) + 1;
245 core_id_bits = mask_width(max_logical/max_cores);
246 if (core_id_bits < 0)
248 pkg_id_bits = core_id_bits + mask_width(max_cores);
250 for (id = 0; id <= MAX_APIC_ID; id++) {
251 /* Check logical CPU availability. */
252 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled)
254 /* Check if logical CPU has the same package ID. */
255 if ((id >> pkg_id_bits) != (boot_cpu_id >> pkg_id_bits))
258 /* Check if logical CPU has the same package and core IDs. */
259 if ((id >> core_id_bits) == (boot_cpu_id >> core_id_bits))
263 KASSERT(cpu_cores >= 1 && cpu_logical >= 1,
264 ("topo_probe_0x4 couldn't find BSP"));
266 cpu_cores /= cpu_logical;
267 hyperthreading_cpus = cpu_logical;
281 /* We only support three levels for now. */
282 for (i = 0; i < 3; i++) {
283 cpuid_count(0x0b, i, p);
285 /* Fall back if CPU leaf 11 doesn't really exist. */
286 if (i == 0 && p[1] == 0) {
292 logical = p[1] &= 0xffff;
293 type = (p[2] >> 8) & 0xff;
294 if (type == 0 || logical == 0)
297 * Because of uniformity assumption we examine only
298 * those logical processors that belong to the same
301 for (cnt = 0, x = 0; x <= MAX_APIC_ID; x++) {
302 if (!cpu_info[x].cpu_present ||
303 cpu_info[x].cpu_disabled)
305 if (x >> bits == boot_cpu_id >> bits)
308 if (type == CPUID_TYPE_SMT)
310 else if (type == CPUID_TYPE_CORE)
313 if (cpu_logical == 0)
315 cpu_cores /= cpu_logical;
319 * Both topology discovery code and code that consumes topology
320 * information assume top-down uniformity of the topology.
321 * That is, all physical packages must be identical and each
322 * core in a package must have the same number of threads.
323 * Topology information is queried only on BSP, on which this
324 * code runs and for which it can query CPUID information.
325 * Then topology is extrapolated on all packages using the
326 * uniformity assumption.
331 static int cpu_topo_probed = 0;
336 CPU_ZERO(&logical_cpus_mask);
338 cpu_cores = cpu_logical = 1;
339 else if (cpu_vendor_id == CPU_VENDOR_AMD)
341 else if (cpu_vendor_id == CPU_VENDOR_INTEL) {
343 * See Intel(R) 64 Architecture Processor
344 * Topology Enumeration article for details.
346 * Note that 0x1 <= cpu_high < 4 case should be
347 * compatible with topo_probe_0x4() logic when
348 * CPUID.1:EBX[23:16] > 0 (cpu_cores will be 1)
349 * or it should trigger the fallback otherwise.
353 else if (cpu_high >= 0x1)
358 * Fallback: assume each logical CPU is in separate
359 * physical package. That is, no multi-core, no SMT.
361 if (cpu_cores == 0 || cpu_logical == 0)
362 cpu_cores = cpu_logical = 1;
372 * Determine whether any threading flags are
376 if (cpu_logical > 1 && hyperthreading_cpus)
377 cg_flags = CG_FLAG_HTT;
378 else if (cpu_logical > 1)
379 cg_flags = CG_FLAG_SMT;
382 if (mp_ncpus % (cpu_cores * cpu_logical) != 0) {
383 printf("WARNING: Non-uniform processors.\n");
384 printf("WARNING: Using suboptimal topology.\n");
385 return (smp_topo_none());
388 * No multi-core or hyper-threaded.
390 if (cpu_logical * cpu_cores == 1)
391 return (smp_topo_none());
393 * Only HTT no multi-core.
395 if (cpu_logical > 1 && cpu_cores == 1)
396 return (smp_topo_1level(CG_SHARE_L1, cpu_logical, cg_flags));
398 * Only multi-core no HTT.
400 if (cpu_cores > 1 && cpu_logical == 1)
401 return (smp_topo_1level(CG_SHARE_L2, cpu_cores, cg_flags));
403 * Both HTT and multi-core.
405 return (smp_topo_2level(CG_SHARE_L2, cpu_cores,
406 CG_SHARE_L1, cpu_logical, cg_flags));
410 * Calculate usable address in base memory for AP trampoline code.
413 mp_bootaddress(u_int basemem)
416 bootMP_size = mptramp_end - mptramp_start;
417 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
418 if (((basemem * 1024) - boot_address) < bootMP_size)
419 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
420 /* 3 levels of page table pages */
421 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
423 return mptramp_pagetables;
427 cpu_add(u_int apic_id, char boot_cpu)
430 if (apic_id > MAX_APIC_ID) {
431 panic("SMP: APIC ID %d too high", apic_id);
434 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice",
436 cpu_info[apic_id].cpu_present = 1;
438 KASSERT(boot_cpu_id == -1,
439 ("CPU %d claims to be BSP, but CPU %d already is", apic_id,
441 boot_cpu_id = apic_id;
442 cpu_info[apic_id].cpu_bsp = 1;
444 if (mp_ncpus < MAXCPU) {
446 mp_maxid = mp_ncpus - 1;
449 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" :
454 cpu_mp_setmaxid(void)
458 * mp_maxid should be already set by calls to cpu_add().
459 * Just sanity check its value here.
462 KASSERT(mp_maxid == 0,
463 ("%s: mp_ncpus is zero, but mp_maxid is not", __func__));
464 else if (mp_ncpus == 1)
467 KASSERT(mp_maxid >= mp_ncpus - 1,
468 ("%s: counters out of sync: max %d, count %d", __func__,
469 mp_maxid, mp_ncpus));
477 * Always record BSP in CPU map so that the mbuf init code works
480 CPU_SETOF(0, &all_cpus);
483 * No CPUs were found, so this must be a UP system. Setup
484 * the variables to represent a system with a single CPU
491 /* At least one CPU was found. */
494 * One CPU was found, so this must be a UP system with
501 /* At least two CPUs were found. */
506 * Initialize the IPI handlers and start up the AP's.
513 /* Initialize the logical ID to APIC ID table. */
514 for (i = 0; i < MAXCPU; i++) {
515 cpu_apic_ids[i] = -1;
516 cpu_ipi_pending[i] = 0;
519 /* Install an inter-CPU IPI for TLB invalidation */
520 setidt(IPI_INVLTLB, IDTVEC(invltlb), SDT_SYSIGT, SEL_KPL, 0);
521 setidt(IPI_INVLPG, IDTVEC(invlpg), SDT_SYSIGT, SEL_KPL, 0);
522 setidt(IPI_INVLRNG, IDTVEC(invlrng), SDT_SYSIGT, SEL_KPL, 0);
524 /* Install an inter-CPU IPI for cache invalidation. */
525 setidt(IPI_INVLCACHE, IDTVEC(invlcache), SDT_SYSIGT, SEL_KPL, 0);
527 /* Install an inter-CPU IPI for all-CPU rendezvous */
528 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), SDT_SYSIGT, SEL_KPL, 0);
530 /* Install generic inter-CPU IPI handler */
531 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler),
532 SDT_SYSIGT, SEL_KPL, 0);
534 /* Install an inter-CPU IPI for CPU stop/restart */
535 setidt(IPI_STOP, IDTVEC(cpustop), SDT_SYSIGT, SEL_KPL, 0);
537 /* Install an inter-CPU IPI for CPU suspend/resume */
538 setidt(IPI_SUSPEND, IDTVEC(cpususpend), SDT_SYSIGT, SEL_KPL, 0);
540 /* Set boot_cpu_id if needed. */
541 if (boot_cpu_id == -1) {
542 boot_cpu_id = PCPU_GET(apic_id);
543 cpu_info[boot_cpu_id].cpu_bsp = 1;
545 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
546 ("BSP's APIC ID doesn't match boot_cpu_id"));
548 /* Probe logical/physical core configuration. */
553 /* Start each Application Processor */
556 set_interrupt_apic_ids();
561 * Print various information about the SMP system hardware and setup.
564 cpu_mp_announce(void)
566 const char *hyperthread;
569 printf("FreeBSD/SMP: %d package(s) x %d core(s)",
570 mp_ncpus / (cpu_cores * cpu_logical), cpu_cores);
571 if (hyperthreading_cpus > 1)
572 printf(" x %d HTT threads", cpu_logical);
573 else if (cpu_logical > 1)
574 printf(" x %d SMT threads", cpu_logical);
577 /* List active CPUs first. */
578 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id);
579 for (i = 1; i < mp_ncpus; i++) {
580 if (cpu_info[cpu_apic_ids[i]].cpu_hyperthread)
584 printf(" cpu%d (AP%s): APIC ID: %2d\n", i, hyperthread,
588 /* List disabled CPUs last. */
589 for (i = 0; i <= MAX_APIC_ID; i++) {
590 if (!cpu_info[i].cpu_present || !cpu_info[i].cpu_disabled)
592 if (cpu_info[i].cpu_hyperthread)
596 printf(" cpu (AP%s): APIC ID: %2d (disabled)\n", hyperthread,
602 * AP CPU's call this to initialize themselves.
611 int cpu, gsel_tss, x;
612 struct region_descriptor ap_gdt;
614 /* Set by the startup code for us to use */
618 common_tss[cpu] = common_tss[0];
619 common_tss[cpu].tss_rsp0 = 0; /* not used until after switch */
620 common_tss[cpu].tss_iobase = sizeof(struct amd64tss) +
622 common_tss[cpu].tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
624 /* The NMI stack runs on IST2. */
625 np = ((struct nmi_pcpu *) &nmi_stack[PAGE_SIZE]) - 1;
626 common_tss[cpu].tss_ist2 = (long) np;
628 /* Prepare private GDT */
629 gdt_segs[GPROC0_SEL].ssd_base = (long) &common_tss[cpu];
630 for (x = 0; x < NGDT; x++) {
631 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) &&
632 x != GUSERLDT_SEL && x != (GUSERLDT_SEL + 1))
633 ssdtosd(&gdt_segs[x], &gdt[NGDT * cpu + x]);
635 ssdtosyssd(&gdt_segs[GPROC0_SEL],
636 (struct system_segment_descriptor *)&gdt[NGDT * cpu + GPROC0_SEL]);
637 ap_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
638 ap_gdt.rd_base = (long) &gdt[NGDT * cpu];
639 lgdt(&ap_gdt); /* does magic intra-segment return */
641 /* Get per-cpu data */
644 /* prime data page for it to use */
645 pcpu_init(pc, cpu, sizeof(struct pcpu));
646 dpcpu_init(dpcpu, cpu);
647 pc->pc_apic_id = cpu_apic_ids[cpu];
648 pc->pc_prvspace = pc;
649 pc->pc_curthread = 0;
650 pc->pc_tssp = &common_tss[cpu];
651 pc->pc_commontssp = &common_tss[cpu];
653 pc->pc_tss = (struct system_segment_descriptor *)&gdt[NGDT * cpu +
655 pc->pc_fs32p = &gdt[NGDT * cpu + GUFS32_SEL];
656 pc->pc_gs32p = &gdt[NGDT * cpu + GUGS32_SEL];
657 pc->pc_ldt = (struct system_segment_descriptor *)&gdt[NGDT * cpu +
660 /* Save the per-cpu pointer for use by the NMI handler. */
661 np->np_pcpu = (register_t) pc;
663 wrmsr(MSR_FSBASE, 0); /* User value */
664 wrmsr(MSR_GSBASE, (u_int64_t)pc);
665 wrmsr(MSR_KGSBASE, (u_int64_t)pc); /* XXX User value while we're in the kernel */
669 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
673 * Set to a known state:
674 * Set by mpboot.s: CR0_PG, CR0_PE
675 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
678 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
681 /* Set up the fast syscall stuff */
682 msr = rdmsr(MSR_EFER) | EFER_SCE;
683 wrmsr(MSR_EFER, msr);
684 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
685 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
686 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
687 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
688 wrmsr(MSR_STAR, msr);
689 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
691 /* Disable local APIC just to be sure. */
694 /* signal our startup to the BSP. */
697 /* Spin until the BSP releases the AP's. */
701 /* Initialize the PAT MSR. */
704 /* set up CPU registers and state */
707 /* set up SSE/NX registers */
710 /* set up FPU state on the AP */
713 /* A quick check from sanity claus */
714 cpuid = PCPU_GET(cpuid);
715 if (PCPU_GET(apic_id) != lapic_id()) {
716 printf("SMP: cpuid = %d\n", cpuid);
717 printf("SMP: actual apic_id = %d\n", lapic_id());
718 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id));
719 panic("cpuid mismatch! boom!!");
722 /* Initialize curthread. */
723 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
724 PCPU_SET(curthread, PCPU_GET(idlethread));
728 mtx_lock_spin(&ap_boot_mtx);
730 /* Init local apic for irq's */
733 /* Set memory range attributes for this CPU to match the BSP */
738 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", cpuid);
739 printf("SMP: AP CPU #%d Launched!\n", cpuid);
741 /* Determine if we are a logical CPU. */
742 /* XXX Calculation depends on cpu_logical being a power of 2, e.g. 2 */
743 if (cpu_logical > 1 && PCPU_GET(apic_id) % cpu_logical != 0)
744 CPU_SET(cpuid, &logical_cpus_mask);
749 if (smp_cpus == mp_ncpus) {
750 /* enable IPI's, tlb shootdown, freezes etc */
751 atomic_store_rel_int(&smp_started, 1);
752 smp_active = 1; /* historic */
756 * Enable global pages TLB extension
757 * This also implicitly flushes the TLB
760 load_cr4(rcr4() | CR4_PGE);
764 mtx_unlock_spin(&ap_boot_mtx);
766 /* Wait until all the AP's are up. */
767 while (smp_started == 0)
770 /* Start per-CPU event timers. */
775 panic("scheduler returned us to %s", __func__);
779 /*******************************************************************
780 * local functions and data
784 * We tell the I/O APIC code about all the CPUs we want to receive
785 * interrupts. If we don't want certain CPUs to receive IRQs we
786 * can simply not tell the I/O APIC code about them in this function.
787 * We also do not tell it about the BSP since it tells itself about
788 * the BSP internally to work with UP kernels and on UP machines.
791 set_interrupt_apic_ids(void)
795 for (i = 0; i < MAXCPU; i++) {
796 apic_id = cpu_apic_ids[i];
799 if (cpu_info[apic_id].cpu_bsp)
801 if (cpu_info[apic_id].cpu_disabled)
804 /* Don't let hyperthreads service interrupts. */
805 if (hyperthreading_cpus > 1 &&
806 apic_id % hyperthreading_cpus != 0)
814 * Assign logical CPU IDs to local APICs.
821 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed",
822 &hyperthreading_allowed);
824 /* Check for explicitly disabled CPUs. */
825 for (i = 0; i <= MAX_APIC_ID; i++) {
826 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp)
829 if (hyperthreading_cpus > 1 && i % hyperthreading_cpus != 0) {
830 cpu_info[i].cpu_hyperthread = 1;
833 * Don't use HT CPU if it has been disabled by a
836 if (hyperthreading_allowed == 0) {
837 cpu_info[i].cpu_disabled = 1;
842 /* Don't use this CPU if it has been disabled by a tunable. */
843 if (resource_disabled("lapic", i)) {
844 cpu_info[i].cpu_disabled = 1;
849 if (hyperthreading_allowed == 0 && hyperthreading_cpus > 1) {
850 hyperthreading_cpus = 0;
855 * Assign CPU IDs to local APIC IDs and disable any CPUs
856 * beyond MAXCPU. CPU 0 is always assigned to the BSP.
858 * To minimize confusion for userland, we attempt to number
859 * CPUs such that all threads and cores in a package are
860 * grouped together. For now we assume that the BSP is always
861 * the first thread in a package and just start adding APs
862 * starting with the BSP's APIC ID.
865 cpu_apic_ids[0] = boot_cpu_id;
866 apic_cpuids[boot_cpu_id] = 0;
867 for (i = boot_cpu_id + 1; i != boot_cpu_id;
868 i == MAX_APIC_ID ? i = 0 : i++) {
869 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp ||
870 cpu_info[i].cpu_disabled)
873 if (mp_ncpus < MAXCPU) {
874 cpu_apic_ids[mp_ncpus] = i;
875 apic_cpuids[i] = mp_ncpus;
878 cpu_info[i].cpu_disabled = 1;
880 KASSERT(mp_maxid >= mp_ncpus - 1,
881 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid,
886 * start each AP in our list
891 vm_offset_t va = boot_address + KERNBASE;
892 u_int64_t *pt4, *pt3, *pt2;
893 u_int32_t mpbioswarmvec;
897 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
899 /* install the AP 1st level boot code */
900 pmap_kenter(va, boot_address);
901 pmap_invalidate_page(kernel_pmap, va);
902 bcopy(mptramp_start, (void *)va, bootMP_size);
904 /* Locate the page tables, they'll be below the trampoline */
905 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
906 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
907 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
909 /* Create the initial 1GB replicated page tables */
910 for (i = 0; i < 512; i++) {
911 /* Each slot of the level 4 pages points to the same level 3 page */
912 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
913 pt4[i] |= PG_V | PG_RW | PG_U;
915 /* Each slot of the level 3 pages points to the same level 2 page */
916 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
917 pt3[i] |= PG_V | PG_RW | PG_U;
919 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
920 pt2[i] = i * (2 * 1024 * 1024);
921 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
924 /* save the current value of the warm-start vector */
925 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
926 outb(CMOS_REG, BIOS_RESET);
927 mpbiosreason = inb(CMOS_DATA);
929 /* setup a vector to our boot code */
930 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
931 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
932 outb(CMOS_REG, BIOS_RESET);
933 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
936 for (cpu = 1; cpu < mp_ncpus; cpu++) {
937 apic_id = cpu_apic_ids[cpu];
939 /* allocate and set up an idle stack data page */
940 bootstacks[cpu] = (void *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE);
941 doublefault_stack = (char *)kmem_alloc(kernel_map, PAGE_SIZE);
942 nmi_stack = (char *)kmem_alloc(kernel_map, PAGE_SIZE);
943 dpcpu = (void *)kmem_alloc(kernel_map, DPCPU_SIZE);
945 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 8;
948 /* attempt to start the Application Processor */
949 if (!start_ap(apic_id)) {
950 /* restore the warmstart vector */
951 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
952 panic("AP #%d (PHY# %d) failed!", cpu, apic_id);
955 CPU_SET(cpu, &all_cpus); /* record AP in CPU map */
958 /* restore the warmstart vector */
959 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
961 outb(CMOS_REG, BIOS_RESET);
962 outb(CMOS_DATA, mpbiosreason);
964 /* number of APs actually started */
970 * This function starts the AP (application processor) identified
971 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
972 * to accomplish this. This is necessary because of the nuances
973 * of the different hardware we might encounter. It isn't pretty,
974 * but it seems to work.
977 start_ap(int apic_id)
982 /* calculate the vector */
983 vector = (boot_address >> 12) & 0xff;
985 /* used as a watchpoint to signal AP startup */
989 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
990 * and running the target CPU. OR this INIT IPI might be latched (P5
991 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
995 /* do an INIT IPI: assert RESET */
996 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
997 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id);
999 /* wait for pending status end */
1002 /* do an INIT IPI: deassert RESET */
1003 lapic_ipi_raw(APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL |
1004 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 0);
1006 /* wait for pending status end */
1007 DELAY(10000); /* wait ~10mS */
1011 * next we do a STARTUP IPI: the previous INIT IPI might still be
1012 * latched, (P5 bug) this 1st STARTUP would then terminate
1013 * immediately, and the previously started INIT IPI would continue. OR
1014 * the previous INIT IPI has already run. and this STARTUP IPI will
1015 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
1019 /* do a STARTUP IPI */
1020 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
1021 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
1024 DELAY(200); /* wait ~200uS */
1027 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
1028 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
1029 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
1030 * recognized after hardware RESET or INIT IPI.
1033 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
1034 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
1037 DELAY(200); /* wait ~200uS */
1039 /* Wait up to 5 seconds for it to start. */
1040 for (ms = 0; ms < 5000; ms++) {
1042 return 1; /* return SUCCESS */
1045 return 0; /* return FAILURE */
1048 #ifdef COUNT_XINVLTLB_HITS
1049 u_int xhits_gbl[MAXCPU];
1050 u_int xhits_pg[MAXCPU];
1051 u_int xhits_rng[MAXCPU];
1052 SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, "");
1053 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl,
1054 sizeof(xhits_gbl), "IU", "");
1055 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg,
1056 sizeof(xhits_pg), "IU", "");
1057 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng,
1058 sizeof(xhits_rng), "IU", "");
1063 u_int ipi_range_size;
1064 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, "");
1065 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, "");
1066 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, "");
1067 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW,
1068 &ipi_range_size, 0, "");
1070 u_int ipi_masked_global;
1071 u_int ipi_masked_page;
1072 u_int ipi_masked_range;
1073 u_int ipi_masked_range_size;
1074 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW,
1075 &ipi_masked_global, 0, "");
1076 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW,
1077 &ipi_masked_page, 0, "");
1078 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW,
1079 &ipi_masked_range, 0, "");
1080 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW,
1081 &ipi_masked_range_size, 0, "");
1082 #endif /* COUNT_XINVLTLB_HITS */
1085 * Send an IPI to specified CPU handling the bitmap logic.
1088 ipi_send_cpu(int cpu, u_int ipi)
1090 u_int bitmap, old_pending, new_pending;
1092 KASSERT(cpu_apic_ids[cpu] != -1, ("IPI to non-existent CPU %d", cpu));
1094 if (IPI_IS_BITMAPED(ipi)) {
1096 ipi = IPI_BITMAP_VECTOR;
1098 old_pending = cpu_ipi_pending[cpu];
1099 new_pending = old_pending | bitmap;
1100 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu],
1101 old_pending, new_pending));
1105 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]);
1109 * Flush the TLB on all other CPU's
1112 smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2)
1116 ncpu = mp_ncpus - 1; /* does not shootdown self */
1118 return; /* no other cpus */
1119 if (!(read_rflags() & PSL_I))
1120 panic("%s: interrupts disabled", __func__);
1121 mtx_lock_spin(&smp_ipi_mtx);
1122 smp_tlb_addr1 = addr1;
1123 smp_tlb_addr2 = addr2;
1124 atomic_store_rel_int(&smp_tlb_wait, 0);
1125 ipi_all_but_self(vector);
1126 while (smp_tlb_wait < ncpu)
1128 mtx_unlock_spin(&smp_ipi_mtx);
1132 smp_targeted_tlb_shootdown(cpuset_t mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2)
1134 int cpu, ncpu, othercpus;
1136 othercpus = mp_ncpus - 1;
1137 if (CPU_ISFULLSET(&mask)) {
1141 CPU_CLR(PCPU_GET(cpuid), &mask);
1142 if (CPU_EMPTY(&mask))
1145 if (!(read_rflags() & PSL_I))
1146 panic("%s: interrupts disabled", __func__);
1147 mtx_lock_spin(&smp_ipi_mtx);
1148 smp_tlb_addr1 = addr1;
1149 smp_tlb_addr2 = addr2;
1150 atomic_store_rel_int(&smp_tlb_wait, 0);
1151 if (CPU_ISFULLSET(&mask)) {
1153 ipi_all_but_self(vector);
1156 while ((cpu = cpusetobj_ffs(&mask)) != 0) {
1158 CPU_CLR(cpu, &mask);
1159 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__,
1161 ipi_send_cpu(cpu, vector);
1165 while (smp_tlb_wait < ncpu)
1167 mtx_unlock_spin(&smp_ipi_mtx);
1171 smp_cache_flush(void)
1175 smp_tlb_shootdown(IPI_INVLCACHE, 0, 0);
1183 smp_tlb_shootdown(IPI_INVLTLB, 0, 0);
1184 #ifdef COUNT_XINVLTLB_HITS
1191 smp_invlpg(vm_offset_t addr)
1195 smp_tlb_shootdown(IPI_INVLPG, addr, 0);
1196 #ifdef COUNT_XINVLTLB_HITS
1203 smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2)
1207 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2);
1208 #ifdef COUNT_XINVLTLB_HITS
1210 ipi_range_size += (addr2 - addr1) / PAGE_SIZE;
1216 smp_masked_invltlb(cpuset_t mask)
1220 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0);
1221 #ifdef COUNT_XINVLTLB_HITS
1222 ipi_masked_global++;
1228 smp_masked_invlpg(cpuset_t mask, vm_offset_t addr)
1232 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0);
1233 #ifdef COUNT_XINVLTLB_HITS
1240 smp_masked_invlpg_range(cpuset_t mask, vm_offset_t addr1, vm_offset_t addr2)
1244 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2);
1245 #ifdef COUNT_XINVLTLB_HITS
1247 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE;
1253 ipi_bitmap_handler(struct trapframe frame)
1255 struct trapframe *oldframe;
1257 int cpu = PCPU_GET(cpuid);
1262 td->td_intr_nesting_level++;
1263 oldframe = td->td_intr_frame;
1264 td->td_intr_frame = &frame;
1265 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]);
1266 if (ipi_bitmap & (1 << IPI_PREEMPT)) {
1268 (*ipi_preempt_counts[cpu])++;
1272 if (ipi_bitmap & (1 << IPI_AST)) {
1274 (*ipi_ast_counts[cpu])++;
1276 /* Nothing to do for AST */
1278 if (ipi_bitmap & (1 << IPI_HARDCLOCK)) {
1280 (*ipi_hardclock_counts[cpu])++;
1284 td->td_intr_frame = oldframe;
1285 td->td_intr_nesting_level--;
1290 * send an IPI to a set of cpus.
1293 ipi_selected(cpuset_t cpus, u_int ipi)
1298 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1299 * of help in order to understand what is the source.
1300 * Set the mask of receiving CPUs for this purpose.
1302 if (ipi == IPI_STOP_HARD)
1303 CPU_OR_ATOMIC(&ipi_nmi_pending, &cpus);
1305 while ((cpu = cpusetobj_ffs(&cpus)) != 0) {
1307 CPU_CLR(cpu, &cpus);
1308 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
1309 ipi_send_cpu(cpu, ipi);
1314 * send an IPI to a specific CPU.
1317 ipi_cpu(int cpu, u_int ipi)
1321 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1322 * of help in order to understand what is the source.
1323 * Set the mask of receiving CPUs for this purpose.
1325 if (ipi == IPI_STOP_HARD)
1326 CPU_SET_ATOMIC(cpu, &ipi_nmi_pending);
1328 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
1329 ipi_send_cpu(cpu, ipi);
1333 * send an IPI to all CPUs EXCEPT myself
1336 ipi_all_but_self(u_int ipi)
1338 cpuset_t other_cpus;
1340 other_cpus = all_cpus;
1341 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
1343 if (IPI_IS_BITMAPED(ipi)) {
1344 ipi_selected(other_cpus, ipi);
1349 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1350 * of help in order to understand what is the source.
1351 * Set the mask of receiving CPUs for this purpose.
1353 if (ipi == IPI_STOP_HARD)
1354 CPU_OR_ATOMIC(&ipi_nmi_pending, &other_cpus);
1356 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
1357 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS);
1366 * As long as there is not a simple way to know about a NMI's
1367 * source, if the bitmask for the current CPU is present in
1368 * the global pending bitword an IPI_STOP_HARD has been issued
1369 * and should be handled.
1371 cpuid = PCPU_GET(cpuid);
1372 if (!CPU_ISSET(cpuid, &ipi_nmi_pending))
1375 CPU_CLR_ATOMIC(cpuid, &ipi_nmi_pending);
1381 * Handle an IPI_STOP by saving our current context and spinning until we
1385 cpustop_handler(void)
1389 cpu = PCPU_GET(cpuid);
1391 savectx(&stoppcbs[cpu]);
1393 /* Indicate that we are stopped */
1394 CPU_SET_ATOMIC(cpu, &stopped_cpus);
1396 /* Wait for restart */
1397 while (!CPU_ISSET(cpu, &started_cpus))
1400 CPU_CLR_ATOMIC(cpu, &started_cpus);
1401 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
1403 if (cpu == 0 && cpustop_restartfunc != NULL) {
1404 cpustop_restartfunc();
1405 cpustop_restartfunc = NULL;
1410 * Handle an IPI_SUSPEND by saving our current context and spinning until we
1414 cpususpend_handler(void)
1419 cpu = PCPU_GET(cpuid);
1421 rf = intr_disable();
1424 if (savectx(susppcbs[cpu])) {
1426 CPU_SET_ATOMIC(cpu, &stopped_cpus);
1429 PCPU_SET(switchtime, 0);
1430 PCPU_SET(switchticks, ticks);
1433 /* Wait for resume */
1434 while (!CPU_ISSET(cpu, &started_cpus))
1437 CPU_CLR_ATOMIC(cpu, &started_cpus);
1438 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
1440 /* Restore CR3 and enable interrupts */
1448 * This is called once the rest of the system is up and running and we're
1449 * ready to let the AP's out of the pen.
1452 release_aps(void *dummy __unused)
1457 atomic_store_rel_int(&aps_ready, 1);
1458 while (smp_started == 0)
1461 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
1465 * Setup interrupt counters for IPI handlers.
1468 mp_ipi_intrcnt(void *dummy)
1474 snprintf(buf, sizeof(buf), "cpu%d:invltlb", i);
1475 intrcnt_add(buf, &ipi_invltlb_counts[i]);
1476 snprintf(buf, sizeof(buf), "cpu%d:invlrng", i);
1477 intrcnt_add(buf, &ipi_invlrng_counts[i]);
1478 snprintf(buf, sizeof(buf), "cpu%d:invlpg", i);
1479 intrcnt_add(buf, &ipi_invlpg_counts[i]);
1480 snprintf(buf, sizeof(buf), "cpu%d:preempt", i);
1481 intrcnt_add(buf, &ipi_preempt_counts[i]);
1482 snprintf(buf, sizeof(buf), "cpu%d:ast", i);
1483 intrcnt_add(buf, &ipi_ast_counts[i]);
1484 snprintf(buf, sizeof(buf), "cpu%d:rendezvous", i);
1485 intrcnt_add(buf, &ipi_rendezvous_counts[i]);
1486 snprintf(buf, sizeof(buf), "cpu%d:hardclock", i);
1487 intrcnt_add(buf, &ipi_hardclock_counts[i]);
1490 SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL);