1 /* From: $NetBSD: pmap.c,v 1.148 2004/04/03 04:35:48 bsh Exp $ */
3 * Copyright 2004 Olivier Houchard.
4 * Copyright 2003 Wasabi Systems, Inc.
7 * Written by Steve C. Woodford for Wasabi Systems, Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
39 * Copyright (c) 2002-2003 Wasabi Systems, Inc.
40 * Copyright (c) 2001 Richard Earnshaw
41 * Copyright (c) 2001-2002 Christopher Gilbert
42 * All rights reserved.
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. The name of the company nor the name of the author may be used to
50 * endorse or promote products derived from this software without specific
51 * prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
66 * Copyright (c) 1999 The NetBSD Foundation, Inc.
67 * All rights reserved.
69 * This code is derived from software contributed to The NetBSD Foundation
70 * by Charles M. Hannum.
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
81 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
82 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
83 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
84 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
85 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
86 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
87 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
88 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
89 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
90 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
91 * POSSIBILITY OF SUCH DAMAGE.
95 * Copyright (c) 1994-1998 Mark Brinicombe.
96 * Copyright (c) 1994 Brini.
97 * All rights reserved.
99 * This code is derived from software written for Brini by Mark Brinicombe
101 * Redistribution and use in source and binary forms, with or without
102 * modification, are permitted provided that the following conditions
104 * 1. Redistributions of source code must retain the above copyright
105 * notice, this list of conditions and the following disclaimer.
106 * 2. Redistributions in binary form must reproduce the above copyright
107 * notice, this list of conditions and the following disclaimer in the
108 * documentation and/or other materials provided with the distribution.
109 * 3. All advertising materials mentioning features or use of this software
110 * must display the following acknowledgement:
111 * This product includes software developed by Mark Brinicombe.
112 * 4. The name of the author may not be used to endorse or promote products
113 * derived from this software without specific prior written permission.
115 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
116 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
117 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
118 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
119 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
120 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
121 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
122 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
123 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
125 * RiscBSD kernel project
129 * Machine dependant vm stuff
135 * Special compilation symbols
136 * PMAP_DEBUG - Build in pmap_debug_level code
138 /* Include header files */
142 #include <sys/cdefs.h>
143 __FBSDID("$FreeBSD$");
144 #include <sys/param.h>
145 #include <sys/systm.h>
146 #include <sys/kernel.h>
148 #include <sys/proc.h>
149 #include <sys/malloc.h>
150 #include <sys/msgbuf.h>
151 #include <sys/vmmeter.h>
152 #include <sys/mman.h>
154 #include <sys/sched.h>
159 #include <vm/vm_kern.h>
160 #include <vm/vm_object.h>
161 #include <vm/vm_map.h>
162 #include <vm/vm_page.h>
163 #include <vm/vm_pageout.h>
164 #include <vm/vm_extern.h>
165 #include <sys/lock.h>
166 #include <sys/mutex.h>
167 #include <machine/md_var.h>
168 #include <machine/vmparam.h>
169 #include <machine/cpu.h>
170 #include <machine/cpufunc.h>
171 #include <machine/pcb.h>
174 #define PDEBUG(_lev_,_stat_) \
175 if (pmap_debug_level >= (_lev_)) \
177 #define dprintf printf
179 int pmap_debug_level = 0;
181 #else /* PMAP_DEBUG */
182 #define PDEBUG(_lev_,_stat_) /* Nothing */
183 #define dprintf(x, arg...)
184 #define PMAP_INLINE __inline
185 #endif /* PMAP_DEBUG */
187 extern struct pv_addr systempage;
189 * Internal function prototypes
191 static void pmap_free_pv_entry (pv_entry_t);
192 static pv_entry_t pmap_get_pv_entry(void);
194 static void pmap_enter_locked(pmap_t, vm_offset_t, vm_page_t,
195 vm_prot_t, boolean_t, int);
196 static void pmap_fix_cache(struct vm_page *, pmap_t, vm_offset_t);
197 static void pmap_alloc_l1(pmap_t);
198 static void pmap_free_l1(pmap_t);
200 static int pmap_clearbit(struct vm_page *, u_int);
202 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vm_offset_t);
203 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vm_offset_t);
204 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int);
205 static vm_offset_t kernel_pt_lookup(vm_paddr_t);
207 static MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1");
209 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
210 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
211 vm_offset_t pmap_curmaxkvaddr;
212 vm_paddr_t kernel_l1pa;
215 vm_offset_t kernel_vm_end = 0;
217 struct pmap kernel_pmap_store;
219 static pt_entry_t *csrc_pte, *cdst_pte;
220 static vm_offset_t csrcp, cdstp;
221 static struct mtx cmtx;
223 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *);
225 * These routines are called when the CPU type is identified to set up
226 * the PTE prototypes, cache modes, etc.
228 * The variables are always here, just in case LKMs need to reference
229 * them (though, they shouldn't).
232 pt_entry_t pte_l1_s_cache_mode;
233 pt_entry_t pte_l1_s_cache_mode_pt;
234 pt_entry_t pte_l1_s_cache_mask;
236 pt_entry_t pte_l2_l_cache_mode;
237 pt_entry_t pte_l2_l_cache_mode_pt;
238 pt_entry_t pte_l2_l_cache_mask;
240 pt_entry_t pte_l2_s_cache_mode;
241 pt_entry_t pte_l2_s_cache_mode_pt;
242 pt_entry_t pte_l2_s_cache_mask;
244 pt_entry_t pte_l2_s_prot_u;
245 pt_entry_t pte_l2_s_prot_w;
246 pt_entry_t pte_l2_s_prot_mask;
248 pt_entry_t pte_l1_s_proto;
249 pt_entry_t pte_l1_c_proto;
250 pt_entry_t pte_l2_s_proto;
252 void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t);
253 void (*pmap_zero_page_func)(vm_paddr_t, int, int);
255 * Which pmap is currently 'live' in the cache
257 * XXXSCW: Fix for SMP ...
259 union pmap_cache_state *pmap_cache_state;
261 struct msgbuf *msgbufp = 0;
266 static caddr_t crashdumpmap;
268 extern void bcopy_page(vm_offset_t, vm_offset_t);
269 extern void bzero_page(vm_offset_t);
271 extern vm_offset_t alloc_firstaddr;
276 * Metadata for L1 translation tables.
279 /* Entry on the L1 Table list */
280 SLIST_ENTRY(l1_ttable) l1_link;
282 /* Entry on the L1 Least Recently Used list */
283 TAILQ_ENTRY(l1_ttable) l1_lru;
285 /* Track how many domains are allocated from this L1 */
286 volatile u_int l1_domain_use_count;
289 * A free-list of domain numbers for this L1.
290 * We avoid using ffs() and a bitmap to track domains since ffs()
293 u_int8_t l1_domain_first;
294 u_int8_t l1_domain_free[PMAP_DOMAINS];
296 /* Physical address of this L1 page table */
297 vm_paddr_t l1_physaddr;
299 /* KVA of this L1 page table */
304 * Convert a virtual address into its L1 table index. That is, the
305 * index used to locate the L2 descriptor table pointer in an L1 table.
306 * This is basically used to index l1->l1_kva[].
308 * Each L2 descriptor table represents 1MB of VA space.
310 #define L1_IDX(va) (((vm_offset_t)(va)) >> L1_S_SHIFT)
313 * L1 Page Tables are tracked using a Least Recently Used list.
314 * - New L1s are allocated from the HEAD.
315 * - Freed L1s are added to the TAIl.
316 * - Recently accessed L1s (where an 'access' is some change to one of
317 * the userland pmaps which owns this L1) are moved to the TAIL.
319 static TAILQ_HEAD(, l1_ttable) l1_lru_list;
321 * A list of all L1 tables
323 static SLIST_HEAD(, l1_ttable) l1_list;
324 static struct mtx l1_lru_lock;
327 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots.
329 * This is normally 16MB worth L2 page descriptors for any given pmap.
330 * Reference counts are maintained for L2 descriptors so they can be
334 /* The number of L2 page descriptors allocated to this l2_dtable */
337 /* List of L2 page descriptors */
339 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */
340 vm_paddr_t l2b_phys; /* Physical address of same */
341 u_short l2b_l1idx; /* This L2 table's L1 index */
342 u_short l2b_occupancy; /* How many active descriptors */
343 } l2_bucket[L2_BUCKET_SIZE];
346 /* pmap_kenter_internal flags */
347 #define KENTER_CACHE 0x1
348 #define KENTER_USER 0x2
351 * Given an L1 table index, calculate the corresponding l2_dtable index
352 * and bucket index within the l2_dtable.
354 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \
356 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1))
359 * Given a virtual address, this macro returns the
360 * virtual address required to drop into the next L2 bucket.
362 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE)
367 #define pmap_alloc_l2_dtable() \
368 (void*)uma_zalloc(l2table_zone, M_NOWAIT|M_USE_RESERVE)
369 #define pmap_free_l2_dtable(l2) \
370 uma_zfree(l2table_zone, l2)
373 * We try to map the page tables write-through, if possible. However, not
374 * all CPUs have a write-through cache mode, so on those we have to sync
375 * the cache when we frob page tables.
377 * We try to evaluate this at compile time, if possible. However, it's
378 * not always possible to do that, hence this run-time var.
380 int pmap_needs_pte_sync;
383 * Macro to determine if a mapping might be resident in the
384 * instruction cache and/or TLB
386 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC))
389 * Macro to determine if a mapping might be resident in the
390 * data cache and/or TLB
392 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0)
394 #ifndef PMAP_SHPGPERPROC
395 #define PMAP_SHPGPERPROC 200
398 #define pmap_is_current(pm) ((pm) == pmap_kernel() || \
399 curproc->p_vmspace->vm_map.pmap == (pm))
400 static uma_zone_t pvzone = NULL;
402 static uma_zone_t l2table_zone;
403 static vm_offset_t pmap_kernel_l2dtable_kva;
404 static vm_offset_t pmap_kernel_l2ptp_kva;
405 static vm_paddr_t pmap_kernel_l2ptp_phys;
406 static struct vm_object pvzone_obj;
407 static int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0;
410 * This list exists for the benefit of pmap_map_chunk(). It keeps track
411 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can
412 * find them as necessary.
414 * Note that the data on this list MUST remain valid after initarm() returns,
415 * as pmap_bootstrap() uses it to contruct L2 table metadata.
417 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list);
420 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt)
425 l1->l1_domain_use_count = 0;
426 l1->l1_domain_first = 0;
428 for (i = 0; i < PMAP_DOMAINS; i++)
429 l1->l1_domain_free[i] = i + 1;
432 * Copy the kernel's L1 entries to each new L1.
434 if (l1pt != pmap_kernel()->pm_l1->l1_kva)
435 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE);
437 if ((l1->l1_physaddr = pmap_extract(pmap_kernel(), (vm_offset_t)l1pt)) == 0)
438 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt);
439 SLIST_INSERT_HEAD(&l1_list, l1, l1_link);
440 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
444 kernel_pt_lookup(vm_paddr_t pa)
448 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) {
455 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
457 pmap_pte_init_generic(void)
460 pte_l1_s_cache_mode = L1_S_B|L1_S_C;
461 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic;
463 pte_l2_l_cache_mode = L2_B|L2_C;
464 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic;
466 pte_l2_s_cache_mode = L2_B|L2_C;
467 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic;
470 * If we have a write-through cache, set B and C. If
471 * we have a write-back cache, then we assume setting
472 * only C will make those pages write-through.
474 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) {
475 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;
476 pte_l2_l_cache_mode_pt = L2_B|L2_C;
477 pte_l2_s_cache_mode_pt = L2_B|L2_C;
479 pte_l1_s_cache_mode_pt = L1_S_C;
480 pte_l2_l_cache_mode_pt = L2_C;
481 pte_l2_s_cache_mode_pt = L2_C;
484 pte_l2_s_prot_u = L2_S_PROT_U_generic;
485 pte_l2_s_prot_w = L2_S_PROT_W_generic;
486 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic;
488 pte_l1_s_proto = L1_S_PROTO_generic;
489 pte_l1_c_proto = L1_C_PROTO_generic;
490 pte_l2_s_proto = L2_S_PROTO_generic;
492 pmap_copy_page_func = pmap_copy_page_generic;
493 pmap_zero_page_func = pmap_zero_page_generic;
496 #if defined(CPU_ARM8)
498 pmap_pte_init_arm8(void)
502 * ARM8 is compatible with generic, but we need to use
503 * the page tables uncached.
505 pmap_pte_init_generic();
507 pte_l1_s_cache_mode_pt = 0;
508 pte_l2_l_cache_mode_pt = 0;
509 pte_l2_s_cache_mode_pt = 0;
511 #endif /* CPU_ARM8 */
513 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH)
515 pmap_pte_init_arm9(void)
519 * ARM9 is compatible with generic, but we want to use
520 * write-through caching for now.
522 pmap_pte_init_generic();
524 pte_l1_s_cache_mode = L1_S_C;
525 pte_l2_l_cache_mode = L2_C;
526 pte_l2_s_cache_mode = L2_C;
528 pte_l1_s_cache_mode_pt = L1_S_C;
529 pte_l2_l_cache_mode_pt = L2_C;
530 pte_l2_s_cache_mode_pt = L2_C;
532 #endif /* CPU_ARM9 */
533 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
535 #if defined(CPU_ARM10)
537 pmap_pte_init_arm10(void)
541 * ARM10 is compatible with generic, but we want to use
542 * write-through caching for now.
544 pmap_pte_init_generic();
546 pte_l1_s_cache_mode = L1_S_B | L1_S_C;
547 pte_l2_l_cache_mode = L2_B | L2_C;
548 pte_l2_s_cache_mode = L2_B | L2_C;
550 pte_l1_s_cache_mode_pt = L1_S_C;
551 pte_l2_l_cache_mode_pt = L2_C;
552 pte_l2_s_cache_mode_pt = L2_C;
555 #endif /* CPU_ARM10 */
559 pmap_pte_init_sa1(void)
563 * The StrongARM SA-1 cache does not have a write-through
564 * mode. So, do the generic initialization, then reset
565 * the page table cache mode to B=1,C=1, and note that
566 * the PTEs need to be sync'd.
568 pmap_pte_init_generic();
570 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;
571 pte_l2_l_cache_mode_pt = L2_B|L2_C;
572 pte_l2_s_cache_mode_pt = L2_B|L2_C;
574 pmap_needs_pte_sync = 1;
576 #endif /* ARM_MMU_SA1 == 1*/
578 #if ARM_MMU_XSCALE == 1
579 #if (ARM_NMMUS > 1) || defined (CPU_XSCALE_CORE3)
580 static u_int xscale_use_minidata;
584 pmap_pte_init_xscale(void)
587 int write_through = 0;
589 pte_l1_s_cache_mode = L1_S_B|L1_S_C|L1_S_XSCALE_P;
590 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale;
592 pte_l2_l_cache_mode = L2_B|L2_C;
593 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale;
595 pte_l2_s_cache_mode = L2_B|L2_C;
596 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale;
598 pte_l1_s_cache_mode_pt = L1_S_C;
599 pte_l2_l_cache_mode_pt = L2_C;
600 pte_l2_s_cache_mode_pt = L2_C;
601 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE
603 * The XScale core has an enhanced mode where writes that
604 * miss the cache cause a cache line to be allocated. This
605 * is significantly faster than the traditional, write-through
606 * behavior of this case.
608 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X);
609 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X);
610 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X);
611 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */
612 #ifdef XSCALE_CACHE_WRITE_THROUGH
614 * Some versions of the XScale core have various bugs in
615 * their cache units, the work-around for which is to run
616 * the cache in write-through mode. Unfortunately, this
617 * has a major (negative) impact on performance. So, we
618 * go ahead and run fast-and-loose, in the hopes that we
619 * don't line up the planets in a way that will trip the
622 * However, we give you the option to be slow-but-correct.
625 #elif defined(XSCALE_CACHE_WRITE_BACK)
626 /* force write back cache mode */
628 #elif defined(CPU_XSCALE_PXA2X0)
630 * Intel PXA2[15]0 processors are known to have a bug in
631 * write-back cache on revision 4 and earlier (stepping
632 * A[01] and B[012]). Fixed for C0 and later.
638 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK);
640 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) {
641 if ((id & CPU_ID_REVISION_MASK) < 5) {
642 /* write through for stepping A0-1 and B0-2 */
647 #endif /* XSCALE_CACHE_WRITE_THROUGH */
650 pte_l1_s_cache_mode = L1_S_C;
651 pte_l2_l_cache_mode = L2_C;
652 pte_l2_s_cache_mode = L2_C;
656 xscale_use_minidata = 1;
659 pte_l2_s_prot_u = L2_S_PROT_U_xscale;
660 pte_l2_s_prot_w = L2_S_PROT_W_xscale;
661 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale;
663 pte_l1_s_proto = L1_S_PROTO_xscale;
664 pte_l1_c_proto = L1_C_PROTO_xscale;
665 pte_l2_s_proto = L2_S_PROTO_xscale;
667 #ifdef CPU_XSCALE_CORE3
668 pmap_copy_page_func = pmap_copy_page_generic;
669 pmap_zero_page_func = pmap_zero_page_generic;
670 xscale_use_minidata = 0;
671 /* Make sure it is L2-cachable */
672 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_T);
673 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode &~ L1_S_XSCALE_P;
674 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_T) ;
675 pte_l2_l_cache_mode_pt = pte_l1_s_cache_mode;
676 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_T);
677 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode;
680 pmap_copy_page_func = pmap_copy_page_xscale;
681 pmap_zero_page_func = pmap_zero_page_xscale;
685 * Disable ECC protection of page table access, for now.
687 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl));
688 auxctl &= ~XSCALE_AUXCTL_P;
689 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl));
693 * xscale_setup_minidata:
695 * Set up the mini-data cache clean area. We require the
696 * caller to allocate the right amount of physically and
697 * virtually contiguous space.
699 extern vm_offset_t xscale_minidata_clean_addr;
700 extern vm_size_t xscale_minidata_clean_size; /* already initialized */
702 xscale_setup_minidata(vm_offset_t l1pt, vm_offset_t va, vm_paddr_t pa)
704 pd_entry_t *pde = (pd_entry_t *) l1pt;
709 xscale_minidata_clean_addr = va;
711 /* Round it to page size. */
712 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME;
715 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) {
716 pte = (pt_entry_t *) kernel_pt_lookup(
717 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
719 panic("xscale_setup_minidata: can't find L2 table for "
720 "VA 0x%08x", (u_int32_t) va);
721 pte[l2pte_index(va)] =
722 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
723 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X);
727 * Configure the mini-data cache for write-back with
728 * read/write-allocate.
730 * NOTE: In order to reconfigure the mini-data cache, we must
731 * make sure it contains no valid data! In order to do that,
732 * we must issue a global data cache invalidate command!
734 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED!
735 * THIS IS VERY IMPORTANT!
738 /* Invalidate data and mini-data. */
739 __asm __volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
740 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl));
741 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA;
742 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl));
747 * Allocate an L1 translation table for the specified pmap.
748 * This is called at pmap creation time.
751 pmap_alloc_l1(pmap_t pm)
753 struct l1_ttable *l1;
757 * Remove the L1 at the head of the LRU list
759 mtx_lock(&l1_lru_lock);
760 l1 = TAILQ_FIRST(&l1_lru_list);
761 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
764 * Pick the first available domain number, and update
765 * the link to the next number.
767 domain = l1->l1_domain_first;
768 l1->l1_domain_first = l1->l1_domain_free[domain];
771 * If there are still free domain numbers in this L1,
772 * put it back on the TAIL of the LRU list.
774 if (++l1->l1_domain_use_count < PMAP_DOMAINS)
775 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
777 mtx_unlock(&l1_lru_lock);
780 * Fix up the relevant bits in the pmap structure
783 pm->pm_domain = domain + 1;
787 * Free an L1 translation table.
788 * This is called at pmap destruction time.
791 pmap_free_l1(pmap_t pm)
793 struct l1_ttable *l1 = pm->pm_l1;
795 mtx_lock(&l1_lru_lock);
798 * If this L1 is currently on the LRU list, remove it.
800 if (l1->l1_domain_use_count < PMAP_DOMAINS)
801 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
804 * Free up the domain number which was allocated to the pmap
806 l1->l1_domain_free[pm->pm_domain - 1] = l1->l1_domain_first;
807 l1->l1_domain_first = pm->pm_domain - 1;
808 l1->l1_domain_use_count--;
811 * The L1 now must have at least 1 free domain, so add
812 * it back to the LRU list. If the use count is zero,
813 * put it at the head of the list, otherwise it goes
816 if (l1->l1_domain_use_count == 0) {
817 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru);
819 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
821 mtx_unlock(&l1_lru_lock);
825 * Returns a pointer to the L2 bucket associated with the specified pmap
826 * and VA, or NULL if no L2 bucket exists for the address.
828 static PMAP_INLINE struct l2_bucket *
829 pmap_get_l2_bucket(pmap_t pm, vm_offset_t va)
831 struct l2_dtable *l2;
832 struct l2_bucket *l2b;
837 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL ||
838 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL)
845 * Returns a pointer to the L2 bucket associated with the specified pmap
848 * If no L2 bucket exists, perform the necessary allocations to put an L2
849 * bucket/page table in place.
851 * Note that if a new L2 bucket/page was allocated, the caller *must*
852 * increment the bucket occupancy counter appropriately *before*
853 * releasing the pmap's lock to ensure no other thread or cpu deallocates
854 * the bucket/page in the meantime.
856 static struct l2_bucket *
857 pmap_alloc_l2_bucket(pmap_t pm, vm_offset_t va)
859 struct l2_dtable *l2;
860 struct l2_bucket *l2b;
865 PMAP_ASSERT_LOCKED(pm);
866 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
867 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
869 * No mapping at this address, as there is
870 * no entry in the L1 table.
871 * Need to allocate a new l2_dtable.
875 vm_page_unlock_queues();
876 if ((l2 = pmap_alloc_l2_dtable()) == NULL) {
877 vm_page_lock_queues();
881 vm_page_lock_queues();
883 if (pm->pm_l2[L2_IDX(l1idx)] != NULL) {
885 vm_page_unlock_queues();
886 uma_zfree(l2table_zone, l2);
887 vm_page_lock_queues();
889 l2 = pm->pm_l2[L2_IDX(l1idx)];
893 * Someone already allocated the l2_dtable while
894 * we were doing the same.
897 bzero(l2, sizeof(*l2));
899 * Link it into the parent pmap
901 pm->pm_l2[L2_IDX(l1idx)] = l2;
905 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
908 * Fetch pointer to the L2 page table associated with the address.
910 if (l2b->l2b_kva == NULL) {
914 * No L2 page table has been allocated. Chances are, this
915 * is because we just allocated the l2_dtable, above.
919 vm_page_unlock_queues();
920 ptep = (void*)uma_zalloc(l2zone, M_NOWAIT|M_USE_RESERVE);
921 vm_page_lock_queues();
923 if (l2b->l2b_kva != 0) {
924 /* We lost the race. */
926 vm_page_unlock_queues();
927 uma_zfree(l2zone, ptep);
928 vm_page_lock_queues();
930 if (l2b->l2b_kva == 0)
934 l2b->l2b_phys = vtophys(ptep);
937 * Oops, no more L2 page tables available at this
938 * time. We may need to deallocate the l2_dtable
939 * if we allocated a new one above.
941 if (l2->l2_occupancy == 0) {
942 pm->pm_l2[L2_IDX(l1idx)] = NULL;
943 pmap_free_l2_dtable(l2);
950 l2b->l2b_l1idx = l1idx;
956 static PMAP_INLINE void
957 #ifndef PMAP_INCLUDE_PTE_SYNC
958 pmap_free_l2_ptp(pt_entry_t *l2)
960 pmap_free_l2_ptp(boolean_t need_sync, pt_entry_t *l2)
963 #ifdef PMAP_INCLUDE_PTE_SYNC
965 * Note: With a write-back cache, we may need to sync this
966 * L2 table before re-using it.
967 * This is because it may have belonged to a non-current
968 * pmap, in which case the cache syncs would have been
969 * skipped when the pages were being unmapped. If the
970 * L2 table were then to be immediately re-allocated to
971 * the *current* pmap, it may well contain stale mappings
972 * which have not yet been cleared by a cache write-back
973 * and so would still be visible to the mmu.
976 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
978 uma_zfree(l2zone, l2);
981 * One or more mappings in the specified L2 descriptor table have just been
984 * Garbage collect the metadata and descriptor table itself if necessary.
986 * The pmap lock must be acquired when this is called (not necessary
987 * for the kernel pmap).
990 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count)
992 struct l2_dtable *l2;
993 pd_entry_t *pl1pd, l1pd;
999 * Update the bucket's reference count according to how many
1000 * PTEs the caller has just invalidated.
1002 l2b->l2b_occupancy -= count;
1007 * Level 2 page tables allocated to the kernel pmap are never freed
1008 * as that would require checking all Level 1 page tables and
1009 * removing any references to the Level 2 page table. See also the
1010 * comment elsewhere about never freeing bootstrap L2 descriptors.
1012 * We make do with just invalidating the mapping in the L2 table.
1014 * This isn't really a big deal in practice and, in fact, leads
1015 * to a performance win over time as we don't need to continually
1018 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel())
1022 * There are no more valid mappings in this level 2 page table.
1023 * Go ahead and NULL-out the pointer in the bucket, then
1024 * free the page table.
1026 l1idx = l2b->l2b_l1idx;
1027 ptep = l2b->l2b_kva;
1028 l2b->l2b_kva = NULL;
1030 pl1pd = &pm->pm_l1->l1_kva[l1idx];
1033 * If the L1 slot matches the pmap's domain
1034 * number, then invalidate it.
1036 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK);
1037 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) {
1043 * Release the L2 descriptor table back to the pool cache.
1045 #ifndef PMAP_INCLUDE_PTE_SYNC
1046 pmap_free_l2_ptp(ptep);
1048 pmap_free_l2_ptp(!pmap_is_current(pm), ptep);
1052 * Update the reference count in the associated l2_dtable
1054 l2 = pm->pm_l2[L2_IDX(l1idx)];
1055 if (--l2->l2_occupancy > 0)
1059 * There are no more valid mappings in any of the Level 1
1060 * slots managed by this l2_dtable. Go ahead and NULL-out
1061 * the pointer in the parent pmap and free the l2_dtable.
1063 pm->pm_l2[L2_IDX(l1idx)] = NULL;
1064 pmap_free_l2_dtable(l2);
1068 * Pool cache constructors for L2 descriptor tables, metadata and pmap
1072 pmap_l2ptp_ctor(void *mem, int size, void *arg, int flags)
1074 #ifndef PMAP_INCLUDE_PTE_SYNC
1075 struct l2_bucket *l2b;
1076 pt_entry_t *ptep, pte;
1077 #ifdef ARM_USE_SMALL_ALLOC
1080 vm_offset_t va = (vm_offset_t)mem & ~PAGE_MASK;
1083 * The mappings for these page tables were initially made using
1084 * pmap_kenter() by the pool subsystem. Therefore, the cache-
1085 * mode will not be right for page table mappings. To avoid
1086 * polluting the pmap_kenter() code with a special case for
1087 * page tables, we simply fix up the cache-mode here if it's not
1090 #ifdef ARM_USE_SMALL_ALLOC
1091 pde = &kernel_pmap->pm_l1->l1_kva[L1_IDX(va)];
1092 if (!l1pte_section_p(*pde)) {
1094 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
1095 ptep = &l2b->l2b_kva[l2pte_index(va)];
1098 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
1100 * Page tables must have the cache-mode set to
1103 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
1105 cpu_tlb_flushD_SE(va);
1108 #ifdef ARM_USE_SMALL_ALLOC
1112 memset(mem, 0, L2_TABLE_SIZE_REAL);
1113 PTE_SYNC_RANGE(mem, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
1118 * A bunch of routines to conditionally flush the caches/TLB depending
1119 * on whether the specified pmap actually needs to be flushed at any
1122 static PMAP_INLINE void
1123 pmap_tlb_flushID_SE(pmap_t pm, vm_offset_t va)
1126 if (pmap_is_current(pm))
1127 cpu_tlb_flushID_SE(va);
1130 static PMAP_INLINE void
1131 pmap_tlb_flushD_SE(pmap_t pm, vm_offset_t va)
1134 if (pmap_is_current(pm))
1135 cpu_tlb_flushD_SE(va);
1138 static PMAP_INLINE void
1139 pmap_tlb_flushID(pmap_t pm)
1142 if (pmap_is_current(pm))
1145 static PMAP_INLINE void
1146 pmap_tlb_flushD(pmap_t pm)
1149 if (pmap_is_current(pm))
1154 pmap_has_valid_mapping(pmap_t pm, vm_offset_t va)
1159 if (pmap_get_pde_pte(pm, va, &pde, &ptep) &&
1160 ptep && ((*ptep & L2_TYPE_MASK) != L2_TYPE_INV))
1166 static PMAP_INLINE void
1167 pmap_idcache_wbinv_range(pmap_t pm, vm_offset_t va, vm_size_t len)
1171 CTR4(KTR_PMAP, "pmap_dcache_wbinv_range: pmap %p is_kernel %d va 0x%08x"
1172 " len 0x%x ", pm, pm == pmap_kernel(), va, len);
1174 if (pmap_is_current(pm) || pm == pmap_kernel()) {
1175 rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len);
1177 if (pmap_has_valid_mapping(pm, va)) {
1178 cpu_idcache_wbinv_range(va, rest);
1179 cpu_l2cache_wbinv_range(va, rest);
1183 rest = MIN(PAGE_SIZE, len);
1188 static PMAP_INLINE void
1189 pmap_dcache_wb_range(pmap_t pm, vm_offset_t va, vm_size_t len, boolean_t do_inv,
1194 CTR4(KTR_PMAP, "pmap_dcache_wb_range: pmap %p is_kernel %d va 0x%08x "
1195 "len 0x%x ", pm, pm == pmap_kernel(), va, len);
1196 CTR2(KTR_PMAP, " do_inv %d rd_only %d", do_inv, rd_only);
1198 if (pmap_is_current(pm)) {
1199 rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len);
1201 if (pmap_has_valid_mapping(pm, va)) {
1202 if (do_inv && rd_only) {
1203 cpu_dcache_inv_range(va, rest);
1204 cpu_l2cache_inv_range(va, rest);
1205 } else if (do_inv) {
1206 cpu_dcache_wbinv_range(va, rest);
1207 cpu_l2cache_wbinv_range(va, rest);
1208 } else if (!rd_only) {
1209 cpu_dcache_wb_range(va, rest);
1210 cpu_l2cache_wb_range(va, rest);
1216 rest = MIN(PAGE_SIZE, len);
1221 static PMAP_INLINE void
1222 pmap_idcache_wbinv_all(pmap_t pm)
1225 if (pmap_is_current(pm)) {
1226 cpu_idcache_wbinv_all();
1227 cpu_l2cache_wbinv_all();
1232 static PMAP_INLINE void
1233 pmap_dcache_wbinv_all(pmap_t pm)
1236 if (pmap_is_current(pm)) {
1237 cpu_dcache_wbinv_all();
1238 cpu_l2cache_wbinv_all();
1246 * Make sure the pte is written out to RAM.
1247 * We need to do this for one of two cases:
1248 * - We're dealing with the kernel pmap
1249 * - There is no pmap active in the cache/tlb.
1250 * - The specified pmap is 'active' in the cache/tlb.
1252 #ifdef PMAP_INCLUDE_PTE_SYNC
1253 #define PTE_SYNC_CURRENT(pm, ptep) \
1255 if (PMAP_NEEDS_PTE_SYNC && \
1256 pmap_is_current(pm)) \
1258 } while (/*CONSTCOND*/0)
1260 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */
1264 * cacheable == -1 means we must make the entry uncacheable, 1 means
1267 static __inline void
1268 pmap_set_cache_entry(pv_entry_t pv, pmap_t pm, vm_offset_t va, int cacheable)
1270 struct l2_bucket *l2b;
1271 pt_entry_t *ptep, pte;
1273 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
1274 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
1276 if (cacheable == 1) {
1277 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode;
1278 if (l2pte_valid(pte)) {
1279 if (PV_BEEN_EXECD(pv->pv_flags)) {
1280 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va);
1281 } else if (PV_BEEN_REFD(pv->pv_flags)) {
1282 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va);
1286 pte = *ptep &~ L2_S_CACHE_MASK;
1287 if ((va != pv->pv_va || pm != pv->pv_pmap) &&
1289 if (PV_BEEN_EXECD(pv->pv_flags)) {
1290 pmap_idcache_wbinv_range(pv->pv_pmap,
1291 pv->pv_va, PAGE_SIZE);
1292 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va);
1293 } else if (PV_BEEN_REFD(pv->pv_flags)) {
1294 pmap_dcache_wb_range(pv->pv_pmap,
1295 pv->pv_va, PAGE_SIZE, TRUE,
1296 (pv->pv_flags & PVF_WRITE) == 0);
1297 pmap_tlb_flushD_SE(pv->pv_pmap,
1303 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
1307 pmap_fix_cache(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1310 int writable = 0, kwritable = 0, uwritable = 0;
1311 int entries = 0, kentries = 0, uentries = 0;
1312 struct pv_entry *pv;
1314 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1316 /* the cache gets written back/invalidated on context switch.
1317 * therefore, if a user page shares an entry in the same page or
1318 * with the kernel map and at least one is writable, then the
1319 * cache entry must be set write-through.
1322 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1323 /* generate a count of the pv_entry uses */
1324 if (pv->pv_flags & PVF_WRITE) {
1325 if (pv->pv_pmap == pmap_kernel())
1327 else if (pv->pv_pmap == pm)
1331 if (pv->pv_pmap == pmap_kernel())
1334 if (pv->pv_pmap == pm)
1340 * check if the user duplicate mapping has
1343 if ((pm != pmap_kernel()) && (((uentries > 1) && uwritable) ||
1347 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1348 /* check for user uncachable conditions - order is important */
1349 if (pm != pmap_kernel() &&
1350 (pv->pv_pmap == pm || pv->pv_pmap == pmap_kernel())) {
1352 if ((uentries > 1 && uwritable) || uwritable > 1) {
1354 /* user duplicate mapping */
1355 if (pv->pv_pmap != pmap_kernel())
1356 pv->pv_flags |= PVF_MWC;
1358 if (!(pv->pv_flags & PVF_NC)) {
1359 pv->pv_flags |= PVF_NC;
1360 pmap_set_cache_entry(pv, pm, va, -1);
1363 } else /* no longer a duplicate user */
1364 pv->pv_flags &= ~PVF_MWC;
1368 * check for kernel uncachable conditions
1369 * kernel writable or kernel readable with writable user entry
1371 if ((kwritable && (entries || kentries > 1)) ||
1373 ((kwritable != writable) && kentries &&
1374 (pv->pv_pmap == pmap_kernel() ||
1375 (pv->pv_flags & PVF_WRITE) ||
1376 (pv->pv_flags & PVF_MWC)))) {
1378 if (!(pv->pv_flags & PVF_NC)) {
1379 pv->pv_flags |= PVF_NC;
1380 pmap_set_cache_entry(pv, pm, va, -1);
1385 /* kernel and user are cachable */
1386 if ((pm == pmap_kernel()) && !(pv->pv_flags & PVF_MWC) &&
1387 (pv->pv_flags & PVF_NC)) {
1389 pv->pv_flags &= ~PVF_NC;
1390 pmap_set_cache_entry(pv, pm, va, 1);
1393 /* user is no longer sharable and writable */
1394 if (pm != pmap_kernel() &&
1395 (pv->pv_pmap == pm || pv->pv_pmap == pmap_kernel()) &&
1396 !pmwc && (pv->pv_flags & PVF_NC)) {
1398 pv->pv_flags &= ~(PVF_NC | PVF_MWC);
1399 pmap_set_cache_entry(pv, pm, va, 1);
1403 if ((kwritable == 0) && (writable == 0)) {
1404 pg->md.pvh_attrs &= ~PVF_MOD;
1405 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1411 * Modify pte bits for all ptes corresponding to the given physical address.
1412 * We use `maskbits' rather than `clearbits' because we're always passing
1413 * constants and the latter would require an extra inversion at run-time.
1416 pmap_clearbit(struct vm_page *pg, u_int maskbits)
1418 struct l2_bucket *l2b;
1419 struct pv_entry *pv;
1420 pt_entry_t *ptep, npte, opte;
1426 vm_page_lock_queues();
1428 if (maskbits & PVF_WRITE)
1429 maskbits |= PVF_MOD;
1431 * Clear saved attributes (modify, reference)
1433 pg->md.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF));
1435 if (TAILQ_EMPTY(&pg->md.pv_list)) {
1436 vm_page_unlock_queues();
1441 * Loop over all current mappings setting/clearing as appropos
1443 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1446 oflags = pv->pv_flags;
1448 if (!(oflags & maskbits)) {
1449 if ((maskbits & PVF_WRITE) && (pv->pv_flags & PVF_NC)) {
1450 /* It is safe to re-enable cacheing here. */
1452 l2b = pmap_get_l2_bucket(pm, va);
1453 ptep = &l2b->l2b_kva[l2pte_index(va)];
1454 *ptep |= pte_l2_s_cache_mode;
1457 pv->pv_flags &= ~(PVF_NC | PVF_MWC);
1462 pv->pv_flags &= ~maskbits;
1466 l2b = pmap_get_l2_bucket(pm, va);
1468 ptep = &l2b->l2b_kva[l2pte_index(va)];
1469 npte = opte = *ptep;
1471 if (maskbits & (PVF_WRITE|PVF_MOD)) {
1472 if ((pv->pv_flags & PVF_NC)) {
1474 * Entry is not cacheable:
1476 * Don't turn caching on again if this is a
1477 * modified emulation. This would be
1478 * inconsitent with the settings created by
1479 * pmap_fix_cache(). Otherwise, it's safe
1480 * to re-enable cacheing.
1482 * There's no need to call pmap_fix_cache()
1483 * here: all pages are losing their write
1486 if (maskbits & PVF_WRITE) {
1487 npte |= pte_l2_s_cache_mode;
1488 pv->pv_flags &= ~(PVF_NC | PVF_MWC);
1491 if (opte & L2_S_PROT_W) {
1494 * Entry is writable/cacheable: check if pmap
1495 * is current if it is flush it, otherwise it
1496 * won't be in the cache
1498 if (PV_BEEN_EXECD(oflags))
1499 pmap_idcache_wbinv_range(pm, pv->pv_va,
1502 if (PV_BEEN_REFD(oflags))
1503 pmap_dcache_wb_range(pm, pv->pv_va,
1505 (maskbits & PVF_REF) ? TRUE : FALSE,
1509 /* make the pte read only */
1510 npte &= ~L2_S_PROT_W;
1513 if (maskbits & PVF_REF) {
1514 if ((pv->pv_flags & PVF_NC) == 0 &&
1515 (maskbits & (PVF_WRITE|PVF_MOD)) == 0) {
1517 * Check npte here; we may have already
1518 * done the wbinv above, and the validity
1519 * of the PTE is the same for opte and
1522 if (npte & L2_S_PROT_W) {
1523 if (PV_BEEN_EXECD(oflags))
1524 pmap_idcache_wbinv_range(pm,
1525 pv->pv_va, PAGE_SIZE);
1527 if (PV_BEEN_REFD(oflags))
1528 pmap_dcache_wb_range(pm,
1529 pv->pv_va, PAGE_SIZE,
1532 if ((npte & L2_TYPE_MASK) != L2_TYPE_INV) {
1533 /* XXXJRT need idcache_inv_range */
1534 if (PV_BEEN_EXECD(oflags))
1535 pmap_idcache_wbinv_range(pm,
1536 pv->pv_va, PAGE_SIZE);
1538 if (PV_BEEN_REFD(oflags))
1539 pmap_dcache_wb_range(pm,
1540 pv->pv_va, PAGE_SIZE,
1546 * Make the PTE invalid so that we will take a
1547 * page fault the next time the mapping is
1550 npte &= ~L2_TYPE_MASK;
1551 npte |= L2_TYPE_INV;
1558 /* Flush the TLB entry if a current pmap. */
1559 if (PV_BEEN_EXECD(oflags))
1560 pmap_tlb_flushID_SE(pm, pv->pv_va);
1562 if (PV_BEEN_REFD(oflags))
1563 pmap_tlb_flushD_SE(pm, pv->pv_va);
1570 if (maskbits & PVF_WRITE)
1571 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1572 vm_page_unlock_queues();
1577 * main pv_entry manipulation functions:
1578 * pmap_enter_pv: enter a mapping onto a vm_page list
1579 * pmap_remove_pv: remove a mappiing from a vm_page list
1581 * NOTE: pmap_enter_pv expects to lock the pvh itself
1582 * pmap_remove_pv expects te caller to lock the pvh before calling
1586 * pmap_enter_pv: enter a mapping onto a vm_page lst
1588 * => caller should hold the proper lock on pmap_main_lock
1589 * => caller should have pmap locked
1590 * => we will gain the lock on the vm_page and allocate the new pv_entry
1591 * => caller should adjust ptp's wire_count before calling
1592 * => caller should not adjust pmap's wire_count
1595 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm,
1596 vm_offset_t va, u_int flags)
1601 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1603 if (pg->md.pv_kva) {
1604 /* PMAP_ASSERT_LOCKED(pmap_kernel()); */
1605 pve->pv_pmap = pmap_kernel();
1606 pve->pv_va = pg->md.pv_kva;
1607 pve->pv_flags = PVF_WRITE | PVF_UNMAN;
1610 if (!(km = PMAP_OWNED(pmap_kernel())))
1611 PMAP_LOCK(pmap_kernel());
1612 TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list);
1613 TAILQ_INSERT_HEAD(&pve->pv_pmap->pm_pvlist, pve, pv_plist);
1614 PMAP_UNLOCK(pmap_kernel());
1615 vm_page_unlock_queues();
1616 if ((pve = pmap_get_pv_entry()) == NULL)
1617 panic("pmap_kenter_internal: no pv entries");
1618 vm_page_lock_queues();
1620 PMAP_LOCK(pmap_kernel());
1623 PMAP_ASSERT_LOCKED(pm);
1626 pve->pv_flags = flags;
1628 TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list);
1629 TAILQ_INSERT_HEAD(&pm->pm_pvlist, pve, pv_plist);
1630 pg->md.pvh_attrs |= flags & (PVF_REF | PVF_MOD);
1631 if (pve->pv_flags & PVF_WIRED)
1632 ++pm->pm_stats.wired_count;
1633 vm_page_aflag_set(pg, PGA_REFERENCED);
1638 * pmap_find_pv: Find a pv entry
1640 * => caller should hold lock on vm_page
1642 static PMAP_INLINE struct pv_entry *
1643 pmap_find_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1645 struct pv_entry *pv;
1647 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1648 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list)
1649 if (pm == pv->pv_pmap && va == pv->pv_va)
1655 * vector_page_setprot:
1657 * Manipulate the protection of the vector page.
1660 vector_page_setprot(int prot)
1662 struct l2_bucket *l2b;
1665 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page);
1667 ptep = &l2b->l2b_kva[l2pte_index(vector_page)];
1669 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot);
1671 cpu_tlb_flushD_SE(vector_page);
1676 * pmap_remove_pv: try to remove a mapping from a pv_list
1678 * => caller should hold proper lock on pmap_main_lock
1679 * => pmap should be locked
1680 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1681 * => caller should adjust ptp's wire_count and free PTP if needed
1682 * => caller should NOT adjust pmap's wire_count
1683 * => we return the removed pve
1687 pmap_nuke_pv(struct vm_page *pg, pmap_t pm, struct pv_entry *pve)
1690 struct pv_entry *pv;
1691 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1692 PMAP_ASSERT_LOCKED(pm);
1693 TAILQ_REMOVE(&pg->md.pv_list, pve, pv_list);
1694 TAILQ_REMOVE(&pm->pm_pvlist, pve, pv_plist);
1695 if (pve->pv_flags & PVF_WIRED)
1696 --pm->pm_stats.wired_count;
1697 if (pg->md.pvh_attrs & PVF_MOD)
1699 if (TAILQ_FIRST(&pg->md.pv_list) == NULL)
1700 pg->md.pvh_attrs &= ~PVF_REF;
1702 vm_page_aflag_set(pg, PGA_REFERENCED);
1703 if ((pve->pv_flags & PVF_NC) && ((pm == pmap_kernel()) ||
1704 (pve->pv_flags & PVF_WRITE) || !(pve->pv_flags & PVF_MWC)))
1705 pmap_fix_cache(pg, pm, 0);
1706 else if (pve->pv_flags & PVF_WRITE) {
1707 TAILQ_FOREACH(pve, &pg->md.pv_list, pv_list)
1708 if (pve->pv_flags & PVF_WRITE)
1711 pg->md.pvh_attrs &= ~PVF_MOD;
1712 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1715 pv = TAILQ_FIRST(&pg->md.pv_list);
1716 if (pv != NULL && (pv->pv_flags & PVF_UNMAN) &&
1717 TAILQ_NEXT(pv, pv_list) == NULL) {
1719 pg->md.pv_kva = pv->pv_va;
1720 /* a recursive pmap_nuke_pv */
1721 TAILQ_REMOVE(&pg->md.pv_list, pv, pv_list);
1722 TAILQ_REMOVE(&pm->pm_pvlist, pv, pv_plist);
1723 if (pv->pv_flags & PVF_WIRED)
1724 --pm->pm_stats.wired_count;
1725 pg->md.pvh_attrs &= ~PVF_REF;
1726 pg->md.pvh_attrs &= ~PVF_MOD;
1727 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1728 pmap_free_pv_entry(pv);
1732 static struct pv_entry *
1733 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1735 struct pv_entry *pve;
1737 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1738 pve = TAILQ_FIRST(&pg->md.pv_list);
1741 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */
1742 pmap_nuke_pv(pg, pm, pve);
1745 pve = TAILQ_NEXT(pve, pv_list);
1748 if (pve == NULL && pg->md.pv_kva == va)
1751 return(pve); /* return removed pve */
1755 * pmap_modify_pv: Update pv flags
1757 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1758 * => caller should NOT adjust pmap's wire_count
1759 * => we return the old flags
1761 * Modify a physical-virtual mapping in the pv table
1764 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va,
1765 u_int clr_mask, u_int set_mask)
1767 struct pv_entry *npv;
1768 u_int flags, oflags;
1770 PMAP_ASSERT_LOCKED(pm);
1771 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1772 if ((npv = pmap_find_pv(pg, pm, va)) == NULL)
1776 * There is at least one VA mapping this page.
1779 if (clr_mask & (PVF_REF | PVF_MOD))
1780 pg->md.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD);
1782 oflags = npv->pv_flags;
1783 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask;
1785 if ((flags ^ oflags) & PVF_WIRED) {
1786 if (flags & PVF_WIRED)
1787 ++pm->pm_stats.wired_count;
1789 --pm->pm_stats.wired_count;
1792 if ((flags ^ oflags) & PVF_WRITE)
1793 pmap_fix_cache(pg, pm, 0);
1798 /* Function to set the debug level of the pmap code */
1801 pmap_debug(int level)
1803 pmap_debug_level = level;
1804 dprintf("pmap_debug: level=%d\n", pmap_debug_level);
1806 #endif /* PMAP_DEBUG */
1809 pmap_pinit0(struct pmap *pmap)
1811 PDEBUG(1, printf("pmap_pinit0: pmap = %08x\n", (u_int32_t) pmap));
1813 dprintf("pmap_pinit0: pmap = %08x, pm_pdir = %08x\n",
1814 (u_int32_t) pmap, (u_int32_t) pmap->pm_pdir);
1815 bcopy(kernel_pmap, pmap, sizeof(*pmap));
1816 bzero(&pmap->pm_mtx, sizeof(pmap->pm_mtx));
1817 PMAP_LOCK_INIT(pmap);
1821 * Initialize a vm_page's machine-dependent fields.
1824 pmap_page_init(vm_page_t m)
1827 TAILQ_INIT(&m->md.pv_list);
1831 * Initialize the pmap module.
1832 * Called by vm_init, to initialize any structures that the pmap
1833 * system needs to map virtual memory.
1838 int shpgperproc = PMAP_SHPGPERPROC;
1840 PDEBUG(1, printf("pmap_init: phys_start = %08x\n", PHYSADDR));
1843 * init the pv free list
1845 pvzone = uma_zcreate("PV ENTRY", sizeof (struct pv_entry), NULL, NULL,
1846 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1848 * Now it is safe to enable pv_table recording.
1850 PDEBUG(1, printf("pmap_init: done!\n"));
1852 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1854 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
1855 pv_entry_high_water = 9 * (pv_entry_max / 10);
1856 l2zone = uma_zcreate("L2 Table", L2_TABLE_SIZE_REAL, pmap_l2ptp_ctor,
1857 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1858 l2table_zone = uma_zcreate("L2 Table", sizeof(struct l2_dtable),
1859 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1860 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1862 uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max);
1867 pmap_fault_fixup(pmap_t pm, vm_offset_t va, vm_prot_t ftype, int user)
1869 struct l2_dtable *l2;
1870 struct l2_bucket *l2b;
1871 pd_entry_t *pl1pd, l1pd;
1872 pt_entry_t *ptep, pte;
1878 vm_page_lock_queues();
1882 * If there is no l2_dtable for this address, then the process
1883 * has no business accessing it.
1885 * Note: This will catch userland processes trying to access
1888 l2 = pm->pm_l2[L2_IDX(l1idx)];
1893 * Likewise if there is no L2 descriptor table
1895 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
1896 if (l2b->l2b_kva == NULL)
1900 * Check the PTE itself.
1902 ptep = &l2b->l2b_kva[l2pte_index(va)];
1908 * Catch a userland access to the vector page mapped at 0x0
1910 if (user && (pte & L2_S_PROT_U) == 0)
1912 if (va == vector_page)
1917 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) {
1919 * This looks like a good candidate for "page modified"
1922 struct pv_entry *pv;
1925 /* Extract the physical address of the page */
1926 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) {
1929 /* Get the current flags for this page. */
1931 pv = pmap_find_pv(pg, pm, va);
1937 * Do the flags say this page is writable? If not then it
1938 * is a genuine write fault. If yes then the write fault is
1939 * our fault as we did not reflect the write access in the
1940 * PTE. Now we know a write has occurred we can correct this
1941 * and also set the modified bit
1943 if ((pv->pv_flags & PVF_WRITE) == 0) {
1947 pg->md.pvh_attrs |= PVF_REF | PVF_MOD;
1949 pv->pv_flags |= PVF_REF | PVF_MOD;
1952 * Re-enable write permissions for the page. No need to call
1953 * pmap_fix_cache(), since this is just a
1954 * modified-emulation fault, and the PVF_WRITE bit isn't
1955 * changing. We've already set the cacheable bits based on
1956 * the assumption that we can write to this page.
1958 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W;
1962 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) {
1964 * This looks like a good candidate for "page referenced"
1967 struct pv_entry *pv;
1970 /* Extract the physical address of the page */
1971 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL)
1973 /* Get the current flags for this page. */
1975 pv = pmap_find_pv(pg, pm, va);
1979 pg->md.pvh_attrs |= PVF_REF;
1980 pv->pv_flags |= PVF_REF;
1983 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO;
1989 * We know there is a valid mapping here, so simply
1990 * fix up the L1 if necessary.
1992 pl1pd = &pm->pm_l1->l1_kva[l1idx];
1993 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO;
1994 if (*pl1pd != l1pd) {
2002 * There are bugs in the rev K SA110. This is a check for one
2005 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 &&
2006 curcpu()->ci_arm_cpurev < 3) {
2007 /* Always current pmap */
2008 if (l2pte_valid(pte)) {
2009 extern int kernel_debug;
2010 if (kernel_debug & 1) {
2011 struct proc *p = curlwp->l_proc;
2012 printf("prefetch_abort: page is already "
2013 "mapped - pte=%p *pte=%08x\n", ptep, pte);
2014 printf("prefetch_abort: pc=%08lx proc=%p "
2015 "process=%s\n", va, p, p->p_comm);
2016 printf("prefetch_abort: far=%08x fs=%x\n",
2017 cpu_faultaddress(), cpu_faultstatus());
2020 if (kernel_debug & 2)
2026 #endif /* CPU_SA110 */
2030 * If 'rv == 0' at this point, it generally indicates that there is a
2031 * stale TLB entry for the faulting address. This happens when two or
2032 * more processes are sharing an L1. Since we don't flush the TLB on
2033 * a context switch between such processes, we can take domain faults
2034 * for mappings which exist at the same VA in both processes. EVEN IF
2035 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for
2038 * This is extremely likely to happen if pmap_enter() updated the L1
2039 * entry for a recently entered mapping. In this case, the TLB is
2040 * flushed for the new mapping, but there may still be TLB entries for
2041 * other mappings belonging to other processes in the 1MB range
2042 * covered by the L1 entry.
2044 * Since 'rv == 0', we know that the L1 already contains the correct
2045 * value, so the fault must be due to a stale TLB entry.
2047 * Since we always need to flush the TLB anyway in the case where we
2048 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with
2049 * stale TLB entries dynamically.
2051 * However, the above condition can ONLY happen if the current L1 is
2052 * being shared. If it happens when the L1 is unshared, it indicates
2053 * that other parts of the pmap are not doing their job WRT managing
2056 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) {
2057 extern int last_fault_code;
2058 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n",
2060 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n",
2061 l2, l2b, ptep, pl1pd);
2062 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n",
2063 pte, l1pd, last_fault_code);
2070 cpu_tlb_flushID_SE(va);
2076 vm_page_unlock_queues();
2084 struct l2_bucket *l2b;
2085 struct l1_ttable *l1;
2087 pt_entry_t *ptep, pte;
2088 vm_offset_t va, eva;
2091 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0);
2093 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK);
2095 for (loop = 0; loop < needed; loop++, l1++) {
2096 /* Allocate a L1 page table */
2097 va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_VMPMAP, 0, 0x0,
2098 0xffffffff, L1_TABLE_SIZE, 0);
2101 panic("Cannot allocate L1 KVM");
2103 eva = va + L1_TABLE_SIZE;
2104 pl1pt = (pd_entry_t *)va;
2107 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2108 ptep = &l2b->l2b_kva[l2pte_index(va)];
2110 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
2113 cpu_tlb_flushD_SE(va);
2117 pmap_init_l1(l1, pl1pt);
2122 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n",
2128 * This is used to stuff certain critical values into the PCB where they
2129 * can be accessed quickly from cpu_switch() et al.
2132 pmap_set_pcb_pagedir(pmap_t pm, struct pcb *pcb)
2134 struct l2_bucket *l2b;
2136 pcb->pcb_pagedir = pm->pm_l1->l1_physaddr;
2137 pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) |
2138 (DOMAIN_CLIENT << (pm->pm_domain * 2));
2140 if (vector_page < KERNBASE) {
2141 pcb->pcb_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)];
2142 l2b = pmap_get_l2_bucket(pm, vector_page);
2143 pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO |
2144 L1_C_DOM(pm->pm_domain) | L1_C_DOM(PMAP_DOMAIN_KERNEL);
2146 pcb->pcb_pl1vec = NULL;
2150 pmap_activate(struct thread *td)
2155 pm = vmspace_pmap(td->td_proc->p_vmspace);
2159 pmap_set_pcb_pagedir(pm, pcb);
2161 if (td == curthread) {
2162 u_int cur_dacr, cur_ttb;
2164 __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb));
2165 __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr));
2167 cur_ttb &= ~(L1_TABLE_SIZE - 1);
2169 if (cur_ttb == (u_int)pcb->pcb_pagedir &&
2170 cur_dacr == pcb->pcb_dacr) {
2172 * No need to switch address spaces.
2180 * We MUST, I repeat, MUST fix up the L1 entry corresponding
2181 * to 'vector_page' in the incoming L1 table before switching
2182 * to it otherwise subsequent interrupts/exceptions (including
2183 * domain faults!) will jump into hyperspace.
2185 if (pcb->pcb_pl1vec) {
2187 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
2189 * Don't need to PTE_SYNC() at this point since
2190 * cpu_setttb() is about to flush both the cache
2195 cpu_domains(pcb->pcb_dacr);
2196 cpu_setttb(pcb->pcb_pagedir);
2202 pmap_set_pt_cache_mode(pd_entry_t *kl1, vm_offset_t va)
2204 pd_entry_t *pdep, pde;
2205 pt_entry_t *ptep, pte;
2210 * Make sure the descriptor itself has the correct cache mode
2212 pdep = &kl1[L1_IDX(va)];
2215 if (l1pte_section_p(pde)) {
2216 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) {
2217 *pdep = (pde & ~L1_S_CACHE_MASK) |
2218 pte_l1_s_cache_mode_pt;
2220 cpu_dcache_wbinv_range((vm_offset_t)pdep,
2222 cpu_l2cache_wbinv_range((vm_offset_t)pdep,
2227 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
2228 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
2230 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep);
2232 ptep = &ptep[l2pte_index(va)];
2234 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
2235 *ptep = (pte & ~L2_S_CACHE_MASK) |
2236 pte_l2_s_cache_mode_pt;
2238 cpu_dcache_wbinv_range((vm_offset_t)ptep,
2240 cpu_l2cache_wbinv_range((vm_offset_t)ptep,
2250 pmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap,
2253 vm_offset_t va = *availp;
2254 struct l2_bucket *l2b;
2257 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2259 panic("pmap_alloc_specials: no l2b for 0x%x", va);
2261 *ptep = &l2b->l2b_kva[l2pte_index(va)];
2265 *availp = va + (PAGE_SIZE * pages);
2269 * Bootstrap the system enough to run with virtual memory.
2271 * On the arm this is called after mapping has already been enabled
2272 * and just syncs the pmap module with what has already been done.
2273 * [We can't call it easily with mapping off since the kernel is not
2274 * mapped with PA == VA, hence we would have to relocate every address
2275 * from the linked base (virtual) address "KERNBASE" to the actual
2276 * (physical) address starting relative to 0]
2278 #define PMAP_STATIC_L2_SIZE 16
2279 #ifdef ARM_USE_SMALL_ALLOC
2280 extern struct mtx smallalloc_mtx;
2284 pmap_bootstrap(vm_offset_t firstaddr, vm_offset_t lastaddr, struct pv_addr *l1pt)
2286 static struct l1_ttable static_l1;
2287 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE];
2288 struct l1_ttable *l1 = &static_l1;
2289 struct l2_dtable *l2;
2290 struct l2_bucket *l2b;
2292 pd_entry_t *kernel_l1pt = (pd_entry_t *)l1pt->pv_va;
2297 int l1idx, l2idx, l2next = 0;
2299 PDEBUG(1, printf("firstaddr = %08x, lastaddr = %08x\n",
2300 firstaddr, lastaddr));
2302 virtual_avail = firstaddr;
2303 kernel_pmap->pm_l1 = l1;
2304 kernel_l1pa = l1pt->pv_pa;
2307 * Scan the L1 translation table created by initarm() and create
2308 * the required metadata for all valid mappings found in it.
2310 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) {
2311 pde = kernel_l1pt[l1idx];
2314 * We're only interested in Coarse mappings.
2315 * pmap_extract() can deal with section mappings without
2316 * recourse to checking L2 metadata.
2318 if ((pde & L1_TYPE_MASK) != L1_TYPE_C)
2322 * Lookup the KVA of this L2 descriptor table
2324 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
2325 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
2328 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx",
2329 (u_int)l1idx << L1_S_SHIFT, (long unsigned int)pa);
2333 * Fetch the associated L2 metadata structure.
2334 * Allocate a new one if necessary.
2336 if ((l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]) == NULL) {
2337 if (l2next == PMAP_STATIC_L2_SIZE)
2338 panic("pmap_bootstrap: out of static L2s");
2339 kernel_pmap->pm_l2[L2_IDX(l1idx)] = l2 =
2340 &static_l2[l2next++];
2344 * One more L1 slot tracked...
2349 * Fill in the details of the L2 descriptor in the
2350 * appropriate bucket.
2352 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2353 l2b->l2b_kva = ptep;
2355 l2b->l2b_l1idx = l1idx;
2358 * Establish an initial occupancy count for this descriptor
2361 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
2363 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) {
2364 l2b->l2b_occupancy++;
2369 * Make sure the descriptor itself has the correct cache mode.
2370 * If not, fix it, but whine about the problem. Port-meisters
2371 * should consider this a clue to fix up their initarm()
2374 if (pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)ptep)) {
2375 printf("pmap_bootstrap: WARNING! wrong cache mode for "
2376 "L2 pte @ %p\n", ptep);
2382 * Ensure the primary (kernel) L1 has the correct cache mode for
2383 * a page table. Bitch if it is not correctly set.
2385 for (va = (vm_offset_t)kernel_l1pt;
2386 va < ((vm_offset_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) {
2387 if (pmap_set_pt_cache_mode(kernel_l1pt, va))
2388 printf("pmap_bootstrap: WARNING! wrong cache mode for "
2389 "primary L1 @ 0x%x\n", va);
2392 cpu_dcache_wbinv_all();
2393 cpu_l2cache_wbinv_all();
2397 PMAP_LOCK_INIT(kernel_pmap);
2398 CPU_FILL(&kernel_pmap->pm_active);
2399 kernel_pmap->pm_domain = PMAP_DOMAIN_KERNEL;
2400 TAILQ_INIT(&kernel_pmap->pm_pvlist);
2403 * Reserve some special page table entries/VA space for temporary
2406 #define SYSMAP(c, p, v, n) \
2407 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
2409 pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte);
2410 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)csrc_pte);
2411 pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte);
2412 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)cdst_pte);
2413 size = ((lastaddr - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE;
2414 pmap_alloc_specials(&virtual_avail,
2415 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE,
2416 &pmap_kernel_l2ptp_kva, NULL);
2418 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE;
2419 pmap_alloc_specials(&virtual_avail,
2420 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE,
2421 &pmap_kernel_l2dtable_kva, NULL);
2423 pmap_alloc_specials(&virtual_avail,
2424 1, (vm_offset_t*)&_tmppt, NULL);
2425 pmap_alloc_specials(&virtual_avail,
2426 MAXDUMPPGS, (vm_offset_t *)&crashdumpmap, NULL);
2427 SLIST_INIT(&l1_list);
2428 TAILQ_INIT(&l1_lru_list);
2429 mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF);
2430 pmap_init_l1(l1, kernel_l1pt);
2431 cpu_dcache_wbinv_all();
2432 cpu_l2cache_wbinv_all();
2434 virtual_avail = round_page(virtual_avail);
2435 virtual_end = lastaddr;
2436 kernel_vm_end = pmap_curmaxkvaddr;
2437 arm_nocache_startaddr = lastaddr;
2438 mtx_init(&cmtx, "TMP mappings mtx", NULL, MTX_DEF);
2440 #ifdef ARM_USE_SMALL_ALLOC
2441 mtx_init(&smallalloc_mtx, "Small alloc page list", NULL, MTX_DEF);
2442 arm_init_smallalloc();
2444 pmap_set_pcb_pagedir(kernel_pmap, thread0.td_pcb);
2447 /***************************************************
2448 * Pmap allocation/deallocation routines.
2449 ***************************************************/
2452 * Release any resources held by the given physical map.
2453 * Called when a pmap initialized by pmap_pinit is being released.
2454 * Should only be called if the map contains no valid mappings.
2457 pmap_release(pmap_t pmap)
2461 pmap_idcache_wbinv_all(pmap);
2462 cpu_l2cache_wbinv_all();
2463 pmap_tlb_flushID(pmap);
2465 if (vector_page < KERNBASE) {
2466 struct pcb *curpcb = PCPU_GET(curpcb);
2467 pcb = thread0.td_pcb;
2468 if (pmap_is_current(pmap)) {
2470 * Frob the L1 entry corresponding to the vector
2471 * page so that it contains the kernel pmap's domain
2472 * number. This will ensure pmap_remove() does not
2473 * pull the current vector page out from under us.
2476 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
2477 cpu_domains(pcb->pcb_dacr);
2478 cpu_setttb(pcb->pcb_pagedir);
2481 pmap_remove(pmap, vector_page, vector_page + PAGE_SIZE);
2483 * Make sure cpu_switch(), et al, DTRT. This is safe to do
2484 * since this process has no remaining mappings of its own.
2486 curpcb->pcb_pl1vec = pcb->pcb_pl1vec;
2487 curpcb->pcb_l1vec = pcb->pcb_l1vec;
2488 curpcb->pcb_dacr = pcb->pcb_dacr;
2489 curpcb->pcb_pagedir = pcb->pcb_pagedir;
2493 PMAP_LOCK_DESTROY(pmap);
2495 dprintf("pmap_release()\n");
2501 * Helper function for pmap_grow_l2_bucket()
2504 pmap_grow_map(vm_offset_t va, pt_entry_t cache_mode, vm_paddr_t *pap)
2506 struct l2_bucket *l2b;
2511 pg = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
2514 pa = VM_PAGE_TO_PHYS(pg);
2519 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2521 ptep = &l2b->l2b_kva[l2pte_index(va)];
2522 *ptep = L2_S_PROTO | pa | cache_mode |
2523 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE);
2529 * This is the same as pmap_alloc_l2_bucket(), except that it is only
2530 * used by pmap_growkernel().
2532 static __inline struct l2_bucket *
2533 pmap_grow_l2_bucket(pmap_t pm, vm_offset_t va)
2535 struct l2_dtable *l2;
2536 struct l2_bucket *l2b;
2537 struct l1_ttable *l1;
2544 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
2546 * No mapping at this address, as there is
2547 * no entry in the L1 table.
2548 * Need to allocate a new l2_dtable.
2550 nva = pmap_kernel_l2dtable_kva;
2551 if ((nva & PAGE_MASK) == 0) {
2553 * Need to allocate a backing page
2555 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2559 l2 = (struct l2_dtable *)nva;
2560 nva += sizeof(struct l2_dtable);
2562 if ((nva & PAGE_MASK) < (pmap_kernel_l2dtable_kva &
2565 * The new l2_dtable straddles a page boundary.
2566 * Map in another page to cover it.
2568 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2572 pmap_kernel_l2dtable_kva = nva;
2575 * Link it into the parent pmap
2577 pm->pm_l2[L2_IDX(l1idx)] = l2;
2578 memset(l2, 0, sizeof(*l2));
2581 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2584 * Fetch pointer to the L2 page table associated with the address.
2586 if (l2b->l2b_kva == NULL) {
2590 * No L2 page table has been allocated. Chances are, this
2591 * is because we just allocated the l2_dtable, above.
2593 nva = pmap_kernel_l2ptp_kva;
2594 ptep = (pt_entry_t *)nva;
2595 if ((nva & PAGE_MASK) == 0) {
2597 * Need to allocate a backing page
2599 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt,
2600 &pmap_kernel_l2ptp_phys))
2602 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t));
2604 memset(ptep, 0, L2_TABLE_SIZE_REAL);
2606 l2b->l2b_kva = ptep;
2607 l2b->l2b_l1idx = l1idx;
2608 l2b->l2b_phys = pmap_kernel_l2ptp_phys;
2610 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL;
2611 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL;
2614 /* Distribute new L1 entry to all other L1s */
2615 SLIST_FOREACH(l1, &l1_list, l1_link) {
2616 pl1pd = &l1->l1_kva[L1_IDX(va)];
2617 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) |
2627 * grow the number of kernel page table entries, if needed
2630 pmap_growkernel(vm_offset_t addr)
2632 pmap_t kpm = pmap_kernel();
2634 if (addr <= pmap_curmaxkvaddr)
2635 return; /* we are OK */
2638 * whoops! we need to add kernel PTPs
2641 /* Map 1MB at a time */
2642 for (; pmap_curmaxkvaddr < addr; pmap_curmaxkvaddr += L1_S_SIZE)
2643 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr);
2646 * flush out the cache, expensive but growkernel will happen so
2649 cpu_dcache_wbinv_all();
2650 cpu_l2cache_wbinv_all();
2653 kernel_vm_end = pmap_curmaxkvaddr;
2658 * Remove all pages from specified address space
2659 * this aids process exit speeds. Also, this code
2660 * is special cased for current process only, but
2661 * can have the more generic (and slightly slower)
2662 * mode enabled. This is much faster than pmap_remove
2663 * in the case of running down an entire address space.
2666 pmap_remove_pages(pmap_t pmap)
2668 struct pv_entry *pv, *npv;
2669 struct l2_bucket *l2b = NULL;
2673 vm_page_lock_queues();
2675 cpu_idcache_wbinv_all();
2676 cpu_l2cache_wbinv_all();
2677 for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) {
2678 if (pv->pv_flags & PVF_WIRED || pv->pv_flags & PVF_UNMAN) {
2679 /* Cannot remove wired or unmanaged pages now. */
2680 npv = TAILQ_NEXT(pv, pv_plist);
2683 pmap->pm_stats.resident_count--;
2684 l2b = pmap_get_l2_bucket(pmap, pv->pv_va);
2685 KASSERT(l2b != NULL, ("No L2 bucket in pmap_remove_pages"));
2686 pt = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
2687 m = PHYS_TO_VM_PAGE(*pt & L2_ADDR_MASK);
2688 #ifdef ARM_USE_SMALL_ALLOC
2689 KASSERT((vm_offset_t)m >= alloc_firstaddr, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt));
2691 KASSERT((vm_offset_t)m >= KERNBASE, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt));
2695 npv = TAILQ_NEXT(pv, pv_plist);
2696 pmap_nuke_pv(m, pmap, pv);
2697 if (TAILQ_EMPTY(&m->md.pv_list))
2698 vm_page_aflag_clear(m, PGA_WRITEABLE);
2699 pmap_free_pv_entry(pv);
2700 pmap_free_l2_bucket(pmap, l2b, 1);
2702 vm_page_unlock_queues();
2709 /***************************************************
2710 * Low level mapping routines.....
2711 ***************************************************/
2713 #ifdef ARM_HAVE_SUPERSECTIONS
2714 /* Map a super section into the KVA. */
2717 pmap_kenter_supersection(vm_offset_t va, uint64_t pa, int flags)
2719 pd_entry_t pd = L1_S_PROTO | L1_S_SUPERSEC | (pa & L1_SUP_FRAME) |
2720 (((pa >> 32) & 0xf) << 20) | L1_S_PROT(PTE_KERNEL,
2721 VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL);
2722 struct l1_ttable *l1;
2723 vm_offset_t va0, va_end;
2725 KASSERT(((va | pa) & L1_SUP_OFFSET) == 0,
2726 ("Not a valid super section mapping"));
2727 if (flags & SECTION_CACHE)
2728 pd |= pte_l1_s_cache_mode;
2729 else if (flags & SECTION_PT)
2730 pd |= pte_l1_s_cache_mode_pt;
2731 va0 = va & L1_SUP_FRAME;
2732 va_end = va + L1_SUP_SIZE;
2733 SLIST_FOREACH(l1, &l1_list, l1_link) {
2735 for (; va < va_end; va += L1_S_SIZE) {
2736 l1->l1_kva[L1_IDX(va)] = pd;
2737 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
2743 /* Map a section into the KVA. */
2746 pmap_kenter_section(vm_offset_t va, vm_offset_t pa, int flags)
2748 pd_entry_t pd = L1_S_PROTO | pa | L1_S_PROT(PTE_KERNEL,
2749 VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL);
2750 struct l1_ttable *l1;
2752 KASSERT(((va | pa) & L1_S_OFFSET) == 0,
2753 ("Not a valid section mapping"));
2754 if (flags & SECTION_CACHE)
2755 pd |= pte_l1_s_cache_mode;
2756 else if (flags & SECTION_PT)
2757 pd |= pte_l1_s_cache_mode_pt;
2758 SLIST_FOREACH(l1, &l1_list, l1_link) {
2759 l1->l1_kva[L1_IDX(va)] = pd;
2760 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
2765 * Make a temporary mapping for a physical address. This is only intended
2766 * to be used for panic dumps.
2769 pmap_kenter_temp(vm_paddr_t pa, int i)
2773 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
2774 pmap_kenter(va, pa);
2775 return ((void *)crashdumpmap);
2779 * add a wired page to the kva
2780 * note that in order for the mapping to take effect -- you
2781 * should do a invltlb after doing the pmap_kenter...
2783 static PMAP_INLINE void
2784 pmap_kenter_internal(vm_offset_t va, vm_offset_t pa, int flags)
2786 struct l2_bucket *l2b;
2789 struct pv_entry *pve;
2792 PDEBUG(1, printf("pmap_kenter: va = %08x, pa = %08x\n",
2793 (uint32_t) va, (uint32_t) pa));
2796 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2798 l2b = pmap_grow_l2_bucket(pmap_kernel(), va);
2799 KASSERT(l2b != NULL, ("No L2 Bucket"));
2800 pte = &l2b->l2b_kva[l2pte_index(va)];
2802 PDEBUG(1, printf("pmap_kenter: pte = %08x, opte = %08x, npte = %08x\n",
2803 (uint32_t) pte, opte, *pte));
2804 if (l2pte_valid(opte)) {
2808 l2b->l2b_occupancy++;
2810 *pte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL,
2811 VM_PROT_READ | VM_PROT_WRITE);
2812 if (flags & KENTER_CACHE)
2813 *pte |= pte_l2_s_cache_mode;
2814 if (flags & KENTER_USER)
2815 *pte |= L2_S_PROT_U;
2818 /* kernel direct mappings can be shared, so use a pv_entry
2819 * to ensure proper caching.
2821 * The pvzone is used to delay the recording of kernel
2822 * mappings until the VM is running.
2824 * This expects the physical memory to have vm_page_array entry.
2826 if (pvzone != NULL && (m = vm_phys_paddr_to_vm_page(pa))) {
2827 vm_page_lock_queues();
2828 if (!TAILQ_EMPTY(&m->md.pv_list) || m->md.pv_kva) {
2829 /* release vm_page lock for pv_entry UMA */
2830 vm_page_unlock_queues();
2831 if ((pve = pmap_get_pv_entry()) == NULL)
2832 panic("pmap_kenter_internal: no pv entries");
2833 vm_page_lock_queues();
2834 PMAP_LOCK(pmap_kernel());
2835 pmap_enter_pv(m, pve, pmap_kernel(), va,
2836 PVF_WRITE | PVF_UNMAN);
2837 pmap_fix_cache(m, pmap_kernel(), va);
2838 PMAP_UNLOCK(pmap_kernel());
2842 vm_page_unlock_queues();
2847 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
2849 pmap_kenter_internal(va, pa, KENTER_CACHE);
2853 pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa)
2856 pmap_kenter_internal(va, pa, 0);
2860 pmap_kenter_user(vm_offset_t va, vm_paddr_t pa)
2863 pmap_kenter_internal(va, pa, KENTER_CACHE|KENTER_USER);
2865 * Call pmap_fault_fixup now, to make sure we'll have no exception
2866 * at the first use of the new address, or bad things will happen,
2867 * as we use one of these addresses in the exception handlers.
2869 pmap_fault_fixup(pmap_kernel(), va, VM_PROT_READ|VM_PROT_WRITE, 1);
2873 * remove a page from the kernel pagetables
2876 pmap_kremove(vm_offset_t va)
2878 struct l2_bucket *l2b;
2879 pt_entry_t *pte, opte;
2880 struct pv_entry *pve;
2884 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2887 KASSERT(l2b != NULL, ("No L2 Bucket"));
2888 pte = &l2b->l2b_kva[l2pte_index(va)];
2890 if (l2pte_valid(opte)) {
2891 /* pa = vtophs(va) taken from pmap_extract() */
2892 switch (opte & L2_TYPE_MASK) {
2894 pa = (opte & L2_L_FRAME) | (va & L2_L_OFFSET);
2897 pa = (opte & L2_S_FRAME) | (va & L2_S_OFFSET);
2900 /* note: should never have to remove an allocation
2901 * before the pvzone is initialized.
2903 vm_page_lock_queues();
2904 PMAP_LOCK(pmap_kernel());
2905 if (pvzone != NULL && (m = vm_phys_paddr_to_vm_page(pa)) &&
2906 (pve = pmap_remove_pv(m, pmap_kernel(), va)))
2907 pmap_free_pv_entry(pve);
2908 PMAP_UNLOCK(pmap_kernel());
2909 vm_page_unlock_queues();
2910 va = va & ~PAGE_MASK;
2911 cpu_dcache_wbinv_range(va, PAGE_SIZE);
2912 cpu_l2cache_wbinv_range(va, PAGE_SIZE);
2913 cpu_tlb_flushD_SE(va);
2921 * Used to map a range of physical addresses into kernel
2922 * virtual address space.
2924 * The value passed in '*virt' is a suggested virtual address for
2925 * the mapping. Architectures which can support a direct-mapped
2926 * physical to virtual region can return the appropriate address
2927 * within that region, leaving '*virt' unchanged. Other
2928 * architectures should map the pages starting at '*virt' and
2929 * update '*virt' with the first usable address after the mapped
2933 pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot)
2935 #ifdef ARM_USE_SMALL_ALLOC
2936 return (arm_ptovirt(start));
2938 vm_offset_t sva = *virt;
2939 vm_offset_t va = sva;
2941 PDEBUG(1, printf("pmap_map: virt = %08x, start = %08x, end = %08x, "
2942 "prot = %d\n", (uint32_t) *virt, (uint32_t) start, (uint32_t) end,
2945 while (start < end) {
2946 pmap_kenter(va, start);
2956 pmap_wb_page(vm_page_t m)
2958 struct pv_entry *pv;
2960 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
2961 pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, FALSE,
2962 (pv->pv_flags & PVF_WRITE) == 0);
2966 pmap_inv_page(vm_page_t m)
2968 struct pv_entry *pv;
2970 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
2971 pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, TRUE, TRUE);
2974 * Add a list of wired pages to the kva
2975 * this routine is only used for temporary
2976 * kernel mappings that do not need to have
2977 * page modification or references recorded.
2978 * Note that old mappings are simply written
2979 * over. The page *must* be wired.
2982 pmap_qenter(vm_offset_t va, vm_page_t *m, int count)
2986 for (i = 0; i < count; i++) {
2988 pmap_kenter_internal(va, VM_PAGE_TO_PHYS(m[i]),
2996 * this routine jerks page mappings from the
2997 * kernel -- it is meant only for temporary mappings.
3000 pmap_qremove(vm_offset_t va, int count)
3005 for (i = 0; i < count; i++) {
3008 pmap_inv_page(PHYS_TO_VM_PAGE(pa));
3017 * pmap_object_init_pt preloads the ptes for a given object
3018 * into the specified pmap. This eliminates the blast of soft
3019 * faults on process startup and immediately after an mmap.
3022 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3023 vm_pindex_t pindex, vm_size_t size)
3026 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
3027 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3028 ("pmap_object_init_pt: non-device object"));
3033 * pmap_is_prefaultable:
3035 * Return whether or not the specified virtual address is elgible
3039 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
3044 if (!pmap_get_pde_pte(pmap, addr, &pde, &pte))
3046 KASSERT(pte != NULL, ("Valid mapping but no pte ?"));
3053 * Fetch pointers to the PDE/PTE for the given pmap/VA pair.
3054 * Returns TRUE if the mapping exists, else FALSE.
3056 * NOTE: This function is only used by a couple of arm-specific modules.
3057 * It is not safe to take any pmap locks here, since we could be right
3058 * in the middle of debugging the pmap anyway...
3060 * It is possible for this routine to return FALSE even though a valid
3061 * mapping does exist. This is because we don't lock, so the metadata
3062 * state may be inconsistent.
3064 * NOTE: We can return a NULL *ptp in the case where the L1 pde is
3065 * a "section" mapping.
3068 pmap_get_pde_pte(pmap_t pm, vm_offset_t va, pd_entry_t **pdp, pt_entry_t **ptp)
3070 struct l2_dtable *l2;
3071 pd_entry_t *pl1pd, l1pd;
3075 if (pm->pm_l1 == NULL)
3079 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx];
3082 if (l1pte_section_p(l1pd)) {
3087 if (pm->pm_l2 == NULL)
3090 l2 = pm->pm_l2[L2_IDX(l1idx)];
3093 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3097 *ptp = &ptep[l2pte_index(va)];
3102 * Routine: pmap_remove_all
3104 * Removes this physical page from
3105 * all physical maps in which it resides.
3106 * Reflects back modify bits to the pager.
3109 * Original versions of this routine were very
3110 * inefficient because they iteratively called
3111 * pmap_remove (slow...)
3114 pmap_remove_all(vm_page_t m)
3118 struct l2_bucket *l2b;
3119 boolean_t flush = FALSE;
3123 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3124 ("pmap_remove_all: page %p is not managed", m));
3125 if (TAILQ_EMPTY(&m->md.pv_list))
3127 vm_page_lock_queues();
3128 pmap_remove_write(m);
3129 curpm = vmspace_pmap(curproc->p_vmspace);
3130 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3131 if (flush == FALSE && (pv->pv_pmap == curpm ||
3132 pv->pv_pmap == pmap_kernel()))
3135 PMAP_LOCK(pv->pv_pmap);
3137 * Cached contents were written-back in pmap_remove_write(),
3138 * but we still have to invalidate the cache entry to make
3139 * sure stale data are not retrieved when another page will be
3140 * mapped under this virtual address.
3142 if (pmap_is_current(pv->pv_pmap)) {
3143 cpu_dcache_inv_range(pv->pv_va, PAGE_SIZE);
3144 if (pmap_has_valid_mapping(pv->pv_pmap, pv->pv_va))
3145 cpu_l2cache_inv_range(pv->pv_va, PAGE_SIZE);
3148 if (pv->pv_flags & PVF_UNMAN) {
3149 /* remove the pv entry, but do not remove the mapping
3150 * and remember this is a kernel mapped page
3152 m->md.pv_kva = pv->pv_va;
3154 /* remove the mapping and pv entry */
3155 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
3156 KASSERT(l2b != NULL, ("No l2 bucket"));
3157 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
3159 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
3160 pmap_free_l2_bucket(pv->pv_pmap, l2b, 1);
3161 pv->pv_pmap->pm_stats.resident_count--;
3162 flags |= pv->pv_flags;
3164 pmap_nuke_pv(m, pv->pv_pmap, pv);
3165 PMAP_UNLOCK(pv->pv_pmap);
3166 pmap_free_pv_entry(pv);
3170 if (PV_BEEN_EXECD(flags))
3171 pmap_tlb_flushID(curpm);
3173 pmap_tlb_flushD(curpm);
3175 vm_page_aflag_clear(m, PGA_WRITEABLE);
3176 vm_page_unlock_queues();
3181 * Set the physical protection on the
3182 * specified range of this map as requested.
3185 pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3187 struct l2_bucket *l2b;
3188 pt_entry_t *ptep, pte;
3189 vm_offset_t next_bucket;
3193 CTR4(KTR_PMAP, "pmap_protect: pmap %p sva 0x%08x eva 0x%08x prot %x",
3194 pm, sva, eva, prot);
3196 if ((prot & VM_PROT_READ) == 0) {
3197 pmap_remove(pm, sva, eva);
3201 if (prot & VM_PROT_WRITE) {
3203 * If this is a read->write transition, just ignore it and let
3204 * vm_fault() take care of it later.
3209 vm_page_lock_queues();
3213 * OK, at this point, we know we're doing write-protect operation.
3214 * If the pmap is active, write-back the range.
3216 pmap_dcache_wb_range(pm, sva, eva - sva, FALSE, FALSE);
3218 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1;
3222 next_bucket = L2_NEXT_BUCKET(sva);
3223 if (next_bucket > eva)
3226 l2b = pmap_get_l2_bucket(pm, sva);
3232 ptep = &l2b->l2b_kva[l2pte_index(sva)];
3234 while (sva < next_bucket) {
3235 if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) {
3239 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte));
3240 pte &= ~L2_S_PROT_W;
3245 if (!(pg->oflags & VPO_UNMANAGED)) {
3246 f = pmap_modify_pv(pg, pm, sva,
3252 f = PVF_REF | PVF_EXEC;
3258 if (PV_BEEN_EXECD(f))
3259 pmap_tlb_flushID_SE(pm, sva);
3261 if (PV_BEEN_REFD(f))
3262 pmap_tlb_flushD_SE(pm, sva);
3272 if (PV_BEEN_EXECD(flags))
3273 pmap_tlb_flushID(pm);
3275 if (PV_BEEN_REFD(flags))
3276 pmap_tlb_flushD(pm);
3278 vm_page_unlock_queues();
3285 * Insert the given physical page (p) at
3286 * the specified virtual address (v) in the
3287 * target physical map with the protection requested.
3289 * If specified, the page will be wired down, meaning
3290 * that the related pte can not be reclaimed.
3292 * NB: This is the only routine which MAY NOT lazy-evaluate
3293 * or lose information. That is, this routine must actually
3294 * insert this page into the given map NOW.
3298 pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m,
3299 vm_prot_t prot, boolean_t wired)
3302 vm_page_lock_queues();
3304 pmap_enter_locked(pmap, va, m, prot, wired, M_WAITOK);
3305 vm_page_unlock_queues();
3310 * The page queues and pmap must be locked.
3313 pmap_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3314 boolean_t wired, int flags)
3316 struct l2_bucket *l2b = NULL;
3317 struct vm_page *opg;
3318 struct pv_entry *pve = NULL;
3319 pt_entry_t *ptep, npte, opte;
3324 PMAP_ASSERT_LOCKED(pmap);
3325 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
3326 if (va == vector_page) {
3327 pa = systempage.pv_pa;
3330 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 ||
3331 (flags & M_NOWAIT) != 0,
3332 ("pmap_enter_locked: page %p is not busy", m));
3333 pa = VM_PAGE_TO_PHYS(m);
3336 if (prot & VM_PROT_WRITE)
3337 nflags |= PVF_WRITE;
3338 if (prot & VM_PROT_EXECUTE)
3341 nflags |= PVF_WIRED;
3342 PDEBUG(1, printf("pmap_enter: pmap = %08x, va = %08x, m = %08x, prot = %x, "
3343 "wired = %x\n", (uint32_t) pmap, va, (uint32_t) m, prot, wired));
3345 if (pmap == pmap_kernel()) {
3346 l2b = pmap_get_l2_bucket(pmap, va);
3348 l2b = pmap_grow_l2_bucket(pmap, va);
3351 l2b = pmap_alloc_l2_bucket(pmap, va);
3353 if (flags & M_WAITOK) {
3355 vm_page_unlock_queues();
3357 vm_page_lock_queues();
3365 ptep = &l2b->l2b_kva[l2pte_index(va)];
3372 * There is already a mapping at this address.
3373 * If the physical address is different, lookup the
3376 if (l2pte_pa(opte) != pa)
3377 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte));
3383 if ((prot & (VM_PROT_ALL)) ||
3384 (!m || m->md.pvh_attrs & PVF_REF)) {
3386 * - The access type indicates that we don't need
3387 * to do referenced emulation.
3389 * - The physical page has already been referenced
3390 * so no need to re-do referenced emulation here.
3396 if (m && ((prot & VM_PROT_WRITE) != 0 ||
3397 (m->md.pvh_attrs & PVF_MOD))) {
3399 * This is a writable mapping, and the
3400 * page's mod state indicates it has
3401 * already been modified. Make it
3402 * writable from the outset.
3405 if (!(m->md.pvh_attrs & PVF_MOD))
3409 vm_page_aflag_set(m, PGA_REFERENCED);
3412 * Need to do page referenced emulation.
3414 npte |= L2_TYPE_INV;
3417 if (prot & VM_PROT_WRITE) {
3418 npte |= L2_S_PROT_W;
3420 (m->oflags & VPO_UNMANAGED) == 0)
3421 vm_page_aflag_set(m, PGA_WRITEABLE);
3423 npte |= pte_l2_s_cache_mode;
3424 if (m && m == opg) {
3426 * We're changing the attrs of an existing mapping.
3428 oflags = pmap_modify_pv(m, pmap, va,
3429 PVF_WRITE | PVF_EXEC | PVF_WIRED |
3430 PVF_MOD | PVF_REF, nflags);
3433 * We may need to flush the cache if we're
3436 if (pmap_is_current(pmap) &&
3437 (oflags & PVF_NC) == 0 &&
3438 (opte & L2_S_PROT_W) != 0 &&
3439 (prot & VM_PROT_WRITE) == 0 &&
3440 (opte & L2_TYPE_MASK) != L2_TYPE_INV) {
3441 cpu_dcache_wb_range(va, PAGE_SIZE);
3442 cpu_l2cache_wb_range(va, PAGE_SIZE);
3446 * New mapping, or changing the backing page
3447 * of an existing mapping.
3451 * Replacing an existing mapping with a new one.
3452 * It is part of our managed memory so we
3453 * must remove it from the PV list
3455 if ((pve = pmap_remove_pv(opg, pmap, va))) {
3457 /* note for patch: the oflags/invalidation was moved
3458 * because PG_FICTITIOUS pages could free the pve
3460 oflags = pve->pv_flags;
3462 * If the old mapping was valid (ref/mod
3463 * emulation creates 'invalid' mappings
3464 * initially) then make sure to frob
3467 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) {
3468 if (PV_BEEN_EXECD(oflags)) {
3469 pmap_idcache_wbinv_range(pmap, va,
3472 if (PV_BEEN_REFD(oflags)) {
3473 pmap_dcache_wb_range(pmap, va,
3475 (oflags & PVF_WRITE) == 0);
3479 /* free/allocate a pv_entry for UNMANAGED pages if
3480 * this physical page is not/is already mapped.
3483 if (m && (m->oflags & VPO_UNMANAGED) &&
3485 TAILQ_EMPTY(&m->md.pv_list)) {
3486 pmap_free_pv_entry(pve);
3490 (!(m->oflags & VPO_UNMANAGED) || m->md.pv_kva ||
3491 !TAILQ_EMPTY(&m->md.pv_list)))
3492 pve = pmap_get_pv_entry();
3494 (!(m->oflags & VPO_UNMANAGED) || m->md.pv_kva ||
3495 !TAILQ_EMPTY(&m->md.pv_list)))
3496 pve = pmap_get_pv_entry();
3499 if ((m->oflags & VPO_UNMANAGED)) {
3500 if (!TAILQ_EMPTY(&m->md.pv_list) ||
3502 KASSERT(pve != NULL, ("No pv"));
3503 nflags |= PVF_UNMAN;
3504 pmap_enter_pv(m, pve, pmap, va, nflags);
3508 KASSERT(va < kmi.clean_sva ||
3509 va >= kmi.clean_eva,
3510 ("pmap_enter: managed mapping within the clean submap"));
3511 KASSERT(pve != NULL, ("No pv"));
3512 pmap_enter_pv(m, pve, pmap, va, nflags);
3517 * Make sure userland mappings get the right permissions
3519 if (pmap != pmap_kernel() && va != vector_page) {
3520 npte |= L2_S_PROT_U;
3524 * Keep the stats up to date
3527 l2b->l2b_occupancy++;
3528 pmap->pm_stats.resident_count++;
3533 * If this is just a wiring change, the two PTEs will be
3534 * identical, so there's no need to update the page table.
3537 boolean_t is_cached = pmap_is_current(pmap);
3542 * We only need to frob the cache/tlb if this pmap
3546 if (L1_IDX(va) != L1_IDX(vector_page) &&
3547 l2pte_valid(npte)) {
3549 * This mapping is likely to be accessed as
3550 * soon as we return to userland. Fix up the
3551 * L1 entry to avoid taking another
3552 * page/domain fault.
3554 pd_entry_t *pl1pd, l1pd;
3556 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
3557 l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) |
3559 if (*pl1pd != l1pd) {
3566 if (PV_BEEN_EXECD(oflags))
3567 pmap_tlb_flushID_SE(pmap, va);
3568 else if (PV_BEEN_REFD(oflags))
3569 pmap_tlb_flushD_SE(pmap, va);
3573 pmap_fix_cache(m, pmap, va);
3578 * Maps a sequence of resident pages belonging to the same object.
3579 * The sequence begins with the given page m_start. This page is
3580 * mapped at the given virtual address start. Each subsequent page is
3581 * mapped at a virtual address that is offset from start by the same
3582 * amount as the page is offset from m_start within the object. The
3583 * last page in the sequence is the page with the largest offset from
3584 * m_start that can be mapped at a virtual address less than the given
3585 * virtual address end. Not every virtual page between start and end
3586 * is mapped; only those for which a resident page exists with the
3587 * corresponding offset from m_start are mapped.
3590 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3591 vm_page_t m_start, vm_prot_t prot)
3594 vm_pindex_t diff, psize;
3596 psize = atop(end - start);
3598 vm_page_lock_queues();
3600 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3601 pmap_enter_locked(pmap, start + ptoa(diff), m, prot &
3602 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE, M_NOWAIT);
3603 m = TAILQ_NEXT(m, listq);
3605 vm_page_unlock_queues();
3610 * this code makes some *MAJOR* assumptions:
3611 * 1. Current pmap & pmap exists.
3614 * 4. No page table pages.
3615 * but is *MUCH* faster than pmap_enter...
3619 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3622 vm_page_lock_queues();
3624 pmap_enter_locked(pmap, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
3626 vm_page_unlock_queues();
3631 * Routine: pmap_change_wiring
3632 * Function: Change the wiring attribute for a map/virtual-address
3634 * In/out conditions:
3635 * The mapping must already exist in the pmap.
3638 pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
3640 struct l2_bucket *l2b;
3641 pt_entry_t *ptep, pte;
3644 vm_page_lock_queues();
3646 l2b = pmap_get_l2_bucket(pmap, va);
3647 KASSERT(l2b, ("No l2b bucket in pmap_change_wiring"));
3648 ptep = &l2b->l2b_kva[l2pte_index(va)];
3650 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte));
3652 pmap_modify_pv(pg, pmap, va, PVF_WIRED, wired ? PVF_WIRED : 0);
3653 vm_page_unlock_queues();
3659 * Copy the range specified by src_addr/len
3660 * from the source map to the range dst_addr/len
3661 * in the destination map.
3663 * This routine is only advisory and need not do anything.
3666 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
3667 vm_size_t len, vm_offset_t src_addr)
3673 * Routine: pmap_extract
3675 * Extract the physical page address associated
3676 * with the given map/virtual_address pair.
3679 pmap_extract(pmap_t pm, vm_offset_t va)
3681 struct l2_dtable *l2;
3683 pt_entry_t *ptep, pte;
3689 l1pd = pm->pm_l1->l1_kva[l1idx];
3690 if (l1pte_section_p(l1pd)) {
3692 * These should only happen for pmap_kernel()
3694 KASSERT(pm == pmap_kernel(), ("huh"));
3695 /* XXX: what to do about the bits > 32 ? */
3696 if (l1pd & L1_S_SUPERSEC)
3697 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
3699 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3702 * Note that we can't rely on the validity of the L1
3703 * descriptor as an indication that a mapping exists.
3704 * We have to look it up in the L2 dtable.
3706 l2 = pm->pm_l2[L2_IDX(l1idx)];
3709 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3714 ptep = &ptep[l2pte_index(va)];
3722 switch (pte & L2_TYPE_MASK) {
3724 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3728 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3738 * Atomically extract and hold the physical page with the given
3739 * pmap and virtual address pair if that mapping permits the given
3744 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3746 struct l2_dtable *l2;
3748 pt_entry_t *ptep, pte;
3749 vm_paddr_t pa, paddr;
3757 l1pd = pmap->pm_l1->l1_kva[l1idx];
3758 if (l1pte_section_p(l1pd)) {
3760 * These should only happen for pmap_kernel()
3762 KASSERT(pmap == pmap_kernel(), ("huh"));
3763 /* XXX: what to do about the bits > 32 ? */
3764 if (l1pd & L1_S_SUPERSEC)
3765 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
3767 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3768 if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr))
3770 if (l1pd & L1_S_PROT_W || (prot & VM_PROT_WRITE) == 0) {
3771 m = PHYS_TO_VM_PAGE(pa);
3777 * Note that we can't rely on the validity of the L1
3778 * descriptor as an indication that a mapping exists.
3779 * We have to look it up in the L2 dtable.
3781 l2 = pmap->pm_l2[L2_IDX(l1idx)];
3784 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3789 ptep = &ptep[l2pte_index(va)];
3796 if (pte & L2_S_PROT_W || (prot & VM_PROT_WRITE) == 0) {
3797 switch (pte & L2_TYPE_MASK) {
3799 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3803 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3806 if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr))
3808 m = PHYS_TO_VM_PAGE(pa);
3814 PA_UNLOCK_COND(paddr);
3819 * Initialize a preallocated and zeroed pmap structure,
3820 * such as one in a vmspace structure.
3824 pmap_pinit(pmap_t pmap)
3826 PDEBUG(1, printf("pmap_pinit: pmap = %08x\n", (uint32_t) pmap));
3828 PMAP_LOCK_INIT(pmap);
3829 pmap_alloc_l1(pmap);
3830 bzero(pmap->pm_l2, sizeof(pmap->pm_l2));
3832 CPU_ZERO(&pmap->pm_active);
3834 TAILQ_INIT(&pmap->pm_pvlist);
3835 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3836 pmap->pm_stats.resident_count = 1;
3837 if (vector_page < KERNBASE) {
3838 pmap_enter(pmap, vector_page,
3839 VM_PROT_READ, PHYS_TO_VM_PAGE(systempage.pv_pa),
3846 /***************************************************
3847 * page management routines.
3848 ***************************************************/
3852 pmap_free_pv_entry(pv_entry_t pv)
3855 uma_zfree(pvzone, pv);
3860 * get a new pv_entry, allocating a block from the system
3862 * the memory allocation is performed bypassing the malloc code
3863 * because of the possibility of allocations at interrupt time.
3866 pmap_get_pv_entry(void)
3868 pv_entry_t ret_value;
3871 if (pv_entry_count > pv_entry_high_water)
3872 pagedaemon_wakeup();
3873 ret_value = uma_zalloc(pvzone, M_NOWAIT);
3878 * Remove the given range of addresses from the specified map.
3880 * It is assumed that the start and end are properly
3881 * rounded to the page size.
3883 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3
3885 pmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva)
3887 struct l2_bucket *l2b;
3888 vm_offset_t next_bucket;
3891 u_int mappings, is_exec, is_refd;
3896 * we lock in the pmap => pv_head direction
3899 vm_page_lock_queues();
3904 * Do one L2 bucket's worth at a time.
3906 next_bucket = L2_NEXT_BUCKET(sva);
3907 if (next_bucket > eva)
3910 l2b = pmap_get_l2_bucket(pm, sva);
3916 ptep = &l2b->l2b_kva[l2pte_index(sva)];
3919 while (sva < next_bucket) {
3928 * Nothing here, move along
3935 pm->pm_stats.resident_count--;
3941 * Update flags. In a number of circumstances,
3942 * we could cluster a lot of these and do a
3943 * number of sequential pages in one go.
3945 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) {
3946 struct pv_entry *pve;
3948 pve = pmap_remove_pv(pg, pm, sva);
3950 is_exec = PV_BEEN_EXECD(pve->pv_flags);
3951 is_refd = PV_BEEN_REFD(pve->pv_flags);
3952 pmap_free_pv_entry(pve);
3956 if (l2pte_valid(pte) && pmap_is_current(pm)) {
3957 if (total < PMAP_REMOVE_CLEAN_LIST_SIZE) {
3960 cpu_idcache_wbinv_range(sva,
3962 cpu_l2cache_wbinv_range(sva,
3964 cpu_tlb_flushID_SE(sva);
3965 } else if (is_refd) {
3966 cpu_dcache_wbinv_range(sva,
3968 cpu_l2cache_wbinv_range(sva,
3970 cpu_tlb_flushD_SE(sva);
3972 } else if (total == PMAP_REMOVE_CLEAN_LIST_SIZE) {
3973 /* flushall will also only get set for
3974 * for a current pmap
3976 cpu_idcache_wbinv_all();
3977 cpu_l2cache_wbinv_all();
3990 pmap_free_l2_bucket(pm, l2b, mappings);
3993 vm_page_unlock_queues();
4002 * Zero a given physical page by mapping it at a page hook point.
4003 * In doing the zero page op, the page we zero is mapped cachable, as with
4004 * StrongARM accesses to non-cached pages are non-burst making writing
4005 * _any_ bulk data very slow.
4007 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_CORE3)
4009 pmap_zero_page_generic(vm_paddr_t phys, int off, int size)
4011 #ifdef ARM_USE_SMALL_ALLOC
4016 struct vm_page *pg = PHYS_TO_VM_PAGE(phys);
4018 if (pg->md.pvh_list != NULL)
4019 panic("pmap_zero_page: page has mappings");
4022 if (_arm_bzero && size >= _min_bzero_size &&
4023 _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0)
4026 #ifdef ARM_USE_SMALL_ALLOC
4027 dstpg = (char *)arm_ptovirt(phys);
4028 if (off || size != PAGE_SIZE) {
4029 bzero(dstpg + off, size);
4030 cpu_dcache_wbinv_range((vm_offset_t)(dstpg + off), size);
4031 cpu_l2cache_wbinv_range((vm_offset_t)(dstpg + off), size);
4033 bzero_page((vm_offset_t)dstpg);
4034 cpu_dcache_wbinv_range((vm_offset_t)dstpg, PAGE_SIZE);
4035 cpu_l2cache_wbinv_range((vm_offset_t)dstpg, PAGE_SIZE);
4041 * Hook in the page, zero it, invalidate the TLB as needed.
4043 * Note the temporary zero-page mapping must be a non-cached page in
4044 * order to work without corruption when write-allocate is enabled.
4046 *cdst_pte = L2_S_PROTO | phys | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE);
4047 cpu_tlb_flushD_SE(cdstp);
4049 if (off || size != PAGE_SIZE)
4050 bzero((void *)(cdstp + off), size);
4057 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
4059 #if ARM_MMU_XSCALE == 1
4061 pmap_zero_page_xscale(vm_paddr_t phys, int off, int size)
4063 #ifdef ARM_USE_SMALL_ALLOC
4067 if (_arm_bzero && size >= _min_bzero_size &&
4068 _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0)
4070 #ifdef ARM_USE_SMALL_ALLOC
4071 dstpg = (char *)arm_ptovirt(phys);
4072 if (off || size != PAGE_SIZE) {
4073 bzero(dstpg + off, size);
4074 cpu_dcache_wbinv_range((vm_offset_t)(dstpg + off), size);
4076 bzero_page((vm_offset_t)dstpg);
4077 cpu_dcache_wbinv_range((vm_offset_t)dstpg, PAGE_SIZE);
4082 * Hook in the page, zero it, and purge the cache for that
4083 * zeroed page. Invalidate the TLB as needed.
4085 *cdst_pte = L2_S_PROTO | phys |
4086 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4087 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4089 cpu_tlb_flushD_SE(cdstp);
4091 if (off || size != PAGE_SIZE)
4092 bzero((void *)(cdstp + off), size);
4096 xscale_cache_clean_minidata();
4101 * Change the PTEs for the specified kernel mappings such that they
4102 * will use the mini data cache instead of the main data cache.
4105 pmap_use_minicache(vm_offset_t va, vm_size_t size)
4107 struct l2_bucket *l2b;
4108 pt_entry_t *ptep, *sptep, pte;
4109 vm_offset_t next_bucket, eva;
4111 #if (ARM_NMMUS > 1) || defined(CPU_XSCALE_CORE3)
4112 if (xscale_use_minidata == 0)
4119 next_bucket = L2_NEXT_BUCKET(va);
4120 if (next_bucket > eva)
4123 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
4125 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)];
4127 while (va < next_bucket) {
4129 if (!l2pte_minidata(pte)) {
4130 cpu_dcache_wbinv_range(va, PAGE_SIZE);
4131 cpu_tlb_flushD_SE(va);
4132 *ptep = pte & ~L2_B;
4137 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep));
4141 #endif /* ARM_MMU_XSCALE == 1 */
4144 * pmap_zero_page zeros the specified hardware page by mapping
4145 * the page into KVM and using bzero to clear its contents.
4148 pmap_zero_page(vm_page_t m)
4150 pmap_zero_page_func(VM_PAGE_TO_PHYS(m), 0, PAGE_SIZE);
4155 * pmap_zero_page_area zeros the specified hardware page by mapping
4156 * the page into KVM and using bzero to clear its contents.
4158 * off and size may not cover an area beyond a single hardware page.
4161 pmap_zero_page_area(vm_page_t m, int off, int size)
4164 pmap_zero_page_func(VM_PAGE_TO_PHYS(m), off, size);
4169 * pmap_zero_page_idle zeros the specified hardware page by mapping
4170 * the page into KVM and using bzero to clear its contents. This
4171 * is intended to be called from the vm_pagezero process only and
4175 pmap_zero_page_idle(vm_page_t m)
4185 * This is a local function used to work out the best strategy to clean
4186 * a single page referenced by its entry in the PV table. It should be used by
4187 * pmap_copy_page, pmap_zero page and maybe some others later on.
4189 * Its policy is effectively:
4190 * o If there are no mappings, we don't bother doing anything with the cache.
4191 * o If there is one mapping, we clean just that page.
4192 * o If there are multiple mappings, we clean the entire cache.
4194 * So that some functions can be further optimised, it returns 0 if it didn't
4195 * clean the entire cache, or 1 if it did.
4197 * XXX One bug in this routine is that if the pv_entry has a single page
4198 * mapped at 0x00000000 a whole cache clean will be performed rather than
4199 * just the 1 page. Since this should not occur in everyday use and if it does
4200 * it will just result in not the most efficient clean for the page.
4202 * We don't yet use this function but may want to.
4205 pmap_clean_page(struct pv_entry *pv, boolean_t is_src)
4207 pmap_t pm, pm_to_clean = NULL;
4208 struct pv_entry *npv;
4209 u_int cache_needs_cleaning = 0;
4211 vm_offset_t page_to_clean = 0;
4214 /* nothing mapped in so nothing to flush */
4219 * Since we flush the cache each time we change to a different
4220 * user vmspace, we only need to flush the page if it is in the
4224 pm = vmspace_pmap(curproc->p_vmspace);
4228 for (npv = pv; npv; npv = TAILQ_NEXT(npv, pv_list)) {
4229 if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) {
4230 flags |= npv->pv_flags;
4232 * The page is mapped non-cacheable in
4233 * this map. No need to flush the cache.
4235 if (npv->pv_flags & PVF_NC) {
4237 if (cache_needs_cleaning)
4238 panic("pmap_clean_page: "
4239 "cache inconsistency");
4242 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0)
4244 if (cache_needs_cleaning) {
4248 page_to_clean = npv->pv_va;
4249 pm_to_clean = npv->pv_pmap;
4251 cache_needs_cleaning = 1;
4254 if (page_to_clean) {
4255 if (PV_BEEN_EXECD(flags))
4256 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean,
4259 pmap_dcache_wb_range(pm_to_clean, page_to_clean,
4260 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0);
4261 } else if (cache_needs_cleaning) {
4262 if (PV_BEEN_EXECD(flags))
4263 pmap_idcache_wbinv_all(pm);
4265 pmap_dcache_wbinv_all(pm);
4273 * pmap_copy_page copies the specified (machine independent)
4274 * page by mapping the page into virtual memory and using
4275 * bcopy to copy the page, one machine dependent page at a
4282 * Copy one physical page into another, by mapping the pages into
4283 * hook points. The same comment regarding cachability as in
4284 * pmap_zero_page also applies here.
4286 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined (CPU_XSCALE_CORE3)
4288 pmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst)
4291 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src);
4294 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst);
4296 if (dst_pg->md.pvh_list != NULL)
4297 panic("pmap_copy_page: dst page has mappings");
4302 * Clean the source page. Hold the source page's lock for
4303 * the duration of the copy so that no other mappings can
4304 * be created while we have a potentially aliased mapping.
4308 * XXX: Not needed while we call cpu_dcache_wbinv_all() in
4311 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE);
4314 * Map the pages into the page hook points, copy them, and purge
4315 * the cache for the appropriate page. Invalidate the TLB
4319 *csrc_pte = L2_S_PROTO | src |
4320 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode;
4322 *cdst_pte = L2_S_PROTO | dst |
4323 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode;
4325 cpu_tlb_flushD_SE(csrcp);
4326 cpu_tlb_flushD_SE(cdstp);
4328 bcopy_page(csrcp, cdstp);
4330 cpu_dcache_inv_range(csrcp, PAGE_SIZE);
4331 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE);
4332 cpu_l2cache_inv_range(csrcp, PAGE_SIZE);
4333 cpu_l2cache_wbinv_range(cdstp, PAGE_SIZE);
4335 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
4337 #if ARM_MMU_XSCALE == 1
4339 pmap_copy_page_xscale(vm_paddr_t src, vm_paddr_t dst)
4342 /* XXX: Only needed for pmap_clean_page(), which is commented out. */
4343 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src);
4346 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst);
4348 if (dst_pg->md.pvh_list != NULL)
4349 panic("pmap_copy_page: dst page has mappings");
4354 * Clean the source page. Hold the source page's lock for
4355 * the duration of the copy so that no other mappings can
4356 * be created while we have a potentially aliased mapping.
4360 * XXX: Not needed while we call cpu_dcache_wbinv_all() in
4363 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE);
4366 * Map the pages into the page hook points, copy them, and purge
4367 * the cache for the appropriate page. Invalidate the TLB
4371 *csrc_pte = L2_S_PROTO | src |
4372 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
4373 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4375 *cdst_pte = L2_S_PROTO | dst |
4376 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4377 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4379 cpu_tlb_flushD_SE(csrcp);
4380 cpu_tlb_flushD_SE(cdstp);
4382 bcopy_page(csrcp, cdstp);
4384 xscale_cache_clean_minidata();
4386 #endif /* ARM_MMU_XSCALE == 1 */
4389 pmap_copy_page(vm_page_t src, vm_page_t dst)
4391 #ifdef ARM_USE_SMALL_ALLOC
4392 vm_offset_t srcpg, dstpg;
4395 cpu_dcache_wbinv_all();
4396 cpu_l2cache_wbinv_all();
4397 if (_arm_memcpy && PAGE_SIZE >= _min_memcpy_size &&
4398 _arm_memcpy((void *)VM_PAGE_TO_PHYS(dst),
4399 (void *)VM_PAGE_TO_PHYS(src), PAGE_SIZE, IS_PHYSICAL) == 0)
4401 #ifdef ARM_USE_SMALL_ALLOC
4402 srcpg = arm_ptovirt(VM_PAGE_TO_PHYS(src));
4403 dstpg = arm_ptovirt(VM_PAGE_TO_PHYS(dst));
4404 bcopy_page(srcpg, dstpg);
4405 cpu_dcache_wbinv_range(dstpg, PAGE_SIZE);
4406 cpu_l2cache_wbinv_range(dstpg, PAGE_SIZE);
4408 pmap_copy_page_func(VM_PAGE_TO_PHYS(src), VM_PAGE_TO_PHYS(dst));
4416 * this routine returns true if a physical page resides
4417 * in the given pmap.
4420 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4426 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4427 ("pmap_page_exists_quick: page %p is not managed", m));
4429 vm_page_lock_queues();
4430 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4431 if (pv->pv_pmap == pmap) {
4439 vm_page_unlock_queues();
4444 * pmap_page_wired_mappings:
4446 * Return the number of managed mappings to the given physical page
4450 pmap_page_wired_mappings(vm_page_t m)
4456 if ((m->oflags & VPO_UNMANAGED) != 0)
4458 vm_page_lock_queues();
4459 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
4460 if ((pv->pv_flags & PVF_WIRED) != 0)
4462 vm_page_unlock_queues();
4467 * pmap_ts_referenced:
4469 * Return the count of reference bits for a page, clearing all of them.
4472 pmap_ts_referenced(vm_page_t m)
4475 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4476 ("pmap_ts_referenced: page %p is not managed", m));
4477 return (pmap_clearbit(m, PVF_REF));
4482 pmap_is_modified(vm_page_t m)
4485 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4486 ("pmap_is_modified: page %p is not managed", m));
4487 if (m->md.pvh_attrs & PVF_MOD)
4495 * Clear the modify bits on the specified physical page.
4498 pmap_clear_modify(vm_page_t m)
4501 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4502 ("pmap_clear_modify: page %p is not managed", m));
4503 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
4504 KASSERT((m->oflags & VPO_BUSY) == 0,
4505 ("pmap_clear_modify: page %p is busy", m));
4508 * If the page is not PGA_WRITEABLE, then no mappings can be modified.
4509 * If the object containing the page is locked and the page is not
4510 * VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set.
4512 if ((m->aflags & PGA_WRITEABLE) == 0)
4514 if (m->md.pvh_attrs & PVF_MOD)
4515 pmap_clearbit(m, PVF_MOD);
4520 * pmap_is_referenced:
4522 * Return whether or not the specified physical page was referenced
4523 * in any physical maps.
4526 pmap_is_referenced(vm_page_t m)
4529 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4530 ("pmap_is_referenced: page %p is not managed", m));
4531 return ((m->md.pvh_attrs & PVF_REF) != 0);
4535 * pmap_clear_reference:
4537 * Clear the reference bit on the specified physical page.
4540 pmap_clear_reference(vm_page_t m)
4543 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4544 ("pmap_clear_reference: page %p is not managed", m));
4545 if (m->md.pvh_attrs & PVF_REF)
4546 pmap_clearbit(m, PVF_REF);
4551 * Clear the write and modified bits in each of the given page's mappings.
4554 pmap_remove_write(vm_page_t m)
4557 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4558 ("pmap_remove_write: page %p is not managed", m));
4561 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by
4562 * another thread while the object is locked. Thus, if PGA_WRITEABLE
4563 * is clear, no page table entries need updating.
4565 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
4566 if ((m->oflags & VPO_BUSY) != 0 ||
4567 (m->aflags & PGA_WRITEABLE) != 0)
4568 pmap_clearbit(m, PVF_WRITE);
4573 * perform the pmap work for mincore
4576 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
4578 printf("pmap_mincore()\n");
4585 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
4591 * Increase the starting virtual address of the given mapping if a
4592 * different alignment might result in more superpage mappings.
4595 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
4596 vm_offset_t *addr, vm_size_t size)
4602 * Map a set of physical memory pages into the kernel virtual
4603 * address space. Return a pointer to where it is mapped. This
4604 * routine is intended to be used for mapping device memory,
4608 pmap_mapdev(vm_offset_t pa, vm_size_t size)
4610 vm_offset_t va, tmpva, offset;
4612 offset = pa & PAGE_MASK;
4613 size = roundup(size, PAGE_SIZE);
4617 va = kmem_alloc_nofault(kernel_map, size);
4619 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
4620 for (tmpva = va; size > 0;) {
4621 pmap_kenter_internal(tmpva, pa, 0);
4627 return ((void *)(va + offset));
4630 #define BOOTSTRAP_DEBUG
4635 * Create a single section mapping.
4638 pmap_map_section(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
4639 int prot, int cache)
4641 pd_entry_t *pde = (pd_entry_t *) l1pt;
4644 KASSERT(((va | pa) & L1_S_OFFSET) == 0, ("ouin2"));
4653 fl = pte_l1_s_cache_mode;
4657 fl = pte_l1_s_cache_mode_pt;
4661 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
4662 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL);
4663 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
4670 * Link the L2 page table specified by l2pv.pv_pa into the L1
4671 * page table at the slot for "va".
4674 pmap_link_l2pt(vm_offset_t l1pt, vm_offset_t va, struct pv_addr *l2pv)
4676 pd_entry_t *pde = (pd_entry_t *) l1pt, proto;
4677 u_int slot = va >> L1_S_SHIFT;
4679 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO;
4681 #ifdef VERBOSE_INIT_ARM
4682 printf("pmap_link_l2pt: pa=0x%x va=0x%x\n", l2pv->pv_pa, l2pv->pv_va);
4685 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000);
4687 PTE_SYNC(&pde[slot]);
4689 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list);
4697 * Create a single page mapping.
4700 pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot,
4703 pd_entry_t *pde = (pd_entry_t *) l1pt;
4707 KASSERT(((va | pa) & PAGE_MASK) == 0, ("ouin"));
4716 fl = pte_l2_s_cache_mode;
4720 fl = pte_l2_s_cache_mode_pt;
4724 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
4725 panic("pmap_map_entry: no L2 table for VA 0x%08x", va);
4727 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK);
4730 panic("pmap_map_entry: can't find L2 table for VA 0x%08x", va);
4732 pte[l2pte_index(va)] =
4733 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl;
4734 PTE_SYNC(&pte[l2pte_index(va)]);
4740 * Map a chunk of memory using the most efficient mappings
4741 * possible (section. large page, small page) into the
4742 * provided L1 and L2 tables at the specified virtual address.
4745 pmap_map_chunk(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
4746 vm_size_t size, int prot, int cache)
4748 pd_entry_t *pde = (pd_entry_t *) l1pt;
4749 pt_entry_t *pte, f1, f2s, f2l;
4753 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
4756 panic("pmap_map_chunk: no L1 table provided");
4758 #ifdef VERBOSE_INIT_ARM
4759 printf("pmap_map_chunk: pa=0x%x va=0x%x size=0x%x resid=0x%x "
4760 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache);
4772 f1 = pte_l1_s_cache_mode;
4773 f2l = pte_l2_l_cache_mode;
4774 f2s = pte_l2_s_cache_mode;
4778 f1 = pte_l1_s_cache_mode_pt;
4779 f2l = pte_l2_l_cache_mode_pt;
4780 f2s = pte_l2_s_cache_mode_pt;
4787 /* See if we can use a section mapping. */
4788 if (L1_S_MAPPABLE_P(va, pa, resid)) {
4789 #ifdef VERBOSE_INIT_ARM
4792 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
4793 L1_S_PROT(PTE_KERNEL, prot) | f1 |
4794 L1_S_DOM(PMAP_DOMAIN_KERNEL);
4795 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
4803 * Ok, we're going to use an L2 table. Make sure
4804 * one is actually in the corresponding L1 slot
4805 * for the current VA.
4807 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
4808 panic("pmap_map_chunk: no L2 table for VA 0x%08x", va);
4810 pte = (pt_entry_t *) kernel_pt_lookup(
4811 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
4813 panic("pmap_map_chunk: can't find L2 table for VA"
4815 /* See if we can use a L2 large page mapping. */
4816 if (L2_L_MAPPABLE_P(va, pa, resid)) {
4817 #ifdef VERBOSE_INIT_ARM
4820 for (i = 0; i < 16; i++) {
4821 pte[l2pte_index(va) + i] =
4823 L2_L_PROT(PTE_KERNEL, prot) | f2l;
4824 PTE_SYNC(&pte[l2pte_index(va) + i]);
4832 /* Use a small page mapping. */
4833 #ifdef VERBOSE_INIT_ARM
4836 pte[l2pte_index(va)] =
4837 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s;
4838 PTE_SYNC(&pte[l2pte_index(va)]);
4843 #ifdef VERBOSE_INIT_ARM
4850 /********************** Static device map routines ***************************/
4852 static const struct pmap_devmap *pmap_devmap_table;
4855 * Register the devmap table. This is provided in case early console
4856 * initialization needs to register mappings created by bootstrap code
4857 * before pmap_devmap_bootstrap() is called.
4860 pmap_devmap_register(const struct pmap_devmap *table)
4863 pmap_devmap_table = table;
4867 * Map all of the static regions in the devmap table, and remember
4868 * the devmap table so other parts of the kernel can look up entries
4872 pmap_devmap_bootstrap(vm_offset_t l1pt, const struct pmap_devmap *table)
4876 pmap_devmap_table = table;
4878 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
4879 #ifdef VERBOSE_INIT_ARM
4880 printf("devmap: %08x -> %08x @ %08x\n",
4881 pmap_devmap_table[i].pd_pa,
4882 pmap_devmap_table[i].pd_pa +
4883 pmap_devmap_table[i].pd_size - 1,
4884 pmap_devmap_table[i].pd_va);
4886 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va,
4887 pmap_devmap_table[i].pd_pa,
4888 pmap_devmap_table[i].pd_size,
4889 pmap_devmap_table[i].pd_prot,
4890 pmap_devmap_table[i].pd_cache);
4894 const struct pmap_devmap *
4895 pmap_devmap_find_pa(vm_paddr_t pa, vm_size_t size)
4899 if (pmap_devmap_table == NULL)
4902 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
4903 if (pa >= pmap_devmap_table[i].pd_pa &&
4904 pa + size <= pmap_devmap_table[i].pd_pa +
4905 pmap_devmap_table[i].pd_size)
4906 return (&pmap_devmap_table[i]);
4912 const struct pmap_devmap *
4913 pmap_devmap_find_va(vm_offset_t va, vm_size_t size)
4917 if (pmap_devmap_table == NULL)
4920 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
4921 if (va >= pmap_devmap_table[i].pd_va &&
4922 va + size <= pmap_devmap_table[i].pd_va +
4923 pmap_devmap_table[i].pd_size)
4924 return (&pmap_devmap_table[i]);