1 /***********************license start***************
2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * * Neither the name of Cavium Networks nor the names of
19 * its contributors may be used to endorse or promote products
20 * derived from this software without specific prior written
23 * This Software, including technical data, may be subject to U.S. export control
24 * laws, including the U.S. Export Administration Act and its associated
25 * regulations, and may be subject to export or import regulations in other
28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
38 ***********************license end**************************************/
44 * Automatically generated error messages for cn56xxp1.
46 * This file is auto generated. Do not edit.
50 * <hr><h2>Error tree for CN56XXP1</h2>
55 * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
56 * edge [fontsize=7, font=helvitica];
57 * cvmx_root [label="ROOT|<root>root"];
58 * cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<mii>mii"];
59 * cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
60 * cvmx_ciu_int0_sum0:mii:e -> cvmx_mix0_isr [label="mii"];
61 * cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
62 * cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"];
63 * cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
64 * cvmx_npei_rsl_int_blocks [label="PEXP_NPEI_RSL_INT_BLOCKS|<l2c>l2c|<agl>agl|<gmx0>gmx0|<gmx1>gmx1|<ipd>ipd|<tim>tim|<pko>pko|<pow>pow|<npei>npei|<rad>rad|<lmc1>lmc1|<asxpcs1>asxpcs1|<asxpcs0>asxpcs0|<key>key|<mio>mio|<pip>pip|<fpa>fpa|<lmc0>lmc0|<iob>iob|<zip>zip|<usb>usb"];
65 * cvmx_l2c_int_stat [label="L2C_INT_STAT|<l2tsec>l2tsec|<l2dsec>l2dsec|<oob1>oob1|<oob2>oob2|<oob3>oob3|<l2tded>l2tded|<l2dded>l2dded|<lck>lck|<lck2>lck2"];
66 * cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2c_int_stat [label="l2c"];
67 * cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
68 * cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
69 * cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
70 * cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
71 * cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<out_ovr>out_ovr|<loststat>loststat"];
72 * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"];
73 * cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"];
74 * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"];
75 * cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"];
76 * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"];
77 * cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
78 * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
79 * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"];
80 * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
81 * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"];
82 * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
83 * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"];
84 * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
85 * cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"];
86 * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
87 * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw"];
88 * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
89 * cvmx_gmx1_bad_reg [label="GMXX_BAD_REG(1)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
90 * cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_bad_reg [label="gmx1"];
91 * cvmx_gmx1_rx0_int_reg [label="GMXX_RXX_INT_REG(0,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"];
92 * cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx0_int_reg [label="gmx1"];
93 * cvmx_gmx1_rx1_int_reg [label="GMXX_RXX_INT_REG(1,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"];
94 * cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx1_int_reg [label="gmx1"];
95 * cvmx_gmx1_rx2_int_reg [label="GMXX_RXX_INT_REG(2,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"];
96 * cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx2_int_reg [label="gmx1"];
97 * cvmx_gmx1_rx3_int_reg [label="GMXX_RXX_INT_REG(3,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"];
98 * cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx3_int_reg [label="gmx1"];
99 * cvmx_gmx1_tx_int_reg [label="GMXX_TX_INT_REG(1)|<pko_nxa>pko_nxa|<undflw>undflw"];
100 * cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_tx_int_reg [label="gmx1"];
101 * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
102 * cvmx_npei_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
103 * cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
104 * cvmx_npei_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
105 * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
106 * cvmx_npei_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
107 * cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
108 * cvmx_npei_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
109 * cvmx_npei_int_sum [label="PEXP_NPEI_INT_SUM|<c0_ldwn>c0_ldwn|<c0_se>c0_se|<c0_un_b0>c0_un_b0|<c0_un_b1>c0_un_b1|<c0_un_b2>c0_un_b2|<c0_un_bx>c0_un_bx|<c0_un_wf>c0_un_wf|<c0_un_wi>c0_un_wi|<c0_up_b0>c0_up_b0|<c0_up_b1>c0_up_b1|<c0_up_b2>c0_up_b2|<c0_up_bx>c0_up_bx|<c0_up_wf>c0_up_wf|<c0_up_wi>c0_up_wi|<c0_wake>c0_wake|<c1_ldwn>c1_ldwn|<c1_se>c1_se|<c1_un_b0>c1_un_b0|<c1_un_b1>c1_un_b1|<c1_un_b2>c1_un_b2|<c1_un_bx>c1_un_bx|<c1_un_wf>c1_un_wf|<c1_un_wi>c1_un_wi|<c1_up_b0>c1_up_b0|<c1_up_b1>c1_up_b1|<c1_up_b2>c1_up_b2|<c1_up_bx>c1_up_bx|<c1_up_wf>c1_up_wf|<c1_up_wi>c1_up_wi|<c1_wake>c1_wake|<bar0_to>bar0_to|<dma0dbo>dma0dbo|<dma1dbo>dma1dbo|<dma2dbo>dma2dbo|<dma3dbo>dma3dbo|<iob2big>iob2big|<rml_rto>rml_rto|<rml_wto>rml_wto|<dma4dbo>dma4dbo|<c0_exc>c0_exc|<c1_exc>c1_exc"];
110 * cvmx_pesc0_dbg_info [label="PESCX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
111 * cvmx_npei_int_sum:c0_exc:e -> cvmx_pesc0_dbg_info [label="c0_exc"];
112 * cvmx_pesc1_dbg_info [label="PESCX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
113 * cvmx_npei_int_sum:c1_exc:e -> cvmx_pesc1_dbg_info [label="c1_exc"];
114 * cvmx_npei_rsl_int_blocks:npei:e -> cvmx_npei_int_sum [label="npei"];
115 * cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
116 * cvmx_npei_rsl_int_blocks:rad:e -> cvmx_rad_reg_error [label="rad"];
117 * cvmx_lmc1_mem_cfg0 [label="LMCX_MEM_CFG0(1)|<sec_err>sec_err|<ded_err>ded_err"];
118 * cvmx_npei_rsl_int_blocks:lmc1:e -> cvmx_lmc1_mem_cfg0 [label="lmc1"];
119 * cvmx_pcs1_int0_reg [label="PCSX_INTX_REG(0,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
120 * cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int0_reg [label="asxpcs1"];
121 * cvmx_pcs1_int1_reg [label="PCSX_INTX_REG(1,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
122 * cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int1_reg [label="asxpcs1"];
123 * cvmx_pcs1_int2_reg [label="PCSX_INTX_REG(2,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
124 * cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int2_reg [label="asxpcs1"];
125 * cvmx_pcs1_int3_reg [label="PCSX_INTX_REG(3,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
126 * cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int3_reg [label="asxpcs1"];
127 * cvmx_pcsx1_int_reg [label="PCSXX_INT_REG(1)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos"];
128 * cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcsx1_int_reg [label="asxpcs1"];
129 * cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
130 * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
131 * cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
132 * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"];
133 * cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
134 * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
135 * cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
136 * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
137 * cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos"];
138 * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
139 * cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
140 * cvmx_npei_rsl_int_blocks:key:e -> cvmx_key_int_sum [label="key"];
141 * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
142 * cvmx_npei_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
143 * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr"];
144 * cvmx_npei_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
145 * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
146 * cvmx_npei_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
147 * cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
148 * cvmx_npei_rsl_int_blocks:lmc0:e -> cvmx_lmc0_mem_cfg0 [label="lmc0"];
149 * cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
150 * cvmx_npei_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
151 * cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
152 * cvmx_npei_rsl_int_blocks:zip:e -> cvmx_zip_error [label="zip"];
153 * cvmx_usbn0_int_sum [label="USBNX_INT_SUM(0)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
154 * cvmx_npei_rsl_int_blocks:usb:e -> cvmx_usbn0_int_sum [label="usb"];
155 * cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis];
156 * cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis];
157 * cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
158 * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
159 * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
160 * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
161 * cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
162 * cvmx_gmx1_bad_reg -> cvmx_gmx1_rx0_int_reg [style=invis];
163 * cvmx_gmx1_rx0_int_reg -> cvmx_gmx1_rx1_int_reg [style=invis];
164 * cvmx_gmx1_rx1_int_reg -> cvmx_gmx1_rx2_int_reg [style=invis];
165 * cvmx_gmx1_rx2_int_reg -> cvmx_gmx1_rx3_int_reg [style=invis];
166 * cvmx_gmx1_rx3_int_reg -> cvmx_gmx1_tx_int_reg [style=invis];
167 * cvmx_pcs1_int0_reg -> cvmx_pcs1_int1_reg [style=invis];
168 * cvmx_pcs1_int1_reg -> cvmx_pcs1_int2_reg [style=invis];
169 * cvmx_pcs1_int2_reg -> cvmx_pcs1_int3_reg [style=invis];
170 * cvmx_pcs1_int3_reg -> cvmx_pcsx1_int_reg [style=invis];
171 * cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
172 * cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis];
173 * cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis];
174 * cvmx_pcs0_int3_reg -> cvmx_pcsx0_int_reg [style=invis];
175 * cvmx_root:root:e -> cvmx_npei_rsl_int_blocks [label="root"];
179 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
180 #include <asm/octeon/cvmx.h>
181 #include <asm/octeon/cvmx-error.h>
182 #include <asm/octeon/cvmx-error-custom.h>
183 #include <asm/octeon/cvmx-csr-typedefs.h>
186 #include "cvmx-error.h"
187 #include "cvmx-error-custom.h"
190 int cvmx_error_initialize_cn56xxp1(void);
192 int cvmx_error_initialize_cn56xxp1(void)
194 cvmx_error_info_t info;
197 /* CVMX_CIU_INTX_SUM0(0) */
198 info.reg_type = CVMX_ERROR_REGISTER_IO64;
199 info.status_addr = CVMX_CIU_INTX_SUM0(0);
200 info.status_mask = 0;
201 info.enable_addr = 0;
202 info.enable_mask = 0;
204 info.group = CVMX_ERROR_GROUP_INTERNAL;
205 info.group_index = 0;
206 info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
207 info.parent.status_addr = 0;
208 info.parent.status_mask = 0;
209 info.func = __cvmx_error_decode;
211 fail |= cvmx_error_add(&info);
213 /* CVMX_MIXX_ISR(0) */
214 info.reg_type = CVMX_ERROR_REGISTER_IO64;
215 info.status_addr = CVMX_MIXX_ISR(0);
216 info.status_mask = 1ull<<0 /* odblovf */;
217 info.enable_addr = CVMX_MIXX_INTENA(0);
218 info.enable_mask = 1ull<<0 /* ovfena */;
220 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
221 info.group_index = 0;
222 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
223 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
224 info.parent.status_mask = 1ull<<62 /* mii */;
225 info.func = __cvmx_error_display;
226 info.user_info = (long)
227 "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
228 " If SW attempts to write to the MIX_ORING2[ODBELL]\n"
229 " with a value greater than the remaining #of\n"
230 " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
231 " the following occurs:\n"
232 " 1) The MIX_ORING2[ODBELL] write is IGNORED\n"
233 " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
234 " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
235 " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
236 " and the local interrupt mask bit(OVFENA) is set, than an\n"
237 " interrupt is reported for this event.\n"
238 " SW should keep track of the #I-Ring Entries in use\n"
239 " (ie: cumulative # of ODBELL writes), and ensure that\n"
240 " future ODBELL writes don't exceed the size of the\n"
241 " O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
242 " SW must reclaim O-Ring Entries by writing to the\n"
243 " MIX_ORCNT[ORCNT]. .\n"
244 " NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
245 " If it occurs, it's an indication that SW has\n"
246 " overwritten the O-Ring buffer, and the only recourse\n"
248 fail |= cvmx_error_add(&info);
250 info.reg_type = CVMX_ERROR_REGISTER_IO64;
251 info.status_addr = CVMX_MIXX_ISR(0);
252 info.status_mask = 1ull<<1 /* idblovf */;
253 info.enable_addr = CVMX_MIXX_INTENA(0);
254 info.enable_mask = 1ull<<1 /* ivfena */;
256 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
257 info.group_index = 0;
258 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
259 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
260 info.parent.status_mask = 1ull<<62 /* mii */;
261 info.func = __cvmx_error_display;
262 info.user_info = (long)
263 "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
264 " If SW attempts to write to the MIX_IRING2[IDBELL]\n"
265 " with a value greater than the remaining #of\n"
266 " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
267 " the following occurs:\n"
268 " 1) The MIX_IRING2[IDBELL] write is IGNORED\n"
269 " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
270 " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
271 " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
272 " and the local interrupt mask bit(IVFENA) is set, than an\n"
273 " interrupt is reported for this event.\n"
274 " SW should keep track of the #I-Ring Entries in use\n"
275 " (ie: cumulative # of IDBELL writes), and ensure that\n"
276 " future IDBELL writes don't exceed the size of the\n"
277 " I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
278 " SW must reclaim I-Ring Entries by keeping track of the\n"
279 " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
280 " NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
281 " total #packets(not IRing Entries) and SW must further\n"
282 " keep track of the # of I-Ring Entries associated with\n"
283 " each packet as they are processed.\n"
284 " NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
285 " If it occurs, it's an indication that SW has\n"
286 " overwritten the I-Ring buffer, and the only recourse\n"
288 fail |= cvmx_error_add(&info);
290 info.reg_type = CVMX_ERROR_REGISTER_IO64;
291 info.status_addr = CVMX_MIXX_ISR(0);
292 info.status_mask = 1ull<<4 /* data_drp */;
293 info.enable_addr = CVMX_MIXX_INTENA(0);
294 info.enable_mask = 1ull<<4 /* data_drpena */;
296 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
297 info.group_index = 0;
298 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
299 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
300 info.parent.status_mask = 1ull<<62 /* mii */;
301 info.func = __cvmx_error_display;
302 info.user_info = (long)
303 "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
304 " If this does occur, the DATA_DRP is set and the\n"
305 " CIU_INTx_SUM0,4[MII] bits are set.\n"
306 " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
307 " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
308 " interrupt is reported for this event.\n";
309 fail |= cvmx_error_add(&info);
311 info.reg_type = CVMX_ERROR_REGISTER_IO64;
312 info.status_addr = CVMX_MIXX_ISR(0);
313 info.status_mask = 1ull<<5 /* irun */;
314 info.enable_addr = CVMX_MIXX_INTENA(0);
315 info.enable_mask = 1ull<<5 /* irunena */;
317 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
318 info.group_index = 0;
319 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
320 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
321 info.parent.status_mask = 1ull<<62 /* mii */;
322 info.func = __cvmx_error_display;
323 info.user_info = (long)
324 "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n"
325 " If SW writes a larger value than what is currently\n"
326 " in the MIX_IRCNT[IRCNT], then HW will report the\n"
327 " underflow condition.\n"
328 " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
329 " NOTE: If an IRUN underflow condition is detected,\n"
330 " the integrity of the MIX/AGL HW state has\n"
331 " been compromised. To recover, SW must issue a\n"
332 " software reset sequence (see: MIX_CTL[RESET]\n";
333 fail |= cvmx_error_add(&info);
335 info.reg_type = CVMX_ERROR_REGISTER_IO64;
336 info.status_addr = CVMX_MIXX_ISR(0);
337 info.status_mask = 1ull<<6 /* orun */;
338 info.enable_addr = CVMX_MIXX_INTENA(0);
339 info.enable_mask = 1ull<<6 /* orunena */;
341 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
342 info.group_index = 0;
343 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
344 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
345 info.parent.status_mask = 1ull<<62 /* mii */;
346 info.func = __cvmx_error_display;
347 info.user_info = (long)
348 "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n"
349 " If SW writes a larger value than what is currently\n"
350 " in the MIX_ORCNT[ORCNT], then HW will report the\n"
351 " underflow condition.\n"
352 " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
353 " NOTE: If an ORUN underflow condition is detected,\n"
354 " the integrity of the MIX/AGL HW state has\n"
355 " been compromised. To recover, SW must issue a\n"
356 " software reset sequence (see: MIX_CTL[RESET]\n";
357 fail |= cvmx_error_add(&info);
359 /* CVMX_CIU_INT_SUM1 */
360 /* CVMX_PEXP_NPEI_RSL_INT_BLOCKS */
361 info.reg_type = CVMX_ERROR_REGISTER_IO64;
362 info.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
363 info.status_mask = 0;
364 info.enable_addr = 0;
365 info.enable_mask = 0;
367 info.group = CVMX_ERROR_GROUP_INTERNAL;
368 info.group_index = 0;
369 info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
370 info.parent.status_addr = 0;
371 info.parent.status_mask = 0;
372 info.func = __cvmx_error_decode;
374 fail |= cvmx_error_add(&info);
376 /* CVMX_L2C_INT_STAT */
377 info.reg_type = CVMX_ERROR_REGISTER_IO64;
378 info.status_addr = CVMX_L2C_INT_STAT;
379 info.status_mask = 1ull<<3 /* l2tsec */;
380 info.enable_addr = CVMX_L2C_INT_EN;
381 info.enable_mask = 1ull<<3 /* l2tsecen */;
382 info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
383 info.group = CVMX_ERROR_GROUP_INTERNAL;
384 info.group_index = 0;
385 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
386 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
387 info.parent.status_mask = 1ull<<16 /* l2c */;
388 info.func = __cvmx_error_display;
389 info.user_info = (long)
390 "ERROR L2C_INT_STAT[L2TSEC]: L2T Single Bit Error corrected (SEC) status\n"
391 " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
392 " given index) are checked for single bit errors(SBEs).\n"
393 " This bit is set if ANY of the 8 sets contains an SBE.\n"
394 " SBEs are auto corrected in HW and generate an\n"
395 " interrupt(if enabled).\n"
396 " NOTE: This is the 'same' bit as L2T_ERR[SEC_ERR]\n";
397 fail |= cvmx_error_add(&info);
399 info.reg_type = CVMX_ERROR_REGISTER_IO64;
400 info.status_addr = CVMX_L2C_INT_STAT;
401 info.status_mask = 1ull<<5 /* l2dsec */;
402 info.enable_addr = CVMX_L2C_INT_EN;
403 info.enable_mask = 1ull<<5 /* l2dsecen */;
404 info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
405 info.group = CVMX_ERROR_GROUP_INTERNAL;
406 info.group_index = 0;
407 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
408 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
409 info.parent.status_mask = 1ull<<16 /* l2c */;
410 info.func = __cvmx_error_display;
411 info.user_info = (long)
412 "ERROR L2C_INT_STAT[L2DSEC]: L2D Single Error corrected (SEC)\n"
413 " NOTE: This is the 'same' bit as L2D_ERR[SEC_ERR]\n";
414 fail |= cvmx_error_add(&info);
416 info.reg_type = CVMX_ERROR_REGISTER_IO64;
417 info.status_addr = CVMX_L2C_INT_STAT;
418 info.status_mask = 1ull<<0 /* oob1 */;
419 info.enable_addr = CVMX_L2C_INT_EN;
420 info.enable_mask = 1ull<<0 /* oob1en */;
422 info.group = CVMX_ERROR_GROUP_INTERNAL;
423 info.group_index = 0;
424 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
425 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
426 info.parent.status_mask = 1ull<<16 /* l2c */;
427 info.func = __cvmx_error_display;
428 info.user_info = (long)
429 "ERROR L2C_INT_STAT[OOB1]: DMA Out of Bounds Interrupt Status Range#1\n";
430 fail |= cvmx_error_add(&info);
432 info.reg_type = CVMX_ERROR_REGISTER_IO64;
433 info.status_addr = CVMX_L2C_INT_STAT;
434 info.status_mask = 1ull<<1 /* oob2 */;
435 info.enable_addr = CVMX_L2C_INT_EN;
436 info.enable_mask = 1ull<<1 /* oob2en */;
438 info.group = CVMX_ERROR_GROUP_INTERNAL;
439 info.group_index = 0;
440 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
441 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
442 info.parent.status_mask = 1ull<<16 /* l2c */;
443 info.func = __cvmx_error_display;
444 info.user_info = (long)
445 "ERROR L2C_INT_STAT[OOB2]: DMA Out of Bounds Interrupt Status Range#2\n";
446 fail |= cvmx_error_add(&info);
448 info.reg_type = CVMX_ERROR_REGISTER_IO64;
449 info.status_addr = CVMX_L2C_INT_STAT;
450 info.status_mask = 1ull<<2 /* oob3 */;
451 info.enable_addr = CVMX_L2C_INT_EN;
452 info.enable_mask = 1ull<<2 /* oob3en */;
454 info.group = CVMX_ERROR_GROUP_INTERNAL;
455 info.group_index = 0;
456 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
457 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
458 info.parent.status_mask = 1ull<<16 /* l2c */;
459 info.func = __cvmx_error_display;
460 info.user_info = (long)
461 "ERROR L2C_INT_STAT[OOB3]: DMA Out of Bounds Interrupt Status Range#3\n";
462 fail |= cvmx_error_add(&info);
464 info.reg_type = CVMX_ERROR_REGISTER_IO64;
465 info.status_addr = CVMX_L2C_INT_STAT;
466 info.status_mask = 1ull<<4 /* l2tded */;
467 info.enable_addr = CVMX_L2C_INT_EN;
468 info.enable_mask = 1ull<<4 /* l2tdeden */;
470 info.group = CVMX_ERROR_GROUP_INTERNAL;
471 info.group_index = 0;
472 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
473 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
474 info.parent.status_mask = 1ull<<16 /* l2c */;
475 info.func = __cvmx_error_display;
476 info.user_info = (long)
477 "ERROR L2C_INT_STAT[L2TDED]: L2T Double Bit Error detected (DED)\n"
478 " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
479 " given index) are checked for double bit errors(DBEs).\n"
480 " This bit is set if ANY of the 8 sets contains a DBE.\n"
481 " DBEs also generated an interrupt(if enabled).\n"
482 " NOTE: This is the 'same' bit as L2T_ERR[DED_ERR]\n";
483 fail |= cvmx_error_add(&info);
485 info.reg_type = CVMX_ERROR_REGISTER_IO64;
486 info.status_addr = CVMX_L2C_INT_STAT;
487 info.status_mask = 1ull<<6 /* l2dded */;
488 info.enable_addr = CVMX_L2C_INT_EN;
489 info.enable_mask = 1ull<<6 /* l2ddeden */;
491 info.group = CVMX_ERROR_GROUP_INTERNAL;
492 info.group_index = 0;
493 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
494 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
495 info.parent.status_mask = 1ull<<16 /* l2c */;
496 info.func = __cvmx_error_display;
497 info.user_info = (long)
498 "ERROR L2C_INT_STAT[L2DDED]: L2D Double Error detected (DED)\n"
499 " NOTE: This is the 'same' bit as L2D_ERR[DED_ERR]\n";
500 fail |= cvmx_error_add(&info);
502 info.reg_type = CVMX_ERROR_REGISTER_IO64;
503 info.status_addr = CVMX_L2C_INT_STAT;
504 info.status_mask = 1ull<<7 /* lck */;
505 info.enable_addr = CVMX_L2C_INT_EN;
506 info.enable_mask = 1ull<<7 /* lckena */;
508 info.group = CVMX_ERROR_GROUP_INTERNAL;
509 info.group_index = 0;
510 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
511 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
512 info.parent.status_mask = 1ull<<16 /* l2c */;
513 info.func = __cvmx_error_display;
514 info.user_info = (long)
515 "ERROR L2C_INT_STAT[LCK]: SW attempted to LOCK DOWN the last available set of\n"
516 " the INDEX (which is ignored by HW - but reported to SW).\n"
517 " The LDD(L1 load-miss) for the LOCK operation is completed\n"
518 " successfully, however the address is NOT locked.\n"
519 " NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
520 " into account. For example, if diagnostic PPx has\n"
521 " UMSKx defined to only use SETs [1:0], and SET1 had\n"
522 " been previously LOCKED, then an attempt to LOCK the\n"
523 " last available SET0 would result in a LCKERR. (This\n"
524 " is to ensure that at least 1 SET at each INDEX is\n"
525 " not LOCKED for general use by other PPs).\n"
526 " NOTE: This is the 'same' bit as L2T_ERR[LCKERR]\n";
527 fail |= cvmx_error_add(&info);
529 info.reg_type = CVMX_ERROR_REGISTER_IO64;
530 info.status_addr = CVMX_L2C_INT_STAT;
531 info.status_mask = 1ull<<8 /* lck2 */;
532 info.enable_addr = CVMX_L2C_INT_EN;
533 info.enable_mask = 1ull<<8 /* lck2ena */;
535 info.group = CVMX_ERROR_GROUP_INTERNAL;
536 info.group_index = 0;
537 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
538 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
539 info.parent.status_mask = 1ull<<16 /* l2c */;
540 info.func = __cvmx_error_display;
541 info.user_info = (long)
542 "ERROR L2C_INT_STAT[LCK2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
543 " could not find an available/unlocked set (for\n"
545 " Most likely, this is a result of SW mixing SET\n"
546 " PARTITIONING with ADDRESS LOCKING. If SW allows\n"
547 " another PP to LOCKDOWN all SETs available to PP#n,\n"
548 " then a Rd/Wr Miss from PP#n will be unable\n"
549 " to determine a 'valid' replacement set (since LOCKED\n"
550 " addresses should NEVER be replaced).\n"
551 " If such an event occurs, the HW will select the smallest\n"
552 " available SET(specified by UMSK'x)' as the replacement\n"
553 " set, and the address is unlocked.\n"
554 " NOTE: This is the 'same' bit as L2T_ERR[LCKERR2]\n";
555 fail |= cvmx_error_add(&info);
558 info.reg_type = CVMX_ERROR_REGISTER_IO64;
559 info.status_addr = CVMX_L2D_ERR;
560 info.status_mask = 1ull<<3 /* sec_err */;
561 info.enable_addr = CVMX_L2D_ERR;
562 info.enable_mask = 1ull<<1 /* sec_intena */;
563 info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
564 info.group = CVMX_ERROR_GROUP_INTERNAL;
565 info.group_index = 0;
566 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
567 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
568 info.parent.status_mask = 1ull<<16 /* l2c */;
569 info.func = __cvmx_error_handle_l2d_err_sec_err;
570 info.user_info = (long)
571 "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
572 fail |= cvmx_error_add(&info);
574 info.reg_type = CVMX_ERROR_REGISTER_IO64;
575 info.status_addr = CVMX_L2D_ERR;
576 info.status_mask = 1ull<<4 /* ded_err */;
577 info.enable_addr = CVMX_L2D_ERR;
578 info.enable_mask = 1ull<<2 /* ded_intena */;
580 info.group = CVMX_ERROR_GROUP_INTERNAL;
581 info.group_index = 0;
582 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
583 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
584 info.parent.status_mask = 1ull<<16 /* l2c */;
585 info.func = __cvmx_error_handle_l2d_err_ded_err;
586 info.user_info = (long)
587 "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
588 fail |= cvmx_error_add(&info);
591 info.reg_type = CVMX_ERROR_REGISTER_IO64;
592 info.status_addr = CVMX_L2T_ERR;
593 info.status_mask = 1ull<<3 /* sec_err */;
594 info.enable_addr = CVMX_L2T_ERR;
595 info.enable_mask = 1ull<<1 /* sec_intena */;
596 info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
597 info.group = CVMX_ERROR_GROUP_INTERNAL;
598 info.group_index = 0;
599 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
600 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
601 info.parent.status_mask = 1ull<<16 /* l2c */;
602 info.func = __cvmx_error_handle_l2t_err_sec_err;
603 info.user_info = (long)
604 "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
605 " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
606 " given index) are checked for single bit errors(SBEs).\n"
607 " This bit is set if ANY of the 8 sets contains an SBE.\n"
608 " SBEs are auto corrected in HW and generate an\n"
609 " interrupt(if enabled).\n";
610 fail |= cvmx_error_add(&info);
612 info.reg_type = CVMX_ERROR_REGISTER_IO64;
613 info.status_addr = CVMX_L2T_ERR;
614 info.status_mask = 1ull<<4 /* ded_err */;
615 info.enable_addr = CVMX_L2T_ERR;
616 info.enable_mask = 1ull<<2 /* ded_intena */;
618 info.group = CVMX_ERROR_GROUP_INTERNAL;
619 info.group_index = 0;
620 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
621 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
622 info.parent.status_mask = 1ull<<16 /* l2c */;
623 info.func = __cvmx_error_handle_l2t_err_ded_err;
624 info.user_info = (long)
625 "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
626 " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
627 " given index) are checked for double bit errors(DBEs).\n"
628 " This bit is set if ANY of the 8 sets contains a DBE.\n"
629 " DBEs also generated an interrupt(if enabled).\n";
630 fail |= cvmx_error_add(&info);
632 info.reg_type = CVMX_ERROR_REGISTER_IO64;
633 info.status_addr = CVMX_L2T_ERR;
634 info.status_mask = 1ull<<24 /* lckerr */;
635 info.enable_addr = CVMX_L2T_ERR;
636 info.enable_mask = 1ull<<25 /* lck_intena */;
638 info.group = CVMX_ERROR_GROUP_INTERNAL;
639 info.group_index = 0;
640 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
641 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
642 info.parent.status_mask = 1ull<<16 /* l2c */;
643 info.func = __cvmx_error_handle_l2t_err_lckerr;
644 info.user_info = (long)
645 "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
646 " the INDEX (which is ignored by HW - but reported to SW).\n"
647 " The LDD(L1 load-miss) for the LOCK operation is completed\n"
648 " successfully, however the address is NOT locked.\n"
649 " NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
650 " into account. For example, if diagnostic PPx has\n"
651 " UMSKx defined to only use SETs [1:0], and SET1 had\n"
652 " been previously LOCKED, then an attempt to LOCK the\n"
653 " last available SET0 would result in a LCKERR. (This\n"
654 " is to ensure that at least 1 SET at each INDEX is\n"
655 " not LOCKED for general use by other PPs).\n";
656 fail |= cvmx_error_add(&info);
658 info.reg_type = CVMX_ERROR_REGISTER_IO64;
659 info.status_addr = CVMX_L2T_ERR;
660 info.status_mask = 1ull<<26 /* lckerr2 */;
661 info.enable_addr = CVMX_L2T_ERR;
662 info.enable_mask = 1ull<<27 /* lck_intena2 */;
664 info.group = CVMX_ERROR_GROUP_INTERNAL;
665 info.group_index = 0;
666 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
667 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
668 info.parent.status_mask = 1ull<<16 /* l2c */;
669 info.func = __cvmx_error_handle_l2t_err_lckerr2;
670 info.user_info = (long)
671 "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
672 " could not find an available/unlocked set (for\n"
674 " Most likely, this is a result of SW mixing SET\n"
675 " PARTITIONING with ADDRESS LOCKING. If SW allows\n"
676 " another PP to LOCKDOWN all SETs available to PP#n,\n"
677 " then a Rd/Wr Miss from PP#n will be unable\n"
678 " to determine a 'valid' replacement set (since LOCKED\n"
679 " addresses should NEVER be replaced).\n"
680 " If such an event occurs, the HW will select the smallest\n"
681 " available SET(specified by UMSK'x)' as the replacement\n"
682 " set, and the address is unlocked.\n";
683 fail |= cvmx_error_add(&info);
685 /* CVMX_AGL_GMX_BAD_REG */
686 info.reg_type = CVMX_ERROR_REGISTER_IO64;
687 info.status_addr = CVMX_AGL_GMX_BAD_REG;
688 info.status_mask = 1ull<<32 /* ovrflw */;
689 info.enable_addr = 0;
690 info.enable_mask = 0;
692 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
693 info.group_index = 0;
694 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
695 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
696 info.parent.status_mask = 1ull<<28 /* agl */;
697 info.func = __cvmx_error_display;
698 info.user_info = (long)
699 "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow\n";
700 fail |= cvmx_error_add(&info);
702 info.reg_type = CVMX_ERROR_REGISTER_IO64;
703 info.status_addr = CVMX_AGL_GMX_BAD_REG;
704 info.status_mask = 1ull<<33 /* txpop */;
705 info.enable_addr = 0;
706 info.enable_mask = 0;
708 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
709 info.group_index = 0;
710 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
711 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
712 info.parent.status_mask = 1ull<<28 /* agl */;
713 info.func = __cvmx_error_display;
714 info.user_info = (long)
715 "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow\n";
716 fail |= cvmx_error_add(&info);
718 info.reg_type = CVMX_ERROR_REGISTER_IO64;
719 info.status_addr = CVMX_AGL_GMX_BAD_REG;
720 info.status_mask = 1ull<<34 /* txpsh */;
721 info.enable_addr = 0;
722 info.enable_mask = 0;
724 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
725 info.group_index = 0;
726 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
727 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
728 info.parent.status_mask = 1ull<<28 /* agl */;
729 info.func = __cvmx_error_display;
730 info.user_info = (long)
731 "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow\n";
732 fail |= cvmx_error_add(&info);
734 info.reg_type = CVMX_ERROR_REGISTER_IO64;
735 info.status_addr = CVMX_AGL_GMX_BAD_REG;
736 info.status_mask = 1ull<<2 /* out_ovr */;
737 info.enable_addr = 0;
738 info.enable_mask = 0;
740 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
741 info.group_index = 0;
742 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
743 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
744 info.parent.status_mask = 1ull<<28 /* agl */;
745 info.func = __cvmx_error_display;
746 info.user_info = (long)
747 "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n";
748 fail |= cvmx_error_add(&info);
750 info.reg_type = CVMX_ERROR_REGISTER_IO64;
751 info.status_addr = CVMX_AGL_GMX_BAD_REG;
752 info.status_mask = 1ull<<22 /* loststat */;
753 info.enable_addr = 0;
754 info.enable_mask = 0;
756 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
757 info.group_index = 0;
758 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
759 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
760 info.parent.status_mask = 1ull<<28 /* agl */;
761 info.func = __cvmx_error_display;
762 info.user_info = (long)
763 "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n"
764 " TX Stats are corrupted\n";
765 fail |= cvmx_error_add(&info);
767 /* CVMX_AGL_GMX_RXX_INT_REG(0) */
768 info.reg_type = CVMX_ERROR_REGISTER_IO64;
769 info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0);
770 info.status_mask = 1ull<<8 /* skperr */;
771 info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0);
772 info.enable_mask = 1ull<<8 /* skperr */;
774 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
775 info.group_index = 0;
776 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
777 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
778 info.parent.status_mask = 1ull<<28 /* agl */;
779 info.func = __cvmx_error_display;
780 info.user_info = (long)
781 "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n";
782 fail |= cvmx_error_add(&info);
784 info.reg_type = CVMX_ERROR_REGISTER_IO64;
785 info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0);
786 info.status_mask = 1ull<<10 /* ovrerr */;
787 info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0);
788 info.enable_mask = 1ull<<10 /* ovrerr */;
790 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
791 info.group_index = 0;
792 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
793 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
794 info.parent.status_mask = 1ull<<28 /* agl */;
795 info.func = __cvmx_error_display;
796 info.user_info = (long)
797 "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n"
798 " This interrupt should never assert\n";
799 fail |= cvmx_error_add(&info);
801 /* CVMX_AGL_GMX_TX_INT_REG */
802 info.reg_type = CVMX_ERROR_REGISTER_IO64;
803 info.status_addr = CVMX_AGL_GMX_TX_INT_REG;
804 info.status_mask = 1ull<<0 /* pko_nxa */;
805 info.enable_addr = CVMX_AGL_GMX_TX_INT_EN;
806 info.enable_mask = 1ull<<0 /* pko_nxa */;
808 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
809 info.group_index = 0;
810 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
811 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
812 info.parent.status_mask = 1ull<<28 /* agl */;
813 info.func = __cvmx_error_display;
814 info.user_info = (long)
815 "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n";
816 fail |= cvmx_error_add(&info);
818 info.reg_type = CVMX_ERROR_REGISTER_IO64;
819 info.status_addr = CVMX_AGL_GMX_TX_INT_REG;
820 info.status_mask = 1ull<<2 /* undflw */;
821 info.enable_addr = CVMX_AGL_GMX_TX_INT_EN;
822 info.enable_mask = 1ull<<2 /* undflw */;
824 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
825 info.group_index = 0;
826 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
827 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
828 info.parent.status_mask = 1ull<<28 /* agl */;
829 info.func = __cvmx_error_display;
830 info.user_info = (long)
831 "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow (MII mode only)\n";
832 fail |= cvmx_error_add(&info);
834 /* CVMX_GMXX_BAD_REG(0) */
835 info.reg_type = CVMX_ERROR_REGISTER_IO64;
836 info.status_addr = CVMX_GMXX_BAD_REG(0);
837 info.status_mask = 0xfull<<2 /* out_ovr */;
838 info.enable_addr = 0;
839 info.enable_mask = 0;
841 info.group = CVMX_ERROR_GROUP_ETHERNET;
842 info.group_index = 0;
843 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
844 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
845 info.parent.status_mask = 1ull<<1 /* gmx0 */;
846 info.func = __cvmx_error_display;
847 info.user_info = (long)
848 "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
849 fail |= cvmx_error_add(&info);
851 info.reg_type = CVMX_ERROR_REGISTER_IO64;
852 info.status_addr = CVMX_GMXX_BAD_REG(0);
853 info.status_mask = 0xfull<<22 /* loststat */;
854 info.enable_addr = 0;
855 info.enable_mask = 0;
857 info.group = CVMX_ERROR_GROUP_ETHERNET;
858 info.group_index = 0;
859 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
860 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
861 info.parent.status_mask = 1ull<<1 /* gmx0 */;
862 info.func = __cvmx_error_display;
863 info.user_info = (long)
864 "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written\n"
865 " In SGMII, one bit per port\n"
866 " In XAUI, only port0 is used\n"
867 " TX Stats are corrupted\n";
868 fail |= cvmx_error_add(&info);
870 info.reg_type = CVMX_ERROR_REGISTER_IO64;
871 info.status_addr = CVMX_GMXX_BAD_REG(0);
872 info.status_mask = 1ull<<26 /* statovr */;
873 info.enable_addr = 0;
874 info.enable_mask = 0;
876 info.group = CVMX_ERROR_GROUP_ETHERNET;
877 info.group_index = 0;
878 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
879 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
880 info.parent.status_mask = 1ull<<1 /* gmx0 */;
881 info.func = __cvmx_error_display;
882 info.user_info = (long)
883 "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n"
884 " The common FIFO to SGMII and XAUI had an overflow\n"
885 " TX Stats are corrupted\n";
886 fail |= cvmx_error_add(&info);
888 info.reg_type = CVMX_ERROR_REGISTER_IO64;
889 info.status_addr = CVMX_GMXX_BAD_REG(0);
890 info.status_mask = 0xfull<<27 /* inb_nxa */;
891 info.enable_addr = 0;
892 info.enable_mask = 0;
894 info.group = CVMX_ERROR_GROUP_ETHERNET;
895 info.group_index = 0;
896 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
897 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
898 info.parent.status_mask = 1ull<<1 /* gmx0 */;
899 info.func = __cvmx_error_display;
900 info.user_info = (long)
901 "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
902 fail |= cvmx_error_add(&info);
904 /* CVMX_GMXX_RXX_INT_REG(0,0) */
905 info.reg_type = CVMX_ERROR_REGISTER_IO64;
906 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
907 info.status_mask = 1ull<<1 /* carext */;
908 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
909 info.enable_mask = 1ull<<1 /* carext */;
911 info.group = CVMX_ERROR_GROUP_ETHERNET;
912 info.group_index = 0;
913 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
914 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
915 info.parent.status_mask = 1ull<<1 /* gmx0 */;
916 info.func = __cvmx_error_display;
917 info.user_info = (long)
918 "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n"
919 " (SGMII/1000Base-X only)\n";
920 fail |= cvmx_error_add(&info);
922 info.reg_type = CVMX_ERROR_REGISTER_IO64;
923 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
924 info.status_mask = 1ull<<8 /* skperr */;
925 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
926 info.enable_mask = 1ull<<8 /* skperr */;
928 info.group = CVMX_ERROR_GROUP_ETHERNET;
929 info.group_index = 0;
930 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
931 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
932 info.parent.status_mask = 1ull<<1 /* gmx0 */;
933 info.func = __cvmx_error_display;
934 info.user_info = (long)
935 "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
936 fail |= cvmx_error_add(&info);
938 info.reg_type = CVMX_ERROR_REGISTER_IO64;
939 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
940 info.status_mask = 1ull<<10 /* ovrerr */;
941 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
942 info.enable_mask = 1ull<<10 /* ovrerr */;
944 info.group = CVMX_ERROR_GROUP_ETHERNET;
945 info.group_index = 0;
946 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
947 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
948 info.parent.status_mask = 1ull<<1 /* gmx0 */;
949 info.func = __cvmx_error_display;
950 info.user_info = (long)
951 "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
952 " This interrupt should never assert\n"
953 " (SGMII/1000Base-X only)\n";
954 fail |= cvmx_error_add(&info);
956 info.reg_type = CVMX_ERROR_REGISTER_IO64;
957 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
958 info.status_mask = 1ull<<20 /* loc_fault */;
959 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
960 info.enable_mask = 1ull<<20 /* loc_fault */;
962 info.group = CVMX_ERROR_GROUP_ETHERNET;
963 info.group_index = 0;
964 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
965 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
966 info.parent.status_mask = 1ull<<1 /* gmx0 */;
967 info.func = __cvmx_error_display;
968 info.user_info = (long)
969 "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
970 " (XAUI Mode only)\n";
971 fail |= cvmx_error_add(&info);
973 info.reg_type = CVMX_ERROR_REGISTER_IO64;
974 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
975 info.status_mask = 1ull<<21 /* rem_fault */;
976 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
977 info.enable_mask = 1ull<<21 /* rem_fault */;
979 info.group = CVMX_ERROR_GROUP_ETHERNET;
980 info.group_index = 0;
981 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
982 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
983 info.parent.status_mask = 1ull<<1 /* gmx0 */;
984 info.func = __cvmx_error_display;
985 info.user_info = (long)
986 "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
987 " (XAUI Mode only)\n";
988 fail |= cvmx_error_add(&info);
990 info.reg_type = CVMX_ERROR_REGISTER_IO64;
991 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
992 info.status_mask = 1ull<<22 /* bad_seq */;
993 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
994 info.enable_mask = 1ull<<22 /* bad_seq */;
996 info.group = CVMX_ERROR_GROUP_ETHERNET;
997 info.group_index = 0;
998 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
999 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1000 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1001 info.func = __cvmx_error_display;
1002 info.user_info = (long)
1003 "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
1004 " (XAUI Mode only)\n";
1005 fail |= cvmx_error_add(&info);
1007 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1008 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
1009 info.status_mask = 1ull<<23 /* bad_term */;
1010 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
1011 info.enable_mask = 1ull<<23 /* bad_term */;
1013 info.group = CVMX_ERROR_GROUP_ETHERNET;
1014 info.group_index = 0;
1015 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1016 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1017 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1018 info.func = __cvmx_error_display;
1019 info.user_info = (long)
1020 "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n"
1021 " than /T/. The error propagation control\n"
1022 " character /E/ will be included as part of the\n"
1023 " frame and does not cause a frame termination.\n"
1024 " (XAUI Mode only)\n";
1025 fail |= cvmx_error_add(&info);
1027 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1028 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
1029 info.status_mask = 1ull<<24 /* unsop */;
1030 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
1031 info.enable_mask = 1ull<<24 /* unsop */;
1033 info.group = CVMX_ERROR_GROUP_ETHERNET;
1034 info.group_index = 0;
1035 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1036 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1037 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1038 info.func = __cvmx_error_display;
1039 info.user_info = (long)
1040 "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n"
1041 " (XAUI Mode only)\n";
1042 fail |= cvmx_error_add(&info);
1044 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1045 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
1046 info.status_mask = 1ull<<25 /* uneop */;
1047 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
1048 info.enable_mask = 1ull<<25 /* uneop */;
1050 info.group = CVMX_ERROR_GROUP_ETHERNET;
1051 info.group_index = 0;
1052 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1053 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1054 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1055 info.func = __cvmx_error_display;
1056 info.user_info = (long)
1057 "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n"
1058 " (XAUI Mode only)\n";
1059 fail |= cvmx_error_add(&info);
1061 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1062 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
1063 info.status_mask = 1ull<<26 /* undat */;
1064 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
1065 info.enable_mask = 1ull<<26 /* undat */;
1067 info.group = CVMX_ERROR_GROUP_ETHERNET;
1068 info.group_index = 0;
1069 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1070 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1071 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1072 info.func = __cvmx_error_display;
1073 info.user_info = (long)
1074 "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n"
1075 " (XAUI Mode only)\n";
1076 fail |= cvmx_error_add(&info);
1078 /* CVMX_GMXX_RXX_INT_REG(1,0) */
1079 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1080 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
1081 info.status_mask = 1ull<<1 /* carext */;
1082 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
1083 info.enable_mask = 1ull<<1 /* carext */;
1085 info.group = CVMX_ERROR_GROUP_ETHERNET;
1086 info.group_index = 1;
1087 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1088 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1089 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1090 info.func = __cvmx_error_display;
1091 info.user_info = (long)
1092 "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n"
1093 " (SGMII/1000Base-X only)\n";
1094 fail |= cvmx_error_add(&info);
1096 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1097 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
1098 info.status_mask = 1ull<<8 /* skperr */;
1099 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
1100 info.enable_mask = 1ull<<8 /* skperr */;
1102 info.group = CVMX_ERROR_GROUP_ETHERNET;
1103 info.group_index = 1;
1104 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1105 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1106 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1107 info.func = __cvmx_error_display;
1108 info.user_info = (long)
1109 "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
1110 fail |= cvmx_error_add(&info);
1112 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1113 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
1114 info.status_mask = 1ull<<10 /* ovrerr */;
1115 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
1116 info.enable_mask = 1ull<<10 /* ovrerr */;
1118 info.group = CVMX_ERROR_GROUP_ETHERNET;
1119 info.group_index = 1;
1120 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1121 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1122 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1123 info.func = __cvmx_error_display;
1124 info.user_info = (long)
1125 "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
1126 " This interrupt should never assert\n"
1127 " (SGMII/1000Base-X only)\n";
1128 fail |= cvmx_error_add(&info);
1130 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1131 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
1132 info.status_mask = 1ull<<20 /* loc_fault */;
1133 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
1134 info.enable_mask = 1ull<<20 /* loc_fault */;
1136 info.group = CVMX_ERROR_GROUP_ETHERNET;
1137 info.group_index = 1;
1138 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1139 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1140 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1141 info.func = __cvmx_error_display;
1142 info.user_info = (long)
1143 "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
1144 " (XAUI Mode only)\n";
1145 fail |= cvmx_error_add(&info);
1147 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1148 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
1149 info.status_mask = 1ull<<21 /* rem_fault */;
1150 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
1151 info.enable_mask = 1ull<<21 /* rem_fault */;
1153 info.group = CVMX_ERROR_GROUP_ETHERNET;
1154 info.group_index = 1;
1155 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1156 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1157 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1158 info.func = __cvmx_error_display;
1159 info.user_info = (long)
1160 "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
1161 " (XAUI Mode only)\n";
1162 fail |= cvmx_error_add(&info);
1164 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1165 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
1166 info.status_mask = 1ull<<22 /* bad_seq */;
1167 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
1168 info.enable_mask = 1ull<<22 /* bad_seq */;
1170 info.group = CVMX_ERROR_GROUP_ETHERNET;
1171 info.group_index = 1;
1172 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1173 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1174 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1175 info.func = __cvmx_error_display;
1176 info.user_info = (long)
1177 "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
1178 " (XAUI Mode only)\n";
1179 fail |= cvmx_error_add(&info);
1181 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1182 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
1183 info.status_mask = 1ull<<23 /* bad_term */;
1184 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
1185 info.enable_mask = 1ull<<23 /* bad_term */;
1187 info.group = CVMX_ERROR_GROUP_ETHERNET;
1188 info.group_index = 1;
1189 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1190 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1191 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1192 info.func = __cvmx_error_display;
1193 info.user_info = (long)
1194 "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n"
1195 " than /T/. The error propagation control\n"
1196 " character /E/ will be included as part of the\n"
1197 " frame and does not cause a frame termination.\n"
1198 " (XAUI Mode only)\n";
1199 fail |= cvmx_error_add(&info);
1201 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1202 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
1203 info.status_mask = 1ull<<24 /* unsop */;
1204 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
1205 info.enable_mask = 1ull<<24 /* unsop */;
1207 info.group = CVMX_ERROR_GROUP_ETHERNET;
1208 info.group_index = 1;
1209 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1210 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1211 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1212 info.func = __cvmx_error_display;
1213 info.user_info = (long)
1214 "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n"
1215 " (XAUI Mode only)\n";
1216 fail |= cvmx_error_add(&info);
1218 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1219 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
1220 info.status_mask = 1ull<<25 /* uneop */;
1221 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
1222 info.enable_mask = 1ull<<25 /* uneop */;
1224 info.group = CVMX_ERROR_GROUP_ETHERNET;
1225 info.group_index = 1;
1226 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1227 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1228 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1229 info.func = __cvmx_error_display;
1230 info.user_info = (long)
1231 "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n"
1232 " (XAUI Mode only)\n";
1233 fail |= cvmx_error_add(&info);
1235 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1236 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
1237 info.status_mask = 1ull<<26 /* undat */;
1238 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
1239 info.enable_mask = 1ull<<26 /* undat */;
1241 info.group = CVMX_ERROR_GROUP_ETHERNET;
1242 info.group_index = 1;
1243 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1244 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1245 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1246 info.func = __cvmx_error_display;
1247 info.user_info = (long)
1248 "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n"
1249 " (XAUI Mode only)\n";
1250 fail |= cvmx_error_add(&info);
1252 /* CVMX_GMXX_RXX_INT_REG(2,0) */
1253 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1254 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
1255 info.status_mask = 1ull<<1 /* carext */;
1256 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
1257 info.enable_mask = 1ull<<1 /* carext */;
1259 info.group = CVMX_ERROR_GROUP_ETHERNET;
1260 info.group_index = 2;
1261 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1262 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1263 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1264 info.func = __cvmx_error_display;
1265 info.user_info = (long)
1266 "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n"
1267 " (SGMII/1000Base-X only)\n";
1268 fail |= cvmx_error_add(&info);
1270 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1271 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
1272 info.status_mask = 1ull<<8 /* skperr */;
1273 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
1274 info.enable_mask = 1ull<<8 /* skperr */;
1276 info.group = CVMX_ERROR_GROUP_ETHERNET;
1277 info.group_index = 2;
1278 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1279 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1280 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1281 info.func = __cvmx_error_display;
1282 info.user_info = (long)
1283 "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
1284 fail |= cvmx_error_add(&info);
1286 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1287 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
1288 info.status_mask = 1ull<<10 /* ovrerr */;
1289 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
1290 info.enable_mask = 1ull<<10 /* ovrerr */;
1292 info.group = CVMX_ERROR_GROUP_ETHERNET;
1293 info.group_index = 2;
1294 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1295 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1296 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1297 info.func = __cvmx_error_display;
1298 info.user_info = (long)
1299 "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
1300 " This interrupt should never assert\n"
1301 " (SGMII/1000Base-X only)\n";
1302 fail |= cvmx_error_add(&info);
1304 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1305 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
1306 info.status_mask = 1ull<<20 /* loc_fault */;
1307 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
1308 info.enable_mask = 1ull<<20 /* loc_fault */;
1310 info.group = CVMX_ERROR_GROUP_ETHERNET;
1311 info.group_index = 2;
1312 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1313 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1314 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1315 info.func = __cvmx_error_display;
1316 info.user_info = (long)
1317 "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
1318 " (XAUI Mode only)\n";
1319 fail |= cvmx_error_add(&info);
1321 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1322 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
1323 info.status_mask = 1ull<<21 /* rem_fault */;
1324 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
1325 info.enable_mask = 1ull<<21 /* rem_fault */;
1327 info.group = CVMX_ERROR_GROUP_ETHERNET;
1328 info.group_index = 2;
1329 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1330 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1331 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1332 info.func = __cvmx_error_display;
1333 info.user_info = (long)
1334 "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
1335 " (XAUI Mode only)\n";
1336 fail |= cvmx_error_add(&info);
1338 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1339 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
1340 info.status_mask = 1ull<<22 /* bad_seq */;
1341 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
1342 info.enable_mask = 1ull<<22 /* bad_seq */;
1344 info.group = CVMX_ERROR_GROUP_ETHERNET;
1345 info.group_index = 2;
1346 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1347 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1348 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1349 info.func = __cvmx_error_display;
1350 info.user_info = (long)
1351 "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
1352 " (XAUI Mode only)\n";
1353 fail |= cvmx_error_add(&info);
1355 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1356 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
1357 info.status_mask = 1ull<<23 /* bad_term */;
1358 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
1359 info.enable_mask = 1ull<<23 /* bad_term */;
1361 info.group = CVMX_ERROR_GROUP_ETHERNET;
1362 info.group_index = 2;
1363 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1364 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1365 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1366 info.func = __cvmx_error_display;
1367 info.user_info = (long)
1368 "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n"
1369 " than /T/. The error propagation control\n"
1370 " character /E/ will be included as part of the\n"
1371 " frame and does not cause a frame termination.\n"
1372 " (XAUI Mode only)\n";
1373 fail |= cvmx_error_add(&info);
1375 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1376 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
1377 info.status_mask = 1ull<<24 /* unsop */;
1378 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
1379 info.enable_mask = 1ull<<24 /* unsop */;
1381 info.group = CVMX_ERROR_GROUP_ETHERNET;
1382 info.group_index = 2;
1383 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1384 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1385 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1386 info.func = __cvmx_error_display;
1387 info.user_info = (long)
1388 "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n"
1389 " (XAUI Mode only)\n";
1390 fail |= cvmx_error_add(&info);
1392 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1393 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
1394 info.status_mask = 1ull<<25 /* uneop */;
1395 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
1396 info.enable_mask = 1ull<<25 /* uneop */;
1398 info.group = CVMX_ERROR_GROUP_ETHERNET;
1399 info.group_index = 2;
1400 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1401 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1402 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1403 info.func = __cvmx_error_display;
1404 info.user_info = (long)
1405 "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n"
1406 " (XAUI Mode only)\n";
1407 fail |= cvmx_error_add(&info);
1409 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1410 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
1411 info.status_mask = 1ull<<26 /* undat */;
1412 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
1413 info.enable_mask = 1ull<<26 /* undat */;
1415 info.group = CVMX_ERROR_GROUP_ETHERNET;
1416 info.group_index = 2;
1417 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1418 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1419 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1420 info.func = __cvmx_error_display;
1421 info.user_info = (long)
1422 "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n"
1423 " (XAUI Mode only)\n";
1424 fail |= cvmx_error_add(&info);
1426 /* CVMX_GMXX_RXX_INT_REG(3,0) */
1427 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1428 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
1429 info.status_mask = 1ull<<1 /* carext */;
1430 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
1431 info.enable_mask = 1ull<<1 /* carext */;
1433 info.group = CVMX_ERROR_GROUP_ETHERNET;
1434 info.group_index = 3;
1435 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1436 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1437 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1438 info.func = __cvmx_error_display;
1439 info.user_info = (long)
1440 "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n"
1441 " (SGMII/1000Base-X only)\n";
1442 fail |= cvmx_error_add(&info);
1444 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1445 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
1446 info.status_mask = 1ull<<8 /* skperr */;
1447 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
1448 info.enable_mask = 1ull<<8 /* skperr */;
1450 info.group = CVMX_ERROR_GROUP_ETHERNET;
1451 info.group_index = 3;
1452 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1453 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1454 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1455 info.func = __cvmx_error_display;
1456 info.user_info = (long)
1457 "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
1458 fail |= cvmx_error_add(&info);
1460 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1461 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
1462 info.status_mask = 1ull<<10 /* ovrerr */;
1463 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
1464 info.enable_mask = 1ull<<10 /* ovrerr */;
1466 info.group = CVMX_ERROR_GROUP_ETHERNET;
1467 info.group_index = 3;
1468 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1469 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1470 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1471 info.func = __cvmx_error_display;
1472 info.user_info = (long)
1473 "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
1474 " This interrupt should never assert\n"
1475 " (SGMII/1000Base-X only)\n";
1476 fail |= cvmx_error_add(&info);
1478 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1479 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
1480 info.status_mask = 1ull<<20 /* loc_fault */;
1481 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
1482 info.enable_mask = 1ull<<20 /* loc_fault */;
1484 info.group = CVMX_ERROR_GROUP_ETHERNET;
1485 info.group_index = 3;
1486 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1487 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1488 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1489 info.func = __cvmx_error_display;
1490 info.user_info = (long)
1491 "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
1492 " (XAUI Mode only)\n";
1493 fail |= cvmx_error_add(&info);
1495 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1496 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
1497 info.status_mask = 1ull<<21 /* rem_fault */;
1498 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
1499 info.enable_mask = 1ull<<21 /* rem_fault */;
1501 info.group = CVMX_ERROR_GROUP_ETHERNET;
1502 info.group_index = 3;
1503 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1504 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1505 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1506 info.func = __cvmx_error_display;
1507 info.user_info = (long)
1508 "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
1509 " (XAUI Mode only)\n";
1510 fail |= cvmx_error_add(&info);
1512 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1513 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
1514 info.status_mask = 1ull<<22 /* bad_seq */;
1515 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
1516 info.enable_mask = 1ull<<22 /* bad_seq */;
1518 info.group = CVMX_ERROR_GROUP_ETHERNET;
1519 info.group_index = 3;
1520 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1521 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1522 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1523 info.func = __cvmx_error_display;
1524 info.user_info = (long)
1525 "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
1526 " (XAUI Mode only)\n";
1527 fail |= cvmx_error_add(&info);
1529 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1530 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
1531 info.status_mask = 1ull<<23 /* bad_term */;
1532 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
1533 info.enable_mask = 1ull<<23 /* bad_term */;
1535 info.group = CVMX_ERROR_GROUP_ETHERNET;
1536 info.group_index = 3;
1537 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1538 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1539 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1540 info.func = __cvmx_error_display;
1541 info.user_info = (long)
1542 "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n"
1543 " than /T/. The error propagation control\n"
1544 " character /E/ will be included as part of the\n"
1545 " frame and does not cause a frame termination.\n"
1546 " (XAUI Mode only)\n";
1547 fail |= cvmx_error_add(&info);
1549 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1550 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
1551 info.status_mask = 1ull<<24 /* unsop */;
1552 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
1553 info.enable_mask = 1ull<<24 /* unsop */;
1555 info.group = CVMX_ERROR_GROUP_ETHERNET;
1556 info.group_index = 3;
1557 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1558 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1559 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1560 info.func = __cvmx_error_display;
1561 info.user_info = (long)
1562 "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n"
1563 " (XAUI Mode only)\n";
1564 fail |= cvmx_error_add(&info);
1566 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1567 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
1568 info.status_mask = 1ull<<25 /* uneop */;
1569 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
1570 info.enable_mask = 1ull<<25 /* uneop */;
1572 info.group = CVMX_ERROR_GROUP_ETHERNET;
1573 info.group_index = 3;
1574 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1575 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1576 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1577 info.func = __cvmx_error_display;
1578 info.user_info = (long)
1579 "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n"
1580 " (XAUI Mode only)\n";
1581 fail |= cvmx_error_add(&info);
1583 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1584 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
1585 info.status_mask = 1ull<<26 /* undat */;
1586 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
1587 info.enable_mask = 1ull<<26 /* undat */;
1589 info.group = CVMX_ERROR_GROUP_ETHERNET;
1590 info.group_index = 3;
1591 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1592 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1593 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1594 info.func = __cvmx_error_display;
1595 info.user_info = (long)
1596 "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n"
1597 " (XAUI Mode only)\n";
1598 fail |= cvmx_error_add(&info);
1600 /* CVMX_GMXX_TX_INT_REG(0) */
1601 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1602 info.status_addr = CVMX_GMXX_TX_INT_REG(0);
1603 info.status_mask = 1ull<<0 /* pko_nxa */;
1604 info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
1605 info.enable_mask = 1ull<<0 /* pko_nxa */;
1607 info.group = CVMX_ERROR_GROUP_ETHERNET;
1608 info.group_index = 0;
1609 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1610 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1611 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1612 info.func = __cvmx_error_display;
1613 info.user_info = (long)
1614 "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
1615 fail |= cvmx_error_add(&info);
1617 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1618 info.status_addr = CVMX_GMXX_TX_INT_REG(0);
1619 info.status_mask = 0xfull<<2 /* undflw */;
1620 info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
1621 info.enable_mask = 0xfull<<2 /* undflw */;
1623 info.group = CVMX_ERROR_GROUP_ETHERNET;
1624 info.group_index = 0;
1625 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1626 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1627 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1628 info.func = __cvmx_error_display;
1629 info.user_info = (long)
1630 "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n";
1631 fail |= cvmx_error_add(&info);
1633 /* CVMX_GMXX_BAD_REG(1) */
1634 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1635 info.status_addr = CVMX_GMXX_BAD_REG(1);
1636 info.status_mask = 0xfull<<2 /* out_ovr */;
1637 info.enable_addr = 0;
1638 info.enable_mask = 0;
1640 info.group = CVMX_ERROR_GROUP_ETHERNET;
1641 info.group_index = 16;
1642 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1643 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1644 info.parent.status_mask = 1ull<<2 /* gmx1 */;
1645 info.func = __cvmx_error_display;
1646 info.user_info = (long)
1647 "ERROR GMXX_BAD_REG(1)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
1648 fail |= cvmx_error_add(&info);
1650 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1651 info.status_addr = CVMX_GMXX_BAD_REG(1);
1652 info.status_mask = 0xfull<<22 /* loststat */;
1653 info.enable_addr = 0;
1654 info.enable_mask = 0;
1656 info.group = CVMX_ERROR_GROUP_ETHERNET;
1657 info.group_index = 16;
1658 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1659 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1660 info.parent.status_mask = 1ull<<2 /* gmx1 */;
1661 info.func = __cvmx_error_display;
1662 info.user_info = (long)
1663 "ERROR GMXX_BAD_REG(1)[LOSTSTAT]: TX Statistics data was over-written\n"
1664 " In SGMII, one bit per port\n"
1665 " In XAUI, only port0 is used\n"
1666 " TX Stats are corrupted\n";
1667 fail |= cvmx_error_add(&info);
1669 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1670 info.status_addr = CVMX_GMXX_BAD_REG(1);
1671 info.status_mask = 1ull<<26 /* statovr */;
1672 info.enable_addr = 0;
1673 info.enable_mask = 0;
1675 info.group = CVMX_ERROR_GROUP_ETHERNET;
1676 info.group_index = 16;
1677 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1678 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1679 info.parent.status_mask = 1ull<<2 /* gmx1 */;
1680 info.func = __cvmx_error_display;
1681 info.user_info = (long)
1682 "ERROR GMXX_BAD_REG(1)[STATOVR]: TX Statistics overflow\n"
1683 " The common FIFO to SGMII and XAUI had an overflow\n"
1684 " TX Stats are corrupted\n";
1685 fail |= cvmx_error_add(&info);
1687 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1688 info.status_addr = CVMX_GMXX_BAD_REG(1);
1689 info.status_mask = 0xfull<<27 /* inb_nxa */;
1690 info.enable_addr = 0;
1691 info.enable_mask = 0;
1693 info.group = CVMX_ERROR_GROUP_ETHERNET;
1694 info.group_index = 16;
1695 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1696 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1697 info.parent.status_mask = 1ull<<2 /* gmx1 */;
1698 info.func = __cvmx_error_display;
1699 info.user_info = (long)
1700 "ERROR GMXX_BAD_REG(1)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
1701 fail |= cvmx_error_add(&info);
1703 /* CVMX_GMXX_RXX_INT_REG(0,1) */
1704 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1705 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
1706 info.status_mask = 1ull<<1 /* carext */;
1707 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
1708 info.enable_mask = 1ull<<1 /* carext */;
1710 info.group = CVMX_ERROR_GROUP_ETHERNET;
1711 info.group_index = 16;
1712 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1713 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1714 info.parent.status_mask = 1ull<<2 /* gmx1 */;
1715 info.func = __cvmx_error_display;
1716 info.user_info = (long)
1717 "ERROR GMXX_RXX_INT_REG(0,1)[CAREXT]: Carrier extend error\n"
1718 " (SGMII/1000Base-X only)\n";
1719 fail |= cvmx_error_add(&info);
1721 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1722 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
1723 info.status_mask = 1ull<<8 /* skperr */;
1724 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
1725 info.enable_mask = 1ull<<8 /* skperr */;
1727 info.group = CVMX_ERROR_GROUP_ETHERNET;
1728 info.group_index = 16;
1729 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1730 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1731 info.parent.status_mask = 1ull<<2 /* gmx1 */;
1732 info.func = __cvmx_error_display;
1733 info.user_info = (long)
1734 "ERROR GMXX_RXX_INT_REG(0,1)[SKPERR]: Skipper error\n";
1735 fail |= cvmx_error_add(&info);
1737 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1738 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
1739 info.status_mask = 1ull<<10 /* ovrerr */;
1740 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
1741 info.enable_mask = 1ull<<10 /* ovrerr */;
1743 info.group = CVMX_ERROR_GROUP_ETHERNET;
1744 info.group_index = 16;
1745 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1746 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1747 info.parent.status_mask = 1ull<<2 /* gmx1 */;
1748 info.func = __cvmx_error_display;
1749 info.user_info = (long)
1750 "ERROR GMXX_RXX_INT_REG(0,1)[OVRERR]: Internal Data Aggregation Overflow\n"
1751 " This interrupt should never assert\n"
1752 " (SGMII/1000Base-X only)\n";
1753 fail |= cvmx_error_add(&info);
1755 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1756 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
1757 info.status_mask = 1ull<<20 /* loc_fault */;
1758 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
1759 info.enable_mask = 1ull<<20 /* loc_fault */;
1761 info.group = CVMX_ERROR_GROUP_ETHERNET;
1762 info.group_index = 16;
1763 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1764 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1765 info.parent.status_mask = 1ull<<2 /* gmx1 */;
1766 info.func = __cvmx_error_display;
1767 info.user_info = (long)
1768 "ERROR GMXX_RXX_INT_REG(0,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
1769 " (XAUI Mode only)\n";
1770 fail |= cvmx_error_add(&info);
1772 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1773 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
1774 info.status_mask = 1ull<<21 /* rem_fault */;
1775 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
1776 info.enable_mask = 1ull<<21 /* rem_fault */;
1778 info.group = CVMX_ERROR_GROUP_ETHERNET;
1779 info.group_index = 16;
1780 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1781 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1782 info.parent.status_mask = 1ull<<2 /* gmx1 */;
1783 info.func = __cvmx_error_display;
1784 info.user_info = (long)
1785 "ERROR GMXX_RXX_INT_REG(0,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
1786 " (XAUI Mode only)\n";
1787 fail |= cvmx_error_add(&info);
1789 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1790 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
1791 info.status_mask = 1ull<<22 /* bad_seq */;
1792 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
1793 info.enable_mask = 1ull<<22 /* bad_seq */;
1795 info.group = CVMX_ERROR_GROUP_ETHERNET;
1796 info.group_index = 16;
1797 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1798 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1799 info.parent.status_mask = 1ull<<2 /* gmx1 */;
1800 info.func = __cvmx_error_display;
1801 info.user_info = (long)
1802 "ERROR GMXX_RXX_INT_REG(0,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
1803 " (XAUI Mode only)\n";
1804 fail |= cvmx_error_add(&info);
1806 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1807 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
1808 info.status_mask = 1ull<<23 /* bad_term */;
1809 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
1810 info.enable_mask = 1ull<<23 /* bad_term */;
1812 info.group = CVMX_ERROR_GROUP_ETHERNET;
1813 info.group_index = 16;
1814 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1815 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1816 info.parent.status_mask = 1ull<<2 /* gmx1 */;
1817 info.func = __cvmx_error_display;
1818 info.user_info = (long)
1819 "ERROR GMXX_RXX_INT_REG(0,1)[BAD_TERM]: Frame is terminated by control character other\n"
1820 " than /T/. The error propagation control\n"
1821 " character /E/ will be included as part of the\n"
1822 " frame and does not cause a frame termination.\n"
1823 " (XAUI Mode only)\n";
1824 fail |= cvmx_error_add(&info);
1826 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1827 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
1828 info.status_mask = 1ull<<24 /* unsop */;
1829 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
1830 info.enable_mask = 1ull<<24 /* unsop */;
1832 info.group = CVMX_ERROR_GROUP_ETHERNET;
1833 info.group_index = 16;
1834 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1835 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1836 info.parent.status_mask = 1ull<<2 /* gmx1 */;
1837 info.func = __cvmx_error_display;
1838 info.user_info = (long)
1839 "ERROR GMXX_RXX_INT_REG(0,1)[UNSOP]: Unexpected SOP\n"
1840 " (XAUI Mode only)\n";
1841 fail |= cvmx_error_add(&info);
1843 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1844 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
1845 info.status_mask = 1ull<<25 /* uneop */;
1846 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
1847 info.enable_mask = 1ull<<25 /* uneop */;
1849 info.group = CVMX_ERROR_GROUP_ETHERNET;
1850 info.group_index = 16;
1851 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1852 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1853 info.parent.status_mask = 1ull<<2 /* gmx1 */;
1854 info.func = __cvmx_error_display;
1855 info.user_info = (long)
1856 "ERROR GMXX_RXX_INT_REG(0,1)[UNEOP]: Unexpected EOP\n"
1857 " (XAUI Mode only)\n";
1858 fail |= cvmx_error_add(&info);
1860 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1861 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
1862 info.status_mask = 1ull<<26 /* undat */;
1863 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
1864 info.enable_mask = 1ull<<26 /* undat */;
1866 info.group = CVMX_ERROR_GROUP_ETHERNET;
1867 info.group_index = 16;
1868 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1869 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1870 info.parent.status_mask = 1ull<<2 /* gmx1 */;
1871 info.func = __cvmx_error_display;
1872 info.user_info = (long)
1873 "ERROR GMXX_RXX_INT_REG(0,1)[UNDAT]: Unexpected Data\n"
1874 " (XAUI Mode only)\n";
1875 fail |= cvmx_error_add(&info);
1877 /* CVMX_GMXX_RXX_INT_REG(1,1) */
1878 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1879 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
1880 info.status_mask = 1ull<<1 /* carext */;
1881 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
1882 info.enable_mask = 1ull<<1 /* carext */;
1884 info.group = CVMX_ERROR_GROUP_ETHERNET;
1885 info.group_index = 17;
1886 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1887 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1888 info.parent.status_mask = 1ull<<2 /* gmx1 */;
1889 info.func = __cvmx_error_display;
1890 info.user_info = (long)
1891 "ERROR GMXX_RXX_INT_REG(1,1)[CAREXT]: Carrier extend error\n"
1892 " (SGMII/1000Base-X only)\n";
1893 fail |= cvmx_error_add(&info);
1895 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1896 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
1897 info.status_mask = 1ull<<8 /* skperr */;
1898 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
1899 info.enable_mask = 1ull<<8 /* skperr */;
1901 info.group = CVMX_ERROR_GROUP_ETHERNET;
1902 info.group_index = 17;
1903 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1904 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1905 info.parent.status_mask = 1ull<<2 /* gmx1 */;
1906 info.func = __cvmx_error_display;
1907 info.user_info = (long)
1908 "ERROR GMXX_RXX_INT_REG(1,1)[SKPERR]: Skipper error\n";
1909 fail |= cvmx_error_add(&info);
1911 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1912 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
1913 info.status_mask = 1ull<<10 /* ovrerr */;
1914 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
1915 info.enable_mask = 1ull<<10 /* ovrerr */;
1917 info.group = CVMX_ERROR_GROUP_ETHERNET;
1918 info.group_index = 17;
1919 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1920 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1921 info.parent.status_mask = 1ull<<2 /* gmx1 */;
1922 info.func = __cvmx_error_display;
1923 info.user_info = (long)
1924 "ERROR GMXX_RXX_INT_REG(1,1)[OVRERR]: Internal Data Aggregation Overflow\n"
1925 " This interrupt should never assert\n"
1926 " (SGMII/1000Base-X only)\n";
1927 fail |= cvmx_error_add(&info);
1929 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1930 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
1931 info.status_mask = 1ull<<20 /* loc_fault */;
1932 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
1933 info.enable_mask = 1ull<<20 /* loc_fault */;
1935 info.group = CVMX_ERROR_GROUP_ETHERNET;
1936 info.group_index = 17;
1937 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1938 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1939 info.parent.status_mask = 1ull<<2 /* gmx1 */;
1940 info.func = __cvmx_error_display;
1941 info.user_info = (long)
1942 "ERROR GMXX_RXX_INT_REG(1,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
1943 " (XAUI Mode only)\n";
1944 fail |= cvmx_error_add(&info);
1946 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1947 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
1948 info.status_mask = 1ull<<21 /* rem_fault */;
1949 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
1950 info.enable_mask = 1ull<<21 /* rem_fault */;
1952 info.group = CVMX_ERROR_GROUP_ETHERNET;
1953 info.group_index = 17;
1954 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1955 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1956 info.parent.status_mask = 1ull<<2 /* gmx1 */;
1957 info.func = __cvmx_error_display;
1958 info.user_info = (long)
1959 "ERROR GMXX_RXX_INT_REG(1,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
1960 " (XAUI Mode only)\n";
1961 fail |= cvmx_error_add(&info);
1963 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1964 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
1965 info.status_mask = 1ull<<22 /* bad_seq */;
1966 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
1967 info.enable_mask = 1ull<<22 /* bad_seq */;
1969 info.group = CVMX_ERROR_GROUP_ETHERNET;
1970 info.group_index = 17;
1971 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1972 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1973 info.parent.status_mask = 1ull<<2 /* gmx1 */;
1974 info.func = __cvmx_error_display;
1975 info.user_info = (long)
1976 "ERROR GMXX_RXX_INT_REG(1,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
1977 " (XAUI Mode only)\n";
1978 fail |= cvmx_error_add(&info);
1980 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1981 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
1982 info.status_mask = 1ull<<23 /* bad_term */;
1983 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
1984 info.enable_mask = 1ull<<23 /* bad_term */;
1986 info.group = CVMX_ERROR_GROUP_ETHERNET;
1987 info.group_index = 17;
1988 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1989 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1990 info.parent.status_mask = 1ull<<2 /* gmx1 */;
1991 info.func = __cvmx_error_display;
1992 info.user_info = (long)
1993 "ERROR GMXX_RXX_INT_REG(1,1)[BAD_TERM]: Frame is terminated by control character other\n"
1994 " than /T/. The error propagation control\n"
1995 " character /E/ will be included as part of the\n"
1996 " frame and does not cause a frame termination.\n"
1997 " (XAUI Mode only)\n";
1998 fail |= cvmx_error_add(&info);
2000 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2001 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
2002 info.status_mask = 1ull<<24 /* unsop */;
2003 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
2004 info.enable_mask = 1ull<<24 /* unsop */;
2006 info.group = CVMX_ERROR_GROUP_ETHERNET;
2007 info.group_index = 17;
2008 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2009 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2010 info.parent.status_mask = 1ull<<2 /* gmx1 */;
2011 info.func = __cvmx_error_display;
2012 info.user_info = (long)
2013 "ERROR GMXX_RXX_INT_REG(1,1)[UNSOP]: Unexpected SOP\n"
2014 " (XAUI Mode only)\n";
2015 fail |= cvmx_error_add(&info);
2017 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2018 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
2019 info.status_mask = 1ull<<25 /* uneop */;
2020 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
2021 info.enable_mask = 1ull<<25 /* uneop */;
2023 info.group = CVMX_ERROR_GROUP_ETHERNET;
2024 info.group_index = 17;
2025 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2026 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2027 info.parent.status_mask = 1ull<<2 /* gmx1 */;
2028 info.func = __cvmx_error_display;
2029 info.user_info = (long)
2030 "ERROR GMXX_RXX_INT_REG(1,1)[UNEOP]: Unexpected EOP\n"
2031 " (XAUI Mode only)\n";
2032 fail |= cvmx_error_add(&info);
2034 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2035 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
2036 info.status_mask = 1ull<<26 /* undat */;
2037 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
2038 info.enable_mask = 1ull<<26 /* undat */;
2040 info.group = CVMX_ERROR_GROUP_ETHERNET;
2041 info.group_index = 17;
2042 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2043 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2044 info.parent.status_mask = 1ull<<2 /* gmx1 */;
2045 info.func = __cvmx_error_display;
2046 info.user_info = (long)
2047 "ERROR GMXX_RXX_INT_REG(1,1)[UNDAT]: Unexpected Data\n"
2048 " (XAUI Mode only)\n";
2049 fail |= cvmx_error_add(&info);
2051 /* CVMX_GMXX_RXX_INT_REG(2,1) */
2052 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2053 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
2054 info.status_mask = 1ull<<1 /* carext */;
2055 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
2056 info.enable_mask = 1ull<<1 /* carext */;
2058 info.group = CVMX_ERROR_GROUP_ETHERNET;
2059 info.group_index = 18;
2060 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2061 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2062 info.parent.status_mask = 1ull<<2 /* gmx1 */;
2063 info.func = __cvmx_error_display;
2064 info.user_info = (long)
2065 "ERROR GMXX_RXX_INT_REG(2,1)[CAREXT]: Carrier extend error\n"
2066 " (SGMII/1000Base-X only)\n";
2067 fail |= cvmx_error_add(&info);
2069 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2070 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
2071 info.status_mask = 1ull<<8 /* skperr */;
2072 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
2073 info.enable_mask = 1ull<<8 /* skperr */;
2075 info.group = CVMX_ERROR_GROUP_ETHERNET;
2076 info.group_index = 18;
2077 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2078 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2079 info.parent.status_mask = 1ull<<2 /* gmx1 */;
2080 info.func = __cvmx_error_display;
2081 info.user_info = (long)
2082 "ERROR GMXX_RXX_INT_REG(2,1)[SKPERR]: Skipper error\n";
2083 fail |= cvmx_error_add(&info);
2085 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2086 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
2087 info.status_mask = 1ull<<10 /* ovrerr */;
2088 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
2089 info.enable_mask = 1ull<<10 /* ovrerr */;
2091 info.group = CVMX_ERROR_GROUP_ETHERNET;
2092 info.group_index = 18;
2093 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2094 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2095 info.parent.status_mask = 1ull<<2 /* gmx1 */;
2096 info.func = __cvmx_error_display;
2097 info.user_info = (long)
2098 "ERROR GMXX_RXX_INT_REG(2,1)[OVRERR]: Internal Data Aggregation Overflow\n"
2099 " This interrupt should never assert\n"
2100 " (SGMII/1000Base-X only)\n";
2101 fail |= cvmx_error_add(&info);
2103 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2104 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
2105 info.status_mask = 1ull<<20 /* loc_fault */;
2106 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
2107 info.enable_mask = 1ull<<20 /* loc_fault */;
2109 info.group = CVMX_ERROR_GROUP_ETHERNET;
2110 info.group_index = 18;
2111 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2112 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2113 info.parent.status_mask = 1ull<<2 /* gmx1 */;
2114 info.func = __cvmx_error_display;
2115 info.user_info = (long)
2116 "ERROR GMXX_RXX_INT_REG(2,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
2117 " (XAUI Mode only)\n";
2118 fail |= cvmx_error_add(&info);
2120 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2121 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
2122 info.status_mask = 1ull<<21 /* rem_fault */;
2123 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
2124 info.enable_mask = 1ull<<21 /* rem_fault */;
2126 info.group = CVMX_ERROR_GROUP_ETHERNET;
2127 info.group_index = 18;
2128 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2129 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2130 info.parent.status_mask = 1ull<<2 /* gmx1 */;
2131 info.func = __cvmx_error_display;
2132 info.user_info = (long)
2133 "ERROR GMXX_RXX_INT_REG(2,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
2134 " (XAUI Mode only)\n";
2135 fail |= cvmx_error_add(&info);
2137 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2138 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
2139 info.status_mask = 1ull<<22 /* bad_seq */;
2140 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
2141 info.enable_mask = 1ull<<22 /* bad_seq */;
2143 info.group = CVMX_ERROR_GROUP_ETHERNET;
2144 info.group_index = 18;
2145 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2146 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2147 info.parent.status_mask = 1ull<<2 /* gmx1 */;
2148 info.func = __cvmx_error_display;
2149 info.user_info = (long)
2150 "ERROR GMXX_RXX_INT_REG(2,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
2151 " (XAUI Mode only)\n";
2152 fail |= cvmx_error_add(&info);
2154 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2155 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
2156 info.status_mask = 1ull<<23 /* bad_term */;
2157 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
2158 info.enable_mask = 1ull<<23 /* bad_term */;
2160 info.group = CVMX_ERROR_GROUP_ETHERNET;
2161 info.group_index = 18;
2162 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2163 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2164 info.parent.status_mask = 1ull<<2 /* gmx1 */;
2165 info.func = __cvmx_error_display;
2166 info.user_info = (long)
2167 "ERROR GMXX_RXX_INT_REG(2,1)[BAD_TERM]: Frame is terminated by control character other\n"
2168 " than /T/. The error propagation control\n"
2169 " character /E/ will be included as part of the\n"
2170 " frame and does not cause a frame termination.\n"
2171 " (XAUI Mode only)\n";
2172 fail |= cvmx_error_add(&info);
2174 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2175 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
2176 info.status_mask = 1ull<<24 /* unsop */;
2177 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
2178 info.enable_mask = 1ull<<24 /* unsop */;
2180 info.group = CVMX_ERROR_GROUP_ETHERNET;
2181 info.group_index = 18;
2182 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2183 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2184 info.parent.status_mask = 1ull<<2 /* gmx1 */;
2185 info.func = __cvmx_error_display;
2186 info.user_info = (long)
2187 "ERROR GMXX_RXX_INT_REG(2,1)[UNSOP]: Unexpected SOP\n"
2188 " (XAUI Mode only)\n";
2189 fail |= cvmx_error_add(&info);
2191 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2192 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
2193 info.status_mask = 1ull<<25 /* uneop */;
2194 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
2195 info.enable_mask = 1ull<<25 /* uneop */;
2197 info.group = CVMX_ERROR_GROUP_ETHERNET;
2198 info.group_index = 18;
2199 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2200 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2201 info.parent.status_mask = 1ull<<2 /* gmx1 */;
2202 info.func = __cvmx_error_display;
2203 info.user_info = (long)
2204 "ERROR GMXX_RXX_INT_REG(2,1)[UNEOP]: Unexpected EOP\n"
2205 " (XAUI Mode only)\n";
2206 fail |= cvmx_error_add(&info);
2208 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2209 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
2210 info.status_mask = 1ull<<26 /* undat */;
2211 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
2212 info.enable_mask = 1ull<<26 /* undat */;
2214 info.group = CVMX_ERROR_GROUP_ETHERNET;
2215 info.group_index = 18;
2216 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2217 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2218 info.parent.status_mask = 1ull<<2 /* gmx1 */;
2219 info.func = __cvmx_error_display;
2220 info.user_info = (long)
2221 "ERROR GMXX_RXX_INT_REG(2,1)[UNDAT]: Unexpected Data\n"
2222 " (XAUI Mode only)\n";
2223 fail |= cvmx_error_add(&info);
2225 /* CVMX_GMXX_RXX_INT_REG(3,1) */
2226 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2227 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
2228 info.status_mask = 1ull<<1 /* carext */;
2229 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
2230 info.enable_mask = 1ull<<1 /* carext */;
2232 info.group = CVMX_ERROR_GROUP_ETHERNET;
2233 info.group_index = 19;
2234 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2235 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2236 info.parent.status_mask = 1ull<<2 /* gmx1 */;
2237 info.func = __cvmx_error_display;
2238 info.user_info = (long)
2239 "ERROR GMXX_RXX_INT_REG(3,1)[CAREXT]: Carrier extend error\n"
2240 " (SGMII/1000Base-X only)\n";
2241 fail |= cvmx_error_add(&info);
2243 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2244 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
2245 info.status_mask = 1ull<<8 /* skperr */;
2246 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
2247 info.enable_mask = 1ull<<8 /* skperr */;
2249 info.group = CVMX_ERROR_GROUP_ETHERNET;
2250 info.group_index = 19;
2251 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2252 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2253 info.parent.status_mask = 1ull<<2 /* gmx1 */;
2254 info.func = __cvmx_error_display;
2255 info.user_info = (long)
2256 "ERROR GMXX_RXX_INT_REG(3,1)[SKPERR]: Skipper error\n";
2257 fail |= cvmx_error_add(&info);
2259 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2260 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
2261 info.status_mask = 1ull<<10 /* ovrerr */;
2262 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
2263 info.enable_mask = 1ull<<10 /* ovrerr */;
2265 info.group = CVMX_ERROR_GROUP_ETHERNET;
2266 info.group_index = 19;
2267 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2268 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2269 info.parent.status_mask = 1ull<<2 /* gmx1 */;
2270 info.func = __cvmx_error_display;
2271 info.user_info = (long)
2272 "ERROR GMXX_RXX_INT_REG(3,1)[OVRERR]: Internal Data Aggregation Overflow\n"
2273 " This interrupt should never assert\n"
2274 " (SGMII/1000Base-X only)\n";
2275 fail |= cvmx_error_add(&info);
2277 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2278 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
2279 info.status_mask = 1ull<<20 /* loc_fault */;
2280 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
2281 info.enable_mask = 1ull<<20 /* loc_fault */;
2283 info.group = CVMX_ERROR_GROUP_ETHERNET;
2284 info.group_index = 19;
2285 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2286 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2287 info.parent.status_mask = 1ull<<2 /* gmx1 */;
2288 info.func = __cvmx_error_display;
2289 info.user_info = (long)
2290 "ERROR GMXX_RXX_INT_REG(3,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
2291 " (XAUI Mode only)\n";
2292 fail |= cvmx_error_add(&info);
2294 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2295 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
2296 info.status_mask = 1ull<<21 /* rem_fault */;
2297 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
2298 info.enable_mask = 1ull<<21 /* rem_fault */;
2300 info.group = CVMX_ERROR_GROUP_ETHERNET;
2301 info.group_index = 19;
2302 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2303 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2304 info.parent.status_mask = 1ull<<2 /* gmx1 */;
2305 info.func = __cvmx_error_display;
2306 info.user_info = (long)
2307 "ERROR GMXX_RXX_INT_REG(3,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
2308 " (XAUI Mode only)\n";
2309 fail |= cvmx_error_add(&info);
2311 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2312 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
2313 info.status_mask = 1ull<<22 /* bad_seq */;
2314 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
2315 info.enable_mask = 1ull<<22 /* bad_seq */;
2317 info.group = CVMX_ERROR_GROUP_ETHERNET;
2318 info.group_index = 19;
2319 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2320 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2321 info.parent.status_mask = 1ull<<2 /* gmx1 */;
2322 info.func = __cvmx_error_display;
2323 info.user_info = (long)
2324 "ERROR GMXX_RXX_INT_REG(3,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
2325 " (XAUI Mode only)\n";
2326 fail |= cvmx_error_add(&info);
2328 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2329 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
2330 info.status_mask = 1ull<<23 /* bad_term */;
2331 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
2332 info.enable_mask = 1ull<<23 /* bad_term */;
2334 info.group = CVMX_ERROR_GROUP_ETHERNET;
2335 info.group_index = 19;
2336 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2337 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2338 info.parent.status_mask = 1ull<<2 /* gmx1 */;
2339 info.func = __cvmx_error_display;
2340 info.user_info = (long)
2341 "ERROR GMXX_RXX_INT_REG(3,1)[BAD_TERM]: Frame is terminated by control character other\n"
2342 " than /T/. The error propagation control\n"
2343 " character /E/ will be included as part of the\n"
2344 " frame and does not cause a frame termination.\n"
2345 " (XAUI Mode only)\n";
2346 fail |= cvmx_error_add(&info);
2348 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2349 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
2350 info.status_mask = 1ull<<24 /* unsop */;
2351 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
2352 info.enable_mask = 1ull<<24 /* unsop */;
2354 info.group = CVMX_ERROR_GROUP_ETHERNET;
2355 info.group_index = 19;
2356 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2357 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2358 info.parent.status_mask = 1ull<<2 /* gmx1 */;
2359 info.func = __cvmx_error_display;
2360 info.user_info = (long)
2361 "ERROR GMXX_RXX_INT_REG(3,1)[UNSOP]: Unexpected SOP\n"
2362 " (XAUI Mode only)\n";
2363 fail |= cvmx_error_add(&info);
2365 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2366 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
2367 info.status_mask = 1ull<<25 /* uneop */;
2368 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
2369 info.enable_mask = 1ull<<25 /* uneop */;
2371 info.group = CVMX_ERROR_GROUP_ETHERNET;
2372 info.group_index = 19;
2373 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2374 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2375 info.parent.status_mask = 1ull<<2 /* gmx1 */;
2376 info.func = __cvmx_error_display;
2377 info.user_info = (long)
2378 "ERROR GMXX_RXX_INT_REG(3,1)[UNEOP]: Unexpected EOP\n"
2379 " (XAUI Mode only)\n";
2380 fail |= cvmx_error_add(&info);
2382 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2383 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
2384 info.status_mask = 1ull<<26 /* undat */;
2385 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
2386 info.enable_mask = 1ull<<26 /* undat */;
2388 info.group = CVMX_ERROR_GROUP_ETHERNET;
2389 info.group_index = 19;
2390 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2391 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2392 info.parent.status_mask = 1ull<<2 /* gmx1 */;
2393 info.func = __cvmx_error_display;
2394 info.user_info = (long)
2395 "ERROR GMXX_RXX_INT_REG(3,1)[UNDAT]: Unexpected Data\n"
2396 " (XAUI Mode only)\n";
2397 fail |= cvmx_error_add(&info);
2399 /* CVMX_GMXX_TX_INT_REG(1) */
2400 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2401 info.status_addr = CVMX_GMXX_TX_INT_REG(1);
2402 info.status_mask = 1ull<<0 /* pko_nxa */;
2403 info.enable_addr = CVMX_GMXX_TX_INT_EN(1);
2404 info.enable_mask = 1ull<<0 /* pko_nxa */;
2406 info.group = CVMX_ERROR_GROUP_ETHERNET;
2407 info.group_index = 16;
2408 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2409 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2410 info.parent.status_mask = 1ull<<2 /* gmx1 */;
2411 info.func = __cvmx_error_display;
2412 info.user_info = (long)
2413 "ERROR GMXX_TX_INT_REG(1)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
2414 fail |= cvmx_error_add(&info);
2416 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2417 info.status_addr = CVMX_GMXX_TX_INT_REG(1);
2418 info.status_mask = 0xfull<<2 /* undflw */;
2419 info.enable_addr = CVMX_GMXX_TX_INT_EN(1);
2420 info.enable_mask = 0xfull<<2 /* undflw */;
2422 info.group = CVMX_ERROR_GROUP_ETHERNET;
2423 info.group_index = 16;
2424 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2425 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2426 info.parent.status_mask = 1ull<<2 /* gmx1 */;
2427 info.func = __cvmx_error_display;
2428 info.user_info = (long)
2429 "ERROR GMXX_TX_INT_REG(1)[UNDFLW]: TX Underflow\n";
2430 fail |= cvmx_error_add(&info);
2432 /* CVMX_IPD_INT_SUM */
2433 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2434 info.status_addr = CVMX_IPD_INT_SUM;
2435 info.status_mask = 1ull<<0 /* prc_par0 */;
2436 info.enable_addr = CVMX_IPD_INT_ENB;
2437 info.enable_mask = 1ull<<0 /* prc_par0 */;
2439 info.group = CVMX_ERROR_GROUP_INTERNAL;
2440 info.group_index = 0;
2441 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2442 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2443 info.parent.status_mask = 1ull<<9 /* ipd */;
2444 info.func = __cvmx_error_display;
2445 info.user_info = (long)
2446 "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
2447 " [31:0] of the PBM memory.\n";
2448 fail |= cvmx_error_add(&info);
2450 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2451 info.status_addr = CVMX_IPD_INT_SUM;
2452 info.status_mask = 1ull<<1 /* prc_par1 */;
2453 info.enable_addr = CVMX_IPD_INT_ENB;
2454 info.enable_mask = 1ull<<1 /* prc_par1 */;
2456 info.group = CVMX_ERROR_GROUP_INTERNAL;
2457 info.group_index = 0;
2458 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2459 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2460 info.parent.status_mask = 1ull<<9 /* ipd */;
2461 info.func = __cvmx_error_display;
2462 info.user_info = (long)
2463 "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
2464 " [63:32] of the PBM memory.\n";
2465 fail |= cvmx_error_add(&info);
2467 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2468 info.status_addr = CVMX_IPD_INT_SUM;
2469 info.status_mask = 1ull<<2 /* prc_par2 */;
2470 info.enable_addr = CVMX_IPD_INT_ENB;
2471 info.enable_mask = 1ull<<2 /* prc_par2 */;
2473 info.group = CVMX_ERROR_GROUP_INTERNAL;
2474 info.group_index = 0;
2475 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2476 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2477 info.parent.status_mask = 1ull<<9 /* ipd */;
2478 info.func = __cvmx_error_display;
2479 info.user_info = (long)
2480 "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
2481 " [95:64] of the PBM memory.\n";
2482 fail |= cvmx_error_add(&info);
2484 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2485 info.status_addr = CVMX_IPD_INT_SUM;
2486 info.status_mask = 1ull<<3 /* prc_par3 */;
2487 info.enable_addr = CVMX_IPD_INT_ENB;
2488 info.enable_mask = 1ull<<3 /* prc_par3 */;
2490 info.group = CVMX_ERROR_GROUP_INTERNAL;
2491 info.group_index = 0;
2492 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2493 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2494 info.parent.status_mask = 1ull<<9 /* ipd */;
2495 info.func = __cvmx_error_display;
2496 info.user_info = (long)
2497 "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
2498 " [127:96] of the PBM memory.\n";
2499 fail |= cvmx_error_add(&info);
2501 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2502 info.status_addr = CVMX_IPD_INT_SUM;
2503 info.status_mask = 1ull<<4 /* bp_sub */;
2504 info.enable_addr = CVMX_IPD_INT_ENB;
2505 info.enable_mask = 1ull<<4 /* bp_sub */;
2507 info.group = CVMX_ERROR_GROUP_INTERNAL;
2508 info.group_index = 0;
2509 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2510 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2511 info.parent.status_mask = 1ull<<9 /* ipd */;
2512 info.func = __cvmx_error_display;
2513 info.user_info = (long)
2514 "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
2515 " supplied illegal value.\n";
2516 fail |= cvmx_error_add(&info);
2518 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2519 info.status_addr = CVMX_IPD_INT_SUM;
2520 info.status_mask = 1ull<<5 /* dc_ovr */;
2521 info.enable_addr = CVMX_IPD_INT_ENB;
2522 info.enable_mask = 1ull<<5 /* dc_ovr */;
2524 info.group = CVMX_ERROR_GROUP_INTERNAL;
2525 info.group_index = 0;
2526 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2527 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2528 info.parent.status_mask = 1ull<<9 /* ipd */;
2529 info.func = __cvmx_error_display;
2530 info.user_info = (long)
2531 "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n";
2532 fail |= cvmx_error_add(&info);
2534 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2535 info.status_addr = CVMX_IPD_INT_SUM;
2536 info.status_mask = 1ull<<6 /* cc_ovr */;
2537 info.enable_addr = CVMX_IPD_INT_ENB;
2538 info.enable_mask = 1ull<<6 /* cc_ovr */;
2540 info.group = CVMX_ERROR_GROUP_INTERNAL;
2541 info.group_index = 0;
2542 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2543 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2544 info.parent.status_mask = 1ull<<9 /* ipd */;
2545 info.func = __cvmx_error_display;
2546 info.user_info = (long)
2547 "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n";
2548 fail |= cvmx_error_add(&info);
2550 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2551 info.status_addr = CVMX_IPD_INT_SUM;
2552 info.status_mask = 1ull<<7 /* c_coll */;
2553 info.enable_addr = CVMX_IPD_INT_ENB;
2554 info.enable_mask = 1ull<<7 /* c_coll */;
2556 info.group = CVMX_ERROR_GROUP_INTERNAL;
2557 info.group_index = 0;
2558 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2559 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2560 info.parent.status_mask = 1ull<<9 /* ipd */;
2561 info.func = __cvmx_error_display;
2562 info.user_info = (long)
2563 "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
2565 fail |= cvmx_error_add(&info);
2567 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2568 info.status_addr = CVMX_IPD_INT_SUM;
2569 info.status_mask = 1ull<<8 /* d_coll */;
2570 info.enable_addr = CVMX_IPD_INT_ENB;
2571 info.enable_mask = 1ull<<8 /* d_coll */;
2573 info.group = CVMX_ERROR_GROUP_INTERNAL;
2574 info.group_index = 0;
2575 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2576 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2577 info.parent.status_mask = 1ull<<9 /* ipd */;
2578 info.func = __cvmx_error_display;
2579 info.user_info = (long)
2580 "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
2582 fail |= cvmx_error_add(&info);
2584 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2585 info.status_addr = CVMX_IPD_INT_SUM;
2586 info.status_mask = 1ull<<9 /* bc_ovr */;
2587 info.enable_addr = CVMX_IPD_INT_ENB;
2588 info.enable_mask = 1ull<<9 /* bc_ovr */;
2590 info.group = CVMX_ERROR_GROUP_INTERNAL;
2591 info.group_index = 0;
2592 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2593 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2594 info.parent.status_mask = 1ull<<9 /* ipd */;
2595 info.func = __cvmx_error_display;
2596 info.user_info = (long)
2597 "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n";
2598 fail |= cvmx_error_add(&info);
2600 /* CVMX_TIM_REG_ERROR */
2601 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2602 info.status_addr = CVMX_TIM_REG_ERROR;
2603 info.status_mask = 0xffffull<<0 /* mask */;
2604 info.enable_addr = CVMX_TIM_REG_INT_MASK;
2605 info.enable_mask = 0xffffull<<0 /* mask */;
2607 info.group = CVMX_ERROR_GROUP_INTERNAL;
2608 info.group_index = 0;
2609 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2610 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2611 info.parent.status_mask = 1ull<<11 /* tim */;
2612 info.func = __cvmx_error_display;
2613 info.user_info = (long)
2614 "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
2615 fail |= cvmx_error_add(&info);
2617 /* CVMX_PKO_REG_ERROR */
2618 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2619 info.status_addr = CVMX_PKO_REG_ERROR;
2620 info.status_mask = 1ull<<0 /* parity */;
2621 info.enable_addr = CVMX_PKO_REG_INT_MASK;
2622 info.enable_mask = 1ull<<0 /* parity */;
2624 info.group = CVMX_ERROR_GROUP_INTERNAL;
2625 info.group_index = 0;
2626 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2627 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2628 info.parent.status_mask = 1ull<<10 /* pko */;
2629 info.func = __cvmx_error_display;
2630 info.user_info = (long)
2631 "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
2632 fail |= cvmx_error_add(&info);
2634 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2635 info.status_addr = CVMX_PKO_REG_ERROR;
2636 info.status_mask = 1ull<<1 /* doorbell */;
2637 info.enable_addr = CVMX_PKO_REG_INT_MASK;
2638 info.enable_mask = 1ull<<1 /* doorbell */;
2640 info.group = CVMX_ERROR_GROUP_INTERNAL;
2641 info.group_index = 0;
2642 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2643 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2644 info.parent.status_mask = 1ull<<10 /* pko */;
2645 info.func = __cvmx_error_display;
2646 info.user_info = (long)
2647 "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
2648 fail |= cvmx_error_add(&info);
2650 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2651 info.status_addr = CVMX_PKO_REG_ERROR;
2652 info.status_mask = 1ull<<2 /* currzero */;
2653 info.enable_addr = CVMX_PKO_REG_INT_MASK;
2654 info.enable_mask = 1ull<<2 /* currzero */;
2656 info.group = CVMX_ERROR_GROUP_INTERNAL;
2657 info.group_index = 0;
2658 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2659 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2660 info.parent.status_mask = 1ull<<10 /* pko */;
2661 info.func = __cvmx_error_display;
2662 info.user_info = (long)
2663 "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
2664 fail |= cvmx_error_add(&info);
2666 /* CVMX_POW_ECC_ERR */
2667 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2668 info.status_addr = CVMX_POW_ECC_ERR;
2669 info.status_mask = 1ull<<0 /* sbe */;
2670 info.enable_addr = CVMX_POW_ECC_ERR;
2671 info.enable_mask = 1ull<<2 /* sbe_ie */;
2672 info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
2673 info.group = CVMX_ERROR_GROUP_INTERNAL;
2674 info.group_index = 0;
2675 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2676 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2677 info.parent.status_mask = 1ull<<12 /* pow */;
2678 info.func = __cvmx_error_handle_pow_ecc_err_sbe;
2679 info.user_info = (long)
2680 "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
2681 fail |= cvmx_error_add(&info);
2683 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2684 info.status_addr = CVMX_POW_ECC_ERR;
2685 info.status_mask = 1ull<<1 /* dbe */;
2686 info.enable_addr = CVMX_POW_ECC_ERR;
2687 info.enable_mask = 1ull<<3 /* dbe_ie */;
2689 info.group = CVMX_ERROR_GROUP_INTERNAL;
2690 info.group_index = 0;
2691 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2692 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2693 info.parent.status_mask = 1ull<<12 /* pow */;
2694 info.func = __cvmx_error_handle_pow_ecc_err_dbe;
2695 info.user_info = (long)
2696 "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
2697 fail |= cvmx_error_add(&info);
2699 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2700 info.status_addr = CVMX_POW_ECC_ERR;
2701 info.status_mask = 1ull<<12 /* rpe */;
2702 info.enable_addr = CVMX_POW_ECC_ERR;
2703 info.enable_mask = 1ull<<13 /* rpe_ie */;
2705 info.group = CVMX_ERROR_GROUP_INTERNAL;
2706 info.group_index = 0;
2707 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2708 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2709 info.parent.status_mask = 1ull<<12 /* pow */;
2710 info.func = __cvmx_error_handle_pow_ecc_err_rpe;
2711 info.user_info = (long)
2712 "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
2713 fail |= cvmx_error_add(&info);
2715 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2716 info.status_addr = CVMX_POW_ECC_ERR;
2717 info.status_mask = 0x1fffull<<16 /* iop */;
2718 info.enable_addr = CVMX_POW_ECC_ERR;
2719 info.enable_mask = 0x1fffull<<32 /* iop_ie */;
2721 info.group = CVMX_ERROR_GROUP_INTERNAL;
2722 info.group_index = 0;
2723 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2724 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2725 info.parent.status_mask = 1ull<<12 /* pow */;
2726 info.func = __cvmx_error_handle_pow_ecc_err_iop;
2727 info.user_info = (long)
2728 "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
2729 fail |= cvmx_error_add(&info);
2731 /* CVMX_PEXP_NPEI_INT_SUM */
2732 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2733 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
2734 info.status_mask = 1ull<<59 /* c0_ldwn */;
2735 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
2736 info.enable_mask = 1ull<<59 /* c0_ldwn */;
2738 info.group = CVMX_ERROR_GROUP_PCI;
2739 info.group_index = 0;
2740 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2741 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2742 info.parent.status_mask = 1ull<<3 /* npei */;
2743 info.func = __cvmx_error_display;
2744 info.user_info = (long)
2745 "ERROR PEXP_NPEI_INT_SUM[C0_LDWN]: Reset request due to link0 down status.\n";
2746 fail |= cvmx_error_add(&info);
2748 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2749 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
2750 info.status_mask = 1ull<<21 /* c0_se */;
2751 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
2752 info.enable_mask = 1ull<<21 /* c0_se */;
2754 info.group = CVMX_ERROR_GROUP_PCI;
2755 info.group_index = 0;
2756 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2757 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2758 info.parent.status_mask = 1ull<<3 /* npei */;
2759 info.func = __cvmx_error_display;
2760 info.user_info = (long)
2761 "ERROR PEXP_NPEI_INT_SUM[C0_SE]: System Error, RC Mode Only.\n"
2762 " Pcie Core 0. (cfg_sys_err_rc)\n";
2763 fail |= cvmx_error_add(&info);
2765 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2766 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
2767 info.status_mask = 1ull<<38 /* c0_un_b0 */;
2768 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
2769 info.enable_mask = 1ull<<38 /* c0_un_b0 */;
2771 info.group = CVMX_ERROR_GROUP_PCI;
2772 info.group_index = 0;
2773 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2774 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2775 info.parent.status_mask = 1ull<<3 /* npei */;
2776 info.func = __cvmx_error_display;
2777 info.user_info = (long)
2778 "ERROR PEXP_NPEI_INT_SUM[C0_UN_B0]: Received Unsupported N-TLP for Bar0.\n"
2780 fail |= cvmx_error_add(&info);
2782 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2783 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
2784 info.status_mask = 1ull<<39 /* c0_un_b1 */;
2785 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
2786 info.enable_mask = 1ull<<39 /* c0_un_b1 */;
2788 info.group = CVMX_ERROR_GROUP_PCI;
2789 info.group_index = 0;
2790 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2791 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2792 info.parent.status_mask = 1ull<<3 /* npei */;
2793 info.func = __cvmx_error_display;
2794 info.user_info = (long)
2795 "ERROR PEXP_NPEI_INT_SUM[C0_UN_B1]: Received Unsupported N-TLP for Bar1.\n"
2797 fail |= cvmx_error_add(&info);
2799 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2800 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
2801 info.status_mask = 1ull<<40 /* c0_un_b2 */;
2802 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
2803 info.enable_mask = 1ull<<40 /* c0_un_b2 */;
2805 info.group = CVMX_ERROR_GROUP_PCI;
2806 info.group_index = 0;
2807 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2808 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2809 info.parent.status_mask = 1ull<<3 /* npei */;
2810 info.func = __cvmx_error_display;
2811 info.user_info = (long)
2812 "ERROR PEXP_NPEI_INT_SUM[C0_UN_B2]: Received Unsupported N-TLP for Bar2.\n"
2814 fail |= cvmx_error_add(&info);
2816 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2817 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
2818 info.status_mask = 1ull<<42 /* c0_un_bx */;
2819 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
2820 info.enable_mask = 1ull<<42 /* c0_un_bx */;
2822 info.group = CVMX_ERROR_GROUP_PCI;
2823 info.group_index = 0;
2824 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2825 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2826 info.parent.status_mask = 1ull<<3 /* npei */;
2827 info.func = __cvmx_error_display;
2828 info.user_info = (long)
2829 "ERROR PEXP_NPEI_INT_SUM[C0_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n"
2831 fail |= cvmx_error_add(&info);
2833 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2834 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
2835 info.status_mask = 1ull<<53 /* c0_un_wf */;
2836 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
2837 info.enable_mask = 1ull<<53 /* c0_un_wf */;
2839 info.group = CVMX_ERROR_GROUP_PCI;
2840 info.group_index = 0;
2841 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2842 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2843 info.parent.status_mask = 1ull<<3 /* npei */;
2844 info.func = __cvmx_error_display;
2845 info.user_info = (long)
2846 "ERROR PEXP_NPEI_INT_SUM[C0_UN_WF]: Received Unsupported N-TLP for filtered window\n"
2847 " register. Core0.\n";
2848 fail |= cvmx_error_add(&info);
2850 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2851 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
2852 info.status_mask = 1ull<<41 /* c0_un_wi */;
2853 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
2854 info.enable_mask = 1ull<<41 /* c0_un_wi */;
2856 info.group = CVMX_ERROR_GROUP_PCI;
2857 info.group_index = 0;
2858 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2859 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2860 info.parent.status_mask = 1ull<<3 /* npei */;
2861 info.func = __cvmx_error_display;
2862 info.user_info = (long)
2863 "ERROR PEXP_NPEI_INT_SUM[C0_UN_WI]: Received Unsupported N-TLP for Window Register.\n"
2865 fail |= cvmx_error_add(&info);
2867 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2868 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
2869 info.status_mask = 1ull<<33 /* c0_up_b0 */;
2870 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
2871 info.enable_mask = 1ull<<33 /* c0_up_b0 */;
2873 info.group = CVMX_ERROR_GROUP_PCI;
2874 info.group_index = 0;
2875 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2876 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2877 info.parent.status_mask = 1ull<<3 /* npei */;
2878 info.func = __cvmx_error_display;
2879 info.user_info = (long)
2880 "ERROR PEXP_NPEI_INT_SUM[C0_UP_B0]: Received Unsupported P-TLP for Bar0.\n"
2882 fail |= cvmx_error_add(&info);
2884 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2885 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
2886 info.status_mask = 1ull<<34 /* c0_up_b1 */;
2887 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
2888 info.enable_mask = 1ull<<34 /* c0_up_b1 */;
2890 info.group = CVMX_ERROR_GROUP_PCI;
2891 info.group_index = 0;
2892 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2893 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2894 info.parent.status_mask = 1ull<<3 /* npei */;
2895 info.func = __cvmx_error_display;
2896 info.user_info = (long)
2897 "ERROR PEXP_NPEI_INT_SUM[C0_UP_B1]: Received Unsupported P-TLP for Bar1.\n"
2899 fail |= cvmx_error_add(&info);
2901 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2902 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
2903 info.status_mask = 1ull<<35 /* c0_up_b2 */;
2904 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
2905 info.enable_mask = 1ull<<35 /* c0_up_b2 */;
2907 info.group = CVMX_ERROR_GROUP_PCI;
2908 info.group_index = 0;
2909 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2910 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2911 info.parent.status_mask = 1ull<<3 /* npei */;
2912 info.func = __cvmx_error_display;
2913 info.user_info = (long)
2914 "ERROR PEXP_NPEI_INT_SUM[C0_UP_B2]: Received Unsupported P-TLP for Bar2.\n"
2916 fail |= cvmx_error_add(&info);
2918 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2919 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
2920 info.status_mask = 1ull<<37 /* c0_up_bx */;
2921 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
2922 info.enable_mask = 1ull<<37 /* c0_up_bx */;
2924 info.group = CVMX_ERROR_GROUP_PCI;
2925 info.group_index = 0;
2926 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2927 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2928 info.parent.status_mask = 1ull<<3 /* npei */;
2929 info.func = __cvmx_error_display;
2930 info.user_info = (long)
2931 "ERROR PEXP_NPEI_INT_SUM[C0_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n"
2933 fail |= cvmx_error_add(&info);
2935 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2936 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
2937 info.status_mask = 1ull<<55 /* c0_up_wf */;
2938 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
2939 info.enable_mask = 1ull<<55 /* c0_up_wf */;
2941 info.group = CVMX_ERROR_GROUP_PCI;
2942 info.group_index = 0;
2943 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2944 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2945 info.parent.status_mask = 1ull<<3 /* npei */;
2946 info.func = __cvmx_error_display;
2947 info.user_info = (long)
2948 "ERROR PEXP_NPEI_INT_SUM[C0_UP_WF]: Received Unsupported P-TLP for filtered window\n"
2949 " register. Core0.\n";
2950 fail |= cvmx_error_add(&info);
2952 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2953 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
2954 info.status_mask = 1ull<<36 /* c0_up_wi */;
2955 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
2956 info.enable_mask = 1ull<<36 /* c0_up_wi */;
2958 info.group = CVMX_ERROR_GROUP_PCI;
2959 info.group_index = 0;
2960 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2961 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2962 info.parent.status_mask = 1ull<<3 /* npei */;
2963 info.func = __cvmx_error_display;
2964 info.user_info = (long)
2965 "ERROR PEXP_NPEI_INT_SUM[C0_UP_WI]: Received Unsupported P-TLP for Window Register.\n"
2967 fail |= cvmx_error_add(&info);
2969 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2970 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
2971 info.status_mask = 1ull<<23 /* c0_wake */;
2972 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
2973 info.enable_mask = 1ull<<23 /* c0_wake */;
2975 info.group = CVMX_ERROR_GROUP_PCI;
2976 info.group_index = 0;
2977 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2978 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2979 info.parent.status_mask = 1ull<<3 /* npei */;
2980 info.func = __cvmx_error_display;
2981 info.user_info = (long)
2982 "ERROR PEXP_NPEI_INT_SUM[C0_WAKE]: Wake up from Power Management Unit.\n"
2983 " Pcie Core 0. (wake_n)\n"
2984 " Octeon will never generate this interrupt.\n";
2985 fail |= cvmx_error_add(&info);
2987 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2988 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
2989 info.status_mask = 1ull<<60 /* c1_ldwn */;
2990 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
2991 info.enable_mask = 1ull<<60 /* c1_ldwn */;
2993 info.group = CVMX_ERROR_GROUP_PCI;
2994 info.group_index = 1;
2995 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2996 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2997 info.parent.status_mask = 1ull<<3 /* npei */;
2998 info.func = __cvmx_error_display;
2999 info.user_info = (long)
3000 "ERROR PEXP_NPEI_INT_SUM[C1_LDWN]: Reset request due to link1 down status.\n";
3001 fail |= cvmx_error_add(&info);
3003 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3004 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3005 info.status_mask = 1ull<<28 /* c1_se */;
3006 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3007 info.enable_mask = 1ull<<28 /* c1_se */;
3009 info.group = CVMX_ERROR_GROUP_PCI;
3010 info.group_index = 1;
3011 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3012 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3013 info.parent.status_mask = 1ull<<3 /* npei */;
3014 info.func = __cvmx_error_display;
3015 info.user_info = (long)
3016 "ERROR PEXP_NPEI_INT_SUM[C1_SE]: System Error, RC Mode Only.\n"
3017 " Pcie Core 1. (cfg_sys_err_rc)\n";
3018 fail |= cvmx_error_add(&info);
3020 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3021 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3022 info.status_mask = 1ull<<48 /* c1_un_b0 */;
3023 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3024 info.enable_mask = 1ull<<48 /* c1_un_b0 */;
3026 info.group = CVMX_ERROR_GROUP_PCI;
3027 info.group_index = 1;
3028 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3029 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3030 info.parent.status_mask = 1ull<<3 /* npei */;
3031 info.func = __cvmx_error_display;
3032 info.user_info = (long)
3033 "ERROR PEXP_NPEI_INT_SUM[C1_UN_B0]: Received Unsupported N-TLP for Bar0.\n"
3035 fail |= cvmx_error_add(&info);
3037 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3038 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3039 info.status_mask = 1ull<<49 /* c1_un_b1 */;
3040 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3041 info.enable_mask = 1ull<<49 /* c1_un_b1 */;
3043 info.group = CVMX_ERROR_GROUP_PCI;
3044 info.group_index = 1;
3045 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3046 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3047 info.parent.status_mask = 1ull<<3 /* npei */;
3048 info.func = __cvmx_error_display;
3049 info.user_info = (long)
3050 "ERROR PEXP_NPEI_INT_SUM[C1_UN_B1]: Received Unsupported N-TLP for Bar1.\n"
3052 fail |= cvmx_error_add(&info);
3054 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3055 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3056 info.status_mask = 1ull<<50 /* c1_un_b2 */;
3057 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3058 info.enable_mask = 1ull<<50 /* c1_un_b2 */;
3060 info.group = CVMX_ERROR_GROUP_PCI;
3061 info.group_index = 1;
3062 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3063 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3064 info.parent.status_mask = 1ull<<3 /* npei */;
3065 info.func = __cvmx_error_display;
3066 info.user_info = (long)
3067 "ERROR PEXP_NPEI_INT_SUM[C1_UN_B2]: Received Unsupported N-TLP for Bar2.\n"
3069 fail |= cvmx_error_add(&info);
3071 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3072 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3073 info.status_mask = 1ull<<52 /* c1_un_bx */;
3074 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3075 info.enable_mask = 1ull<<52 /* c1_un_bx */;
3077 info.group = CVMX_ERROR_GROUP_PCI;
3078 info.group_index = 1;
3079 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3080 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3081 info.parent.status_mask = 1ull<<3 /* npei */;
3082 info.func = __cvmx_error_display;
3083 info.user_info = (long)
3084 "ERROR PEXP_NPEI_INT_SUM[C1_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n"
3086 fail |= cvmx_error_add(&info);
3088 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3089 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3090 info.status_mask = 1ull<<54 /* c1_un_wf */;
3091 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3092 info.enable_mask = 1ull<<54 /* c1_un_wf */;
3094 info.group = CVMX_ERROR_GROUP_PCI;
3095 info.group_index = 1;
3096 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3097 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3098 info.parent.status_mask = 1ull<<3 /* npei */;
3099 info.func = __cvmx_error_display;
3100 info.user_info = (long)
3101 "ERROR PEXP_NPEI_INT_SUM[C1_UN_WF]: Received Unsupported N-TLP for filtered window\n"
3102 " register. Core1.\n";
3103 fail |= cvmx_error_add(&info);
3105 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3106 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3107 info.status_mask = 1ull<<51 /* c1_un_wi */;
3108 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3109 info.enable_mask = 1ull<<51 /* c1_un_wi */;
3111 info.group = CVMX_ERROR_GROUP_PCI;
3112 info.group_index = 1;
3113 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3114 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3115 info.parent.status_mask = 1ull<<3 /* npei */;
3116 info.func = __cvmx_error_display;
3117 info.user_info = (long)
3118 "ERROR PEXP_NPEI_INT_SUM[C1_UN_WI]: Received Unsupported N-TLP for Window Register.\n"
3120 fail |= cvmx_error_add(&info);
3122 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3123 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3124 info.status_mask = 1ull<<43 /* c1_up_b0 */;
3125 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3126 info.enable_mask = 1ull<<43 /* c1_up_b0 */;
3128 info.group = CVMX_ERROR_GROUP_PCI;
3129 info.group_index = 1;
3130 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3131 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3132 info.parent.status_mask = 1ull<<3 /* npei */;
3133 info.func = __cvmx_error_display;
3134 info.user_info = (long)
3135 "ERROR PEXP_NPEI_INT_SUM[C1_UP_B0]: Received Unsupported P-TLP for Bar0.\n"
3137 fail |= cvmx_error_add(&info);
3139 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3140 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3141 info.status_mask = 1ull<<44 /* c1_up_b1 */;
3142 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3143 info.enable_mask = 1ull<<44 /* c1_up_b1 */;
3145 info.group = CVMX_ERROR_GROUP_PCI;
3146 info.group_index = 1;
3147 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3148 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3149 info.parent.status_mask = 1ull<<3 /* npei */;
3150 info.func = __cvmx_error_display;
3151 info.user_info = (long)
3152 "ERROR PEXP_NPEI_INT_SUM[C1_UP_B1]: Received Unsupported P-TLP for Bar1.\n"
3154 fail |= cvmx_error_add(&info);
3156 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3157 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3158 info.status_mask = 1ull<<45 /* c1_up_b2 */;
3159 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3160 info.enable_mask = 1ull<<45 /* c1_up_b2 */;
3162 info.group = CVMX_ERROR_GROUP_PCI;
3163 info.group_index = 1;
3164 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3165 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3166 info.parent.status_mask = 1ull<<3 /* npei */;
3167 info.func = __cvmx_error_display;
3168 info.user_info = (long)
3169 "ERROR PEXP_NPEI_INT_SUM[C1_UP_B2]: Received Unsupported P-TLP for Bar2.\n"
3171 fail |= cvmx_error_add(&info);
3173 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3174 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3175 info.status_mask = 1ull<<47 /* c1_up_bx */;
3176 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3177 info.enable_mask = 1ull<<47 /* c1_up_bx */;
3179 info.group = CVMX_ERROR_GROUP_PCI;
3180 info.group_index = 1;
3181 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3182 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3183 info.parent.status_mask = 1ull<<3 /* npei */;
3184 info.func = __cvmx_error_display;
3185 info.user_info = (long)
3186 "ERROR PEXP_NPEI_INT_SUM[C1_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n"
3188 fail |= cvmx_error_add(&info);
3190 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3191 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3192 info.status_mask = 1ull<<56 /* c1_up_wf */;
3193 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3194 info.enable_mask = 1ull<<56 /* c1_up_wf */;
3196 info.group = CVMX_ERROR_GROUP_PCI;
3197 info.group_index = 1;
3198 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3199 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3200 info.parent.status_mask = 1ull<<3 /* npei */;
3201 info.func = __cvmx_error_display;
3202 info.user_info = (long)
3203 "ERROR PEXP_NPEI_INT_SUM[C1_UP_WF]: Received Unsupported P-TLP for filtered window\n"
3204 " register. Core1.\n";
3205 fail |= cvmx_error_add(&info);
3207 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3208 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3209 info.status_mask = 1ull<<46 /* c1_up_wi */;
3210 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3211 info.enable_mask = 1ull<<46 /* c1_up_wi */;
3213 info.group = CVMX_ERROR_GROUP_PCI;
3214 info.group_index = 1;
3215 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3216 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3217 info.parent.status_mask = 1ull<<3 /* npei */;
3218 info.func = __cvmx_error_display;
3219 info.user_info = (long)
3220 "ERROR PEXP_NPEI_INT_SUM[C1_UP_WI]: Received Unsupported P-TLP for Window Register.\n"
3222 fail |= cvmx_error_add(&info);
3224 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3225 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3226 info.status_mask = 1ull<<30 /* c1_wake */;
3227 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3228 info.enable_mask = 1ull<<30 /* c1_wake */;
3230 info.group = CVMX_ERROR_GROUP_PCI;
3231 info.group_index = 1;
3232 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3233 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3234 info.parent.status_mask = 1ull<<3 /* npei */;
3235 info.func = __cvmx_error_display;
3236 info.user_info = (long)
3237 "ERROR PEXP_NPEI_INT_SUM[C1_WAKE]: Wake up from Power Management Unit.\n"
3238 " Pcie Core 1. (wake_n)\n"
3239 " Octeon will never generate this interrupt.\n";
3240 fail |= cvmx_error_add(&info);
3242 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3243 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3244 info.status_mask = 1ull<<2 /* bar0_to */;
3245 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3246 info.enable_mask = 1ull<<2 /* bar0_to */;
3248 info.group = CVMX_ERROR_GROUP_INTERNAL;
3249 info.group_index = 0;
3250 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3251 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3252 info.parent.status_mask = 1ull<<3 /* npei */;
3253 info.func = __cvmx_error_display;
3254 info.user_info = (long)
3255 "ERROR PEXP_NPEI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
3256 " read-data/commit in 0xffff core clocks.\n";
3257 fail |= cvmx_error_add(&info);
3259 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3260 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3261 info.status_mask = 1ull<<4 /* dma0dbo */;
3262 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3263 info.enable_mask = 1ull<<4 /* dma0dbo */;
3265 info.group = CVMX_ERROR_GROUP_INTERNAL;
3266 info.group_index = 0;
3267 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3268 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3269 info.parent.status_mask = 1ull<<3 /* npei */;
3270 info.func = __cvmx_error_display;
3271 info.user_info = (long)
3272 "ERROR PEXP_NPEI_INT_SUM[DMA0DBO]: DMA0 doorbell overflow.\n"
3273 " Bit[32] of the doorbell count was set.\n";
3274 fail |= cvmx_error_add(&info);
3276 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3277 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3278 info.status_mask = 1ull<<5 /* dma1dbo */;
3279 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3280 info.enable_mask = 1ull<<5 /* dma1dbo */;
3282 info.group = CVMX_ERROR_GROUP_INTERNAL;
3283 info.group_index = 0;
3284 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3285 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3286 info.parent.status_mask = 1ull<<3 /* npei */;
3287 info.func = __cvmx_error_display;
3288 info.user_info = (long)
3289 "ERROR PEXP_NPEI_INT_SUM[DMA1DBO]: DMA1 doorbell overflow.\n"
3290 " Bit[32] of the doorbell count was set.\n";
3291 fail |= cvmx_error_add(&info);
3293 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3294 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3295 info.status_mask = 1ull<<6 /* dma2dbo */;
3296 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3297 info.enable_mask = 1ull<<6 /* dma2dbo */;
3299 info.group = CVMX_ERROR_GROUP_INTERNAL;
3300 info.group_index = 0;
3301 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3302 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3303 info.parent.status_mask = 1ull<<3 /* npei */;
3304 info.func = __cvmx_error_display;
3305 info.user_info = (long)
3306 "ERROR PEXP_NPEI_INT_SUM[DMA2DBO]: DMA2 doorbell overflow.\n"
3307 " Bit[32] of the doorbell count was set.\n";
3308 fail |= cvmx_error_add(&info);
3310 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3311 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3312 info.status_mask = 1ull<<7 /* dma3dbo */;
3313 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3314 info.enable_mask = 1ull<<7 /* dma3dbo */;
3316 info.group = CVMX_ERROR_GROUP_INTERNAL;
3317 info.group_index = 0;
3318 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3319 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3320 info.parent.status_mask = 1ull<<3 /* npei */;
3321 info.func = __cvmx_error_display;
3322 info.user_info = (long)
3323 "ERROR PEXP_NPEI_INT_SUM[DMA3DBO]: DMA3 doorbell overflow.\n"
3324 " Bit[32] of the doorbell count was set.\n";
3325 fail |= cvmx_error_add(&info);
3327 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3328 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3329 info.status_mask = 1ull<<3 /* iob2big */;
3330 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3331 info.enable_mask = 1ull<<3 /* iob2big */;
3333 info.group = CVMX_ERROR_GROUP_INTERNAL;
3334 info.group_index = 0;
3335 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3336 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3337 info.parent.status_mask = 1ull<<3 /* npei */;
3338 info.func = __cvmx_error_display;
3339 info.user_info = (long)
3340 "ERROR PEXP_NPEI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n";
3341 fail |= cvmx_error_add(&info);
3343 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3344 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3345 info.status_mask = 1ull<<0 /* rml_rto */;
3346 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3347 info.enable_mask = 1ull<<0 /* rml_rto */;
3349 info.group = CVMX_ERROR_GROUP_INTERNAL;
3350 info.group_index = 0;
3351 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3352 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3353 info.parent.status_mask = 1ull<<3 /* npei */;
3354 info.func = __cvmx_error_display;
3355 info.user_info = (long)
3356 "ERROR PEXP_NPEI_INT_SUM[RML_RTO]: RML read did not return data in 0xffff core clocks.\n";
3357 fail |= cvmx_error_add(&info);
3359 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3360 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3361 info.status_mask = 1ull<<1 /* rml_wto */;
3362 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3363 info.enable_mask = 1ull<<1 /* rml_wto */;
3365 info.group = CVMX_ERROR_GROUP_INTERNAL;
3366 info.group_index = 0;
3367 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3368 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3369 info.parent.status_mask = 1ull<<3 /* npei */;
3370 info.func = __cvmx_error_display;
3371 info.user_info = (long)
3372 "ERROR PEXP_NPEI_INT_SUM[RML_WTO]: RML write did not get commit in 0xffff core clocks.\n";
3373 fail |= cvmx_error_add(&info);
3375 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3376 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3377 info.status_mask = 1ull<<8 /* dma4dbo */;
3378 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3379 info.enable_mask = 1ull<<8 /* dma4dbo */;
3381 info.group = CVMX_ERROR_GROUP_INTERNAL;
3382 info.group_index = 0;
3383 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3384 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3385 info.parent.status_mask = 1ull<<3 /* npei */;
3386 info.func = __cvmx_error_display;
3387 info.user_info = (long)
3388 "ERROR PEXP_NPEI_INT_SUM[DMA4DBO]: DMA4 doorbell overflow.\n"
3389 " Bit[32] of the doorbell count was set.\n";
3390 fail |= cvmx_error_add(&info);
3392 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3393 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3394 info.status_mask = 0;
3395 info.enable_addr = 0;
3396 info.enable_mask = 0;
3398 info.group = CVMX_ERROR_GROUP_INTERNAL;
3399 info.group_index = 0;
3400 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3401 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3402 info.parent.status_mask = 1ull<<3 /* npei */;
3403 info.func = __cvmx_error_decode;
3405 fail |= cvmx_error_add(&info);
3407 /* CVMX_PESCX_DBG_INFO(0) */
3408 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3409 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3410 info.status_mask = 1ull<<0 /* spoison */;
3411 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3412 info.enable_mask = 1ull<<0 /* spoison */;
3414 info.group = CVMX_ERROR_GROUP_PCI;
3415 info.group_index = 0;
3416 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3417 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3418 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3419 info.func = __cvmx_error_display;
3420 info.user_info = (long)
3421 "ERROR PESCX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent\n"
3422 " peai__client0_tlp_ep & peai__client0_tlp_hv\n";
3423 fail |= cvmx_error_add(&info);
3425 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3426 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3427 info.status_mask = 1ull<<2 /* rtlplle */;
3428 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3429 info.enable_mask = 1ull<<2 /* rtlplle */;
3431 info.group = CVMX_ERROR_GROUP_PCI;
3432 info.group_index = 0;
3433 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3434 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3435 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3436 info.func = __cvmx_error_display;
3437 info.user_info = (long)
3438 "ERROR PESCX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error\n"
3439 " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
3440 fail |= cvmx_error_add(&info);
3442 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3443 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3444 info.status_mask = 1ull<<3 /* recrce */;
3445 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3446 info.enable_mask = 1ull<<3 /* recrce */;
3448 info.group = CVMX_ERROR_GROUP_PCI;
3449 info.group_index = 0;
3450 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3451 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3452 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3453 info.func = __cvmx_error_display;
3454 info.user_info = (long)
3455 "ERROR PESCX_DBG_INFO(0)[RECRCE]: Received ECRC Error\n"
3456 " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
3457 fail |= cvmx_error_add(&info);
3459 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3460 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3461 info.status_mask = 1ull<<4 /* rpoison */;
3462 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3463 info.enable_mask = 1ull<<4 /* rpoison */;
3465 info.group = CVMX_ERROR_GROUP_PCI;
3466 info.group_index = 0;
3467 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3468 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3469 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3470 info.func = __cvmx_error_display;
3471 info.user_info = (long)
3472 "ERROR PESCX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP\n"
3473 " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
3474 fail |= cvmx_error_add(&info);
3476 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3477 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3478 info.status_mask = 1ull<<5 /* rcemrc */;
3479 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3480 info.enable_mask = 1ull<<5 /* rcemrc */;
3482 info.group = CVMX_ERROR_GROUP_PCI;
3483 info.group_index = 0;
3484 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3485 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3486 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3487 info.func = __cvmx_error_display;
3488 info.user_info = (long)
3489 "ERROR PESCX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
3490 " pedc_radm_correctable_err\n";
3491 fail |= cvmx_error_add(&info);
3493 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3494 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3495 info.status_mask = 1ull<<6 /* rnfemrc */;
3496 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3497 info.enable_mask = 1ull<<6 /* rnfemrc */;
3499 info.group = CVMX_ERROR_GROUP_PCI;
3500 info.group_index = 0;
3501 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3502 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3503 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3504 info.func = __cvmx_error_display;
3505 info.user_info = (long)
3506 "ERROR PESCX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
3507 " pedc_radm_nonfatal_err\n";
3508 fail |= cvmx_error_add(&info);
3510 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3511 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3512 info.status_mask = 1ull<<7 /* rfemrc */;
3513 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3514 info.enable_mask = 1ull<<7 /* rfemrc */;
3516 info.group = CVMX_ERROR_GROUP_PCI;
3517 info.group_index = 0;
3518 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3519 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3520 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3521 info.func = __cvmx_error_display;
3522 info.user_info = (long)
3523 "ERROR PESCX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
3524 " pedc_radm_fatal_err\n"
3525 " Bit set when a message with ERR_FATAL is set.\n";
3526 fail |= cvmx_error_add(&info);
3528 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3529 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3530 info.status_mask = 1ull<<8 /* rpmerc */;
3531 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3532 info.enable_mask = 1ull<<8 /* rpmerc */;
3534 info.group = CVMX_ERROR_GROUP_PCI;
3535 info.group_index = 0;
3536 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3537 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3538 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3539 info.func = __cvmx_error_display;
3540 info.user_info = (long)
3541 "ERROR PESCX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)\n"
3542 " pedc_radm_pm_pme\n";
3543 fail |= cvmx_error_add(&info);
3545 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3546 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3547 info.status_mask = 1ull<<9 /* rptamrc */;
3548 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3549 info.enable_mask = 1ull<<9 /* rptamrc */;
3551 info.group = CVMX_ERROR_GROUP_PCI;
3552 info.group_index = 0;
3553 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3554 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3555 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3556 info.func = __cvmx_error_display;
3557 info.user_info = (long)
3558 "ERROR PESCX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
3560 " pedc_radm_pm_to_ack\n";
3561 fail |= cvmx_error_add(&info);
3563 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3564 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3565 info.status_mask = 1ull<<10 /* rumep */;
3566 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3567 info.enable_mask = 1ull<<10 /* rumep */;
3569 info.group = CVMX_ERROR_GROUP_PCI;
3570 info.group_index = 0;
3571 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3572 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3573 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3574 info.func = __cvmx_error_display;
3575 info.user_info = (long)
3576 "ERROR PESCX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
3577 " pedc_radm_msg_unlock\n";
3578 fail |= cvmx_error_add(&info);
3580 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3581 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3582 info.status_mask = 1ull<<11 /* rvdm */;
3583 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3584 info.enable_mask = 1ull<<11 /* rvdm */;
3586 info.group = CVMX_ERROR_GROUP_PCI;
3587 info.group_index = 0;
3588 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3589 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3590 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3591 info.func = __cvmx_error_display;
3592 info.user_info = (long)
3593 "ERROR PESCX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message\n"
3594 " pedc_radm_vendor_msg\n";
3595 fail |= cvmx_error_add(&info);
3597 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3598 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3599 info.status_mask = 1ull<<12 /* acto */;
3600 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3601 info.enable_mask = 1ull<<12 /* acto */;
3603 info.group = CVMX_ERROR_GROUP_PCI;
3604 info.group_index = 0;
3605 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3606 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3607 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3608 info.func = __cvmx_error_display;
3609 info.user_info = (long)
3610 "ERROR PESCX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured\n"
3611 " pedc_radm_cpl_timeout\n";
3612 fail |= cvmx_error_add(&info);
3614 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3615 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3616 info.status_mask = 1ull<<13 /* rte */;
3617 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3618 info.enable_mask = 1ull<<13 /* rte */;
3620 info.group = CVMX_ERROR_GROUP_PCI;
3621 info.group_index = 0;
3622 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3623 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3624 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3625 info.func = __cvmx_error_display;
3626 info.user_info = (long)
3627 "ERROR PESCX_DBG_INFO(0)[RTE]: Replay Timer Expired\n"
3628 " xdlh_replay_timeout_err\n"
3629 " This bit is set when the REPLAY_TIMER expires in\n"
3630 " the PCIE core. The probability of this bit being\n"
3631 " set will increase with the traffic load.\n";
3632 fail |= cvmx_error_add(&info);
3634 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3635 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3636 info.status_mask = 1ull<<14 /* mre */;
3637 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3638 info.enable_mask = 1ull<<14 /* mre */;
3640 info.group = CVMX_ERROR_GROUP_PCI;
3641 info.group_index = 0;
3642 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3643 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3644 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3645 info.func = __cvmx_error_display;
3646 info.user_info = (long)
3647 "ERROR PESCX_DBG_INFO(0)[MRE]: Max Retries Exceeded\n"
3648 " xdlh_replay_num_rlover_err\n";
3649 fail |= cvmx_error_add(&info);
3651 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3652 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3653 info.status_mask = 1ull<<15 /* rdwdle */;
3654 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3655 info.enable_mask = 1ull<<15 /* rdwdle */;
3657 info.group = CVMX_ERROR_GROUP_PCI;
3658 info.group_index = 0;
3659 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3660 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3661 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3662 info.func = __cvmx_error_display;
3663 info.user_info = (long)
3664 "ERROR PESCX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
3665 " rdlh_bad_dllp_err\n";
3666 fail |= cvmx_error_add(&info);
3668 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3669 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3670 info.status_mask = 1ull<<16 /* rtwdle */;
3671 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3672 info.enable_mask = 1ull<<16 /* rtwdle */;
3674 info.group = CVMX_ERROR_GROUP_PCI;
3675 info.group_index = 0;
3676 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3677 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3678 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3679 info.func = __cvmx_error_display;
3680 info.user_info = (long)
3681 "ERROR PESCX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error\n"
3682 " rdlh_bad_tlp_err\n";
3683 fail |= cvmx_error_add(&info);
3685 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3686 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3687 info.status_mask = 1ull<<17 /* dpeoosd */;
3688 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3689 info.enable_mask = 1ull<<17 /* dpeoosd */;
3691 info.group = CVMX_ERROR_GROUP_PCI;
3692 info.group_index = 0;
3693 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3694 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3695 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3696 info.func = __cvmx_error_display;
3697 info.user_info = (long)
3698 "ERROR PESCX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
3700 fail |= cvmx_error_add(&info);
3702 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3703 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3704 info.status_mask = 1ull<<18 /* fcpvwt */;
3705 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3706 info.enable_mask = 1ull<<18 /* fcpvwt */;
3708 info.group = CVMX_ERROR_GROUP_PCI;
3709 info.group_index = 0;
3710 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3711 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3712 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3713 info.func = __cvmx_error_display;
3714 info.user_info = (long)
3715 "ERROR PESCX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
3716 " rtlh_fc_prot_err\n";
3717 fail |= cvmx_error_add(&info);
3719 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3720 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3721 info.status_mask = 1ull<<19 /* rpe */;
3722 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3723 info.enable_mask = 1ull<<19 /* rpe */;
3725 info.group = CVMX_ERROR_GROUP_PCI;
3726 info.group_index = 0;
3727 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3728 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3729 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3730 info.func = __cvmx_error_display;
3731 info.user_info = (long)
3732 "ERROR PESCX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error\n"
3733 " (RxStatus = 3b100) or disparity error\n"
3734 " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
3737 fail |= cvmx_error_add(&info);
3739 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3740 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3741 info.status_mask = 1ull<<20 /* fcuv */;
3742 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3743 info.enable_mask = 1ull<<20 /* fcuv */;
3745 info.group = CVMX_ERROR_GROUP_PCI;
3746 info.group_index = 0;
3747 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3748 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3749 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3750 info.func = __cvmx_error_display;
3751 info.user_info = (long)
3752 "ERROR PESCX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)\n"
3753 " int_xadm_fc_prot_err\n";
3754 fail |= cvmx_error_add(&info);
3756 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3757 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3758 info.status_mask = 1ull<<21 /* rqo */;
3759 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3760 info.enable_mask = 1ull<<21 /* rqo */;
3762 info.group = CVMX_ERROR_GROUP_PCI;
3763 info.group_index = 0;
3764 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3765 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3766 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3767 info.func = __cvmx_error_display;
3768 info.user_info = (long)
3769 "ERROR PESCX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when\n"
3770 " flow control advertisements are ignored\n"
3771 " radm_qoverflow\n";
3772 fail |= cvmx_error_add(&info);
3774 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3775 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3776 info.status_mask = 1ull<<22 /* rauc */;
3777 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3778 info.enable_mask = 1ull<<22 /* rauc */;
3780 info.group = CVMX_ERROR_GROUP_PCI;
3781 info.group_index = 0;
3782 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3783 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3784 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3785 info.func = __cvmx_error_display;
3786 info.user_info = (long)
3787 "ERROR PESCX_DBG_INFO(0)[RAUC]: Received an unexpected completion\n"
3788 " radm_unexp_cpl_err\n";
3789 fail |= cvmx_error_add(&info);
3791 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3792 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3793 info.status_mask = 1ull<<23 /* racur */;
3794 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3795 info.enable_mask = 1ull<<23 /* racur */;
3797 info.group = CVMX_ERROR_GROUP_PCI;
3798 info.group_index = 0;
3799 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3800 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3801 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3802 info.func = __cvmx_error_display;
3803 info.user_info = (long)
3804 "ERROR PESCX_DBG_INFO(0)[RACUR]: Received a completion with UR status\n"
3805 " radm_rcvd_cpl_ur\n";
3806 fail |= cvmx_error_add(&info);
3808 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3809 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3810 info.status_mask = 1ull<<24 /* racca */;
3811 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3812 info.enable_mask = 1ull<<24 /* racca */;
3814 info.group = CVMX_ERROR_GROUP_PCI;
3815 info.group_index = 0;
3816 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3817 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3818 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3819 info.func = __cvmx_error_display;
3820 info.user_info = (long)
3821 "ERROR PESCX_DBG_INFO(0)[RACCA]: Received a completion with CA status\n"
3822 " radm_rcvd_cpl_ca\n";
3823 fail |= cvmx_error_add(&info);
3825 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3826 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3827 info.status_mask = 1ull<<25 /* caar */;
3828 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3829 info.enable_mask = 1ull<<25 /* caar */;
3831 info.group = CVMX_ERROR_GROUP_PCI;
3832 info.group_index = 0;
3833 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3834 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3835 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3836 info.func = __cvmx_error_display;
3837 info.user_info = (long)
3838 "ERROR PESCX_DBG_INFO(0)[CAAR]: Completer aborted a request\n"
3839 " radm_rcvd_ca_req\n"
3840 " This bit will never be set because Octeon does\n"
3841 " not generate Completer Aborts.\n";
3842 fail |= cvmx_error_add(&info);
3844 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3845 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3846 info.status_mask = 1ull<<26 /* rarwdns */;
3847 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3848 info.enable_mask = 1ull<<26 /* rarwdns */;
3850 info.group = CVMX_ERROR_GROUP_PCI;
3851 info.group_index = 0;
3852 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3853 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3854 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3855 info.func = __cvmx_error_display;
3856 info.user_info = (long)
3857 "ERROR PESCX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support\n"
3858 " radm_rcvd_ur_req\n";
3859 fail |= cvmx_error_add(&info);
3861 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3862 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3863 info.status_mask = 1ull<<27 /* ramtlp */;
3864 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3865 info.enable_mask = 1ull<<27 /* ramtlp */;
3867 info.group = CVMX_ERROR_GROUP_PCI;
3868 info.group_index = 0;
3869 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3870 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3871 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3872 info.func = __cvmx_error_display;
3873 info.user_info = (long)
3874 "ERROR PESCX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP\n"
3875 " radm_mlf_tlp_err\n";
3876 fail |= cvmx_error_add(&info);
3878 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3879 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3880 info.status_mask = 1ull<<28 /* racpp */;
3881 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3882 info.enable_mask = 1ull<<28 /* racpp */;
3884 info.group = CVMX_ERROR_GROUP_PCI;
3885 info.group_index = 0;
3886 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3887 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3888 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3889 info.func = __cvmx_error_display;
3890 info.user_info = (long)
3891 "ERROR PESCX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload\n"
3892 " radm_rcvd_cpl_poisoned\n";
3893 fail |= cvmx_error_add(&info);
3895 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3896 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3897 info.status_mask = 1ull<<29 /* rawwpp */;
3898 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3899 info.enable_mask = 1ull<<29 /* rawwpp */;
3901 info.group = CVMX_ERROR_GROUP_PCI;
3902 info.group_index = 0;
3903 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3904 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3905 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3906 info.func = __cvmx_error_display;
3907 info.user_info = (long)
3908 "ERROR PESCX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload\n"
3909 " radm_rcvd_wreq_poisoned\n";
3910 fail |= cvmx_error_add(&info);
3912 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3913 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3914 info.status_mask = 1ull<<30 /* ecrc_e */;
3915 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3916 info.enable_mask = 1ull<<30 /* ecrc_e */;
3918 info.group = CVMX_ERROR_GROUP_PCI;
3919 info.group_index = 0;
3920 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3921 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3922 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3923 info.func = __cvmx_error_display;
3924 info.user_info = (long)
3925 "ERROR PESCX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.\n"
3927 fail |= cvmx_error_add(&info);
3929 /* CVMX_PESCX_DBG_INFO(1) */
3930 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3931 info.status_addr = CVMX_PESCX_DBG_INFO(1);
3932 info.status_mask = 1ull<<0 /* spoison */;
3933 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
3934 info.enable_mask = 1ull<<0 /* spoison */;
3936 info.group = CVMX_ERROR_GROUP_PCI;
3937 info.group_index = 1;
3938 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3939 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3940 info.parent.status_mask = 1ull<<58 /* c1_exc */;
3941 info.func = __cvmx_error_display;
3942 info.user_info = (long)
3943 "ERROR PESCX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent\n"
3944 " peai__client0_tlp_ep & peai__client0_tlp_hv\n";
3945 fail |= cvmx_error_add(&info);
3947 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3948 info.status_addr = CVMX_PESCX_DBG_INFO(1);
3949 info.status_mask = 1ull<<2 /* rtlplle */;
3950 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
3951 info.enable_mask = 1ull<<2 /* rtlplle */;
3953 info.group = CVMX_ERROR_GROUP_PCI;
3954 info.group_index = 1;
3955 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3956 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3957 info.parent.status_mask = 1ull<<58 /* c1_exc */;
3958 info.func = __cvmx_error_display;
3959 info.user_info = (long)
3960 "ERROR PESCX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error\n"
3961 " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
3962 fail |= cvmx_error_add(&info);
3964 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3965 info.status_addr = CVMX_PESCX_DBG_INFO(1);
3966 info.status_mask = 1ull<<3 /* recrce */;
3967 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
3968 info.enable_mask = 1ull<<3 /* recrce */;
3970 info.group = CVMX_ERROR_GROUP_PCI;
3971 info.group_index = 1;
3972 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3973 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3974 info.parent.status_mask = 1ull<<58 /* c1_exc */;
3975 info.func = __cvmx_error_display;
3976 info.user_info = (long)
3977 "ERROR PESCX_DBG_INFO(1)[RECRCE]: Received ECRC Error\n"
3978 " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
3979 fail |= cvmx_error_add(&info);
3981 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3982 info.status_addr = CVMX_PESCX_DBG_INFO(1);
3983 info.status_mask = 1ull<<4 /* rpoison */;
3984 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
3985 info.enable_mask = 1ull<<4 /* rpoison */;
3987 info.group = CVMX_ERROR_GROUP_PCI;
3988 info.group_index = 1;
3989 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3990 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3991 info.parent.status_mask = 1ull<<58 /* c1_exc */;
3992 info.func = __cvmx_error_display;
3993 info.user_info = (long)
3994 "ERROR PESCX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP\n"
3995 " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
3996 fail |= cvmx_error_add(&info);
3998 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3999 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4000 info.status_mask = 1ull<<5 /* rcemrc */;
4001 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4002 info.enable_mask = 1ull<<5 /* rcemrc */;
4004 info.group = CVMX_ERROR_GROUP_PCI;
4005 info.group_index = 1;
4006 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4007 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4008 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4009 info.func = __cvmx_error_display;
4010 info.user_info = (long)
4011 "ERROR PESCX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
4012 " pedc_radm_correctable_err\n";
4013 fail |= cvmx_error_add(&info);
4015 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4016 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4017 info.status_mask = 1ull<<6 /* rnfemrc */;
4018 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4019 info.enable_mask = 1ull<<6 /* rnfemrc */;
4021 info.group = CVMX_ERROR_GROUP_PCI;
4022 info.group_index = 1;
4023 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4024 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4025 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4026 info.func = __cvmx_error_display;
4027 info.user_info = (long)
4028 "ERROR PESCX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
4029 " pedc_radm_nonfatal_err\n";
4030 fail |= cvmx_error_add(&info);
4032 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4033 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4034 info.status_mask = 1ull<<7 /* rfemrc */;
4035 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4036 info.enable_mask = 1ull<<7 /* rfemrc */;
4038 info.group = CVMX_ERROR_GROUP_PCI;
4039 info.group_index = 1;
4040 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4041 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4042 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4043 info.func = __cvmx_error_display;
4044 info.user_info = (long)
4045 "ERROR PESCX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
4046 " pedc_radm_fatal_err\n"
4047 " Bit set when a message with ERR_FATAL is set.\n";
4048 fail |= cvmx_error_add(&info);
4050 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4051 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4052 info.status_mask = 1ull<<8 /* rpmerc */;
4053 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4054 info.enable_mask = 1ull<<8 /* rpmerc */;
4056 info.group = CVMX_ERROR_GROUP_PCI;
4057 info.group_index = 1;
4058 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4059 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4060 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4061 info.func = __cvmx_error_display;
4062 info.user_info = (long)
4063 "ERROR PESCX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)\n"
4064 " pedc_radm_pm_pme\n";
4065 fail |= cvmx_error_add(&info);
4067 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4068 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4069 info.status_mask = 1ull<<9 /* rptamrc */;
4070 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4071 info.enable_mask = 1ull<<9 /* rptamrc */;
4073 info.group = CVMX_ERROR_GROUP_PCI;
4074 info.group_index = 1;
4075 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4076 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4077 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4078 info.func = __cvmx_error_display;
4079 info.user_info = (long)
4080 "ERROR PESCX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
4082 " pedc_radm_pm_to_ack\n";
4083 fail |= cvmx_error_add(&info);
4085 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4086 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4087 info.status_mask = 1ull<<10 /* rumep */;
4088 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4089 info.enable_mask = 1ull<<10 /* rumep */;
4091 info.group = CVMX_ERROR_GROUP_PCI;
4092 info.group_index = 1;
4093 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4094 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4095 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4096 info.func = __cvmx_error_display;
4097 info.user_info = (long)
4098 "ERROR PESCX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
4099 " pedc_radm_msg_unlock\n";
4100 fail |= cvmx_error_add(&info);
4102 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4103 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4104 info.status_mask = 1ull<<11 /* rvdm */;
4105 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4106 info.enable_mask = 1ull<<11 /* rvdm */;
4108 info.group = CVMX_ERROR_GROUP_PCI;
4109 info.group_index = 1;
4110 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4111 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4112 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4113 info.func = __cvmx_error_display;
4114 info.user_info = (long)
4115 "ERROR PESCX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message\n"
4116 " pedc_radm_vendor_msg\n";
4117 fail |= cvmx_error_add(&info);
4119 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4120 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4121 info.status_mask = 1ull<<12 /* acto */;
4122 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4123 info.enable_mask = 1ull<<12 /* acto */;
4125 info.group = CVMX_ERROR_GROUP_PCI;
4126 info.group_index = 1;
4127 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4128 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4129 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4130 info.func = __cvmx_error_display;
4131 info.user_info = (long)
4132 "ERROR PESCX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured\n"
4133 " pedc_radm_cpl_timeout\n";
4134 fail |= cvmx_error_add(&info);
4136 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4137 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4138 info.status_mask = 1ull<<13 /* rte */;
4139 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4140 info.enable_mask = 1ull<<13 /* rte */;
4142 info.group = CVMX_ERROR_GROUP_PCI;
4143 info.group_index = 1;
4144 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4145 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4146 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4147 info.func = __cvmx_error_display;
4148 info.user_info = (long)
4149 "ERROR PESCX_DBG_INFO(1)[RTE]: Replay Timer Expired\n"
4150 " xdlh_replay_timeout_err\n"
4151 " This bit is set when the REPLAY_TIMER expires in\n"
4152 " the PCIE core. The probability of this bit being\n"
4153 " set will increase with the traffic load.\n";
4154 fail |= cvmx_error_add(&info);
4156 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4157 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4158 info.status_mask = 1ull<<14 /* mre */;
4159 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4160 info.enable_mask = 1ull<<14 /* mre */;
4162 info.group = CVMX_ERROR_GROUP_PCI;
4163 info.group_index = 1;
4164 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4165 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4166 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4167 info.func = __cvmx_error_display;
4168 info.user_info = (long)
4169 "ERROR PESCX_DBG_INFO(1)[MRE]: Max Retries Exceeded\n"
4170 " xdlh_replay_num_rlover_err\n";
4171 fail |= cvmx_error_add(&info);
4173 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4174 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4175 info.status_mask = 1ull<<15 /* rdwdle */;
4176 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4177 info.enable_mask = 1ull<<15 /* rdwdle */;
4179 info.group = CVMX_ERROR_GROUP_PCI;
4180 info.group_index = 1;
4181 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4182 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4183 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4184 info.func = __cvmx_error_display;
4185 info.user_info = (long)
4186 "ERROR PESCX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
4187 " rdlh_bad_dllp_err\n";
4188 fail |= cvmx_error_add(&info);
4190 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4191 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4192 info.status_mask = 1ull<<16 /* rtwdle */;
4193 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4194 info.enable_mask = 1ull<<16 /* rtwdle */;
4196 info.group = CVMX_ERROR_GROUP_PCI;
4197 info.group_index = 1;
4198 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4199 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4200 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4201 info.func = __cvmx_error_display;
4202 info.user_info = (long)
4203 "ERROR PESCX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error\n"
4204 " rdlh_bad_tlp_err\n";
4205 fail |= cvmx_error_add(&info);
4207 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4208 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4209 info.status_mask = 1ull<<17 /* dpeoosd */;
4210 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4211 info.enable_mask = 1ull<<17 /* dpeoosd */;
4213 info.group = CVMX_ERROR_GROUP_PCI;
4214 info.group_index = 1;
4215 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4216 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4217 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4218 info.func = __cvmx_error_display;
4219 info.user_info = (long)
4220 "ERROR PESCX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
4222 fail |= cvmx_error_add(&info);
4224 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4225 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4226 info.status_mask = 1ull<<18 /* fcpvwt */;
4227 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4228 info.enable_mask = 1ull<<18 /* fcpvwt */;
4230 info.group = CVMX_ERROR_GROUP_PCI;
4231 info.group_index = 1;
4232 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4233 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4234 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4235 info.func = __cvmx_error_display;
4236 info.user_info = (long)
4237 "ERROR PESCX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
4238 " rtlh_fc_prot_err\n";
4239 fail |= cvmx_error_add(&info);
4241 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4242 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4243 info.status_mask = 1ull<<19 /* rpe */;
4244 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4245 info.enable_mask = 1ull<<19 /* rpe */;
4247 info.group = CVMX_ERROR_GROUP_PCI;
4248 info.group_index = 1;
4249 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4250 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4251 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4252 info.func = __cvmx_error_display;
4253 info.user_info = (long)
4254 "ERROR PESCX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error\n"
4255 " (RxStatus = 3b100) or disparity error\n"
4256 " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
4259 fail |= cvmx_error_add(&info);
4261 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4262 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4263 info.status_mask = 1ull<<20 /* fcuv */;
4264 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4265 info.enable_mask = 1ull<<20 /* fcuv */;
4267 info.group = CVMX_ERROR_GROUP_PCI;
4268 info.group_index = 1;
4269 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4270 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4271 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4272 info.func = __cvmx_error_display;
4273 info.user_info = (long)
4274 "ERROR PESCX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)\n"
4275 " int_xadm_fc_prot_err\n";
4276 fail |= cvmx_error_add(&info);
4278 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4279 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4280 info.status_mask = 1ull<<21 /* rqo */;
4281 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4282 info.enable_mask = 1ull<<21 /* rqo */;
4284 info.group = CVMX_ERROR_GROUP_PCI;
4285 info.group_index = 1;
4286 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4287 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4288 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4289 info.func = __cvmx_error_display;
4290 info.user_info = (long)
4291 "ERROR PESCX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when\n"
4292 " flow control advertisements are ignored\n"
4293 " radm_qoverflow\n";
4294 fail |= cvmx_error_add(&info);
4296 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4297 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4298 info.status_mask = 1ull<<22 /* rauc */;
4299 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4300 info.enable_mask = 1ull<<22 /* rauc */;
4302 info.group = CVMX_ERROR_GROUP_PCI;
4303 info.group_index = 1;
4304 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4305 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4306 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4307 info.func = __cvmx_error_display;
4308 info.user_info = (long)
4309 "ERROR PESCX_DBG_INFO(1)[RAUC]: Received an unexpected completion\n"
4310 " radm_unexp_cpl_err\n";
4311 fail |= cvmx_error_add(&info);
4313 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4314 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4315 info.status_mask = 1ull<<23 /* racur */;
4316 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4317 info.enable_mask = 1ull<<23 /* racur */;
4319 info.group = CVMX_ERROR_GROUP_PCI;
4320 info.group_index = 1;
4321 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4322 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4323 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4324 info.func = __cvmx_error_display;
4325 info.user_info = (long)
4326 "ERROR PESCX_DBG_INFO(1)[RACUR]: Received a completion with UR status\n"
4327 " radm_rcvd_cpl_ur\n";
4328 fail |= cvmx_error_add(&info);
4330 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4331 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4332 info.status_mask = 1ull<<24 /* racca */;
4333 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4334 info.enable_mask = 1ull<<24 /* racca */;
4336 info.group = CVMX_ERROR_GROUP_PCI;
4337 info.group_index = 1;
4338 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4339 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4340 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4341 info.func = __cvmx_error_display;
4342 info.user_info = (long)
4343 "ERROR PESCX_DBG_INFO(1)[RACCA]: Received a completion with CA status\n"
4344 " radm_rcvd_cpl_ca\n";
4345 fail |= cvmx_error_add(&info);
4347 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4348 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4349 info.status_mask = 1ull<<25 /* caar */;
4350 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4351 info.enable_mask = 1ull<<25 /* caar */;
4353 info.group = CVMX_ERROR_GROUP_PCI;
4354 info.group_index = 1;
4355 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4356 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4357 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4358 info.func = __cvmx_error_display;
4359 info.user_info = (long)
4360 "ERROR PESCX_DBG_INFO(1)[CAAR]: Completer aborted a request\n"
4361 " radm_rcvd_ca_req\n"
4362 " This bit will never be set because Octeon does\n"
4363 " not generate Completer Aborts.\n";
4364 fail |= cvmx_error_add(&info);
4366 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4367 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4368 info.status_mask = 1ull<<26 /* rarwdns */;
4369 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4370 info.enable_mask = 1ull<<26 /* rarwdns */;
4372 info.group = CVMX_ERROR_GROUP_PCI;
4373 info.group_index = 1;
4374 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4375 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4376 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4377 info.func = __cvmx_error_display;
4378 info.user_info = (long)
4379 "ERROR PESCX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support\n"
4380 " radm_rcvd_ur_req\n";
4381 fail |= cvmx_error_add(&info);
4383 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4384 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4385 info.status_mask = 1ull<<27 /* ramtlp */;
4386 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4387 info.enable_mask = 1ull<<27 /* ramtlp */;
4389 info.group = CVMX_ERROR_GROUP_PCI;
4390 info.group_index = 1;
4391 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4392 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4393 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4394 info.func = __cvmx_error_display;
4395 info.user_info = (long)
4396 "ERROR PESCX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP\n"
4397 " radm_mlf_tlp_err\n";
4398 fail |= cvmx_error_add(&info);
4400 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4401 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4402 info.status_mask = 1ull<<28 /* racpp */;
4403 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4404 info.enable_mask = 1ull<<28 /* racpp */;
4406 info.group = CVMX_ERROR_GROUP_PCI;
4407 info.group_index = 1;
4408 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4409 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4410 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4411 info.func = __cvmx_error_display;
4412 info.user_info = (long)
4413 "ERROR PESCX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload\n"
4414 " radm_rcvd_cpl_poisoned\n";
4415 fail |= cvmx_error_add(&info);
4417 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4418 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4419 info.status_mask = 1ull<<29 /* rawwpp */;
4420 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4421 info.enable_mask = 1ull<<29 /* rawwpp */;
4423 info.group = CVMX_ERROR_GROUP_PCI;
4424 info.group_index = 1;
4425 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4426 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4427 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4428 info.func = __cvmx_error_display;
4429 info.user_info = (long)
4430 "ERROR PESCX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload\n"
4431 " radm_rcvd_wreq_poisoned\n";
4432 fail |= cvmx_error_add(&info);
4434 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4435 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4436 info.status_mask = 1ull<<30 /* ecrc_e */;
4437 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4438 info.enable_mask = 1ull<<30 /* ecrc_e */;
4440 info.group = CVMX_ERROR_GROUP_PCI;
4441 info.group_index = 1;
4442 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4443 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4444 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4445 info.func = __cvmx_error_display;
4446 info.user_info = (long)
4447 "ERROR PESCX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.\n"
4449 fail |= cvmx_error_add(&info);
4451 /* CVMX_RAD_REG_ERROR */
4452 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4453 info.status_addr = CVMX_RAD_REG_ERROR;
4454 info.status_mask = 1ull<<0 /* doorbell */;
4455 info.enable_addr = CVMX_RAD_REG_INT_MASK;
4456 info.enable_mask = 1ull<<0 /* doorbell */;
4458 info.group = CVMX_ERROR_GROUP_INTERNAL;
4459 info.group_index = 0;
4460 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4461 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4462 info.parent.status_mask = 1ull<<14 /* rad */;
4463 info.func = __cvmx_error_display;
4464 info.user_info = (long)
4465 "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
4466 fail |= cvmx_error_add(&info);
4468 /* CVMX_LMCX_MEM_CFG0(1) */
4469 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4470 info.status_addr = CVMX_LMCX_MEM_CFG0(1);
4471 info.status_mask = 0xfull<<21 /* sec_err */;
4472 info.enable_addr = CVMX_LMCX_MEM_CFG0(1);
4473 info.enable_mask = 1ull<<19 /* intr_sec_ena */;
4474 info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
4475 info.group = CVMX_ERROR_GROUP_LMC;
4476 info.group_index = 1;
4477 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4478 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4479 info.parent.status_mask = 1ull<<29 /* lmc1 */;
4480 info.func = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
4481 info.user_info = (long)
4482 "ERROR LMCX_MEM_CFG0(1)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
4483 " In 64b mode, ecc is calculated on 2 cycle worth of data\n"
4484 " [0] corresponds to DQ[63:0]_c0_p0\n"
4485 " [1] corresponds to DQ[63:0]_c0_p1\n"
4486 " [2] corresponds to DQ[63:0]_c1_p0\n"
4487 " [3] corresponds to DQ[63:0]_c1_p1\n"
4488 " In 32b mode, ecc is calculated on 4 cycle worth of data\n"
4489 " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
4490 " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
4491 " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
4492 " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
4493 " where _cC_pP denotes cycle C and phase P\n"
4494 " Write of 1 will clear the corresponding error bit\n";
4495 fail |= cvmx_error_add(&info);
4497 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4498 info.status_addr = CVMX_LMCX_MEM_CFG0(1);
4499 info.status_mask = 0xfull<<25 /* ded_err */;
4500 info.enable_addr = CVMX_LMCX_MEM_CFG0(1);
4501 info.enable_mask = 1ull<<20 /* intr_ded_ena */;
4503 info.group = CVMX_ERROR_GROUP_LMC;
4504 info.group_index = 1;
4505 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4506 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4507 info.parent.status_mask = 1ull<<29 /* lmc1 */;
4508 info.func = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
4509 info.user_info = (long)
4510 "ERROR LMCX_MEM_CFG0(1)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
4511 " In 64b mode, ecc is calculated on 2 cycle worth of data\n"
4512 " [0] corresponds to DQ[63:0]_c0_p0\n"
4513 " [1] corresponds to DQ[63:0]_c0_p1\n"
4514 " [2] corresponds to DQ[63:0]_c1_p0\n"
4515 " [3] corresponds to DQ[63:0]_c1_p1\n"
4516 " In 32b mode, ecc is calculated on 4 cycle worth of data\n"
4517 " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
4518 " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
4519 " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
4520 " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
4521 " where _cC_pP denotes cycle C and phase P\n"
4522 " Write of 1 will clear the corresponding error bit\n";
4523 fail |= cvmx_error_add(&info);
4525 /* CVMX_PCSX_INTX_REG(0,1) */
4526 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4527 info.status_addr = CVMX_PCSX_INTX_REG(0,1);
4528 info.status_mask = 1ull<<2 /* an_err */;
4529 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
4530 info.enable_mask = 1ull<<2 /* an_err_en */;
4532 info.group = CVMX_ERROR_GROUP_ETHERNET;
4533 info.group_index = 16;
4534 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4535 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4536 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
4537 info.func = __cvmx_error_display;
4538 info.user_info = (long)
4539 "ERROR PCSX_INTX_REG(0,1)[AN_ERR]: AN Error, AN resolution function failed\n";
4540 fail |= cvmx_error_add(&info);
4542 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4543 info.status_addr = CVMX_PCSX_INTX_REG(0,1);
4544 info.status_mask = 1ull<<3 /* txfifu */;
4545 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
4546 info.enable_mask = 1ull<<3 /* txfifu_en */;
4548 info.group = CVMX_ERROR_GROUP_ETHERNET;
4549 info.group_index = 16;
4550 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4551 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4552 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
4553 info.func = __cvmx_error_display;
4554 info.user_info = (long)
4555 "ERROR PCSX_INTX_REG(0,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
4557 fail |= cvmx_error_add(&info);
4559 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4560 info.status_addr = CVMX_PCSX_INTX_REG(0,1);
4561 info.status_mask = 1ull<<4 /* txfifo */;
4562 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
4563 info.enable_mask = 1ull<<4 /* txfifo_en */;
4565 info.group = CVMX_ERROR_GROUP_ETHERNET;
4566 info.group_index = 16;
4567 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4568 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4569 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
4570 info.func = __cvmx_error_display;
4571 info.user_info = (long)
4572 "ERROR PCSX_INTX_REG(0,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
4574 fail |= cvmx_error_add(&info);
4576 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4577 info.status_addr = CVMX_PCSX_INTX_REG(0,1);
4578 info.status_mask = 1ull<<5 /* txbad */;
4579 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
4580 info.enable_mask = 1ull<<5 /* txbad_en */;
4582 info.group = CVMX_ERROR_GROUP_ETHERNET;
4583 info.group_index = 16;
4584 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4585 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4586 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
4587 info.func = __cvmx_error_display;
4588 info.user_info = (long)
4589 "ERROR PCSX_INTX_REG(0,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
4590 " state. Should never be set during normal operation\n";
4591 fail |= cvmx_error_add(&info);
4593 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4594 info.status_addr = CVMX_PCSX_INTX_REG(0,1);
4595 info.status_mask = 1ull<<7 /* rxbad */;
4596 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
4597 info.enable_mask = 1ull<<7 /* rxbad_en */;
4599 info.group = CVMX_ERROR_GROUP_ETHERNET;
4600 info.group_index = 16;
4601 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4602 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4603 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
4604 info.func = __cvmx_error_display;
4605 info.user_info = (long)
4606 "ERROR PCSX_INTX_REG(0,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
4607 " state. Should never be set during normal operation\n";
4608 fail |= cvmx_error_add(&info);
4610 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4611 info.status_addr = CVMX_PCSX_INTX_REG(0,1);
4612 info.status_mask = 1ull<<8 /* rxlock */;
4613 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
4614 info.enable_mask = 1ull<<8 /* rxlock_en */;
4616 info.group = CVMX_ERROR_GROUP_ETHERNET;
4617 info.group_index = 16;
4618 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4619 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4620 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
4621 info.func = __cvmx_error_display;
4622 info.user_info = (long)
4623 "ERROR PCSX_INTX_REG(0,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
4625 " Cannot fire in loopback1 mode\n";
4626 fail |= cvmx_error_add(&info);
4628 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4629 info.status_addr = CVMX_PCSX_INTX_REG(0,1);
4630 info.status_mask = 1ull<<9 /* an_bad */;
4631 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
4632 info.enable_mask = 1ull<<9 /* an_bad_en */;
4634 info.group = CVMX_ERROR_GROUP_ETHERNET;
4635 info.group_index = 16;
4636 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4637 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4638 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
4639 info.func = __cvmx_error_display;
4640 info.user_info = (long)
4641 "ERROR PCSX_INTX_REG(0,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
4642 " state. Should never be set during normal operation\n";
4643 fail |= cvmx_error_add(&info);
4645 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4646 info.status_addr = CVMX_PCSX_INTX_REG(0,1);
4647 info.status_mask = 1ull<<10 /* sync_bad */;
4648 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
4649 info.enable_mask = 1ull<<10 /* sync_bad_en */;
4651 info.group = CVMX_ERROR_GROUP_ETHERNET;
4652 info.group_index = 16;
4653 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4654 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4655 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
4656 info.func = __cvmx_error_display;
4657 info.user_info = (long)
4658 "ERROR PCSX_INTX_REG(0,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
4659 " state. Should never be set during normal operation\n";
4660 fail |= cvmx_error_add(&info);
4662 /* CVMX_PCSX_INTX_REG(1,1) */
4663 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4664 info.status_addr = CVMX_PCSX_INTX_REG(1,1);
4665 info.status_mask = 1ull<<2 /* an_err */;
4666 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
4667 info.enable_mask = 1ull<<2 /* an_err_en */;
4669 info.group = CVMX_ERROR_GROUP_ETHERNET;
4670 info.group_index = 17;
4671 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4672 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4673 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
4674 info.func = __cvmx_error_display;
4675 info.user_info = (long)
4676 "ERROR PCSX_INTX_REG(1,1)[AN_ERR]: AN Error, AN resolution function failed\n";
4677 fail |= cvmx_error_add(&info);
4679 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4680 info.status_addr = CVMX_PCSX_INTX_REG(1,1);
4681 info.status_mask = 1ull<<3 /* txfifu */;
4682 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
4683 info.enable_mask = 1ull<<3 /* txfifu_en */;
4685 info.group = CVMX_ERROR_GROUP_ETHERNET;
4686 info.group_index = 17;
4687 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4688 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4689 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
4690 info.func = __cvmx_error_display;
4691 info.user_info = (long)
4692 "ERROR PCSX_INTX_REG(1,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
4694 fail |= cvmx_error_add(&info);
4696 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4697 info.status_addr = CVMX_PCSX_INTX_REG(1,1);
4698 info.status_mask = 1ull<<4 /* txfifo */;
4699 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
4700 info.enable_mask = 1ull<<4 /* txfifo_en */;
4702 info.group = CVMX_ERROR_GROUP_ETHERNET;
4703 info.group_index = 17;
4704 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4705 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4706 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
4707 info.func = __cvmx_error_display;
4708 info.user_info = (long)
4709 "ERROR PCSX_INTX_REG(1,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
4711 fail |= cvmx_error_add(&info);
4713 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4714 info.status_addr = CVMX_PCSX_INTX_REG(1,1);
4715 info.status_mask = 1ull<<5 /* txbad */;
4716 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
4717 info.enable_mask = 1ull<<5 /* txbad_en */;
4719 info.group = CVMX_ERROR_GROUP_ETHERNET;
4720 info.group_index = 17;
4721 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4722 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4723 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
4724 info.func = __cvmx_error_display;
4725 info.user_info = (long)
4726 "ERROR PCSX_INTX_REG(1,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
4727 " state. Should never be set during normal operation\n";
4728 fail |= cvmx_error_add(&info);
4730 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4731 info.status_addr = CVMX_PCSX_INTX_REG(1,1);
4732 info.status_mask = 1ull<<7 /* rxbad */;
4733 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
4734 info.enable_mask = 1ull<<7 /* rxbad_en */;
4736 info.group = CVMX_ERROR_GROUP_ETHERNET;
4737 info.group_index = 17;
4738 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4739 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4740 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
4741 info.func = __cvmx_error_display;
4742 info.user_info = (long)
4743 "ERROR PCSX_INTX_REG(1,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
4744 " state. Should never be set during normal operation\n";
4745 fail |= cvmx_error_add(&info);
4747 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4748 info.status_addr = CVMX_PCSX_INTX_REG(1,1);
4749 info.status_mask = 1ull<<8 /* rxlock */;
4750 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
4751 info.enable_mask = 1ull<<8 /* rxlock_en */;
4753 info.group = CVMX_ERROR_GROUP_ETHERNET;
4754 info.group_index = 17;
4755 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4756 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4757 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
4758 info.func = __cvmx_error_display;
4759 info.user_info = (long)
4760 "ERROR PCSX_INTX_REG(1,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
4762 " Cannot fire in loopback1 mode\n";
4763 fail |= cvmx_error_add(&info);
4765 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4766 info.status_addr = CVMX_PCSX_INTX_REG(1,1);
4767 info.status_mask = 1ull<<9 /* an_bad */;
4768 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
4769 info.enable_mask = 1ull<<9 /* an_bad_en */;
4771 info.group = CVMX_ERROR_GROUP_ETHERNET;
4772 info.group_index = 17;
4773 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4774 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4775 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
4776 info.func = __cvmx_error_display;
4777 info.user_info = (long)
4778 "ERROR PCSX_INTX_REG(1,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
4779 " state. Should never be set during normal operation\n";
4780 fail |= cvmx_error_add(&info);
4782 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4783 info.status_addr = CVMX_PCSX_INTX_REG(1,1);
4784 info.status_mask = 1ull<<10 /* sync_bad */;
4785 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
4786 info.enable_mask = 1ull<<10 /* sync_bad_en */;
4788 info.group = CVMX_ERROR_GROUP_ETHERNET;
4789 info.group_index = 17;
4790 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4791 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4792 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
4793 info.func = __cvmx_error_display;
4794 info.user_info = (long)
4795 "ERROR PCSX_INTX_REG(1,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
4796 " state. Should never be set during normal operation\n";
4797 fail |= cvmx_error_add(&info);
4799 /* CVMX_PCSX_INTX_REG(2,1) */
4800 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4801 info.status_addr = CVMX_PCSX_INTX_REG(2,1);
4802 info.status_mask = 1ull<<2 /* an_err */;
4803 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
4804 info.enable_mask = 1ull<<2 /* an_err_en */;
4806 info.group = CVMX_ERROR_GROUP_ETHERNET;
4807 info.group_index = 18;
4808 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4809 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4810 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
4811 info.func = __cvmx_error_display;
4812 info.user_info = (long)
4813 "ERROR PCSX_INTX_REG(2,1)[AN_ERR]: AN Error, AN resolution function failed\n";
4814 fail |= cvmx_error_add(&info);
4816 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4817 info.status_addr = CVMX_PCSX_INTX_REG(2,1);
4818 info.status_mask = 1ull<<3 /* txfifu */;
4819 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
4820 info.enable_mask = 1ull<<3 /* txfifu_en */;
4822 info.group = CVMX_ERROR_GROUP_ETHERNET;
4823 info.group_index = 18;
4824 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4825 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4826 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
4827 info.func = __cvmx_error_display;
4828 info.user_info = (long)
4829 "ERROR PCSX_INTX_REG(2,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
4831 fail |= cvmx_error_add(&info);
4833 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4834 info.status_addr = CVMX_PCSX_INTX_REG(2,1);
4835 info.status_mask = 1ull<<4 /* txfifo */;
4836 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
4837 info.enable_mask = 1ull<<4 /* txfifo_en */;
4839 info.group = CVMX_ERROR_GROUP_ETHERNET;
4840 info.group_index = 18;
4841 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4842 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4843 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
4844 info.func = __cvmx_error_display;
4845 info.user_info = (long)
4846 "ERROR PCSX_INTX_REG(2,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
4848 fail |= cvmx_error_add(&info);
4850 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4851 info.status_addr = CVMX_PCSX_INTX_REG(2,1);
4852 info.status_mask = 1ull<<5 /* txbad */;
4853 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
4854 info.enable_mask = 1ull<<5 /* txbad_en */;
4856 info.group = CVMX_ERROR_GROUP_ETHERNET;
4857 info.group_index = 18;
4858 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4859 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4860 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
4861 info.func = __cvmx_error_display;
4862 info.user_info = (long)
4863 "ERROR PCSX_INTX_REG(2,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
4864 " state. Should never be set during normal operation\n";
4865 fail |= cvmx_error_add(&info);
4867 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4868 info.status_addr = CVMX_PCSX_INTX_REG(2,1);
4869 info.status_mask = 1ull<<7 /* rxbad */;
4870 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
4871 info.enable_mask = 1ull<<7 /* rxbad_en */;
4873 info.group = CVMX_ERROR_GROUP_ETHERNET;
4874 info.group_index = 18;
4875 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4876 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4877 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
4878 info.func = __cvmx_error_display;
4879 info.user_info = (long)
4880 "ERROR PCSX_INTX_REG(2,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
4881 " state. Should never be set during normal operation\n";
4882 fail |= cvmx_error_add(&info);
4884 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4885 info.status_addr = CVMX_PCSX_INTX_REG(2,1);
4886 info.status_mask = 1ull<<8 /* rxlock */;
4887 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
4888 info.enable_mask = 1ull<<8 /* rxlock_en */;
4890 info.group = CVMX_ERROR_GROUP_ETHERNET;
4891 info.group_index = 18;
4892 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4893 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4894 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
4895 info.func = __cvmx_error_display;
4896 info.user_info = (long)
4897 "ERROR PCSX_INTX_REG(2,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
4899 " Cannot fire in loopback1 mode\n";
4900 fail |= cvmx_error_add(&info);
4902 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4903 info.status_addr = CVMX_PCSX_INTX_REG(2,1);
4904 info.status_mask = 1ull<<9 /* an_bad */;
4905 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
4906 info.enable_mask = 1ull<<9 /* an_bad_en */;
4908 info.group = CVMX_ERROR_GROUP_ETHERNET;
4909 info.group_index = 18;
4910 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4911 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4912 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
4913 info.func = __cvmx_error_display;
4914 info.user_info = (long)
4915 "ERROR PCSX_INTX_REG(2,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
4916 " state. Should never be set during normal operation\n";
4917 fail |= cvmx_error_add(&info);
4919 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4920 info.status_addr = CVMX_PCSX_INTX_REG(2,1);
4921 info.status_mask = 1ull<<10 /* sync_bad */;
4922 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
4923 info.enable_mask = 1ull<<10 /* sync_bad_en */;
4925 info.group = CVMX_ERROR_GROUP_ETHERNET;
4926 info.group_index = 18;
4927 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4928 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4929 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
4930 info.func = __cvmx_error_display;
4931 info.user_info = (long)
4932 "ERROR PCSX_INTX_REG(2,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
4933 " state. Should never be set during normal operation\n";
4934 fail |= cvmx_error_add(&info);
4936 /* CVMX_PCSX_INTX_REG(3,1) */
4937 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4938 info.status_addr = CVMX_PCSX_INTX_REG(3,1);
4939 info.status_mask = 1ull<<2 /* an_err */;
4940 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
4941 info.enable_mask = 1ull<<2 /* an_err_en */;
4943 info.group = CVMX_ERROR_GROUP_ETHERNET;
4944 info.group_index = 19;
4945 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4946 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4947 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
4948 info.func = __cvmx_error_display;
4949 info.user_info = (long)
4950 "ERROR PCSX_INTX_REG(3,1)[AN_ERR]: AN Error, AN resolution function failed\n";
4951 fail |= cvmx_error_add(&info);
4953 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4954 info.status_addr = CVMX_PCSX_INTX_REG(3,1);
4955 info.status_mask = 1ull<<3 /* txfifu */;
4956 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
4957 info.enable_mask = 1ull<<3 /* txfifu_en */;
4959 info.group = CVMX_ERROR_GROUP_ETHERNET;
4960 info.group_index = 19;
4961 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4962 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4963 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
4964 info.func = __cvmx_error_display;
4965 info.user_info = (long)
4966 "ERROR PCSX_INTX_REG(3,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
4968 fail |= cvmx_error_add(&info);
4970 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4971 info.status_addr = CVMX_PCSX_INTX_REG(3,1);
4972 info.status_mask = 1ull<<4 /* txfifo */;
4973 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
4974 info.enable_mask = 1ull<<4 /* txfifo_en */;
4976 info.group = CVMX_ERROR_GROUP_ETHERNET;
4977 info.group_index = 19;
4978 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4979 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4980 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
4981 info.func = __cvmx_error_display;
4982 info.user_info = (long)
4983 "ERROR PCSX_INTX_REG(3,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
4985 fail |= cvmx_error_add(&info);
4987 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4988 info.status_addr = CVMX_PCSX_INTX_REG(3,1);
4989 info.status_mask = 1ull<<5 /* txbad */;
4990 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
4991 info.enable_mask = 1ull<<5 /* txbad_en */;
4993 info.group = CVMX_ERROR_GROUP_ETHERNET;
4994 info.group_index = 19;
4995 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4996 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4997 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
4998 info.func = __cvmx_error_display;
4999 info.user_info = (long)
5000 "ERROR PCSX_INTX_REG(3,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
5001 " state. Should never be set during normal operation\n";
5002 fail |= cvmx_error_add(&info);
5004 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5005 info.status_addr = CVMX_PCSX_INTX_REG(3,1);
5006 info.status_mask = 1ull<<7 /* rxbad */;
5007 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
5008 info.enable_mask = 1ull<<7 /* rxbad_en */;
5010 info.group = CVMX_ERROR_GROUP_ETHERNET;
5011 info.group_index = 19;
5012 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5013 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5014 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5015 info.func = __cvmx_error_display;
5016 info.user_info = (long)
5017 "ERROR PCSX_INTX_REG(3,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
5018 " state. Should never be set during normal operation\n";
5019 fail |= cvmx_error_add(&info);
5021 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5022 info.status_addr = CVMX_PCSX_INTX_REG(3,1);
5023 info.status_mask = 1ull<<8 /* rxlock */;
5024 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
5025 info.enable_mask = 1ull<<8 /* rxlock_en */;
5027 info.group = CVMX_ERROR_GROUP_ETHERNET;
5028 info.group_index = 19;
5029 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5030 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5031 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5032 info.func = __cvmx_error_display;
5033 info.user_info = (long)
5034 "ERROR PCSX_INTX_REG(3,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
5036 " Cannot fire in loopback1 mode\n";
5037 fail |= cvmx_error_add(&info);
5039 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5040 info.status_addr = CVMX_PCSX_INTX_REG(3,1);
5041 info.status_mask = 1ull<<9 /* an_bad */;
5042 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
5043 info.enable_mask = 1ull<<9 /* an_bad_en */;
5045 info.group = CVMX_ERROR_GROUP_ETHERNET;
5046 info.group_index = 19;
5047 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5048 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5049 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5050 info.func = __cvmx_error_display;
5051 info.user_info = (long)
5052 "ERROR PCSX_INTX_REG(3,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
5053 " state. Should never be set during normal operation\n";
5054 fail |= cvmx_error_add(&info);
5056 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5057 info.status_addr = CVMX_PCSX_INTX_REG(3,1);
5058 info.status_mask = 1ull<<10 /* sync_bad */;
5059 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
5060 info.enable_mask = 1ull<<10 /* sync_bad_en */;
5062 info.group = CVMX_ERROR_GROUP_ETHERNET;
5063 info.group_index = 19;
5064 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5065 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5066 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5067 info.func = __cvmx_error_display;
5068 info.user_info = (long)
5069 "ERROR PCSX_INTX_REG(3,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
5070 " state. Should never be set during normal operation\n";
5071 fail |= cvmx_error_add(&info);
5073 /* CVMX_PCSXX_INT_REG(1) */
5074 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5075 info.status_addr = CVMX_PCSXX_INT_REG(1);
5076 info.status_mask = 1ull<<0 /* txflt */;
5077 info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
5078 info.enable_mask = 1ull<<0 /* txflt_en */;
5080 info.group = CVMX_ERROR_GROUP_ETHERNET;
5081 info.group_index = 16;
5082 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5083 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5084 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5085 info.func = __cvmx_error_display;
5086 info.user_info = (long)
5087 "ERROR PCSXX_INT_REG(1)[TXFLT]: None defined at this time, always 0x0\n";
5088 fail |= cvmx_error_add(&info);
5090 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5091 info.status_addr = CVMX_PCSXX_INT_REG(1);
5092 info.status_mask = 1ull<<1 /* rxbad */;
5093 info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
5094 info.enable_mask = 1ull<<1 /* rxbad_en */;
5096 info.group = CVMX_ERROR_GROUP_ETHERNET;
5097 info.group_index = 16;
5098 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5099 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5100 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5101 info.func = __cvmx_error_display;
5102 info.user_info = (long)
5103 "ERROR PCSXX_INT_REG(1)[RXBAD]: Set when RX state machine in bad state\n";
5104 fail |= cvmx_error_add(&info);
5106 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5107 info.status_addr = CVMX_PCSXX_INT_REG(1);
5108 info.status_mask = 1ull<<2 /* rxsynbad */;
5109 info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
5110 info.enable_mask = 1ull<<2 /* rxsynbad_en */;
5112 info.group = CVMX_ERROR_GROUP_ETHERNET;
5113 info.group_index = 16;
5114 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5115 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5116 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5117 info.func = __cvmx_error_display;
5118 info.user_info = (long)
5119 "ERROR PCSXX_INT_REG(1)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
5120 " in one of the 4 xaui lanes\n";
5121 fail |= cvmx_error_add(&info);
5123 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5124 info.status_addr = CVMX_PCSXX_INT_REG(1);
5125 info.status_mask = 1ull<<4 /* synlos */;
5126 info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
5127 info.enable_mask = 1ull<<4 /* synlos_en */;
5129 info.group = CVMX_ERROR_GROUP_ETHERNET;
5130 info.group_index = 16;
5131 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5132 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5133 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5134 info.func = __cvmx_error_display;
5135 info.user_info = (long)
5136 "ERROR PCSXX_INT_REG(1)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n";
5137 fail |= cvmx_error_add(&info);
5139 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5140 info.status_addr = CVMX_PCSXX_INT_REG(1);
5141 info.status_mask = 1ull<<5 /* algnlos */;
5142 info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
5143 info.enable_mask = 1ull<<5 /* algnlos_en */;
5145 info.group = CVMX_ERROR_GROUP_ETHERNET;
5146 info.group_index = 16;
5147 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5148 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5149 info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
5150 info.func = __cvmx_error_display;
5151 info.user_info = (long)
5152 "ERROR PCSXX_INT_REG(1)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
5153 fail |= cvmx_error_add(&info);
5155 /* CVMX_PCSX_INTX_REG(0,0) */
5156 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5157 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
5158 info.status_mask = 1ull<<2 /* an_err */;
5159 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
5160 info.enable_mask = 1ull<<2 /* an_err_en */;
5162 info.group = CVMX_ERROR_GROUP_ETHERNET;
5163 info.group_index = 0;
5164 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5165 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5166 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5167 info.func = __cvmx_error_display;
5168 info.user_info = (long)
5169 "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n";
5170 fail |= cvmx_error_add(&info);
5172 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5173 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
5174 info.status_mask = 1ull<<3 /* txfifu */;
5175 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
5176 info.enable_mask = 1ull<<3 /* txfifu_en */;
5178 info.group = CVMX_ERROR_GROUP_ETHERNET;
5179 info.group_index = 0;
5180 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5181 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5182 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5183 info.func = __cvmx_error_display;
5184 info.user_info = (long)
5185 "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
5187 fail |= cvmx_error_add(&info);
5189 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5190 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
5191 info.status_mask = 1ull<<4 /* txfifo */;
5192 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
5193 info.enable_mask = 1ull<<4 /* txfifo_en */;
5195 info.group = CVMX_ERROR_GROUP_ETHERNET;
5196 info.group_index = 0;
5197 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5198 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5199 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5200 info.func = __cvmx_error_display;
5201 info.user_info = (long)
5202 "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
5204 fail |= cvmx_error_add(&info);
5206 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5207 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
5208 info.status_mask = 1ull<<5 /* txbad */;
5209 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
5210 info.enable_mask = 1ull<<5 /* txbad_en */;
5212 info.group = CVMX_ERROR_GROUP_ETHERNET;
5213 info.group_index = 0;
5214 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5215 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5216 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5217 info.func = __cvmx_error_display;
5218 info.user_info = (long)
5219 "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
5220 " state. Should never be set during normal operation\n";
5221 fail |= cvmx_error_add(&info);
5223 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5224 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
5225 info.status_mask = 1ull<<7 /* rxbad */;
5226 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
5227 info.enable_mask = 1ull<<7 /* rxbad_en */;
5229 info.group = CVMX_ERROR_GROUP_ETHERNET;
5230 info.group_index = 0;
5231 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5232 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5233 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5234 info.func = __cvmx_error_display;
5235 info.user_info = (long)
5236 "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
5237 " state. Should never be set during normal operation\n";
5238 fail |= cvmx_error_add(&info);
5240 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5241 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
5242 info.status_mask = 1ull<<8 /* rxlock */;
5243 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
5244 info.enable_mask = 1ull<<8 /* rxlock_en */;
5246 info.group = CVMX_ERROR_GROUP_ETHERNET;
5247 info.group_index = 0;
5248 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5249 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5250 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5251 info.func = __cvmx_error_display;
5252 info.user_info = (long)
5253 "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
5255 " Cannot fire in loopback1 mode\n";
5256 fail |= cvmx_error_add(&info);
5258 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5259 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
5260 info.status_mask = 1ull<<9 /* an_bad */;
5261 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
5262 info.enable_mask = 1ull<<9 /* an_bad_en */;
5264 info.group = CVMX_ERROR_GROUP_ETHERNET;
5265 info.group_index = 0;
5266 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5267 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5268 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5269 info.func = __cvmx_error_display;
5270 info.user_info = (long)
5271 "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
5272 " state. Should never be set during normal operation\n";
5273 fail |= cvmx_error_add(&info);
5275 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5276 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
5277 info.status_mask = 1ull<<10 /* sync_bad */;
5278 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
5279 info.enable_mask = 1ull<<10 /* sync_bad_en */;
5281 info.group = CVMX_ERROR_GROUP_ETHERNET;
5282 info.group_index = 0;
5283 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5284 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5285 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5286 info.func = __cvmx_error_display;
5287 info.user_info = (long)
5288 "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
5289 " state. Should never be set during normal operation\n";
5290 fail |= cvmx_error_add(&info);
5292 /* CVMX_PCSX_INTX_REG(1,0) */
5293 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5294 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
5295 info.status_mask = 1ull<<2 /* an_err */;
5296 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
5297 info.enable_mask = 1ull<<2 /* an_err_en */;
5299 info.group = CVMX_ERROR_GROUP_ETHERNET;
5300 info.group_index = 1;
5301 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5302 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5303 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5304 info.func = __cvmx_error_display;
5305 info.user_info = (long)
5306 "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n";
5307 fail |= cvmx_error_add(&info);
5309 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5310 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
5311 info.status_mask = 1ull<<3 /* txfifu */;
5312 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
5313 info.enable_mask = 1ull<<3 /* txfifu_en */;
5315 info.group = CVMX_ERROR_GROUP_ETHERNET;
5316 info.group_index = 1;
5317 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5318 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5319 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5320 info.func = __cvmx_error_display;
5321 info.user_info = (long)
5322 "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
5324 fail |= cvmx_error_add(&info);
5326 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5327 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
5328 info.status_mask = 1ull<<4 /* txfifo */;
5329 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
5330 info.enable_mask = 1ull<<4 /* txfifo_en */;
5332 info.group = CVMX_ERROR_GROUP_ETHERNET;
5333 info.group_index = 1;
5334 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5335 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5336 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5337 info.func = __cvmx_error_display;
5338 info.user_info = (long)
5339 "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
5341 fail |= cvmx_error_add(&info);
5343 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5344 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
5345 info.status_mask = 1ull<<5 /* txbad */;
5346 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
5347 info.enable_mask = 1ull<<5 /* txbad_en */;
5349 info.group = CVMX_ERROR_GROUP_ETHERNET;
5350 info.group_index = 1;
5351 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5352 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5353 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5354 info.func = __cvmx_error_display;
5355 info.user_info = (long)
5356 "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
5357 " state. Should never be set during normal operation\n";
5358 fail |= cvmx_error_add(&info);
5360 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5361 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
5362 info.status_mask = 1ull<<7 /* rxbad */;
5363 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
5364 info.enable_mask = 1ull<<7 /* rxbad_en */;
5366 info.group = CVMX_ERROR_GROUP_ETHERNET;
5367 info.group_index = 1;
5368 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5369 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5370 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5371 info.func = __cvmx_error_display;
5372 info.user_info = (long)
5373 "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
5374 " state. Should never be set during normal operation\n";
5375 fail |= cvmx_error_add(&info);
5377 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5378 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
5379 info.status_mask = 1ull<<8 /* rxlock */;
5380 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
5381 info.enable_mask = 1ull<<8 /* rxlock_en */;
5383 info.group = CVMX_ERROR_GROUP_ETHERNET;
5384 info.group_index = 1;
5385 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5386 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5387 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5388 info.func = __cvmx_error_display;
5389 info.user_info = (long)
5390 "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
5392 " Cannot fire in loopback1 mode\n";
5393 fail |= cvmx_error_add(&info);
5395 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5396 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
5397 info.status_mask = 1ull<<9 /* an_bad */;
5398 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
5399 info.enable_mask = 1ull<<9 /* an_bad_en */;
5401 info.group = CVMX_ERROR_GROUP_ETHERNET;
5402 info.group_index = 1;
5403 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5404 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5405 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5406 info.func = __cvmx_error_display;
5407 info.user_info = (long)
5408 "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
5409 " state. Should never be set during normal operation\n";
5410 fail |= cvmx_error_add(&info);
5412 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5413 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
5414 info.status_mask = 1ull<<10 /* sync_bad */;
5415 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
5416 info.enable_mask = 1ull<<10 /* sync_bad_en */;
5418 info.group = CVMX_ERROR_GROUP_ETHERNET;
5419 info.group_index = 1;
5420 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5421 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5422 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5423 info.func = __cvmx_error_display;
5424 info.user_info = (long)
5425 "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
5426 " state. Should never be set during normal operation\n";
5427 fail |= cvmx_error_add(&info);
5429 /* CVMX_PCSX_INTX_REG(2,0) */
5430 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5431 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
5432 info.status_mask = 1ull<<2 /* an_err */;
5433 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
5434 info.enable_mask = 1ull<<2 /* an_err_en */;
5436 info.group = CVMX_ERROR_GROUP_ETHERNET;
5437 info.group_index = 2;
5438 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5439 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5440 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5441 info.func = __cvmx_error_display;
5442 info.user_info = (long)
5443 "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n";
5444 fail |= cvmx_error_add(&info);
5446 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5447 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
5448 info.status_mask = 1ull<<3 /* txfifu */;
5449 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
5450 info.enable_mask = 1ull<<3 /* txfifu_en */;
5452 info.group = CVMX_ERROR_GROUP_ETHERNET;
5453 info.group_index = 2;
5454 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5455 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5456 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5457 info.func = __cvmx_error_display;
5458 info.user_info = (long)
5459 "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
5461 fail |= cvmx_error_add(&info);
5463 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5464 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
5465 info.status_mask = 1ull<<4 /* txfifo */;
5466 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
5467 info.enable_mask = 1ull<<4 /* txfifo_en */;
5469 info.group = CVMX_ERROR_GROUP_ETHERNET;
5470 info.group_index = 2;
5471 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5472 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5473 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5474 info.func = __cvmx_error_display;
5475 info.user_info = (long)
5476 "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
5478 fail |= cvmx_error_add(&info);
5480 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5481 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
5482 info.status_mask = 1ull<<5 /* txbad */;
5483 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
5484 info.enable_mask = 1ull<<5 /* txbad_en */;
5486 info.group = CVMX_ERROR_GROUP_ETHERNET;
5487 info.group_index = 2;
5488 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5489 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5490 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5491 info.func = __cvmx_error_display;
5492 info.user_info = (long)
5493 "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
5494 " state. Should never be set during normal operation\n";
5495 fail |= cvmx_error_add(&info);
5497 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5498 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
5499 info.status_mask = 1ull<<7 /* rxbad */;
5500 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
5501 info.enable_mask = 1ull<<7 /* rxbad_en */;
5503 info.group = CVMX_ERROR_GROUP_ETHERNET;
5504 info.group_index = 2;
5505 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5506 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5507 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5508 info.func = __cvmx_error_display;
5509 info.user_info = (long)
5510 "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
5511 " state. Should never be set during normal operation\n";
5512 fail |= cvmx_error_add(&info);
5514 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5515 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
5516 info.status_mask = 1ull<<8 /* rxlock */;
5517 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
5518 info.enable_mask = 1ull<<8 /* rxlock_en */;
5520 info.group = CVMX_ERROR_GROUP_ETHERNET;
5521 info.group_index = 2;
5522 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5523 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5524 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5525 info.func = __cvmx_error_display;
5526 info.user_info = (long)
5527 "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
5529 " Cannot fire in loopback1 mode\n";
5530 fail |= cvmx_error_add(&info);
5532 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5533 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
5534 info.status_mask = 1ull<<9 /* an_bad */;
5535 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
5536 info.enable_mask = 1ull<<9 /* an_bad_en */;
5538 info.group = CVMX_ERROR_GROUP_ETHERNET;
5539 info.group_index = 2;
5540 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5541 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5542 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5543 info.func = __cvmx_error_display;
5544 info.user_info = (long)
5545 "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
5546 " state. Should never be set during normal operation\n";
5547 fail |= cvmx_error_add(&info);
5549 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5550 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
5551 info.status_mask = 1ull<<10 /* sync_bad */;
5552 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
5553 info.enable_mask = 1ull<<10 /* sync_bad_en */;
5555 info.group = CVMX_ERROR_GROUP_ETHERNET;
5556 info.group_index = 2;
5557 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5558 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5559 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5560 info.func = __cvmx_error_display;
5561 info.user_info = (long)
5562 "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
5563 " state. Should never be set during normal operation\n";
5564 fail |= cvmx_error_add(&info);
5566 /* CVMX_PCSX_INTX_REG(3,0) */
5567 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5568 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
5569 info.status_mask = 1ull<<2 /* an_err */;
5570 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
5571 info.enable_mask = 1ull<<2 /* an_err_en */;
5573 info.group = CVMX_ERROR_GROUP_ETHERNET;
5574 info.group_index = 3;
5575 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5576 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5577 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5578 info.func = __cvmx_error_display;
5579 info.user_info = (long)
5580 "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n";
5581 fail |= cvmx_error_add(&info);
5583 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5584 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
5585 info.status_mask = 1ull<<3 /* txfifu */;
5586 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
5587 info.enable_mask = 1ull<<3 /* txfifu_en */;
5589 info.group = CVMX_ERROR_GROUP_ETHERNET;
5590 info.group_index = 3;
5591 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5592 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5593 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5594 info.func = __cvmx_error_display;
5595 info.user_info = (long)
5596 "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
5598 fail |= cvmx_error_add(&info);
5600 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5601 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
5602 info.status_mask = 1ull<<4 /* txfifo */;
5603 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
5604 info.enable_mask = 1ull<<4 /* txfifo_en */;
5606 info.group = CVMX_ERROR_GROUP_ETHERNET;
5607 info.group_index = 3;
5608 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5609 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5610 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5611 info.func = __cvmx_error_display;
5612 info.user_info = (long)
5613 "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
5615 fail |= cvmx_error_add(&info);
5617 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5618 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
5619 info.status_mask = 1ull<<5 /* txbad */;
5620 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
5621 info.enable_mask = 1ull<<5 /* txbad_en */;
5623 info.group = CVMX_ERROR_GROUP_ETHERNET;
5624 info.group_index = 3;
5625 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5626 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5627 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5628 info.func = __cvmx_error_display;
5629 info.user_info = (long)
5630 "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
5631 " state. Should never be set during normal operation\n";
5632 fail |= cvmx_error_add(&info);
5634 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5635 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
5636 info.status_mask = 1ull<<7 /* rxbad */;
5637 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
5638 info.enable_mask = 1ull<<7 /* rxbad_en */;
5640 info.group = CVMX_ERROR_GROUP_ETHERNET;
5641 info.group_index = 3;
5642 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5643 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5644 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5645 info.func = __cvmx_error_display;
5646 info.user_info = (long)
5647 "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
5648 " state. Should never be set during normal operation\n";
5649 fail |= cvmx_error_add(&info);
5651 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5652 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
5653 info.status_mask = 1ull<<8 /* rxlock */;
5654 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
5655 info.enable_mask = 1ull<<8 /* rxlock_en */;
5657 info.group = CVMX_ERROR_GROUP_ETHERNET;
5658 info.group_index = 3;
5659 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5660 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5661 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5662 info.func = __cvmx_error_display;
5663 info.user_info = (long)
5664 "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
5666 " Cannot fire in loopback1 mode\n";
5667 fail |= cvmx_error_add(&info);
5669 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5670 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
5671 info.status_mask = 1ull<<9 /* an_bad */;
5672 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
5673 info.enable_mask = 1ull<<9 /* an_bad_en */;
5675 info.group = CVMX_ERROR_GROUP_ETHERNET;
5676 info.group_index = 3;
5677 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5678 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5679 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5680 info.func = __cvmx_error_display;
5681 info.user_info = (long)
5682 "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
5683 " state. Should never be set during normal operation\n";
5684 fail |= cvmx_error_add(&info);
5686 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5687 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
5688 info.status_mask = 1ull<<10 /* sync_bad */;
5689 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
5690 info.enable_mask = 1ull<<10 /* sync_bad_en */;
5692 info.group = CVMX_ERROR_GROUP_ETHERNET;
5693 info.group_index = 3;
5694 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5695 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5696 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5697 info.func = __cvmx_error_display;
5698 info.user_info = (long)
5699 "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
5700 " state. Should never be set during normal operation\n";
5701 fail |= cvmx_error_add(&info);
5703 /* CVMX_PCSXX_INT_REG(0) */
5704 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5705 info.status_addr = CVMX_PCSXX_INT_REG(0);
5706 info.status_mask = 1ull<<0 /* txflt */;
5707 info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
5708 info.enable_mask = 1ull<<0 /* txflt_en */;
5710 info.group = CVMX_ERROR_GROUP_ETHERNET;
5711 info.group_index = 0;
5712 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5713 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5714 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5715 info.func = __cvmx_error_display;
5716 info.user_info = (long)
5717 "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n";
5718 fail |= cvmx_error_add(&info);
5720 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5721 info.status_addr = CVMX_PCSXX_INT_REG(0);
5722 info.status_mask = 1ull<<1 /* rxbad */;
5723 info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
5724 info.enable_mask = 1ull<<1 /* rxbad_en */;
5726 info.group = CVMX_ERROR_GROUP_ETHERNET;
5727 info.group_index = 0;
5728 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5729 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5730 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5731 info.func = __cvmx_error_display;
5732 info.user_info = (long)
5733 "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n";
5734 fail |= cvmx_error_add(&info);
5736 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5737 info.status_addr = CVMX_PCSXX_INT_REG(0);
5738 info.status_mask = 1ull<<2 /* rxsynbad */;
5739 info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
5740 info.enable_mask = 1ull<<2 /* rxsynbad_en */;
5742 info.group = CVMX_ERROR_GROUP_ETHERNET;
5743 info.group_index = 0;
5744 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5745 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5746 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5747 info.func = __cvmx_error_display;
5748 info.user_info = (long)
5749 "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
5750 " in one of the 4 xaui lanes\n";
5751 fail |= cvmx_error_add(&info);
5753 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5754 info.status_addr = CVMX_PCSXX_INT_REG(0);
5755 info.status_mask = 1ull<<4 /* synlos */;
5756 info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
5757 info.enable_mask = 1ull<<4 /* synlos_en */;
5759 info.group = CVMX_ERROR_GROUP_ETHERNET;
5760 info.group_index = 0;
5761 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5762 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5763 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5764 info.func = __cvmx_error_display;
5765 info.user_info = (long)
5766 "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n";
5767 fail |= cvmx_error_add(&info);
5769 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5770 info.status_addr = CVMX_PCSXX_INT_REG(0);
5771 info.status_mask = 1ull<<5 /* algnlos */;
5772 info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
5773 info.enable_mask = 1ull<<5 /* algnlos_en */;
5775 info.group = CVMX_ERROR_GROUP_ETHERNET;
5776 info.group_index = 0;
5777 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5778 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5779 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5780 info.func = __cvmx_error_display;
5781 info.user_info = (long)
5782 "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
5783 fail |= cvmx_error_add(&info);
5785 /* CVMX_KEY_INT_SUM */
5786 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5787 info.status_addr = CVMX_KEY_INT_SUM;
5788 info.status_mask = 1ull<<0 /* ked0_sbe */;
5789 info.enable_addr = CVMX_KEY_INT_ENB;
5790 info.enable_mask = 1ull<<0 /* ked0_sbe */;
5792 info.group = CVMX_ERROR_GROUP_INTERNAL;
5793 info.group_index = 0;
5794 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5795 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5796 info.parent.status_mask = 1ull<<4 /* key */;
5797 info.func = __cvmx_error_display;
5798 info.user_info = (long)
5799 "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
5801 fail |= cvmx_error_add(&info);
5803 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5804 info.status_addr = CVMX_KEY_INT_SUM;
5805 info.status_mask = 1ull<<1 /* ked0_dbe */;
5806 info.enable_addr = CVMX_KEY_INT_ENB;
5807 info.enable_mask = 1ull<<1 /* ked0_dbe */;
5809 info.group = CVMX_ERROR_GROUP_INTERNAL;
5810 info.group_index = 0;
5811 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5812 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5813 info.parent.status_mask = 1ull<<4 /* key */;
5814 info.func = __cvmx_error_display;
5815 info.user_info = (long)
5816 "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
5818 fail |= cvmx_error_add(&info);
5820 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5821 info.status_addr = CVMX_KEY_INT_SUM;
5822 info.status_mask = 1ull<<2 /* ked1_sbe */;
5823 info.enable_addr = CVMX_KEY_INT_ENB;
5824 info.enable_mask = 1ull<<2 /* ked1_sbe */;
5826 info.group = CVMX_ERROR_GROUP_INTERNAL;
5827 info.group_index = 0;
5828 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5829 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5830 info.parent.status_mask = 1ull<<4 /* key */;
5831 info.func = __cvmx_error_display;
5832 info.user_info = (long)
5833 "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
5835 fail |= cvmx_error_add(&info);
5837 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5838 info.status_addr = CVMX_KEY_INT_SUM;
5839 info.status_mask = 1ull<<3 /* ked1_dbe */;
5840 info.enable_addr = CVMX_KEY_INT_ENB;
5841 info.enable_mask = 1ull<<3 /* ked1_dbe */;
5843 info.group = CVMX_ERROR_GROUP_INTERNAL;
5844 info.group_index = 0;
5845 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5846 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5847 info.parent.status_mask = 1ull<<4 /* key */;
5848 info.func = __cvmx_error_display;
5849 info.user_info = (long)
5850 "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
5852 fail |= cvmx_error_add(&info);
5854 /* CVMX_MIO_BOOT_ERR */
5855 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5856 info.status_addr = CVMX_MIO_BOOT_ERR;
5857 info.status_mask = 1ull<<0 /* adr_err */;
5858 info.enable_addr = CVMX_MIO_BOOT_INT;
5859 info.enable_mask = 1ull<<0 /* adr_int */;
5861 info.group = CVMX_ERROR_GROUP_INTERNAL;
5862 info.group_index = 0;
5863 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5864 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5865 info.parent.status_mask = 1ull<<0 /* mio */;
5866 info.func = __cvmx_error_display;
5867 info.user_info = (long)
5868 "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
5869 fail |= cvmx_error_add(&info);
5871 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5872 info.status_addr = CVMX_MIO_BOOT_ERR;
5873 info.status_mask = 1ull<<1 /* wait_err */;
5874 info.enable_addr = CVMX_MIO_BOOT_INT;
5875 info.enable_mask = 1ull<<1 /* wait_int */;
5877 info.group = CVMX_ERROR_GROUP_INTERNAL;
5878 info.group_index = 0;
5879 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5880 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5881 info.parent.status_mask = 1ull<<0 /* mio */;
5882 info.func = __cvmx_error_display;
5883 info.user_info = (long)
5884 "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
5885 fail |= cvmx_error_add(&info);
5887 /* CVMX_PIP_INT_REG */
5888 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5889 info.status_addr = CVMX_PIP_INT_REG;
5890 info.status_mask = 1ull<<3 /* prtnxa */;
5891 info.enable_addr = CVMX_PIP_INT_EN;
5892 info.enable_mask = 1ull<<3 /* prtnxa */;
5894 info.group = CVMX_ERROR_GROUP_INTERNAL;
5895 info.group_index = 0;
5896 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5897 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5898 info.parent.status_mask = 1ull<<20 /* pip */;
5899 info.func = __cvmx_error_display;
5900 info.user_info = (long)
5901 "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
5902 fail |= cvmx_error_add(&info);
5904 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5905 info.status_addr = CVMX_PIP_INT_REG;
5906 info.status_mask = 1ull<<4 /* badtag */;
5907 info.enable_addr = CVMX_PIP_INT_EN;
5908 info.enable_mask = 1ull<<4 /* badtag */;
5910 info.group = CVMX_ERROR_GROUP_INTERNAL;
5911 info.group_index = 0;
5912 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5913 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5914 info.parent.status_mask = 1ull<<20 /* pip */;
5915 info.func = __cvmx_error_display;
5916 info.user_info = (long)
5917 "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
5918 fail |= cvmx_error_add(&info);
5920 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5921 info.status_addr = CVMX_PIP_INT_REG;
5922 info.status_mask = 1ull<<5 /* skprunt */;
5923 info.enable_addr = CVMX_PIP_INT_EN;
5924 info.enable_mask = 1ull<<5 /* skprunt */;
5926 info.group = CVMX_ERROR_GROUP_INTERNAL;
5927 info.group_index = 0;
5928 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5929 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5930 info.parent.status_mask = 1ull<<20 /* pip */;
5931 info.func = __cvmx_error_display;
5932 info.user_info = (long)
5933 "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
5934 " This interrupt can occur with received PARTIAL\n"
5935 " packets that are truncated to SKIP bytes or\n"
5937 fail |= cvmx_error_add(&info);
5939 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5940 info.status_addr = CVMX_PIP_INT_REG;
5941 info.status_mask = 1ull<<6 /* todoovr */;
5942 info.enable_addr = CVMX_PIP_INT_EN;
5943 info.enable_mask = 1ull<<6 /* todoovr */;
5945 info.group = CVMX_ERROR_GROUP_INTERNAL;
5946 info.group_index = 0;
5947 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5948 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5949 info.parent.status_mask = 1ull<<20 /* pip */;
5950 info.func = __cvmx_error_display;
5951 info.user_info = (long)
5952 "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
5953 fail |= cvmx_error_add(&info);
5955 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5956 info.status_addr = CVMX_PIP_INT_REG;
5957 info.status_mask = 1ull<<7 /* feperr */;
5958 info.enable_addr = CVMX_PIP_INT_EN;
5959 info.enable_mask = 1ull<<7 /* feperr */;
5961 info.group = CVMX_ERROR_GROUP_INTERNAL;
5962 info.group_index = 0;
5963 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5964 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5965 info.parent.status_mask = 1ull<<20 /* pip */;
5966 info.func = __cvmx_error_display;
5967 info.user_info = (long)
5968 "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
5969 fail |= cvmx_error_add(&info);
5971 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5972 info.status_addr = CVMX_PIP_INT_REG;
5973 info.status_mask = 1ull<<8 /* beperr */;
5974 info.enable_addr = CVMX_PIP_INT_EN;
5975 info.enable_mask = 1ull<<8 /* beperr */;
5977 info.group = CVMX_ERROR_GROUP_INTERNAL;
5978 info.group_index = 0;
5979 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5980 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5981 info.parent.status_mask = 1ull<<20 /* pip */;
5982 info.func = __cvmx_error_display;
5983 info.user_info = (long)
5984 "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
5985 fail |= cvmx_error_add(&info);
5987 /* CVMX_FPA_INT_SUM */
5988 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5989 info.status_addr = CVMX_FPA_INT_SUM;
5990 info.status_mask = 1ull<<0 /* fed0_sbe */;
5991 info.enable_addr = CVMX_FPA_INT_ENB;
5992 info.enable_mask = 1ull<<0 /* fed0_sbe */;
5994 info.group = CVMX_ERROR_GROUP_INTERNAL;
5995 info.group_index = 0;
5996 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5997 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5998 info.parent.status_mask = 1ull<<5 /* fpa */;
5999 info.func = __cvmx_error_display;
6000 info.user_info = (long)
6001 "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
6002 fail |= cvmx_error_add(&info);
6004 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6005 info.status_addr = CVMX_FPA_INT_SUM;
6006 info.status_mask = 1ull<<1 /* fed0_dbe */;
6007 info.enable_addr = CVMX_FPA_INT_ENB;
6008 info.enable_mask = 1ull<<1 /* fed0_dbe */;
6010 info.group = CVMX_ERROR_GROUP_INTERNAL;
6011 info.group_index = 0;
6012 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6013 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6014 info.parent.status_mask = 1ull<<5 /* fpa */;
6015 info.func = __cvmx_error_display;
6016 info.user_info = (long)
6017 "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
6018 fail |= cvmx_error_add(&info);
6020 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6021 info.status_addr = CVMX_FPA_INT_SUM;
6022 info.status_mask = 1ull<<2 /* fed1_sbe */;
6023 info.enable_addr = CVMX_FPA_INT_ENB;
6024 info.enable_mask = 1ull<<2 /* fed1_sbe */;
6026 info.group = CVMX_ERROR_GROUP_INTERNAL;
6027 info.group_index = 0;
6028 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6029 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6030 info.parent.status_mask = 1ull<<5 /* fpa */;
6031 info.func = __cvmx_error_display;
6032 info.user_info = (long)
6033 "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
6034 fail |= cvmx_error_add(&info);
6036 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6037 info.status_addr = CVMX_FPA_INT_SUM;
6038 info.status_mask = 1ull<<3 /* fed1_dbe */;
6039 info.enable_addr = CVMX_FPA_INT_ENB;
6040 info.enable_mask = 1ull<<3 /* fed1_dbe */;
6042 info.group = CVMX_ERROR_GROUP_INTERNAL;
6043 info.group_index = 0;
6044 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6045 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6046 info.parent.status_mask = 1ull<<5 /* fpa */;
6047 info.func = __cvmx_error_display;
6048 info.user_info = (long)
6049 "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
6050 fail |= cvmx_error_add(&info);
6052 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6053 info.status_addr = CVMX_FPA_INT_SUM;
6054 info.status_mask = 1ull<<4 /* q0_und */;
6055 info.enable_addr = CVMX_FPA_INT_ENB;
6056 info.enable_mask = 1ull<<4 /* q0_und */;
6058 info.group = CVMX_ERROR_GROUP_INTERNAL;
6059 info.group_index = 0;
6060 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6061 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6062 info.parent.status_mask = 1ull<<5 /* fpa */;
6063 info.func = __cvmx_error_display;
6064 info.user_info = (long)
6065 "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
6067 fail |= cvmx_error_add(&info);
6069 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6070 info.status_addr = CVMX_FPA_INT_SUM;
6071 info.status_mask = 1ull<<5 /* q0_coff */;
6072 info.enable_addr = CVMX_FPA_INT_ENB;
6073 info.enable_mask = 1ull<<5 /* q0_coff */;
6075 info.group = CVMX_ERROR_GROUP_INTERNAL;
6076 info.group_index = 0;
6077 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6078 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6079 info.parent.status_mask = 1ull<<5 /* fpa */;
6080 info.func = __cvmx_error_display;
6081 info.user_info = (long)
6082 "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
6083 " the count available is greater than pointers\n"
6084 " present in the FPA.\n";
6085 fail |= cvmx_error_add(&info);
6087 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6088 info.status_addr = CVMX_FPA_INT_SUM;
6089 info.status_mask = 1ull<<6 /* q0_perr */;
6090 info.enable_addr = CVMX_FPA_INT_ENB;
6091 info.enable_mask = 1ull<<6 /* q0_perr */;
6093 info.group = CVMX_ERROR_GROUP_INTERNAL;
6094 info.group_index = 0;
6095 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6096 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6097 info.parent.status_mask = 1ull<<5 /* fpa */;
6098 info.func = __cvmx_error_display;
6099 info.user_info = (long)
6100 "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
6101 " the L2C does not have the FPA owner ship bit set.\n";
6102 fail |= cvmx_error_add(&info);
6104 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6105 info.status_addr = CVMX_FPA_INT_SUM;
6106 info.status_mask = 1ull<<7 /* q1_und */;
6107 info.enable_addr = CVMX_FPA_INT_ENB;
6108 info.enable_mask = 1ull<<7 /* q1_und */;
6110 info.group = CVMX_ERROR_GROUP_INTERNAL;
6111 info.group_index = 0;
6112 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6113 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6114 info.parent.status_mask = 1ull<<5 /* fpa */;
6115 info.func = __cvmx_error_display;
6116 info.user_info = (long)
6117 "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
6119 fail |= cvmx_error_add(&info);
6121 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6122 info.status_addr = CVMX_FPA_INT_SUM;
6123 info.status_mask = 1ull<<8 /* q1_coff */;
6124 info.enable_addr = CVMX_FPA_INT_ENB;
6125 info.enable_mask = 1ull<<8 /* q1_coff */;
6127 info.group = CVMX_ERROR_GROUP_INTERNAL;
6128 info.group_index = 0;
6129 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6130 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6131 info.parent.status_mask = 1ull<<5 /* fpa */;
6132 info.func = __cvmx_error_display;
6133 info.user_info = (long)
6134 "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
6135 " the count available is greater than pointers\n"
6136 " present in the FPA.\n";
6137 fail |= cvmx_error_add(&info);
6139 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6140 info.status_addr = CVMX_FPA_INT_SUM;
6141 info.status_mask = 1ull<<9 /* q1_perr */;
6142 info.enable_addr = CVMX_FPA_INT_ENB;
6143 info.enable_mask = 1ull<<9 /* q1_perr */;
6145 info.group = CVMX_ERROR_GROUP_INTERNAL;
6146 info.group_index = 0;
6147 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6148 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6149 info.parent.status_mask = 1ull<<5 /* fpa */;
6150 info.func = __cvmx_error_display;
6151 info.user_info = (long)
6152 "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
6153 " the L2C does not have the FPA owner ship bit set.\n";
6154 fail |= cvmx_error_add(&info);
6156 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6157 info.status_addr = CVMX_FPA_INT_SUM;
6158 info.status_mask = 1ull<<10 /* q2_und */;
6159 info.enable_addr = CVMX_FPA_INT_ENB;
6160 info.enable_mask = 1ull<<10 /* q2_und */;
6162 info.group = CVMX_ERROR_GROUP_INTERNAL;
6163 info.group_index = 0;
6164 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6165 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6166 info.parent.status_mask = 1ull<<5 /* fpa */;
6167 info.func = __cvmx_error_display;
6168 info.user_info = (long)
6169 "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
6171 fail |= cvmx_error_add(&info);
6173 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6174 info.status_addr = CVMX_FPA_INT_SUM;
6175 info.status_mask = 1ull<<11 /* q2_coff */;
6176 info.enable_addr = CVMX_FPA_INT_ENB;
6177 info.enable_mask = 1ull<<11 /* q2_coff */;
6179 info.group = CVMX_ERROR_GROUP_INTERNAL;
6180 info.group_index = 0;
6181 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6182 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6183 info.parent.status_mask = 1ull<<5 /* fpa */;
6184 info.func = __cvmx_error_display;
6185 info.user_info = (long)
6186 "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
6187 " the count available is greater than than pointers\n"
6188 " present in the FPA.\n";
6189 fail |= cvmx_error_add(&info);
6191 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6192 info.status_addr = CVMX_FPA_INT_SUM;
6193 info.status_mask = 1ull<<12 /* q2_perr */;
6194 info.enable_addr = CVMX_FPA_INT_ENB;
6195 info.enable_mask = 1ull<<12 /* q2_perr */;
6197 info.group = CVMX_ERROR_GROUP_INTERNAL;
6198 info.group_index = 0;
6199 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6200 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6201 info.parent.status_mask = 1ull<<5 /* fpa */;
6202 info.func = __cvmx_error_display;
6203 info.user_info = (long)
6204 "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
6205 " the L2C does not have the FPA owner ship bit set.\n";
6206 fail |= cvmx_error_add(&info);
6208 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6209 info.status_addr = CVMX_FPA_INT_SUM;
6210 info.status_mask = 1ull<<13 /* q3_und */;
6211 info.enable_addr = CVMX_FPA_INT_ENB;
6212 info.enable_mask = 1ull<<13 /* q3_und */;
6214 info.group = CVMX_ERROR_GROUP_INTERNAL;
6215 info.group_index = 0;
6216 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6217 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6218 info.parent.status_mask = 1ull<<5 /* fpa */;
6219 info.func = __cvmx_error_display;
6220 info.user_info = (long)
6221 "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
6223 fail |= cvmx_error_add(&info);
6225 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6226 info.status_addr = CVMX_FPA_INT_SUM;
6227 info.status_mask = 1ull<<14 /* q3_coff */;
6228 info.enable_addr = CVMX_FPA_INT_ENB;
6229 info.enable_mask = 1ull<<14 /* q3_coff */;
6231 info.group = CVMX_ERROR_GROUP_INTERNAL;
6232 info.group_index = 0;
6233 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6234 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6235 info.parent.status_mask = 1ull<<5 /* fpa */;
6236 info.func = __cvmx_error_display;
6237 info.user_info = (long)
6238 "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
6239 " the count available is greater than than pointers\n"
6240 " present in the FPA.\n";
6241 fail |= cvmx_error_add(&info);
6243 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6244 info.status_addr = CVMX_FPA_INT_SUM;
6245 info.status_mask = 1ull<<15 /* q3_perr */;
6246 info.enable_addr = CVMX_FPA_INT_ENB;
6247 info.enable_mask = 1ull<<15 /* q3_perr */;
6249 info.group = CVMX_ERROR_GROUP_INTERNAL;
6250 info.group_index = 0;
6251 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6252 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6253 info.parent.status_mask = 1ull<<5 /* fpa */;
6254 info.func = __cvmx_error_display;
6255 info.user_info = (long)
6256 "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
6257 " the L2C does not have the FPA owner ship bit set.\n";
6258 fail |= cvmx_error_add(&info);
6260 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6261 info.status_addr = CVMX_FPA_INT_SUM;
6262 info.status_mask = 1ull<<16 /* q4_und */;
6263 info.enable_addr = CVMX_FPA_INT_ENB;
6264 info.enable_mask = 1ull<<16 /* q4_und */;
6266 info.group = CVMX_ERROR_GROUP_INTERNAL;
6267 info.group_index = 0;
6268 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6269 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6270 info.parent.status_mask = 1ull<<5 /* fpa */;
6271 info.func = __cvmx_error_display;
6272 info.user_info = (long)
6273 "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
6275 fail |= cvmx_error_add(&info);
6277 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6278 info.status_addr = CVMX_FPA_INT_SUM;
6279 info.status_mask = 1ull<<17 /* q4_coff */;
6280 info.enable_addr = CVMX_FPA_INT_ENB;
6281 info.enable_mask = 1ull<<17 /* q4_coff */;
6283 info.group = CVMX_ERROR_GROUP_INTERNAL;
6284 info.group_index = 0;
6285 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6286 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6287 info.parent.status_mask = 1ull<<5 /* fpa */;
6288 info.func = __cvmx_error_display;
6289 info.user_info = (long)
6290 "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
6291 " the count available is greater than than pointers\n"
6292 " present in the FPA.\n";
6293 fail |= cvmx_error_add(&info);
6295 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6296 info.status_addr = CVMX_FPA_INT_SUM;
6297 info.status_mask = 1ull<<18 /* q4_perr */;
6298 info.enable_addr = CVMX_FPA_INT_ENB;
6299 info.enable_mask = 1ull<<18 /* q4_perr */;
6301 info.group = CVMX_ERROR_GROUP_INTERNAL;
6302 info.group_index = 0;
6303 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6304 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6305 info.parent.status_mask = 1ull<<5 /* fpa */;
6306 info.func = __cvmx_error_display;
6307 info.user_info = (long)
6308 "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
6309 " the L2C does not have the FPA owner ship bit set.\n";
6310 fail |= cvmx_error_add(&info);
6312 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6313 info.status_addr = CVMX_FPA_INT_SUM;
6314 info.status_mask = 1ull<<19 /* q5_und */;
6315 info.enable_addr = CVMX_FPA_INT_ENB;
6316 info.enable_mask = 1ull<<19 /* q5_und */;
6318 info.group = CVMX_ERROR_GROUP_INTERNAL;
6319 info.group_index = 0;
6320 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6321 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6322 info.parent.status_mask = 1ull<<5 /* fpa */;
6323 info.func = __cvmx_error_display;
6324 info.user_info = (long)
6325 "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
6327 fail |= cvmx_error_add(&info);
6329 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6330 info.status_addr = CVMX_FPA_INT_SUM;
6331 info.status_mask = 1ull<<20 /* q5_coff */;
6332 info.enable_addr = CVMX_FPA_INT_ENB;
6333 info.enable_mask = 1ull<<20 /* q5_coff */;
6335 info.group = CVMX_ERROR_GROUP_INTERNAL;
6336 info.group_index = 0;
6337 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6338 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6339 info.parent.status_mask = 1ull<<5 /* fpa */;
6340 info.func = __cvmx_error_display;
6341 info.user_info = (long)
6342 "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
6343 " the count available is greater than than pointers\n"
6344 " present in the FPA.\n";
6345 fail |= cvmx_error_add(&info);
6347 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6348 info.status_addr = CVMX_FPA_INT_SUM;
6349 info.status_mask = 1ull<<21 /* q5_perr */;
6350 info.enable_addr = CVMX_FPA_INT_ENB;
6351 info.enable_mask = 1ull<<21 /* q5_perr */;
6353 info.group = CVMX_ERROR_GROUP_INTERNAL;
6354 info.group_index = 0;
6355 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6356 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6357 info.parent.status_mask = 1ull<<5 /* fpa */;
6358 info.func = __cvmx_error_display;
6359 info.user_info = (long)
6360 "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
6361 " the L2C does not have the FPA owner ship bit set.\n";
6362 fail |= cvmx_error_add(&info);
6364 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6365 info.status_addr = CVMX_FPA_INT_SUM;
6366 info.status_mask = 1ull<<22 /* q6_und */;
6367 info.enable_addr = CVMX_FPA_INT_ENB;
6368 info.enable_mask = 1ull<<22 /* q6_und */;
6370 info.group = CVMX_ERROR_GROUP_INTERNAL;
6371 info.group_index = 0;
6372 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6373 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6374 info.parent.status_mask = 1ull<<5 /* fpa */;
6375 info.func = __cvmx_error_display;
6376 info.user_info = (long)
6377 "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
6379 fail |= cvmx_error_add(&info);
6381 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6382 info.status_addr = CVMX_FPA_INT_SUM;
6383 info.status_mask = 1ull<<23 /* q6_coff */;
6384 info.enable_addr = CVMX_FPA_INT_ENB;
6385 info.enable_mask = 1ull<<23 /* q6_coff */;
6387 info.group = CVMX_ERROR_GROUP_INTERNAL;
6388 info.group_index = 0;
6389 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6390 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6391 info.parent.status_mask = 1ull<<5 /* fpa */;
6392 info.func = __cvmx_error_display;
6393 info.user_info = (long)
6394 "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
6395 " the count available is greater than than pointers\n"
6396 " present in the FPA.\n";
6397 fail |= cvmx_error_add(&info);
6399 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6400 info.status_addr = CVMX_FPA_INT_SUM;
6401 info.status_mask = 1ull<<24 /* q6_perr */;
6402 info.enable_addr = CVMX_FPA_INT_ENB;
6403 info.enable_mask = 1ull<<24 /* q6_perr */;
6405 info.group = CVMX_ERROR_GROUP_INTERNAL;
6406 info.group_index = 0;
6407 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6408 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6409 info.parent.status_mask = 1ull<<5 /* fpa */;
6410 info.func = __cvmx_error_display;
6411 info.user_info = (long)
6412 "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
6413 " the L2C does not have the FPA owner ship bit set.\n";
6414 fail |= cvmx_error_add(&info);
6416 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6417 info.status_addr = CVMX_FPA_INT_SUM;
6418 info.status_mask = 1ull<<25 /* q7_und */;
6419 info.enable_addr = CVMX_FPA_INT_ENB;
6420 info.enable_mask = 1ull<<25 /* q7_und */;
6422 info.group = CVMX_ERROR_GROUP_INTERNAL;
6423 info.group_index = 0;
6424 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6425 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6426 info.parent.status_mask = 1ull<<5 /* fpa */;
6427 info.func = __cvmx_error_display;
6428 info.user_info = (long)
6429 "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
6431 fail |= cvmx_error_add(&info);
6433 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6434 info.status_addr = CVMX_FPA_INT_SUM;
6435 info.status_mask = 1ull<<26 /* q7_coff */;
6436 info.enable_addr = CVMX_FPA_INT_ENB;
6437 info.enable_mask = 1ull<<26 /* q7_coff */;
6439 info.group = CVMX_ERROR_GROUP_INTERNAL;
6440 info.group_index = 0;
6441 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6442 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6443 info.parent.status_mask = 1ull<<5 /* fpa */;
6444 info.func = __cvmx_error_display;
6445 info.user_info = (long)
6446 "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
6447 " the count available is greater than than pointers\n"
6448 " present in the FPA.\n";
6449 fail |= cvmx_error_add(&info);
6451 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6452 info.status_addr = CVMX_FPA_INT_SUM;
6453 info.status_mask = 1ull<<27 /* q7_perr */;
6454 info.enable_addr = CVMX_FPA_INT_ENB;
6455 info.enable_mask = 1ull<<27 /* q7_perr */;
6457 info.group = CVMX_ERROR_GROUP_INTERNAL;
6458 info.group_index = 0;
6459 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6460 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6461 info.parent.status_mask = 1ull<<5 /* fpa */;
6462 info.func = __cvmx_error_display;
6463 info.user_info = (long)
6464 "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
6465 " the L2C does not have the FPA owner ship bit set.\n";
6466 fail |= cvmx_error_add(&info);
6468 /* CVMX_LMCX_MEM_CFG0(0) */
6469 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6470 info.status_addr = CVMX_LMCX_MEM_CFG0(0);
6471 info.status_mask = 0xfull<<21 /* sec_err */;
6472 info.enable_addr = CVMX_LMCX_MEM_CFG0(0);
6473 info.enable_mask = 1ull<<19 /* intr_sec_ena */;
6474 info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
6475 info.group = CVMX_ERROR_GROUP_LMC;
6476 info.group_index = 0;
6477 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6478 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6479 info.parent.status_mask = 1ull<<17 /* lmc0 */;
6480 info.func = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
6481 info.user_info = (long)
6482 "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
6483 " In 64b mode, ecc is calculated on 2 cycle worth of data\n"
6484 " [0] corresponds to DQ[63:0]_c0_p0\n"
6485 " [1] corresponds to DQ[63:0]_c0_p1\n"
6486 " [2] corresponds to DQ[63:0]_c1_p0\n"
6487 " [3] corresponds to DQ[63:0]_c1_p1\n"
6488 " In 32b mode, ecc is calculated on 4 cycle worth of data\n"
6489 " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
6490 " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
6491 " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
6492 " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
6493 " where _cC_pP denotes cycle C and phase P\n"
6494 " Write of 1 will clear the corresponding error bit\n";
6495 fail |= cvmx_error_add(&info);
6497 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6498 info.status_addr = CVMX_LMCX_MEM_CFG0(0);
6499 info.status_mask = 0xfull<<25 /* ded_err */;
6500 info.enable_addr = CVMX_LMCX_MEM_CFG0(0);
6501 info.enable_mask = 1ull<<20 /* intr_ded_ena */;
6503 info.group = CVMX_ERROR_GROUP_LMC;
6504 info.group_index = 0;
6505 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6506 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6507 info.parent.status_mask = 1ull<<17 /* lmc0 */;
6508 info.func = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
6509 info.user_info = (long)
6510 "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
6511 " In 64b mode, ecc is calculated on 2 cycle worth of data\n"
6512 " [0] corresponds to DQ[63:0]_c0_p0\n"
6513 " [1] corresponds to DQ[63:0]_c0_p1\n"
6514 " [2] corresponds to DQ[63:0]_c1_p0\n"
6515 " [3] corresponds to DQ[63:0]_c1_p1\n"
6516 " In 32b mode, ecc is calculated on 4 cycle worth of data\n"
6517 " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
6518 " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
6519 " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
6520 " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
6521 " where _cC_pP denotes cycle C and phase P\n"
6522 " Write of 1 will clear the corresponding error bit\n";
6523 fail |= cvmx_error_add(&info);
6525 /* CVMX_IOB_INT_SUM */
6526 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6527 info.status_addr = CVMX_IOB_INT_SUM;
6528 info.status_mask = 1ull<<0 /* np_sop */;
6529 info.enable_addr = CVMX_IOB_INT_ENB;
6530 info.enable_mask = 1ull<<0 /* np_sop */;
6532 info.group = CVMX_ERROR_GROUP_INTERNAL;
6533 info.group_index = 0;
6534 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6535 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6536 info.parent.status_mask = 1ull<<30 /* iob */;
6537 info.func = __cvmx_error_display;
6538 info.user_info = (long)
6539 "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
6540 " port for a non-passthrough packet.\n"
6541 " The first detected error associated with bits [5:0]\n"
6542 " of this register will only be set here. A new bit\n"
6543 " can be set when the previous reported bit is cleared.\n";
6544 fail |= cvmx_error_add(&info);
6546 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6547 info.status_addr = CVMX_IOB_INT_SUM;
6548 info.status_mask = 1ull<<1 /* np_eop */;
6549 info.enable_addr = CVMX_IOB_INT_ENB;
6550 info.enable_mask = 1ull<<1 /* np_eop */;
6552 info.group = CVMX_ERROR_GROUP_INTERNAL;
6553 info.group_index = 0;
6554 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6555 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6556 info.parent.status_mask = 1ull<<30 /* iob */;
6557 info.func = __cvmx_error_display;
6558 info.user_info = (long)
6559 "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
6560 " port for a non-passthrough packet.\n"
6561 " The first detected error associated with bits [5:0]\n"
6562 " of this register will only be set here. A new bit\n"
6563 " can be set when the previous reported bit is cleared.\n";
6564 fail |= cvmx_error_add(&info);
6566 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6567 info.status_addr = CVMX_IOB_INT_SUM;
6568 info.status_mask = 1ull<<2 /* p_sop */;
6569 info.enable_addr = CVMX_IOB_INT_ENB;
6570 info.enable_mask = 1ull<<2 /* p_sop */;
6572 info.group = CVMX_ERROR_GROUP_INTERNAL;
6573 info.group_index = 0;
6574 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6575 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6576 info.parent.status_mask = 1ull<<30 /* iob */;
6577 info.func = __cvmx_error_display;
6578 info.user_info = (long)
6579 "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
6580 " port for a passthrough packet.\n"
6581 " The first detected error associated with bits [5:0]\n"
6582 " of this register will only be set here. A new bit\n"
6583 " can be set when the previous reported bit is cleared.\n";
6584 fail |= cvmx_error_add(&info);
6586 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6587 info.status_addr = CVMX_IOB_INT_SUM;
6588 info.status_mask = 1ull<<3 /* p_eop */;
6589 info.enable_addr = CVMX_IOB_INT_ENB;
6590 info.enable_mask = 1ull<<3 /* p_eop */;
6592 info.group = CVMX_ERROR_GROUP_INTERNAL;
6593 info.group_index = 0;
6594 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6595 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6596 info.parent.status_mask = 1ull<<30 /* iob */;
6597 info.func = __cvmx_error_display;
6598 info.user_info = (long)
6599 "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
6600 " port for a passthrough packet.\n"
6601 " The first detected error associated with bits [5:0]\n"
6602 " of this register will only be set here. A new bit\n"
6603 " can be set when the previous reported bit is cleared.\n";
6604 fail |= cvmx_error_add(&info);
6606 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6607 info.status_addr = CVMX_IOB_INT_SUM;
6608 info.status_mask = 1ull<<4 /* np_dat */;
6609 info.enable_addr = CVMX_IOB_INT_ENB;
6610 info.enable_mask = 1ull<<4 /* np_dat */;
6612 info.group = CVMX_ERROR_GROUP_INTERNAL;
6613 info.group_index = 0;
6614 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6615 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6616 info.parent.status_mask = 1ull<<30 /* iob */;
6617 info.func = __cvmx_error_display;
6618 info.user_info = (long)
6619 "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
6620 " port for a non-passthrough packet.\n"
6621 " The first detected error associated with bits [5:0]\n"
6622 " of this register will only be set here. A new bit\n"
6623 " can be set when the previous reported bit is cleared.\n";
6624 fail |= cvmx_error_add(&info);
6626 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6627 info.status_addr = CVMX_IOB_INT_SUM;
6628 info.status_mask = 1ull<<5 /* p_dat */;
6629 info.enable_addr = CVMX_IOB_INT_ENB;
6630 info.enable_mask = 1ull<<5 /* p_dat */;
6632 info.group = CVMX_ERROR_GROUP_INTERNAL;
6633 info.group_index = 0;
6634 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6635 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6636 info.parent.status_mask = 1ull<<30 /* iob */;
6637 info.func = __cvmx_error_display;
6638 info.user_info = (long)
6639 "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
6640 " port for a passthrough packet.\n"
6641 " The first detected error associated with bits [5:0]\n"
6642 " of this register will only be set here. A new bit\n"
6643 " can be set when the previous reported bit is cleared.\n";
6644 fail |= cvmx_error_add(&info);
6646 /* CVMX_ZIP_ERROR */
6647 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6648 info.status_addr = CVMX_ZIP_ERROR;
6649 info.status_mask = 1ull<<0 /* doorbell */;
6650 info.enable_addr = CVMX_ZIP_INT_MASK;
6651 info.enable_mask = 1ull<<0 /* doorbell */;
6653 info.group = CVMX_ERROR_GROUP_INTERNAL;
6654 info.group_index = 0;
6655 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6656 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6657 info.parent.status_mask = 1ull<<7 /* zip */;
6658 info.func = __cvmx_error_display;
6659 info.user_info = (long)
6660 "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
6661 fail |= cvmx_error_add(&info);
6663 /* CVMX_USBNX_INT_SUM(0) */
6664 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6665 info.status_addr = CVMX_USBNX_INT_SUM(0);
6666 info.status_mask = 1ull<<0 /* pr_po_e */;
6667 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6668 info.enable_mask = 1ull<<0 /* pr_po_e */;
6670 info.group = CVMX_ERROR_GROUP_USB;
6671 info.group_index = 0;
6672 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6673 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6674 info.parent.status_mask = 1ull<<13 /* usb */;
6675 info.func = __cvmx_error_display;
6676 info.user_info = (long)
6677 "ERROR USBNX_INT_SUM(0)[PR_PO_E]: PP Request Fifo Popped When Empty.\n";
6678 fail |= cvmx_error_add(&info);
6680 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6681 info.status_addr = CVMX_USBNX_INT_SUM(0);
6682 info.status_mask = 1ull<<1 /* pr_pu_f */;
6683 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6684 info.enable_mask = 1ull<<1 /* pr_pu_f */;
6686 info.group = CVMX_ERROR_GROUP_USB;
6687 info.group_index = 0;
6688 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6689 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6690 info.parent.status_mask = 1ull<<13 /* usb */;
6691 info.func = __cvmx_error_display;
6692 info.user_info = (long)
6693 "ERROR USBNX_INT_SUM(0)[PR_PU_F]: PP Request Fifo Pushed When Full.\n";
6694 fail |= cvmx_error_add(&info);
6696 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6697 info.status_addr = CVMX_USBNX_INT_SUM(0);
6698 info.status_mask = 1ull<<2 /* nr_po_e */;
6699 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6700 info.enable_mask = 1ull<<2 /* nr_po_e */;
6702 info.group = CVMX_ERROR_GROUP_USB;
6703 info.group_index = 0;
6704 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6705 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6706 info.parent.status_mask = 1ull<<13 /* usb */;
6707 info.func = __cvmx_error_display;
6708 info.user_info = (long)
6709 "ERROR USBNX_INT_SUM(0)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n";
6710 fail |= cvmx_error_add(&info);
6712 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6713 info.status_addr = CVMX_USBNX_INT_SUM(0);
6714 info.status_mask = 1ull<<3 /* nr_pu_f */;
6715 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6716 info.enable_mask = 1ull<<3 /* nr_pu_f */;
6718 info.group = CVMX_ERROR_GROUP_USB;
6719 info.group_index = 0;
6720 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6721 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6722 info.parent.status_mask = 1ull<<13 /* usb */;
6723 info.func = __cvmx_error_display;
6724 info.user_info = (long)
6725 "ERROR USBNX_INT_SUM(0)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n";
6726 fail |= cvmx_error_add(&info);
6728 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6729 info.status_addr = CVMX_USBNX_INT_SUM(0);
6730 info.status_mask = 1ull<<4 /* lr_po_e */;
6731 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6732 info.enable_mask = 1ull<<4 /* lr_po_e */;
6734 info.group = CVMX_ERROR_GROUP_USB;
6735 info.group_index = 0;
6736 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6737 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6738 info.parent.status_mask = 1ull<<13 /* usb */;
6739 info.func = __cvmx_error_display;
6740 info.user_info = (long)
6741 "ERROR USBNX_INT_SUM(0)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n";
6742 fail |= cvmx_error_add(&info);
6744 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6745 info.status_addr = CVMX_USBNX_INT_SUM(0);
6746 info.status_mask = 1ull<<5 /* lr_pu_f */;
6747 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6748 info.enable_mask = 1ull<<5 /* lr_pu_f */;
6750 info.group = CVMX_ERROR_GROUP_USB;
6751 info.group_index = 0;
6752 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6753 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6754 info.parent.status_mask = 1ull<<13 /* usb */;
6755 info.func = __cvmx_error_display;
6756 info.user_info = (long)
6757 "ERROR USBNX_INT_SUM(0)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n";
6758 fail |= cvmx_error_add(&info);
6760 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6761 info.status_addr = CVMX_USBNX_INT_SUM(0);
6762 info.status_mask = 1ull<<6 /* pt_po_e */;
6763 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6764 info.enable_mask = 1ull<<6 /* pt_po_e */;
6766 info.group = CVMX_ERROR_GROUP_USB;
6767 info.group_index = 0;
6768 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6769 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6770 info.parent.status_mask = 1ull<<13 /* usb */;
6771 info.func = __cvmx_error_display;
6772 info.user_info = (long)
6773 "ERROR USBNX_INT_SUM(0)[PT_PO_E]: PP Trasaction Fifo Popped When Full.\n";
6774 fail |= cvmx_error_add(&info);
6776 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6777 info.status_addr = CVMX_USBNX_INT_SUM(0);
6778 info.status_mask = 1ull<<7 /* pt_pu_f */;
6779 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6780 info.enable_mask = 1ull<<7 /* pt_pu_f */;
6782 info.group = CVMX_ERROR_GROUP_USB;
6783 info.group_index = 0;
6784 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6785 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6786 info.parent.status_mask = 1ull<<13 /* usb */;
6787 info.func = __cvmx_error_display;
6788 info.user_info = (long)
6789 "ERROR USBNX_INT_SUM(0)[PT_PU_F]: PP Trasaction Fifo Pushed When Full.\n";
6790 fail |= cvmx_error_add(&info);
6792 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6793 info.status_addr = CVMX_USBNX_INT_SUM(0);
6794 info.status_mask = 1ull<<8 /* nt_po_e */;
6795 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6796 info.enable_mask = 1ull<<8 /* nt_po_e */;
6798 info.group = CVMX_ERROR_GROUP_USB;
6799 info.group_index = 0;
6800 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6801 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6802 info.parent.status_mask = 1ull<<13 /* usb */;
6803 info.func = __cvmx_error_display;
6804 info.user_info = (long)
6805 "ERROR USBNX_INT_SUM(0)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n";
6806 fail |= cvmx_error_add(&info);
6808 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6809 info.status_addr = CVMX_USBNX_INT_SUM(0);
6810 info.status_mask = 1ull<<9 /* nt_pu_f */;
6811 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6812 info.enable_mask = 1ull<<9 /* nt_pu_f */;
6814 info.group = CVMX_ERROR_GROUP_USB;
6815 info.group_index = 0;
6816 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6817 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6818 info.parent.status_mask = 1ull<<13 /* usb */;
6819 info.func = __cvmx_error_display;
6820 info.user_info = (long)
6821 "ERROR USBNX_INT_SUM(0)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n";
6822 fail |= cvmx_error_add(&info);
6824 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6825 info.status_addr = CVMX_USBNX_INT_SUM(0);
6826 info.status_mask = 1ull<<10 /* lt_po_e */;
6827 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6828 info.enable_mask = 1ull<<10 /* lt_po_e */;
6830 info.group = CVMX_ERROR_GROUP_USB;
6831 info.group_index = 0;
6832 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6833 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6834 info.parent.status_mask = 1ull<<13 /* usb */;
6835 info.func = __cvmx_error_display;
6836 info.user_info = (long)
6837 "ERROR USBNX_INT_SUM(0)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n";
6838 fail |= cvmx_error_add(&info);
6840 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6841 info.status_addr = CVMX_USBNX_INT_SUM(0);
6842 info.status_mask = 1ull<<11 /* lt_pu_f */;
6843 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6844 info.enable_mask = 1ull<<11 /* lt_pu_f */;
6846 info.group = CVMX_ERROR_GROUP_USB;
6847 info.group_index = 0;
6848 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6849 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6850 info.parent.status_mask = 1ull<<13 /* usb */;
6851 info.func = __cvmx_error_display;
6852 info.user_info = (long)
6853 "ERROR USBNX_INT_SUM(0)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n";
6854 fail |= cvmx_error_add(&info);
6856 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6857 info.status_addr = CVMX_USBNX_INT_SUM(0);
6858 info.status_mask = 1ull<<12 /* dcred_e */;
6859 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6860 info.enable_mask = 1ull<<12 /* dcred_e */;
6862 info.group = CVMX_ERROR_GROUP_USB;
6863 info.group_index = 0;
6864 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6865 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6866 info.parent.status_mask = 1ull<<13 /* usb */;
6867 info.func = __cvmx_error_display;
6868 info.user_info = (long)
6869 "ERROR USBNX_INT_SUM(0)[DCRED_E]: Data Credit Fifo Pushed When Full.\n";
6870 fail |= cvmx_error_add(&info);
6872 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6873 info.status_addr = CVMX_USBNX_INT_SUM(0);
6874 info.status_mask = 1ull<<13 /* dcred_f */;
6875 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6876 info.enable_mask = 1ull<<13 /* dcred_f */;
6878 info.group = CVMX_ERROR_GROUP_USB;
6879 info.group_index = 0;
6880 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6881 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6882 info.parent.status_mask = 1ull<<13 /* usb */;
6883 info.func = __cvmx_error_display;
6884 info.user_info = (long)
6885 "ERROR USBNX_INT_SUM(0)[DCRED_F]: Data CreditFifo Pushed When Full.\n";
6886 fail |= cvmx_error_add(&info);
6888 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6889 info.status_addr = CVMX_USBNX_INT_SUM(0);
6890 info.status_mask = 1ull<<14 /* l2c_s_e */;
6891 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6892 info.enable_mask = 1ull<<14 /* l2c_s_e */;
6894 info.group = CVMX_ERROR_GROUP_USB;
6895 info.group_index = 0;
6896 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6897 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6898 info.parent.status_mask = 1ull<<13 /* usb */;
6899 info.func = __cvmx_error_display;
6900 info.user_info = (long)
6901 "ERROR USBNX_INT_SUM(0)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n";
6902 fail |= cvmx_error_add(&info);
6904 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6905 info.status_addr = CVMX_USBNX_INT_SUM(0);
6906 info.status_mask = 1ull<<15 /* l2c_a_f */;
6907 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6908 info.enable_mask = 1ull<<15 /* l2c_a_f */;
6910 info.group = CVMX_ERROR_GROUP_USB;
6911 info.group_index = 0;
6912 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6913 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6914 info.parent.status_mask = 1ull<<13 /* usb */;
6915 info.func = __cvmx_error_display;
6916 info.user_info = (long)
6917 "ERROR USBNX_INT_SUM(0)[L2C_A_F]: L2C Credit Count Added When Full.\n";
6918 fail |= cvmx_error_add(&info);
6920 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6921 info.status_addr = CVMX_USBNX_INT_SUM(0);
6922 info.status_mask = 1ull<<16 /* lt_fi_e */;
6923 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6924 info.enable_mask = 1ull<<16 /* l2_fi_e */;
6926 info.group = CVMX_ERROR_GROUP_USB;
6927 info.group_index = 0;
6928 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6929 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6930 info.parent.status_mask = 1ull<<13 /* usb */;
6931 info.func = __cvmx_error_display;
6932 info.user_info = (long)
6933 "ERROR USBNX_INT_SUM(0)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n";
6934 fail |= cvmx_error_add(&info);
6936 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6937 info.status_addr = CVMX_USBNX_INT_SUM(0);
6938 info.status_mask = 1ull<<17 /* lt_fi_f */;
6939 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6940 info.enable_mask = 1ull<<17 /* l2_fi_f */;
6942 info.group = CVMX_ERROR_GROUP_USB;
6943 info.group_index = 0;
6944 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6945 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6946 info.parent.status_mask = 1ull<<13 /* usb */;
6947 info.func = __cvmx_error_display;
6948 info.user_info = (long)
6949 "ERROR USBNX_INT_SUM(0)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n";
6950 fail |= cvmx_error_add(&info);
6952 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6953 info.status_addr = CVMX_USBNX_INT_SUM(0);
6954 info.status_mask = 1ull<<18 /* rg_fi_e */;
6955 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6956 info.enable_mask = 1ull<<18 /* rg_fi_e */;
6958 info.group = CVMX_ERROR_GROUP_USB;
6959 info.group_index = 0;
6960 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6961 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6962 info.parent.status_mask = 1ull<<13 /* usb */;
6963 info.func = __cvmx_error_display;
6964 info.user_info = (long)
6965 "ERROR USBNX_INT_SUM(0)[RG_FI_E]: Register Request Fifo Pushed When Full.\n";
6966 fail |= cvmx_error_add(&info);
6968 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6969 info.status_addr = CVMX_USBNX_INT_SUM(0);
6970 info.status_mask = 1ull<<19 /* rg_fi_f */;
6971 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6972 info.enable_mask = 1ull<<19 /* rg_fi_f */;
6974 info.group = CVMX_ERROR_GROUP_USB;
6975 info.group_index = 0;
6976 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6977 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6978 info.parent.status_mask = 1ull<<13 /* usb */;
6979 info.func = __cvmx_error_display;
6980 info.user_info = (long)
6981 "ERROR USBNX_INT_SUM(0)[RG_FI_F]: Register Request Fifo Pushed When Full.\n";
6982 fail |= cvmx_error_add(&info);
6984 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6985 info.status_addr = CVMX_USBNX_INT_SUM(0);
6986 info.status_mask = 1ull<<20 /* rq_q2_f */;
6987 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6988 info.enable_mask = 1ull<<20 /* rq_q2_f */;
6990 info.group = CVMX_ERROR_GROUP_USB;
6991 info.group_index = 0;
6992 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6993 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6994 info.parent.status_mask = 1ull<<13 /* usb */;
6995 info.func = __cvmx_error_display;
6996 info.user_info = (long)
6997 "ERROR USBNX_INT_SUM(0)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n";
6998 fail |= cvmx_error_add(&info);
7000 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7001 info.status_addr = CVMX_USBNX_INT_SUM(0);
7002 info.status_mask = 1ull<<21 /* rq_q2_e */;
7003 info.enable_addr = CVMX_USBNX_INT_ENB(0);
7004 info.enable_mask = 1ull<<21 /* rq_q2_e */;
7006 info.group = CVMX_ERROR_GROUP_USB;
7007 info.group_index = 0;
7008 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7009 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7010 info.parent.status_mask = 1ull<<13 /* usb */;
7011 info.func = __cvmx_error_display;
7012 info.user_info = (long)
7013 "ERROR USBNX_INT_SUM(0)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n";
7014 fail |= cvmx_error_add(&info);
7016 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7017 info.status_addr = CVMX_USBNX_INT_SUM(0);
7018 info.status_mask = 1ull<<22 /* rq_q3_f */;
7019 info.enable_addr = CVMX_USBNX_INT_ENB(0);
7020 info.enable_mask = 1ull<<22 /* rq_q3_f */;
7022 info.group = CVMX_ERROR_GROUP_USB;
7023 info.group_index = 0;
7024 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7025 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7026 info.parent.status_mask = 1ull<<13 /* usb */;
7027 info.func = __cvmx_error_display;
7028 info.user_info = (long)
7029 "ERROR USBNX_INT_SUM(0)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n";
7030 fail |= cvmx_error_add(&info);
7032 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7033 info.status_addr = CVMX_USBNX_INT_SUM(0);
7034 info.status_mask = 1ull<<23 /* rq_q3_e */;
7035 info.enable_addr = CVMX_USBNX_INT_ENB(0);
7036 info.enable_mask = 1ull<<23 /* rq_q3_e */;
7038 info.group = CVMX_ERROR_GROUP_USB;
7039 info.group_index = 0;
7040 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7041 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7042 info.parent.status_mask = 1ull<<13 /* usb */;
7043 info.func = __cvmx_error_display;
7044 info.user_info = (long)
7045 "ERROR USBNX_INT_SUM(0)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n";
7046 fail |= cvmx_error_add(&info);
7048 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7049 info.status_addr = CVMX_USBNX_INT_SUM(0);
7050 info.status_mask = 1ull<<24 /* uod_pe */;
7051 info.enable_addr = CVMX_USBNX_INT_ENB(0);
7052 info.enable_mask = 1ull<<24 /* uod_pe */;
7054 info.group = CVMX_ERROR_GROUP_USB;
7055 info.group_index = 0;
7056 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7057 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7058 info.parent.status_mask = 1ull<<13 /* usb */;
7059 info.func = __cvmx_error_display;
7060 info.user_info = (long)
7061 "ERROR USBNX_INT_SUM(0)[UOD_PE]: UOD Fifo Pop Empty.\n";
7062 fail |= cvmx_error_add(&info);
7064 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7065 info.status_addr = CVMX_USBNX_INT_SUM(0);
7066 info.status_mask = 1ull<<25 /* uod_pf */;
7067 info.enable_addr = CVMX_USBNX_INT_ENB(0);
7068 info.enable_mask = 1ull<<25 /* uod_pf */;
7070 info.group = CVMX_ERROR_GROUP_USB;
7071 info.group_index = 0;
7072 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7073 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7074 info.parent.status_mask = 1ull<<13 /* usb */;
7075 info.func = __cvmx_error_display;
7076 info.user_info = (long)
7077 "ERROR USBNX_INT_SUM(0)[UOD_PF]: UOD Fifo Push Full.\n";
7078 fail |= cvmx_error_add(&info);
7080 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7081 info.status_addr = CVMX_USBNX_INT_SUM(0);
7082 info.status_mask = 1ull<<32 /* ltl_f_pe */;
7083 info.enable_addr = CVMX_USBNX_INT_ENB(0);
7084 info.enable_mask = 1ull<<32 /* ltl_f_pe */;
7086 info.group = CVMX_ERROR_GROUP_USB;
7087 info.group_index = 0;
7088 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7089 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7090 info.parent.status_mask = 1ull<<13 /* usb */;
7091 info.func = __cvmx_error_display;
7092 info.user_info = (long)
7093 "ERROR USBNX_INT_SUM(0)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n";
7094 fail |= cvmx_error_add(&info);
7096 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7097 info.status_addr = CVMX_USBNX_INT_SUM(0);
7098 info.status_mask = 1ull<<33 /* ltl_f_pf */;
7099 info.enable_addr = CVMX_USBNX_INT_ENB(0);
7100 info.enable_mask = 1ull<<33 /* ltl_f_pf */;
7102 info.group = CVMX_ERROR_GROUP_USB;
7103 info.group_index = 0;
7104 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7105 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7106 info.parent.status_mask = 1ull<<13 /* usb */;
7107 info.func = __cvmx_error_display;
7108 info.user_info = (long)
7109 "ERROR USBNX_INT_SUM(0)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n";
7110 fail |= cvmx_error_add(&info);
7112 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7113 info.status_addr = CVMX_USBNX_INT_SUM(0);
7114 info.status_mask = 1ull<<34 /* nd4o_rpe */;
7115 info.enable_addr = CVMX_USBNX_INT_ENB(0);
7116 info.enable_mask = 1ull<<34 /* nd4o_rpe */;
7118 info.group = CVMX_ERROR_GROUP_USB;
7119 info.group_index = 0;
7120 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7121 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7122 info.parent.status_mask = 1ull<<13 /* usb */;
7123 info.func = __cvmx_error_display;
7124 info.user_info = (long)
7125 "ERROR USBNX_INT_SUM(0)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n";
7126 fail |= cvmx_error_add(&info);
7128 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7129 info.status_addr = CVMX_USBNX_INT_SUM(0);
7130 info.status_mask = 1ull<<35 /* nd4o_rpf */;
7131 info.enable_addr = CVMX_USBNX_INT_ENB(0);
7132 info.enable_mask = 1ull<<35 /* nd4o_rpf */;
7134 info.group = CVMX_ERROR_GROUP_USB;
7135 info.group_index = 0;
7136 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7137 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7138 info.parent.status_mask = 1ull<<13 /* usb */;
7139 info.func = __cvmx_error_display;
7140 info.user_info = (long)
7141 "ERROR USBNX_INT_SUM(0)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n";
7142 fail |= cvmx_error_add(&info);
7144 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7145 info.status_addr = CVMX_USBNX_INT_SUM(0);
7146 info.status_mask = 1ull<<36 /* nd4o_dpe */;
7147 info.enable_addr = CVMX_USBNX_INT_ENB(0);
7148 info.enable_mask = 1ull<<36 /* nd4o_dpe */;
7150 info.group = CVMX_ERROR_GROUP_USB;
7151 info.group_index = 0;
7152 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7153 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7154 info.parent.status_mask = 1ull<<13 /* usb */;
7155 info.func = __cvmx_error_display;
7156 info.user_info = (long)
7157 "ERROR USBNX_INT_SUM(0)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n";
7158 fail |= cvmx_error_add(&info);
7160 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7161 info.status_addr = CVMX_USBNX_INT_SUM(0);
7162 info.status_mask = 1ull<<37 /* nd4o_dpf */;
7163 info.enable_addr = CVMX_USBNX_INT_ENB(0);
7164 info.enable_mask = 1ull<<37 /* nd4o_dpf */;
7166 info.group = CVMX_ERROR_GROUP_USB;
7167 info.group_index = 0;
7168 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7169 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
7170 info.parent.status_mask = 1ull<<13 /* usb */;
7171 info.func = __cvmx_error_display;
7172 info.user_info = (long)
7173 "ERROR USBNX_INT_SUM(0)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n";
7174 fail |= cvmx_error_add(&info);